Rapid design method for interpolated phase-locked loop filter
Through the quick design method of interpolated phase-locked loop loop filter, the complex and time-consuming design of the phase-locked loop chip loop filter is solved, and the rapid design and local phase noise are achieved.
Patent Information
- Application Number
- CN202411590314.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-08
- Publication Date
- 2025-02-28
AI Technical Summary
In the field of microwave communication, the loop filter design of phase-locked loop chips is complex, especially in the absence of rapid design software, which is time-consuming and effort-intensive.
A quick design method for interpolated phase-locked loop loop filter is proposed. By designing the phase-locked loop circuit and the hardware circuit of the loop filter, relevant parameters are obtained, the pole, zero point, bandwidth and phase margin formulas are determined, the resistance and capacitance values are calculated, and the secondary design of the loop filter is completed through simulation software.
This method can quickly complete the secondary design of the loop filter, reduce the design difficulty and time, and meet the system's requirements for local oscillator noise.
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Figure CN119538828A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of filter design, and in particular relates to a fast design method for an interpolation phase-locked loop filter. Background Art
[0002] In the field of microwave communications, the use environment of RF transceiver equipment is becoming more and more diversified, and the frequency source is an indispensable part of these systems. The integration of phase-locked loop chips is getting higher and higher. When the rest of the hardware circuit structure is basically solidified, designers focus more on chip control and loop filter design, and loop filter design is a relatively complex process.
[0003] Many PLL chip manufacturers have launched rapid design software for their own PLL chips, such as ADIsimPLL launched by ADI, PLLatinumSim launched by TI, etc. The software has loaded various parameters of the corresponding PLL, and can simulate loop filter parameters and device values according to the input loop parameters, simplifying the loop filter design. At the same time, more and more manufacturers at home and abroad have launched more general PLL chips or separate phase detector chips. There is no corresponding rapid design software. When designing the loop filter, it is necessary to deduce according to the loop design theory and finally calculate the discrete device value of the loop filter. In the actual application of the PLL circuit, it is often necessary to adjust the loop parameters of the completed design according to the needs. Regardless of whether there is corresponding simulation auxiliary software, the design is a relatively time-consuming and labor-intensive process. Summary of the invention
[0004] Technical purpose: In view of the above technical problems, the present invention proposes a fast design method for an interpolation phase-locked loop loop filter, which can quickly complete the secondary design of the loop filter and meet the system's requirements for local oscillator phase noise.
[0005] Technical solution: To achieve the above technical objectives, the present invention adopts the following technical solution:
[0006] A fast design method for an interpolation phase-locked loop filter comprises the following steps:
[0007] S1. Design the hardware circuit of the phase-locked loop circuit and the loop filter, and set the structure of the loop filter and the loop bandwidth ω c and phase margin φ(ω), the phase-locked loop circuit comprising a reference source, an R divider, a phase detector, the loop filter, a voltage-controlled oscillator and an N divider;
[0008] S2. Obtain relevant parameters in the phase-locked loop circuit, including: phase detector gain K PD , voltage controlled oscillator gain K VCO and the frequency division number N within the loop;
[0009] S3, according to the relevant parameters in the phase-locked loop circuit and the parameters of the loop filter, determine the pole formula, zero formula, loop bandwidth formula and phase margin formula of the loop filter, calculate the values of all resistors and capacitors in the loop filter, that is, the capacitor design value and the resistor design value, and complete the primary design of the loop filter;
[0010] S4. In the simulation software, design an equivalent circuit to the phase-locked loop circuit and set the voltage-controlled oscillator K VCO After changing to n times of the original value, a simulation test is performed to obtain the simulation values of each capacitor and resistor in the loop filter in the equivalent circuit;
[0011] S5, changing each capacitance simulation value by 1 / n times and each resistance value by n times accordingly, to obtain corresponding capacitance conversion value and resistance conversion value;
[0012] S6. Compare the capacitance conversion value and the resistance conversion value obtained in step S5 with the capacitance design value and the resistance design value determined in step S4 to verify whether the difference is within a preset range, thereby completing the secondary design of the loop filter.
[0013] Preferably, the designed loop filter is any one of a second-order loop filter, a third-order loop filter or a fourth-order loop filter.
[0014] Preferably, the designed loop filter is a second-order loop filter composed of a first capacitor C1, a second capacitor C2, a first resistor R1 and a third resistor R2;
[0015] In step S3, the poles and zeros of the second-order loop filter are expressed as:
[0016]
[0017] T2=R2*C2
[0018] The phase margin is expressed as:
[0019] φ(ω)=tan -1 (ω c *T2)-tan -1 (ω c *T1)
[0020] The loop filter loop bandwidth is defined as:
[0021]
[0022] Preferably, the phase-locked loop circuit includes a clock reference source circuit, a phase-locked reference circuit and a phase-locked main loop circuit, and the clock reference circuit includes a 100 MHz crystal oscillator, a harmonic generator, a first power divider, a first filter, a first amplifier, a third filter, a second amplifier, a frequency doubler and a fourth filter;
[0023] The output end of the crystal oscillator is connected to the harmonic generator, and the output end of the harmonic generator is connected to the first power divider to generate a 2.5GHz reference clock and a 1GHz reference clock. The 2.5GHz reference clock is input into a branch consisting of a third filter, a second amplifier, a doubler and a fourth filter, and the doubled frequency generates an interpolated 5GHz local oscillator; the 1GHz reference clock is input into a branch consisting of a first filter and a first amplifier.
[0024] Preferably, the phase-locked reference circuit includes a DDS chip and a second filter, the output end of the first amplifier is connected to the input end of the DDS chip, the 1GHz reference clock is used as the sampling clock of the DDS chip after filtering and amplification, and the DDS chip uses a digital synthesis method to generate a 75-100MHz clock reference signal.
[0025] Preferably, the phase-locked main loop circuit sequentially connects a phase detector, a first filter, a single-pole double-throw switch, a VCO, a second power divider, a third amplifier, an attenuator, a mixer and a sixth filter to form a loop structure, wherein the phase detector receives a 75-100MHz clock reference signal output by a DDS chip to provide a phase reference for the main loop, and the VCO generates a 5.15-5.2GHz signal, which is split into two paths by the second power divider, one path is output and the other path is used as a feedback signal.
[0026] Preferably, the first filter, the second filter, the third filter and the fourth filter are bandpass filters, and the fifth filter and the sixth filter are low-pass filters.
[0027] Beneficial effects: Due to the adoption of the above technical solution, the present invention has the following beneficial effects:
[0028] The present invention provides a method for quickly designing an interpolation phase-locked loop filter, which can reduce the difficulty of designing the phase-locked loop filter and shorten the design time. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] Figure 1 This is the basic architecture block diagram of the phase-locked loop;
[0030] Figure 2 It is the circuit structure diagram of the phase-locked loop passive loop filter;
[0031] Figure 3 A flow chart of a fast design method for an interpolation phase-locked loop filter is provided for the present invention;
[0032] Figure 4 This is the principle block diagram of the interpolation phase-locked loop;
[0033] Figure 5 This is the schematic diagram of the phase-locked main loop circuit;
[0034] Figure 6 Shows Figure 5 The design values of the discrete components of the mid-loop filter;
[0035] Figure 7 It is the phase noise curve of the interpolation phase-locked loop;
[0036] OC1-crystal oscillator, U1-harmonic generator, PV1-first power divider, F1-first filter, AMP1-first amplifier, U2-DDS chip, F2-second filter;
[0037] F3-third filter, AMP2-second amplifier, U3-doubler, F4-fourth filter;
[0038] U4-phase detector, F5-first filter, SW1-single-pole double-throw switch, U5-VCO, PV2-second power divider, AMP3-third amplifier, ATT1-attenuator, MIX1-mixer, F6-sixth filter;
[0039] R1~R3-first resistor to third resistor, R9-ninth resistor, R10-tenth resistor;
[0040] C1~C3-first capacitor to fourth capacitor, C15-fifteenth capacitor, C18-eighteenth capacitor, C19-nineteenth capacitor. DETAILED DESCRIPTION
[0041] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0042] The present invention proposes a method for fast secondary design of an interpolation phase-locked loop, which theoretically derives various parameters of a second-order passive loop filter of a phase-locked loop, summarizes the relationship between discrete devices and various parameters, and thereby extends it to third-order and fourth-order passive loop filters, and combines auxiliary software simulation to avoid complex derivation and calculation.
[0043] 1. Theoretical derivation of design method
[0044] like Figure 1 The architecture of the phase-locked loop shown mainly includes: reference source f osc , R divider, phase detector, loop filter, VCO and N divider, the output signal f vco .
[0045] The gain factor of each part is expressed as: K PDis the phase detector gain, Z (s) is the loop filter transfer function, K VCO is the VCO gain.
[0046] The open-loop transfer function is expressed as:
[0047]
[0048] The closed-loop transfer function is expressed as:
[0049]
[0050] Among them, H = 1 / N.
[0051] Commonly used passive loop filters are divided into second-order, third-order and fourth-order. The specific order is determined by the number of zeros and poles of the filter. In terms of circuit structure, the high-order has one more RC circuit than the low-order. The second-order loop filter is composed of C1, R2, and C2. The third-order loop filter adds R3 and C3 on the basis of the second-order. The fourth-order loop filter adds R4 and C4 on the basis of the third-order. Figure 2 shown.
[0052] The conventional method for calculating the values of each discrete component of the loop filter is to first calculate the loop filter coefficients (A0, A1, A2, A3), then solve the zero poles (T1, T2, T3, T4) of the loop filter based on the loop filter coefficients, and then derive the relationship between the two indicators and the values of each discrete component of the loop filter based on the definition of loop bandwidth and phase margin, and finally substitute the preset loop bandwidth value and phase margin value to calculate the value of the discrete component of the loop filter. The formulas for the coefficients of loop filters of various orders are shown in Table 1:
[0053] Table 1 Passive loop filter coefficient calculation table
[0054]
[0055]
[0056] The transfer function of the fourth-order passive loop filter is expressed as:
[0057]
[0058] The following calculation is performed using a second-order loop filter as an example, and the second-order loop filter coefficients are obtained from Table 1:
[0059] A0=C1+C2 (4)
[0060] A1=C1*C2*R2 (5)
[0061] The transfer function of the second-order passive loop filter is expressed as follows:
[0062]
[0063] The poles and zeros of the second-order loop filter are expressed as:
[0064]
[0065] T2=R2*C2 (8)
[0066] Substituting equation (1) and equation (6) into equation (2), we can obtain the closed-loop transfer function of the second-order loop filter:
[0067] Let s = j*ω, and convert the phase to frequency to get:
[0068]
[0069] According to the loop filter loop bandwidth definition:
[0070]
[0071] The phase margin is expressed as:
[0072] φ(ω)=tan -1 (ω c *T2)-tan -1 (ω c *T1) (12)
[0073] When the phase margin is the largest, the system stability is the best, and its derivative is set to 0:
[0074]
[0075] The relationship between loop bandwidth and zero poles is obtained:
[0076]
[0077] It can also be expressed as:
[0078]
[0079] Substituting formula (15) into formula (12), the phase margin calculation formula is:
[0080]
[0081] According to the inverse tangent formula: Then we have:
[0082]
[0083] After this calculation, according to the known phase detector gain K PD, the known VCO gain K VCO , the known frequency division number N within the loop, and the set parameter loop bandwidth ω c , phase margin φ(ω), and by substituting these parameters into formula (7), formula (8), formula (11), and formula (17), the values of the discrete components C1, R2, and C2 of the loop filter can be calculated, and the loop filter design is completed.
[0084] Further analysis and deduction can be made from the above calculation process. Substituting formula (7) and formula (8) into formula (14) we can obtain:
[0085]
[0086] Substituting formula (8) and formula (18) into formula (17), we can get the phase margin formula at this time:
[0087]
[0088] In order to ensure the stability of loop parameters, according to formula (1), the loop filter transfer function Z is characterized (s) Medium resistance and capacitance value and VCO electrical adjustment sensitivity K VCO The relationship between them, let the product of the two be a fixed constant n0, and we get:
[0089]
[0090] Combining the pole formula (7), zero formula (8), loop bandwidth formula (18), phase margin formula (19) and loop gain stability formula (20), we can conclude that:
[0091] When the VCO electrical sensitivity K VCO After changing to n times of the original value, the capacitance values in the second-order passive loop all become n times of the original value, and the resistance value becomes 1 / n of the original value, which can ensure that the poles, zeros, loop bandwidth and phase margin of the loop filter remain unchanged. Therefore, the loop parameters are stable, and this rule can be used to quickly perform the secondary design of the loop filter.
[0092] 2. Design process
[0093] Based on the above theory, the present invention proposes a fast design method for an interpolation phase-locked loop filter, such as Figure 3 As shown, the steps are as follows:
[0094] S1. Design the hardware circuit of the phase-locked loop circuit and the loop filter, and set the structure of the loop filter and the loop bandwidth ω c and phase margin φ(ω);
[0095] S2. Obtain relevant parameters in the phase-locked loop circuit, such as: phase detector gain KPD , voltage controlled oscillator gain K VCO and the frequency division number N within the loop;
[0096] S3, determining the pole formula, zero formula, loop bandwidth formula and phase margin formula of the loop filter, calculating the values of all resistors and capacitors in the loop filter, that is, the capacitor design value and the resistor design value, and completing the primary design of the loop filter;
[0097] S4. In the simulation software, design an equivalent circuit to the phase-locked loop circuit and set the voltage-controlled oscillator K VCO After changing to n times of the original value, a simulation test is performed to obtain the simulation values of each capacitor and resistor in the loop filter in the equivalent circuit;
[0098] S5, changing each capacitance simulation value by 1 / n times and each resistance value by n times accordingly, to obtain corresponding capacitance conversion value and resistance conversion value;
[0099] S6. Compare the capacitance conversion value and the resistance conversion value obtained in step S5 with the capacitance design value and the resistance design value determined in step S4 to verify whether the difference is within a preset range, thereby completing the secondary design of the loop filter.
[0100] 3. Examples:
[0101] The following is an example of an interpolation phase-locked loop design to introduce the effect of using the above method to design a loop filter.
[0102] The design example is a phase-locked source with a frequency coverage of 5.15-5.2GHz, a step of 1Hz, and a phase noise lower than -130dBc / Hz@10kHz. The principle of the phase-locked loop circuit is as follows Figure 4 As shown, it includes three parts: clock reference source circuit, phase-locked reference circuit and phase-locked main loop circuit.
[0103] The clock reference circuit uses a high-performance 100MHz crystal oscillator with a phase noise of -172dBc / Hz@10kHz, and generates two reference clocks of 2.5GHz and 1GHz through frequency doubling by a harmonic generator. The 2.5GHz reference clock is interpolated into a 5GHz local oscillator through frequency doubling, and the 1GHz reference clock is used as the DDS clock / sampling clock of the DDS chip after filtering and amplification.
[0104] In the phase-locked reference circuit, the DDS chip uses the 1GHz signal generated by the clock reference circuit as the sampling clock, and generates a 75-100MHz clock reference signal through the direct digital synthesis method. After amplification and filtering, it is input into the phase detector U4 to provide a phase reference for the main loop.
[0105] like Figure 5The circuit diagram of a phase-locked main loop circuit is shown in the figure. The VCO uses an oscillator of model HMC480LP4E, and the phase detector model is ADF4002BCPZ. The main loop circuit is equipped with an interpolation loop filter. The 5.15-5.2GHz signal generated by the VCO is split into two paths, one for output, and the other for feedback to the interpolation mixer to mix with the 5GHz in-loop local oscillator to generate a 150-200MHz in-loop intermediate frequency signal. The in-loop intermediate frequency signal is phase-detected with the reference signal generated by the phase-locked reference circuit after the 75-100MHz generated by the internal two-frequency division of the phase detector chip. The error potential is generated by the charge pump, and then a stable voltage signal is generated through the loop filter and the preset circuit to complete the tuning of the VCO.
[0106] According to the loop interpolation scheme, the relevant parameters are calculated. The oscillation frequency of the phase detector is 150-200MHz, and its electrical adjustment sensitivity is consistent with the VCO oscillation frequency of 5.15-5.2GHz, both of which are 100MHz / V. That is, for the phase detector ADF4002, it is equivalent to using a 0-5V voltage to drive an oscillator with an electrical adjustment sensitivity of 100MHz / V and a frequency of 150-200MHz. It is obvious that the electrical adjustment voltage range multiplied by the electrical adjustment sensitivity far exceeds the equivalent oscillator frequency range. When the equivalent oscillator model is placed in ADIsimPLL for parameter simulation, an error will be reported due to parameter exceeding the limit, resulting in simulation failure.
[0107] Therefore, the present invention uses an analog switch to add a preset voltage to the loop filter, and the VCO electrical adjustment voltage can be preset near the corresponding frequency point in advance, and then switched to the loop filter, so that the loop can quickly capture and lock, avoiding the loss of lock and wrong lock problems caused by large-scale capture. When the design parameters are a loop bandwidth of 2MHz, a phase margin of 50°, and an electrical adjustment sensitivity of 100MHz / V, the VCO electrical adjustment sensitivity is divided by 4, that is, it is designed to be 25MHz / V for simulation, and the simulation value of each discrete component is obtained. After the simulation value is converted by 4 times according to the above method, the corresponding conversion value is obtained. It can be seen from Table 2 that the difference between the conversion value and the design value is small, and it can be regarded as equivalent.
[0108] Table 2 Third-order loop filter conversion table
[0109]
[0110]
[0111] After converting to the equivalent electrical adjustment sensitivity of 100MHz / V, the loop filter parameters are shown in Figure 6 As shown in the figure, the complete design of the interpolation phase-locked loop is completed, and the phase noise curve of the interpolation phase-locked loop obtained by simulation test is as follows Figure 7 As shown, the design index requirements are met.
[0112] The above is a derivation based on a second-order loop filter as an example. The conclusion is also applicable to third-order and fourth-order passive loop filters, which can realize fast secondary design of filters. When adjusting the loop filter bandwidth for secondary design, it is also possible to adjust all resistance and capacitance values in the loop filter according to the proportional law without repeated simulation calculations, while keeping other hardware parameters of the phase-locked loop unchanged, to complete the design.
[0113] The above shows and describes the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the above embodiments do not limit the present invention in any form, and any technical solution obtained by equivalent replacement or equivalent transformation falls within the protection scope of the present invention.
Claims
1. A fast design method for an interpolation phase-locked loop filter, characterized in that: The following steps are involved: S1. Design the hardware circuit of the phase-locked loop circuit and the loop filter, and set the structure of the loop filter and the loop bandwidth ω c and phase margin φ(ω), the phase-locked loop circuit comprising a reference source, an R divider, a phase detector, the loop filter, a voltage-controlled oscillator and an N divider; S2. Obtain relevant parameters in the phase-locked loop circuit, including: phase detector gain K PD , voltage controlled oscillator gain K VCO and the frequency division number N within the loop; S3, according to the relevant parameters in the phase-locked loop circuit and the parameters of the loop filter, determine the pole formula, zero formula, loop bandwidth formula and phase margin formula of the loop filter, calculate the values of all resistors and capacitors in the loop filter, that is, the capacitor design value and the resistor design value, and complete the primary design of the loop filter; S4. In the simulation software, design an equivalent circuit to the phase-locked loop circuit and set the voltage-controlled oscillator K VCO After changing to n times of the original value, a simulation test is performed to obtain the simulation values of each capacitor and resistor in the loop filter in the equivalent circuit; S5, changing each capacitance simulation value by 1 / n times and each resistance value by n times accordingly, to obtain corresponding capacitance conversion value and resistance conversion value; S6. Compare the capacitance conversion value and the resistance conversion value obtained in step S5 with the capacitance design value and the resistance design value determined in step S4 to verify whether the difference is within a preset range, thereby completing the secondary design of the loop filter.
2. The method for fast designing an interpolation phase-locked loop filter according to claim 1, characterized in that: The designed loop filter is any one of a second-order loop filter, a third-order loop filter or a fourth-order loop filter.
3. The method for fast designing an interpolation phase-locked loop filter according to claim 1, characterized in that: The designed loop filter is a second-order loop filter composed of a first capacitor C1, a second capacitor C2, a first resistor R1 and a third resistor R2; In step S3, the poles and zeros of the second-order loop filter are expressed as: T2=R2*C2 The phase margin is expressed as: φ(ω)=tan -1 (oh c *T2)-tan -1 (oh c *T1) The loop filter loop bandwidth is defined as:
4. The method for fast designing an interpolation phase-locked loop filter according to claim 1, characterized in that: The designed phase-locked loop circuit includes a clock reference source circuit, a phase-locked reference circuit and a phase-locked main loop circuit. The clock reference circuit includes a 100MHz crystal oscillator (OC1), a harmonic generator (U1), a first power divider (PV1), a first filter (F1), a first amplifier (AMP1), a third filter (F3), a second amplifier (AMP2), a doubler (U3) and a fourth filter (F4); The output end of the crystal oscillator (OC1) is connected to a harmonic generator, and the output end of the harmonic generator is connected to a first power divider (PV1) to generate a 2.5 GHz reference clock and a 1 GHz reference clock. The 2.5 GHz reference clock is input into a branch consisting of a third filter (F3), a second amplifier (AMP2), a doubler (U3) and a fourth filter (F4), and the doubled frequency generates an interpolated 5 GHz local oscillator; the 1 GHz reference clock is input into a branch consisting of a first filter (F1) and a first amplifier (AMP1).
5. The method for fast designing an interpolation phase-locked loop filter according to claim 4, characterized in that: The phase-locked reference circuit comprises a DDS chip (U2) and a second filter (F2), the output end of a first amplifier (AMP1) is connected to the input end of the DDS chip (U2), a 1 GHz reference clock is used as a sampling clock of the DDS chip after filtering and amplification, and the DDS chip (U2) uses a digital synthesis method to generate a 75-100 MHz clock reference signal.
6. The method for fast designing an interpolation phase-locked loop filter according to claim 5, characterized in that: The phase-locked main loop circuit sequentially connects a phase detector (U4), a first filter (F5), a single-pole double-throw switch (SW1), a VCO (U5), a second power divider (PV2), a third amplifier (AMP3), an attenuator (ATT1), a mixer (MIX1) and a sixth filter (F6) to form a loop structure, wherein the phase detector (U4) receives a 75-100 MHz clock reference signal output by a DDS chip (U2) to provide a phase reference for the main loop, and the VCO (U5) generates a 5.15-5.2 GHz signal, which is split into two paths by the second power divider (PV2), one path is output and the other path is used as a feedback signal.
7. The method for fast designing an interpolation phase-locked loop filter according to claim 6, characterized in that: The first filter (F1), the second filter (F2), the third filter (F3) and the fourth filter (F4) are band-pass filters, and the fifth filter (F5) and the sixth filter (F6) are low-pass filters.