A storage device testing system and a storage device testing method

Abstract

The present invention provides a test system and a test method for a storage device, which relates to the field of storage technology, and includes: a test board, which is used to communicate with a memory to be tested to configure corresponding test parameters; and a processor, which is used to communicate with the test board and is configured to: after writing message data to the memory to be tested, generate a plurality of information values ​​to be tested that have different read-write verification errors, and then write each of the information values ​​to be tested to a replay protection memory block in the memory to be tested in sequence, so as to perform a read-write test of each of the information values ​​to be tested to the memory to be tested, and obtain a test result. The test system and the test method for a storage device provided by the present invention can be applied to the development stage of the RPMB processing flow of memory firmware, and the system and firmware test stability and compatibility, and have the advantages of being simple and easy to operate, rich RPMB type configuration, and high test coverage.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a storage device testing system and a testing method thereof. Background Art

[0002] With the widespread application of eMMC (embedded memory standard specification) storage chips in terminal products such as TVs, set-top boxes, tablets or mobile phones, the performance and reliability requirements of eMMC storage chips are getting higher and higher. Among them, the most important thing is to ensure that the data stored in eMMC is stable and reliable. The eMMC storage chip is composed of an ARM CPU (ARM processor) as a controller and NAND Flash (a type of flash memory). The ARM CPU runs the controller software, which is usually called firmware. The main functions of the firmware are responsible for bad block management, GC (garbage collection), early warning, performance improvement and life of NAND Flash, and ensure the reliable use of NAND Flash. The firmware (Firmware) running in the eMMC internal master is crucial. The confidential information such as fingerprints, keys, network provider information, digital rights management and secure payment stored in the eMMC firmware needs to be protected in a dedicated storage area. Among them, the stress test of the eMMC firmware's ability to handle RPMB (Replay Protected Memory Block) is a must-do test verification for the storage chip manufacturer. The strength of the firmware's ability to handle RPMB is directly related to the security of the eMMC memory on the customer's product platform.

[0003] The existing verification of the RPMB processing method of memory firmware is mostly based on white box testing within the firmware, lacking professional and comprehensive testing. Usually, the conditions of the firmware white box test are single and not complex enough to cover the various attacks on the RPMB storage data of the memory in the actual use scenarios of customers. As a result, the internal verification of the firmware is insufficient, and when a large number of RPMB attack errors occur when the memory chip of the memory is applied on the customer platform, if the memory firmware is not processed in time, it will cause serious problems such as storage data corruption and inability to work normally. This is the impact that may occur due to the memory firmware's weak ability to handle RPMB. Summary of the invention

[0004] In view of the shortcomings of the prior art mentioned above, the purpose of the present invention is to provide a test system and a test method for a storage device, which are used to solve the problem that the self-test coverage of the RPMB processing flow inside the memory firmware in the prior art is insufficient, the complexity is single, and it cannot fully cover various attacks on the RPMB area Data (data) that may occur when the client uses the memory chip of the memory. If the memory firmware is not processed in time, the stored data will be damaged and cannot work normally.

[0005] To achieve the above-mentioned purpose and other related purposes, the present invention provides a test system for a storage device, comprising: a test board, which is used to communicate with a memory to be tested to configure corresponding test parameters; and a processor, which is used to communicate with the test board and is configured to: after writing message data to the memory to be tested, generate multiple information values ​​to be tested that have different read and write verification errors, and then write each information value to be tested in turn to a replay protection memory block in the memory to be tested to perform a read and write test of each information value to be tested to the memory to be tested, and obtain a test result; the processor is also configured to change the test parameters of the test board after the read and write test is completed, and re-perform the read and write test of each information value to be tested to the memory to be tested under the changed test parameters, until the read and write test of each information value to be tested to the memory to be tested under all test parameters is completed.

[0006] In one embodiment of the present invention, the processor is configured to: after writing the message data to the memory to be tested, generate a preset information value that completes the correct read and write verification, replay the read and write of the preset information value to protect the memory block, and test and compare it with the read and write of the information value to be tested to obtain the test result.

[0007] In one embodiment of the present invention, the processor is configured to: after generating the preset information value, change the values ​​of some fields in the data structure constituting the preset information value to generate the information value to be tested.

[0008] In one embodiment of the present invention, the processor is configured to: determine whether the read and write results of the information value to be tested and the preset information value are consistent when they are written into the replay protection memory block; if so, continue to complete the read and write tests on the remaining information values ​​to be tested, and after the read and write tests of all the information values ​​to be tested are completed, change the test parameters of the test board to continue the read and write tests; if not, determine whether the firmware of the memory to be tested correctly handles the processing flow of the replay protection memory block.

[0009] In one embodiment of the present invention, the processor is configured to: determine whether the response mechanism of the replay protection memory block correctly identifies the corresponding error test result based on the error test result when the read and write results are inconsistent; if so, determine that the memory firmware to be tested has correctly handled the processing flow of the replay protection memory block; if not, the memory firmware to be tested analyzes the cause of the error test result and modifies the processing flow of the replay protection memory block.

[0010] In one embodiment of the present invention, the processor is configured to: after writing at least two information values ​​to be tested into the replay protection memory block at the same time, perform a read and write test on the replay protection memory block in the memory to be tested.

[0011] In one embodiment of the present invention, the processor includes: an error handling module, which is used to generate an information value to be tested according to a preset information value, and write the preset information value and the information value to be tested into a replay protection memory block of the memory to be tested, respectively; and an error checking module, which is used to respectively receive the read and write results returned when the preset information value and the information value to be tested are written into the replay protection memory block, and determine whether the read and write results of the two are consistent. If so, continue to complete the read and write test of the remaining information values ​​to be tested, and after all the read and write tests of the information values ​​to be tested are completed, change the test parameters of the test board to continue the read and write test; if not, determine whether the firmware memory firmware correctly handles the processing flow of the replay protection memory block.

[0012] In one embodiment of the present invention, the processor is configured such that: the test parameters include one or more of the speed mode, bus length, voltage and temperature selected when configuring the test board.

[0013] In one embodiment of the present invention, the processor is configured to: select a corresponding system image file according to the type of the storage chip and burn it into the storage chip to build a corresponding test environment.

[0014] The present invention also provides a method for testing a storage device, comprising the following steps:

[0015] Connect the test board to the memory to be tested and configure the corresponding test parameters;

[0016] After writing the message data into the memory to be tested, it generates a plurality of information values ​​to be tested that have different read-write check errors, and sequentially writes the information values ​​to be tested into the replay protection memory blocks in the memory to be tested, so as to perform a read-write test of each information value to be tested into the memory to be tested, and obtain a test result;

[0017] After the read and write test is completed, the test parameters of the test board are changed, and the read and write test of each information value to be tested to the memory to be tested is performed again under the changed test parameters until the read and write test of each information value to be tested to the memory to be tested is completed under all test parameters.

[0018] Beneficial effects of the present invention: The present invention proposes a storage device test system and test method thereof, which solves the problem that the self-test coverage of the RPMB processing flow inside the memory firmware is insufficient, the complexity is single, and the various attacks on the RPMB area Data (data) that may occur when the client uses the memory chip cannot be fully covered. At the same time, it can improve the coverage test of the memory firmware RPMB processing capability, comprehensively capture the potential risks and defects in the firmware RPMB processing flow, improve the stability and compatibility of the memory firmware program, and enhance the wide use of the memory in various CPU (processor) manufacturers and various product lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 FIG. 1 is a schematic diagram of the structure of a test system for a storage device in a preferred embodiment of the present invention.

[0020] Figure 2 It is a schematic diagram of the internal architecture of data transmission during memory and processor test processing in a preferred embodiment of the present invention.

[0021] Figure 3 It is a schematic diagram of a UI (User Interface) in a preferred embodiment of the present invention.

[0022] Figure 4 Flow chart of the testing method of the present invention.

[0023] Figure 5 For the present invention Figure 4 Flowchart of steps S10, S20 and S30 in FIG.

[0024] Figure 6 For the present invention Figure 5 Flowchart of step S22 in FIG.

[0025] Component number description

[0026] Test board 1; processor 2; memory chip 3; power module 4; data transmission module 5; dynamic random access memory 6; UI interface 7; memory to be tested 10; flash memory module 11; replay protection memory block 111; error handling module 21; error checking module 22. DETAILED DESCRIPTION

[0027] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0028] See also Figure 1The present invention provides a test system for a storage device, which is highly flexible and compatible with storage chips of different capacities from different storage manufacturers, while supporting tests under high and low temperature and temperature cycling conditions. It can also be applied to the development stage of the processing flow of eMMC firmware for RPMB (replay protection memory block). The system and firmware test stability and compatibility, and have the advantages of simple and easy operation, rich RPMB type configuration, and high test coverage. The test system may include a test board 1, a processor (CPU) 2, a storage chip (SD) 3, a power module (Power) 4, a data transmission module (USB) 5, a dynamic random access memory (DRAM) 6, and a host.

[0029] See also Figure 1 In one embodiment of the present invention, the power module 4 can be used to supply power to the test board 1, the processor 2, and the dynamic random access memory 6. The processor 2 can be a central processing unit. The processor 2 can be communicatively connected to the test board 1, the memory chip 3, the data transmission module 5, and the dynamic random access memory 6. The dynamic random access memory 6 can be a memory, that is, an internal memory that directly exchanges data with the processor 2.

[0030] See also Figure 1 In one embodiment of the present invention, the processor 2 can communicate with the host through the data transmission module 5, and then upload the data to the UI interface 7 of the host and display it. When it is necessary to test the firmware RPMB processing capability of the memory 10 to be tested, the corresponding system image file (SOC Image) can be selected on the UI interface 7 of the host according to the type of the memory chip 3, and the system image file can be burned into the storage particles of the memory chip 3, so that the memory chip 3 can run the corresponding program, thereby completing the firmware RPMB processing capability test of the memory 10 to be tested.

[0031] See also Figure 1 In one embodiment of the present invention, different memory devices to be tested may be manufactured by different manufacturers and their models may not be consistent. Therefore, it is necessary to connect the memory device to be tested to an adapted test board 1 to complete the firmware RPMB processing capability test of the memory device to be tested 10. In this embodiment, the number of test boards 1 may be at least one (e.g. Figure 1As shown), each test board 1 can be communicatively connected to a memory to be tested on its communication interface. Therefore, the number of memories to be tested may also be at least one, and the number of memories to be tested does not exceed the number of test boards 1. In this embodiment, an example is given in which the number of test boards 1 is four (not shown) and the number of memories to be tested is four. The communication interfaces on the four test boards 1 can be represented as Socket1, Socket2, Socket3, and Socket4, respectively. The four memories to be tested can be represented as eMMC Vendor1, eMMC Vendor2, eMMC Vendor3, and eMMC Vendor4, respectively. By connecting multiple memories to be tested with multiple test boards 1, the firmware RPMB processing capability test of multiple memories to be tested 10 can be completed simultaneously.

[0032] See also Figure 1 to Figure 2 , the present invention provides a test system for a storage device. When testing the firmware RPMB processing capability of the memory 10 to be tested, the test board 1 is used to communicate with the memory 10 to be tested to configure the corresponding test parameters. That is to say, after the test board 1 is powered on, first confirm that the connection between it and the test board 1 is normal through the UI interface 7. Then, according to the MMC manufacturer and Density (the amount of binary information stored per unit length) in the Socket (test socket, used to place eMMC particles), the corresponding Speed, Bus Width, Voltage, and Temperature Configuration are selected to complete the configuration of the test environment.

[0033] In one embodiment of the present invention, the processor 2 is connected to the test board 1 in communication. The processor 2 is configured to generate a plurality of information values ​​to be tested that have different read / write check errors before writing the message data to the memory to be tested 10, and then write each information value to be tested to the replay protection memory block 111 in the memory to be tested 10 in sequence, so as to perform a read / write test of each information value to be tested to the memory to be tested 10, and obtain a test result.

[0034] In the present embodiment, after the test board 1 is powered on, a communication connection is established with the test board 1 through the processor 2 to perform a firmware RPMB processing capability test of the memory to be tested 10. Specifically, the information value to be tested is written into the memory to be tested 10 through the processor 2 to perform a read and write test, and then determine whether the information value to be tested can obtain a corresponding test result of a read and write verification error. The information value to be tested can be when the message data (message) is written into the replay protection memory block (RPMB) 111 of the memory to be tested 10, and the message data is processed by the setting of the processor 2 so that different information values ​​to be tested are generated, and the information value to be tested is written into the replay protection memory block 111 of the memory to be tested 10, thereby completing the read and write test of the memory to be tested 10, and determining whether the memory to be tested 10 has a test result corresponding to the read and write verification error in the processor 2.

[0035] In one embodiment of the present invention, the processor 2 is also configured to change the test parameters of the test board 1 after the read and write test is completed, and re-perform the read and write test of each information value to be tested to the memory to be tested 10 under the changed test parameters until the read and write test of each information value to be tested to the memory to be tested 10 is completed under all test parameters.

[0036] In this embodiment, the processor 2 writes each information value to be tested into the replay protection memory block 111 in the memory to be tested 10 in sequence, that is, performs a read and write test of each information value to be tested in the memory to be tested 10 in sequence, and then obtains the test / read and write results. And after completing the test of all information values ​​to be tested under the test parameters of the current test board 1, by changing the test parameters of the test board 1, each information value to be tested is rewritten into the replay protection memory block 111 in sequence, thereby performing a read and write test of each information value to be tested to the memory to be tested 10; repeat the operation until the change test of all test parameters of the test board 1 is completed. The test of all test configurations includes the test configuration of changing the test parameters of the test board 1, and the test configuration of performing a read and write test of the memory to be tested 1 using different information values ​​to be tested. Changing the test configuration of the test parameters of the test board 1 may include reselecting different Speed ​​(speed mode), Bus Width (bus length), Voltage (voltage), and Temperature Configuration (temperature configuration) according to the MMC manufacturer and Density (the amount of binary information stored in a unit length, or the capacity size), so that the eMMC product of different manufacturers and capacity sizes can be easily replaced.

[0037] See also Figure 2In one embodiment of the present invention, when using the information value to be tested to perform a read and write test on the memory to be tested, it is also necessary to set a preset information value that can complete the correct read and write verification, and write it into the memory to be tested 10 in the same way to perform the read and write test. Specifically, the processor 2 is configured to generate a preset information value that completes the correct read and write verification before writing the message data to the memory to be tested 10, read and write the preset information value to the replay protection memory block 111, and compare the preset information value with the information value to be tested in / on the read and write of the memory to be tested 10 to obtain the test result.

[0038] In the present embodiment, when writing message data to the memory to be tested 10, the processor 2 will also generate a preset information value corresponding to the information value to be tested according to the message data. That is to say, by writing the preset information value to the memory to be tested 10, it can complete the correct read and write verification when the memory to be tested 10 is read and written. Furthermore, when performing a read and write test, the preset information value and the information value to be tested are respectively read and written to the replay protection memory block 111 of the memory to be tested 10, and then the reading and writing of the two are tested and compared, so as to determine whether a read and write error occurs in the information value to be tested. When a read and write error is determined, a processing flow is implemented to further determine whether the firmware of the memory to be tested 10 correctly handles the replay protection memory block 111.

[0039] In one embodiment of the present invention, when generating the preset information value and the information value to be tested, for the convenience of processing, the preset information value may be generated first, and then, based on the preset information value, the preset information value may be adjusted to generate the information value to be tested. Specifically, the processor 2 is configured to: after generating the preset information value, change the values ​​of some fields in the data structure constituting the preset information value so as to generate the information value to be tested.

[0040] In one embodiment of the present invention, when the preset information value and the information value to be tested are read and written in the replay protection memory block 111 for test and comparison, the processor 2 is configured to: determine whether the read and write results of the information value to be tested and the preset information value are consistent when they are written into the replay protection memory block 111; if so, continue to complete the read and write test of the remaining information values ​​to be tested, and after all the read and write tests of the information values ​​to be tested are completed, change the test parameters of the test board 1 to continue the read and write test; if not, determine whether the firmware of the memory 10 to be tested correctly handles the processing flow of the replay protection memory block 111.

[0041] In the present embodiment, after the information value to be tested is written into the replay protection memory block 111 and the read-write result is obtained, it is compared with the read-write result obtained after the preset information value is written to determine whether the two are consistent. If the two are consistent, the read-write test of the remaining information values ​​to be tested is continued. If all the information values ​​to be tested are tested, the test parameters of the test board 1 are further changed to continue the read-write test, and the test is terminated after all the test configuration tests are completed. If, during the test comparison, the read-write result of the information value to be tested is inconsistent with the read-write result of the preset information value, it is further determined whether the firmware correctly handles the processing flow of the replay protection memory block 111 to further verify the hardware design of the entire flash memory module 11 and the stability and compatibility of the firmware program.

[0042] In one embodiment of the present invention, when the processor 2 determines that the test result obtained by the preset information value is inconsistent with the test result obtained by the test information value, it will determine that the test result obtained by the test information value is an erroneous test result. And through the erroneous test result, it is further judged whether the firmware correctly handles the processing flow of the replay protection memory block 111. Specifically, the processor 2 is configured to: according to the erroneous test result when the read and write results are inconsistent, judge whether the response mechanism of the replay protection memory block 111 correctly identifies the corresponding erroneous test result. If so, it is determined that the firmware of the memory 10 to be tested has correctly handled the processing flow of the replay protection memory block 111. If not, the firmware of the memory 10 to be tested analyzes the cause of the erroneous test result and modifies the processing flow of the replay protection memory block 111.

[0043] In this embodiment, when an error test result indicating inconsistent read and write results is obtained, the error test result needs to be further analyzed. By judging whether the response mechanism of the replay protection memory block 111 correctly identifies the corresponding error test result, it is determined whether the firmware correctly handles the processing flow of the replay protection memory block 111. In other words, when the response mechanism of the replay protection memory block 111 can correctly identify the corresponding error test result, it means that the firmware analysis has correctly handled the processing flow of the replay protection memory block 111. It means that there is an error in the received data, and the eMMC firmware processing flow can be entered and corresponding processing can be made. If the response mechanism of the replay protection memory block 111 cannot correctly identify the corresponding error test result, it means that the firmware analysis is wrong and the firmware has not detected the error. It means that the firmware has defects in the processing flow of the replay protection memory block 111, which can be solved by correcting the problem and updating the firmware.

[0044] See also Figure 2In a preferred embodiment, when data is transmitted in the replay protection memory block 111, the message data, that is, the Message, is transmitted between the memory to be tested 10 and the processor 2. When the Message is transmitted to the replay protection memory block 111, it is transmitted to the flash memory module 11 (eMMC Device) in the memory to be tested 10, and then the flash memory module 11 (eMMCDevice) encrypts the SHA-256 algorithm to generate a MAC (message authentication code) and stores it in the replay protection memory block 111. At this time, the counter generates the corresponding number of reads and writes. Then, the Message and MAC at the time of writing are returned to the processor 2 (eMMC Host). When the Message is written to the memory to be tested 10, the processor 2 will first generate a preset information value according to the Message, and perform normal read and write operations on the memory to be tested 10. Subsequently, the processor 2 generates the information value to be tested by changing the values ​​of some fields in its data architecture according to the previous preset information value, performs read and write operations on the memory to be tested 10, and returns the corresponding Message and MAC to the processor 2. After returning to processor 2, Message and MAC are decrypted by SHA-256 algorithm, and then tested and compared with Message and MAC obtained by the previous preset information value read and write operation to determine whether the read and write results of the two are consistent. If consistent, continue to complete the read and write test of the remaining information values ​​to be tested. After the reading and writing of the remaining information values ​​to be tested are completed, reset the test parameters of the test board 1, and re-perform the read and write test of writing each information value to be tested into the memory to be tested 10. If inconsistent, further determine whether the firmware of the memory to be tested 10 correctly handles the processing flow of the replay protection memory block 111. That is to say, when the error test result of the inconsistent read and write result is output when the information value to be tested is written compared with the normal test result obtained by the preset information value, the corresponding error test result is correctly identified by further determining whether the response mechanism of the replay protection memory block 111. And when it has been correctly identified, it means that the firmware has correctly processed the processing flow of the replay protection memory block 111 during analysis. If it is not correctly identified, it means that the firmware analysis is wrong. The cause of the erroneous test result is analyzed by the firmware, and the processing flow of the replay protection memory block 111 is modified.

[0045] In one embodiment of the present invention, when writing the information value to be tested to the memory to be tested 10, in order to increase the complexity of the test, a plurality of different information values ​​to be tested can also be written to the memory to be tested 10 at the same time for simultaneous testing. Specifically, the processor 2 is configured to: after writing at least two information values ​​to be tested to the replay protection memory block 111 at the same time, perform a read and write test on the replay protection memory block 111 in the memory to be tested 10. Through the read and write test in the above manner, the test coverage can be further improved to fully verify the potential risks and defects that may occur in the eMMc firmware processing RPMB process, thereby improving the stability and compatibility of the firmware.

[0046] See also Figure 2 In one embodiment of the present invention, the processor 2 includes: an error handling module 21 and an error checking module 22. The error handling module 21 is used to generate an information value to be tested according to a preset information value, and write the preset information value and the information value to be tested into the replay protection memory block 111 of the memory to be tested 10 respectively. The error checking module 22 is used to receive the read and write results returned when the preset information value and the information value to be tested are written into the replay protection memory block 111 respectively, and judge whether the read and write results of the two are consistent. If so, continue to complete the read and write test of the remaining information values ​​to be tested, and after the read and write test of all the information values ​​to be tested is completed, change the test parameters of the test board 1 to continue the read and write test. If not, judge whether the firmware of the memory to be tested 10 correctly handles the processing flow of the replay protection memory block 111.

[0047] In this embodiment, the processor 2 modifies the value of any field of the preset information value through the error processing module 21 (Error Process Module) to obtain the information value to be tested. And the preset information value and the information value to be tested are respectively written into the replay protection memory block 111 of the memory to be tested 10 to perform a read and write test. When the memory to be tested 10 returns the read and write results, the error checking module 22 receives the read and write results corresponding to the preset information value and the information value to be tested respectively. And it is judged whether the read and write results of the two are consistent. If they are consistent, the read and write tests of other generated information values ​​to be tested are continued. And after all the information values ​​to be tested are read and written, the test parameters of the test board 1 are adjusted, and the read and write tests of the information to be tested are continued. When the two are inconsistent, the corresponding error test results when the inconsistency occurs are output, and by judging whether the response mechanism of the replay protection memory block 111 correctly identifies the corresponding error test results, it is further judged whether the firmware correctly handles the processing flow of the replay protection memory block 111.

[0048] In one embodiment of the present invention, the processor 2 is configured as follows: the test parameters include one or more of the speed mode, bus length, voltage and temperature selected when configuring the test board 1. According to the MMC manufacturer and Density (the amount of binary information stored in a unit length, or the capacity) in the Socket (test socket), different Speed, Bus Width, Voltage, and Temperature Configuration are selected, so that eMMC products of different manufacturers and capacity sizes can be easily replaced.

[0049] In one embodiment of the present invention, the processor 2 is configured to: select the corresponding system image file according to the type of the storage chip 3 and burn it into the storage chip 3 to build a corresponding test environment. In this embodiment, the processor 2 can be connected to the host through the data transmission module 5, and then the data can be uploaded to the UI interface 7 of the host and displayed. When it is necessary to test the firmware RPMB processing capability of the memory 10 to be tested, the corresponding system image file (SOC Image) can be selected on the UI interface 7 of the host according to the type of the storage chip 3, and the system image file can be burned into the storage particles of the storage chip 3, so that the storage chip 3 can run the corresponding program, thereby completing the firmware RPMB processing capability test of the memory 10 to be tested.

[0050] Table 1: The overall data structure of a Message.

[0051]

[0052] Please refer to Table 1 for a preferred embodiment, which is a Message data structure sent as a whole. RPMB DataFrame (data frame) is a 512-Byte overall data structure, including 1-bit Start (the starting address of a program or process in memory), 196-Byte StuffBytes (memory space that cannot be used), 32-Byte (256b) Key / (MAC) ((key / message authentication code)), 256-Byte Data (data), 16-Byte Nonce (random value), 4-Byte WriteCounter (write counter), 2-Byte Address (storage unit number), 2-Byte Block Count (total number of blocks on the hard disk partition), 2-Byte Result (result), 2-Byte Req / Resp (Request request, Response response), 2-Byte CRC16 (encoding method for detecting errors in digital data) and 1-bit End (end of program or code segment). Each field has different definitions. The Error Process Module can change the values ​​of different fields sent according to the needs. The purpose is to make the eMMC Device RPMB (replay protection memory block 111 of flash memory module 11) perform SHA256 calculation after receiving the Message and MAC. If a verification error is found, a specific Fail Mode should be returned to the SOC Host (host of the system-on-chip (SOC, System on a Chip)). This verifies the stability and compatibility of the hardware design and firmware program of the entire eMMC RPMB.

[0053] Table 2: Error Handle Case of RPMB operation results.

[0054]

[0055] Please refer to Table 2, which specifically shows the types of Failures that may be encountered during the entire RPMB data transmission process. The corresponding Operation Result includes error code 0x0000 (0x0080)* indicating Operation OK, error code 0x0001 (0x0081) indicating General failure, error code 0x0002 (0x00827 indicating Authentication failure (MAC comparison not matching, MAC calculation failure), error code 0x0003 (0x0083) indicating Counter failure (counters not matching in comparison, counter incrementing failure), error code 0x0004 (0x0084) indicating Address failure (address out of range, wrong address alignment), error code 0x0005 (0x0085) indicating Write failure (data / counter / result write 0x0006 (0x0086) indicates a Read failure (data / counter / result readfailure), and error code 0x0007** indicates an Authentication Key not yet programmed.

[0056] See also Figure 3A preferred embodiment is provided as the host UI interface 7, that is, the PC-side UI RPMB Generate (generate management interface). Among them, Image (memory image) is used as the software running on the RPMB generation sub-board. Configuration (configuration) is the configuration of the test system. Voltage (voltage) / Speed ​​(speed mode) / Clock (clock signal) / Bus Width (bus length) / CMD (instruction) / DATA (data) are the conditions for the entire RPMB to trigger. WriteMethod (write method) can be configured to insert different error messages into the eMMC Device. Info Output Window (a window that displays and records output information during program execution) will output the information status of the entire test.

[0057] It can be seen that the above solution can solve the problems of insufficient memory firmware RPMB processing capability testing, low coverage, and limited manufacturing RPMB test types. At the same time, it can fully verify the potential risks and defects that may exist in the memory firmware processing RPMB process, and improve the stability and compatibility of the firmware.

[0058] like Figure 4 As shown, the present invention also provides a method for testing a storage device, comprising the following steps:

[0059] Step S10, connecting the test board 1 to the memory to be tested 10, and configuring corresponding test parameters;

[0060] Step S20, before writing the message data into the memory under test 10, generate a plurality of information values ​​under test that have different read-write check errors, and sequentially write the information values ​​under test into the replay protection memory block 11 in the memory under test 10, so as to perform a read-write test of each information value under test to the memory under test 10, and obtain a test result;

[0061] Step S30, after the read and write test is completed, change the test parameters of the test board 1, and re-perform the read and write test of each information value to be tested to the memory 10 under the changed test parameters until the read and write test of each information value to be tested to the memory 10 under all test parameters is completed.

[0062] See also Figure 5 In one embodiment of the present invention, when executing step S10, specifically, step S10 may include the following steps:

[0063] Step S11, the RPMB generation control device starts to power on.

[0064] Step S12: The PC is connected to the RPMB generation control device daughter board via a USB cable.

[0065] Step S13, open PC RPMB Generate UI, select Image option to burn RPMB daughter board SOC Image (system-on-chip image file) via USB cable.

[0066] Step S14, the RPMB daughter board is powered on and runs, and the PC UI (host management interface) confirms that the connection with the RPMB daughter board is normal.

[0067] Step S15: Select different Speed / BusWidth / Voltage / Temperature Configurations according to the eMMC manufacturer and Density in the Socket.

[0068] When executing step S20, specifically, step S20 may include the following steps:

[0069] Step S21, set and generate normal operation Message and MAC value, and perform RPMB read and write operations.

[0070] Step S22, set the operation Message and MAC value that generated the exception, and perform RPMB read and write operations.

[0071] Step S23, the RPMB generation sub-board generates different functional test applications according to the configuration settings of the PC-UI RPMB, and performs a large number of RPMB read and write operations.

[0072] Step S24: Determine whether the Error Handle Check verifies whether the received Message and MAC are correct.

[0073] Step S25: If the Error Handle Check verifies that the received Message and MAC are correct, determine whether the processing configuration of the Error Process Module is completed.

[0074] Step S26: If the processing configuration of the Error Process Module is not completed, return to the previous round of Error Process Module configuration file to continue execution.

[0075] Step S27: If the received Message and MAC verified by Error Handle Check are incorrect, determine whether eMMCDevice RPMB RESP (the response mechanism of Replay Protected Memory Block (RPMB) in the eMMC device) correctly identifies the corresponding Operation Result.

[0076] Step S28: If the eMMC Device RPMB RESP correctly identifies the corresponding Operation Result, the firmware has correctly processed the RPMB processing flow.

[0077] Step S29: If the eMMC Device RPMB RESP does not correctly identify the corresponding Operation Result, the firmware analyzes the cause of the error and modifies the RPMB processing flow.

[0078] See also Figure 6 When executing step S22, specifically, step S22 may include the following steps:

[0079] Step S221, set and generate a General failure value, and perform RPMB read and write operations.

[0080] Step S222: Set and generate an Authentication failure (MAC comparison not matching, MAC calculation failure) value, and perform RPMB read and write operations.

[0081] Step S223, set and generate a Counter failure (counters not matching incomparison, counter incrementing failure) value, and perform RPMB read and write operations (counter failure (counters do not match in comparison, counter incrementing failure)).

[0082] Step S224, set and generate the Address failure (address out of range, wrong addressalignment) value, and perform RPMB read and write operations (address error (address out of range, address alignment problem)).

[0083] Step S225, set and generate the Write failure (data / counter / result write failure) value, and perform the RPMB read and write operation (write failure (data, counter, result write failure)).

[0084] Step S226, setting and generating the Read failure (data / counter / result read failure) value, and performing the RPMB read and write operation (read failure (data, counter, result read failure)).

[0085] Step S227, set and generate the Authentication Key not yet programmed value, and perform RPMB read and write operations (the authentication key has not yet been programmed).

[0086] When executing step S30, specifically, step S30 may include the following steps:

[0087] Step S31: If the processing configuration of the Error Process Module is completed, return to the RPMB PC-UI Configuration (RPMB PC-side configuration interface) configuration file to continue execution.

[0088] Step S32: After all test configurations are tested, the entire RPMB test verification is completed.

[0089] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A storage device testing system, characterized in that: include: A test board, used to communicate with the memory to be tested to configure corresponding test parameters; as well as A processor, which is used to communicate with the test board and is configured to: after writing the message data to the memory to be tested, generate a preset information value that completes the correct read and write verification, generate a plurality of information values ​​to be tested that have different read and write verification errors according to the preset information value, and then write the preset information value and the information value to be tested into the replay protection memory block of the memory to be tested respectively, so as to perform a read and write test of the preset information value and each of the information values ​​to be tested to the memory to be tested, obtain the read and write results returned when the preset information value and the information value to be tested are written into the replay protection memory block, and determine whether the read and write results of the two are consistent, if so, continue to complete the read and write test of the remaining information values ​​to be tested, and after the read and write test of all the information values ​​to be tested is completed, change the test environment of the test board to continue the read and write test; if not, determine whether the firmware of the memory to be tested correctly handles the processing flow of the replay protection memory block; The processor is also configured to change the test parameters of the test board after the read and write test is completed, and re-perform the read and write test of each information value to be tested to the memory to be tested under the changed test parameters until the read and write test of each information value to be tested to the memory to be tested is completed under all test parameters.

2. The storage device testing system according to claim 1, wherein: The processor is configured to: after generating the preset information value, change the values ​​of some fields in the data structure constituting the preset information value so as to generate the information value to be tested.

3. The storage device testing system according to claim 1, wherein: The processor is configured to: determine whether the response mechanism of the replay protection memory block correctly identifies the corresponding error test result based on the error test result when the read and write results are inconsistent; if so, determine that the memory firmware to be tested has correctly handled the processing flow of the replay protection memory block; if not, the memory firmware to be tested analyzes the cause of the error test result and modifies the processing flow of the replay protection memory block.

4. The storage device testing system according to claim 1, wherein: The processor is configured to: after writing at least two of the information values ​​to be tested into the replay protection memory block at the same time, perform a read and write test on the replay protection memory block in the memory to be tested.

5. The storage device testing system according to claim 1, wherein: The processor is configured such that: the test parameters include one or more of a speed mode, a bus length, a voltage and a temperature selected when configuring the test board.

6. The storage device testing system according to claim 1, wherein: The processor is configured to: select a corresponding system image file according to the type of the storage chip and burn it into the storage chip to build a corresponding test environment.

7. A test method for a test system of a storage device according to any one of claims 1 to 6, characterized in that: The steps include: Connect the test board to the memory to be tested and configure the corresponding test parameters; After writing the message data into the memory to be tested, it generates a plurality of information values ​​to be tested that have different read-write check errors, and sequentially writes the information values ​​to be tested into the replay protection memory blocks in the memory to be tested, so as to perform a read-write test of each information value to be tested to the memory to be tested, and obtain a test result; After the read and write test is completed, the test parameters of the test board are changed, and the read and write test of each information value to be tested to the memory to be tested is re-performed under the changed test parameters until the read and write test of each information value to be tested to the memory to be tested is completed under all test parameters.

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