Test structure and test method of one-time programmable device

Abstract

The invention discloses a test structure and a test method of a one-time programmable device. The test structure comprises a semiconductor substrate; a plurality of memory cells, each memory cell comprising an active region formed in the semiconductor substrate, and a floating gate and a control gate formed on the semiconductor substrate, the active region extending along a first direction, and the floating gate and the control gate extending along a second direction; the floating gate and the control gate respectively stretch across the plurality of active regions so as to be connected with the plurality of storage units; the first contact hole is electrically connected with the floating gate and is used for applying external voltage to the floating gate; the second contact hole is electrically connected with the control gate and is used for applying external voltage to the control gate; and the third contact hole is electrically connected with the active region and is used for applying external voltage to the active region. The floating gate crosses the plurality of active regions and is led out through the first contact hole, so that the external voltage is applied to the floating gate through the first contact hole, the electrical performance of the OTP device can be tested, and the failure analysis of electric leakage can be realized.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a test structure and a test method for a one-time programmable device. Background Art

[0002] One Time Programmable (OTP) devices are a commonly used non-volatile memory that is compatible with standard complementary metal oxide semiconductor (CMOS) processes and has the advantages of low cost and small area.

[0003] In the field of semiconductor manufacturing, OTP failure is a common failure type. The OTP test structure used in the commonly used wafer acceptance test (WAT) is the same as the actual OTP structure, which can only simply test the read and write performance of the storage unit, and cannot fully monitor the parameters of each structure and perform failure analysis. Summary of the invention

[0004] A series of simplified concepts are introduced in the Summary of the Invention, which will be further described in detail in the Detailed Description of the Invention. The Summary of the Invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0005] In view of the existing problems, an embodiment of the present invention provides a test structure of a one-time programmable device, wherein the test structure of the one-time programmable device comprises: A semiconductor substrate having a plurality of active regions formed therein, the plurality of active regions extending along a first direction; A plurality of memory cells, each of the memory cells comprising an active region formed in the semiconductor substrate, and a floating gate and a control gate formed on the semiconductor substrate, the active region extending along a first direction, and the floating gate and the control gate extending along a second direction; the floating gate and the control gate respectively span across the plurality of active regions to connect the plurality of memory cells; a first contact hole, electrically connected to the floating gate, and used to apply an external voltage to the floating gate; a second contact hole, electrically connected to the control gate, for applying an external voltage to the control gate; and The third contact hole is electrically connected to the active area and is used to apply an external voltage to the active area.

[0006] In some embodiments, the first contact hole is located at an end of the floating gate, and / or the first contact hole is located between the plurality of active regions.

[0007] In some embodiments, the second contact hole is located at an end of the control gate, and / or the second contact hole is located between the plurality of active regions.

[0008] In some embodiments, the third contact hole is disposed on each of the plurality of active regions spanned by the floating gate.

[0009] In some embodiments, a gate dielectric layer is formed between the floating gate and the semiconductor substrate, and the gate dielectric layers corresponding to at least two floating gates are different.

[0010] In some embodiments, at least two of the active regions have different widths, and / or at least two of the floating gates have different widths.

[0011] In some embodiments, the test structure is disposed in a scribe line of a wafer.

[0012] In some embodiments, the one-time programmable device is a series transistor type one-time programmable device.

[0013] Another aspect of an embodiment of the present invention provides a method for testing a one-time programmable device. The method tests the one-time programmable device based on the test structure as described above.

[0014] In some embodiments, testing the one-time programmable device includes testing electrical performance of the one-time programmable device and performing leakage-related failure analysis.

[0015] According to the test structure of the one-time programmable device provided by the present invention, the floating gates of multiple storage cells are connected together and brought out through contact holes, and external voltages are applied to the floating gates through the contact holes, so that more parameters can be obtained in the test. The failure position can be quickly located during failure analysis, saving analysis costs and providing a reference for timely improvement. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The following drawings of the present invention are used to understand the present invention as part of the present invention. The embodiments of the present invention are shown in the drawings and the description thereof is used to explain the principle of the present invention.

[0017] In the attached figure: Figure 1 A schematic diagram showing common failure locations of OTP devices; Figure 2 A top view of a test structure of a one-time programmable device in the related art is shown; Figure 3 A cross-sectional view of a test structure of a one-time programmable device in the related art is shown; Figure 4 A top view of a test structure of a one-time programmable device according to an embodiment of the present invention is shown; Figure 5 A cross-sectional view showing a test structure of a one-time programmable device according to an embodiment of the present invention; Figure 6 A top view of a test structure of a one-time programmable device according to another embodiment of the present invention is shown. DETAILED DESCRIPTION

[0018] In the following description, a large number of specific details are provided to provide a more thorough understanding of the present invention. However, it is apparent to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features well known in the art are not described.

[0019] It should be understood that the present invention can be implemented in different forms and should not be construed as being limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and fully convey the scope of the present invention to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals throughout represent the same elements.

[0020] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0021] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0022] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0023] See also Figure 1 The failure of OTP devices is usually due to abnormalities in the metal silicide barrier layer (SAB) overlay (OVL), abnormalities in the spacer or metal silicide, or abnormalities in the gate dielectric layer (GOX), which leads to floating gate leakage and thus causes data storage failure.

[0024] like Figure 2 and Figure 3 As shown, the OTP test structure used in the currently known WAT is the same as the actual OTP structure, that is, a plurality of active regions 101 are formed in the semiconductor substrate 100, a plurality of memory cells are formed on the active region 101, the floating gates 102 of the memory cells are independent of each other and are not connected to the contact holes, only a control gate contact hole 104 is provided on the control gate 103 and an active region contact hole 105 is provided on the active region 101, and the active region contact hole only connects a middle memory cell (for example Figure 2 The memory cell shown in the dotted box in the middle is led out, and the surroundings are all dummy patterns. This test structure can only simply test the read and write performance of the memory cell, and cannot fully monitor the parameters of each structure and perform failure analysis.

[0025] In view of the above problems, an embodiment of the present invention provides a test structure of a one-time programmable device. Figure 4 and Figure 5 The test structure of the embodiment of the present invention is described in detail. Figure 4 A top view of a test structure of a one-time programmable device according to a specific embodiment of the present invention is shown. Figure 5 A cross-sectional view of a test structure of a one-time programmable device according to a specific embodiment of the present invention is shown.

[0026] Specifically, Figure 4 , Figure 5 As shown, the test structure of the one-time programmable device of the embodiment of the present invention includes: a semiconductor substrate 400; a plurality of memory cells, each memory cell includes an active area formed in the semiconductor substrate 400, and a floating gate 402 and a control gate 403 formed on the semiconductor substrate 400, the active area 401 extends along a first direction, and the floating gate 402 and the control gate 403 extend along a second direction; the floating gate 402 and the control gate 403 respectively span across the plurality of active areas 401 to connect the plurality of memory cells; a first contact hole 404, electrically connected to the floating gate 402, for applying an external voltage to the floating gate 402; a second contact hole 405, electrically connected to the control gate 403, for applying an external voltage to the control gate; and a third contact hole 406, electrically connected to the active area 401, for applying an external voltage to the active area 401.

[0027] The material of the semiconductor substrate 400 may include at least one of the following: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs or other III / V compound semiconductors, or the semiconductor substrate 400 may also include silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) or germanium on insulator (GeOI), etc. Although several examples of materials that can form the semiconductor substrate 400 are described herein, any material that can be used as the semiconductor substrate 400 falls within the spirit and scope of the present invention.

[0028] A plurality of active regions 401 are formed in the semiconductor substrate 400, and the plurality of active regions extend along a first direction. The active regions 401 may be formed by ion implantation into the semiconductor substrate 400. Figure 4 In the example of FIG. 4 , the plurality of active regions 401 are arranged at intervals from each other and extend in the longitudinal direction; the active regions 401 may be isolated by a shallow trench isolation (STI) structure.

[0029] A plurality of floating gates 402 and a plurality of control gates 403 are formed on the semiconductor substrate 400. The floating gates 402 and the control gates 403 extend along a second direction. Exemplarily, the second direction is perpendicular to the first direction. Figure 5 As shown, an active region 401 and a floating gate 402 and a control gate 403 formed above the active region 401 constitute a memory cell.

[0030] Specifically, the types of OTP devices include coupling capacitor type, series transistor type and dielectric breakdown type, etc. The test structure of the embodiment of the present invention is used to test the series transistor type OTP device. The series transistor type OTP device includes a plurality of storage cells, each of which includes two transistors connected in series, one of which is a control transistor and the other is a read transistor. Among them, the control transistor includes a control gate, the control gate is connected to the control gate contact hole, and a programming voltage is applied to the control gate through the control gate contact hole; the read transistor includes a floating gate, and the programming voltage on the control transistor is coupled to the floating gate, and then the floating gate is charged. Based on the hot carrier injection effect, the threshold voltage on the read transistor will change significantly, so as to achieve the purpose of changing the on and off state of the read transistor, thereby realizing data storage.

[0031] As mentioned above, the test structure of the previous OTP device is the same as the actual OTP device mentioned above, that is, the floating gates of each storage unit are independent of each other and no contact holes are set. Figure 4 The floating gate 402 of the embodiment of the present invention is connected to multiple active areas 401, and a first contact hole 404 is set on the floating gate 402. An external voltage is applied to the floating gate 402 through the first contact hole 404, so that more parameters (such as the threshold voltage Vt of the floating gate, leakage current leakage, etc.) can be obtained in the WAT test. During failure analysis, the failure position can be quickly located, which saves analysis costs and provides a reference for timely improvement.

[0032] In one example, the first contact hole 404 may be disposed at the end of the floating gate 402 (ie, Figure 4 The first contact hole 404 is located at the leftmost side of the floating gate 402 in the floating gate 402, thereby testing multiple read transistors connected to the floating gate 402. In another example, the first contact hole 404 can also be located between multiple active areas 401 connected to the floating gate 402, and can be specifically set above the shallow trench isolation structure between two adjacent active areas 401. The position of the first contact hole 404 can be set according to the length of the floating gate 402. If the floating gate 402 is longer, the voltage drop is larger. In this case, multiple first contact holes 404 can be set to make the voltage drop more balanced.

[0033] A second contact hole 405 is provided on the control gate 403 for applying an external voltage to the control gate 403. Similar to the floating gate 402, the second contact hole 405 can be provided at the end of the control gate 403 (i.e. Figure 4 The second contact hole 405 is located at the leftmost side of the control gate 403 in the middle of the control gate 403, thereby testing multiple control transistors connected to the control gate 403. Alternatively, the second contact hole 405 can also be located between multiple active areas 401 connected to the control gate 403, and can be specifically arranged above the shallow trench isolation structure between two adjacent active areas 401. The position of the second contact hole 405 can be set according to the length of the control gate 403. If the control gate 403 is longer, the voltage drop is larger. In this case, multiple second contact holes 405 can be arranged to make the voltage drop more balanced.

[0034] A third contact hole 406 is disposed on the active region 401, and a third contact hole 406 is disposed on each of the plurality of active regions 401 spanned by the floating gate 402. Figure 2 In the test structure shown, since each floating gate 402 is independent of each other, and WAT cannot choose to test only one memory cell, an active region contact hole 105 is only provided on the middle memory cell, and only this memory cell can be tested. In contrast, the embodiment of the present invention connects multiple memory cells through the floating gate 402, so that the third contact hole 406 can be provided on each of the multiple memory cells, and the multiple memory cells can be tested simultaneously.

[0035] For example, the test structure of the embodiment of the present invention may be disposed in a cutting path of a wafer, and the test structure may be removed when the wafer is cut, without affecting the OTP device actually used.

[0036] By way of example, the floating gate 402 and the control gate 403 may be made of polysilicon material, or may be formed using metal, metal nitride, metal silicide or similar compounds.

[0037] In some embodiments, a gate dielectric layer (not shown) is further formed between the floating gate 402, the control gate 403 and the semiconductor substrate 400. By way of example, the gate dielectric layer may include a conventional dielectric material such as silicon oxide. Alternatively, the gate dielectric layer may include a dielectric material with a relatively high dielectric constant, such as hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate, and lead zirconate titanate.

[0038] See also Figure 6 In one embodiment, at least two active regions 401 have different widths. Since a third contact hole 406 is provided on each active region 401 in the embodiment of the present invention, OTP devices with different channel widths can be tested by providing active regions 401 with different widths. Figure 6In the example, there are at least two floating gates 402 with different widths. Since the first contact hole 404 is provided on the floating gate 402 in the embodiment of the present invention, the OPT devices with different channel lengths can be tested by providing floating gates 402 with different widths.

[0039] Since one of the reasons for floating gate failure is abnormal gate dielectric layer, in one embodiment, at least two floating gates 402 have different gate dielectric layers corresponding to them, so as to test the leakage of different gate dielectric layers. Different gate dielectric layers may include different gate dielectric layer thicknesses and / or different gate dielectric layer materials.

[0040] Therefore, by setting different active area widths, floating gate widths or gate dielectric layers, monitoring and / or testing of OTP devices of multiple sizes can be achieved based on the same test structure.

[0041] Exemplarily, spacers are formed on both sides of the floating gate 402 and the control gate 403. The spacers are used to protect the sidewalls of the floating gate 402 and the control gate 403 to prevent them from being damaged during the etching process.

[0042] Exemplarily, a metal silicide layer (silicide) and a metal silicide blocking layer (SAB) are also formed on the floating gate 402 and the control gate 403, the first contact hole 404, the second contact hole 405 and the third contact hole 406 are formed on the metal silicide, and the metal silicide blocking layer is formed in the area where the metal silicide is not formed.

[0043] Specifically, when the first contact hole 404, the second contact hole 405, and the third contact hole 406 are formed by the self-aligned metal silicide (Salicide) process, a metal silicide barrier layer (SAB) can be formed using a material that does not react with metal to cover the area where the metal silicide does not need to be formed. Since the metal can react with silicon but not with the metal silicide barrier layer, the metal will only react with the exposed surface of the semiconductor substrate 400 or the surface of the floating gate 402 and the control gate 403 to form a metal silicide, and the first contact hole 404, the second contact hole 405, and the third contact hole 406 can be formed on the metal silicide subsequently.

[0044] Exemplarily, an interlayer dielectric layer (not shown) is also formed on the semiconductor substrate 400, and the first contact hole 404, the second contact hole 405 and the third contact hole 406 are formed in the interlayer dielectric layer. Exemplarily, the material of the interlayer dielectric layer can be an insulating material such as silicon dioxide, fluorocarbon, carbon-doped silicon oxide, or silicon carbonitride. The interlayer dielectric layer can be formed by various deposition methods commonly used in the art, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD) or atomic layer deposition (ALD). Exemplarily, the interlayer dielectric layer can be etched to form a first contact hole 404 connected to the floating gate 402, a second contact hole 405 connected to the control gate 403 and a third contact hole 406 connected to the active area 401, and a conductive material is filled therein, and the conductive material can include one or more of Ag, Au, Cu, Pd, Cr, Mo, Ti, Ta, W and Al.

[0045] According to the test structure of the one-time programmable device provided by the embodiment of the present invention, the floating gates of multiple storage cells are connected together and led out through contact holes. External voltage is applied to the floating gates through the contact holes, so that more parameters can be obtained in the test. The failure position can be quickly located during failure analysis, saving analysis costs and providing a reference for timely improvement. Based on the test structure of the embodiment of the present invention, at 50*50um 2 The area can hold storage units ranging from 1 bit to 2k.

[0046] The second aspect of the present invention also provides a method for testing a one-time programmable device. The method tests the one-time programmable device based on the test structure described above.

[0047] In some embodiments, testing the one-time programmable device includes: testing the electrical performance of the one-time programmable device and performing leakage-related failure analysis. Based on the conventional test structure, only the read and write performance of the storage unit can be simply tested. Based on the above test structure, the embodiment of the present invention can obtain more OTP-related parameters (such as the threshold voltage Vt of FG, leakage current leakage, etc.) in the WAT test, and the failure position can be quickly located when performing failure analysis on the OTP, saving costs.

[0048] The present invention has been described by the above embodiments, but it should be understood that the above embodiments are only for the purpose of example and description, and are not intended to limit the present invention to the scope of the described embodiments. In addition, it can be understood by those skilled in the art that the present invention is not limited to the above embodiments, and more variations and modifications can be made according to the teachings of the present invention, and these variations and modifications all fall within the scope of the protection claimed by the present invention. The protection scope of the present invention is defined by the attached claims and their equivalents.

Claims

1. A test structure for a one-time programmable device, characterized in that: The test structure includes: Semiconductor substrate, A plurality of memory cells, each of the memory cells comprising an active region formed in the semiconductor substrate, and a floating gate and a control gate formed on the semiconductor substrate, the active region extending along a first direction, and the floating gate and the control gate extending along a second direction; the floating gate and the control gate respectively span across the plurality of active regions to connect the plurality of memory cells; a first contact hole, electrically connected to the floating gate, and used to apply an external voltage to the floating gate; a second contact hole, electrically connected to the control gate, for applying an external voltage to the control gate; and The third contact hole is electrically connected to the active area and is used to apply an external voltage to the active area.

2. The test structure according to claim 1, characterized in that The first contact hole is located at an end of the floating gate, and / or the first contact hole is located between the plurality of active regions.

3. The test structure according to claim 1, characterized in that: The second contact hole is located at an end of the control gate, and / or the second contact hole is located between the plurality of active regions.

4. The test structure according to claim 1, characterized in that: The third contact hole is disposed on each of the plurality of active regions spanned by the floating gate.

5. The test structure according to claim 1, characterized in that: A gate dielectric layer is formed between the floating gate and the semiconductor substrate, and the gate dielectric layers corresponding to at least two floating gates are different.

6. The test structure according to claim 1, characterized in that: At least two of the active regions have different widths, and / or at least two of the floating gates have different widths.

7. The test structure according to claim 1, characterized in that: The test structure is arranged in a dicing street of a wafer.

8. The test structure according to claim 1, characterized in that: The one-time programmable device is a series transistor type one-time programmable device.

9. A method for testing a one-time programmable device, characterized in that: The testing method tests a one-time programmable device based on the testing structure according to any one of claims 1 to 8.

10. The testing method according to claim 9, characterized in that: Testing the one-time programmable device includes: testing the electrical performance of the one-time programmable device and performing failure analysis related to leakage.

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