Manufacturing method of semiconductor structure
By mounting multiple structures to be wired on the same carrier board in semiconductor packaging technology and forming a rewiring layer on the side facing away from the carrier board, the problems of low chip mounting accuracy and poor quality of the plastic sealing layer in the prior art are solved, and a more efficient manufacturing process and lower manufacturing cost are achieved.
Patent Information
- Application Number
- CN202311114812.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-08-30
- Publication Date
- 2025-02-28
AI Technical Summary
In the existing semiconductor packaging technology, when preparing larger-sized plastic seal structures, the chip mounting accuracy is low and the quality of the plastic seal layer is poor, resulting in low processing efficiency of semiconductor products.
By attaching multiple structures to be wired on the same carrier board and forming a rewiring layer on the side facing away from the carrier board, the process steps are performed while multiple structures to be wired are performed to improve manufacturing efficiency.
The efficiency of manufacturing semiconductor structures is improved, the utilization rate of the carrier board mounting area is improved, and the manufacturing cost is reduced.
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Figure CN119542146A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology and in particular to a method for manufacturing a semiconductor structure. Background Art
[0002] Common semiconductor packaging technologies, such as chip packaging technology, may include the following process steps: firstly, mounting the chip on a carrier board, then forming a plastic packaging layer to encapsulate the chip to obtain a plastic packaging structure, and finally forming a rewiring layer on the plastic packaging structure to be electrically connected to the chip's pads.
[0003] If a larger-sized plastic packaging structure is to be prepared using current mounting equipment and plastic packaging equipment, problems such as low chip mounting accuracy and poor quality of the plastic packaging layer will occur. Therefore, only smaller-sized plastic packaging structures can be prepared while ensuring product quality. For example, the cross-sectional size of the plastic packaging structure is less than or equal to 300mm*300mm, and the rewiring layer can only be formed on the smaller-sized plastic packaging structure, resulting in low processing efficiency of semiconductor products. Summary of the invention
[0004] The present application provides a method for manufacturing a semiconductor structure. The method for manufacturing a semiconductor structure includes:
[0005] Providing a plurality of structures to be wired, the structures to be wired comprising a plurality of packaging structures and a plastic packaging layer, the packaging structure comprising at least one electrical component, the electrical component comprising an electrode, and the plastic packaging layer at least encapsulating a side surface of the packaging structure;
[0006] Mounting the plurality of structures to be wired on the same carrier, with the electrodes facing away from the carrier;
[0007] A rewiring layer is formed on a side of the plurality of structures to be wired that is away from the carrier, and the rewiring layer is electrically connected to the electrodes of each of the electrical components.
[0008] In one embodiment, before forming a rewiring layer on a side of the plurality of structures to be wired away from the carrier, the method for manufacturing the semiconductor structure further comprises:
[0009] forming an insulating layer on a side of the plurality of structures to be wired away from the carrier, wherein the insulating layer fills gaps between adjacent structures to be wired;
[0010] forming a plurality of openings on the insulating layer, wherein at least a portion of a surface of each of the electrodes is exposed by the openings;
[0011] The redistribution layer is electrically connected to the electrode through the opening.
[0012] In one embodiment, the distance between adjacent structures to be wired is less than or equal to 100 μm.
[0013] In one embodiment, the surface of the insulating layer facing away from the carrier is flush everywhere.
[0014] In one embodiment, the electrical components in the structures to be wired are the same, and the forming of a rewiring layer on a side of the structures to be wired away from the carrier board comprises:
[0015] A rewiring layer is simultaneously formed on a side of the plurality of structures to be wired that is away from the carrier.
[0016] In one embodiment, the electrical components in at least two structures to be wired are different, and the forming of a rewiring layer on a side of the plurality of structures to be wired away from the carrier board comprises:
[0017] Simultaneously forming a seed layer on the surfaces of the plurality of structures to be wired away from the carrier;
[0018] Simultaneously forming a photoresist layer covering the seed layer in a region of the seed layer opposite to the plurality of structures to be packaged;
[0019] Performing patterning processing in sequence on the portion of the photoresist layer that is opposite to the at least two structures to be wired;
[0020] Simultaneously forming a metal layer in the region of the seed layer that is opposite to each of the structures to be wired and is not covered by the photoresist layer;
[0021] The seed layer and the regions not covered by the metal layer are etched simultaneously to obtain a rewiring layer including the retained portion of the seed layer and the metal layer.
[0022] In one embodiment, the thicknesses of the structures to be wired are the same.
[0023] In one embodiment, the structure to be wired is in a cubic shape.
[0024] In one embodiment, the cross-section area of each of the structures to be wired ranges from 100 mm*100 mm to 300 mm*300 mm.
[0025] In one embodiment, the electrical component includes at least one of a chip and a passive device, and the passive device includes at least one of an inductor, a resistor, and a capacitor.
[0026] The main technical effects achieved by the embodiments of the present application are:
[0027] The manufacturing method of the semiconductor structure provided in the embodiment of the present application, by mounting multiple structures to be wired on the same carrier, at least part of the process steps can be carried out simultaneously on the side of the multiple structures to be wired away from the carrier when forming a rewiring layer. Compared with the solution of mounting different structures to be wired on different carriers and forming rewiring layers on each structure to be wired respectively, it helps to improve the efficiency of manufacturing the semiconductor structure; and when the number of the same electrical components in the same batch is small and the mounting area of the carrier cannot be fully utilized when the prepared structures to be wired are mounted on the carrier, the structures to be wired including other types of electrical components can be mounted on the carrier together to improve the utilization rate of the mounting area of the carrier, which helps to reduce manufacturing costs. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] Figure 1 is a flow chart of a method for manufacturing a semiconductor structure provided by an exemplary embodiment of the present application;
[0029] Figure 2 is a partial cross-sectional view of a first intermediate structure provided by an exemplary embodiment of the present application;
[0030] Figure 3 yes Figure 2 a top view of the first intermediate structure shown;
[0031] Figure 4 is a partial cross-sectional view of a second intermediate structure provided by an exemplary embodiment of the present application;
[0032] Figure 5 is a partial cross-sectional view of a structure to be wired provided by an exemplary embodiment of the present application;
[0033] Figure 6 is a partial cross-sectional view of a third intermediate structure provided by an exemplary embodiment of the present application;
[0034] Figure 7 yes Figure 6 a top view of the third intermediate structure shown;
[0035] Figure 8 is a partial cross-sectional view of a fourth intermediate structure provided by an exemplary embodiment of the present application;
[0036] Fig. 9 yes Figure 8 A top view of the fourth intermediate structure shown;
[0037] Fig.10 is a partial cross-sectional view of a fifth intermediate structure provided by an exemplary embodiment of the present application;
[0038] Fig.11 yes Fig.10 a top view of the fifth intermediate structure shown;
[0039] Fig.12 is a partial cross-sectional view of a sixth intermediate structure provided by an exemplary embodiment of the present application;
[0040] Fig.13 is a partial cross-sectional view of a seventh intermediate structure provided by an exemplary embodiment of the present application;
[0041] Fig.14 is a partial cross-sectional view of an eighth intermediate structure provided by an exemplary embodiment of the present application;
[0042] Fig.15 is a cross-sectional view of a semiconductor structure provided by an exemplary embodiment of the present application. Specific embodiments
[0043] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.
[0044] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms of "a", "said" and "the" used in this application and the appended claims are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.
[0045] It should be understood that although the terms first, second, third, etc. may be used in the present application to describe various information, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".
[0046] Some embodiments of the present application are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.
[0047] The present application provides a method for manufacturing a semiconductor structure. Figure 1 The method for manufacturing the semiconductor structure includes the following steps 110 to 130.
[0048] In step 110, a plurality of structures to be wired are provided, wherein the structures to be wired include a plurality of packaging structures and a plastic packaging layer, wherein the packaging structure includes at least one electrical component including an electrode, and the plastic packaging layer at least encapsulates a side surface of the packaging structure.
[0049] In step 120, the plurality of structures to be wired are mounted on the same carrier, with the electrodes facing away from the carrier.
[0050] In step 130, a rewiring layer is formed on a side of the plurality of structures to be wired that is away from the carrier, and the rewiring layer is electrically connected to the electrodes of each of the electrical components.
[0051] The manufacturing method of the semiconductor structure provided in the embodiment of the present application, by mounting multiple structures to be wired on the same carrier, at least part of the process steps can be carried out simultaneously on the side of the multiple structures to be wired away from the carrier when forming the rewiring layer. Compared with the solution of mounting different structures to be wired on different carriers and forming the rewiring layer on each structure to be wired respectively, it helps to improve the efficiency of manufacturing the semiconductor structure; and when the number of the same electrical components in the same batch is small and the mounting area of the carrier cannot be fully utilized when the prepared structures to be wired are mounted on the carrier, the structures to be wired including other types of electrical components can be mounted on the carrier together to improve the utilization rate of the mounting area of the carrier, which helps to reduce manufacturing costs.
[0052] The following is a detailed introduction to each step of the method for manufacturing a semiconductor structure provided in an embodiment of the present application.
[0053] In step 110, a plurality of structures to be wired are provided, wherein the structures to be wired include a plurality of packaging structures and a plastic packaging layer, wherein the packaging structure includes at least one electrical component including an electrode, and the plastic packaging layer at least encapsulates a side surface of the packaging structure.
[0054] In one embodiment, each of the structures to be wired can be prepared through the following process.
[0055] First, a plurality of packaging structures are mounted on a substrate, with electrodes of electrical components included in the packaging structures facing the substrate.
[0056] The packaging structure may be an electrical component, or a plastic package including the electrical component, wherein the plastic package includes a plastic film layer encapsulating the electrical component. The electrical component includes at least one of a chip and a passive device, wherein the passive device includes at least one of an inductor, a resistor and a capacitor. The electrical components in the same structure to be wired may be the same.
[0057] Through this step, we can obtain Figure 2 and Figure 3 The first intermediate structure shown. Figure 2 and Figure 3 As shown, the plurality of package structures are all chips 10, and the pads 11 of the chip 10 are electrodes; the chip 10 is provided with a protective layer 12, and the protective layer 12 is provided with an opening 121, and the opening 121 exposes at least part of the surface of the pad 11. The openings 121 and the pads 11 may correspond one to one, and each opening 121 exposes the corresponding pad 11. The chip 10 is mounted on the substrate 22 through the adhesive layer 21, and the pads 11 of the chip 10 face the substrate 22. The adhesive layer 21 may be made of an easily peelable material so that the substrate 22 can be peeled off later. For example, the adhesive layer 21 may be a thermal release film layer, which can lose its viscosity by heating.
[0058] Then, a plastic sealing layer is formed.
[0059] Through this step, we can obtain Figure 4 The second intermediate structure shown. Figure 4 As shown, the plastic encapsulation layer 30 encapsulates the side surfaces of the chip 10 and the surface of the chip 10 facing away from the substrate 22 .
[0060] In one embodiment, before forming the plastic encapsulation layer, some pre-processing steps, such as chemical cleaning, plasma cleaning, etc., can be performed to remove impurities on the surface of the chip 10 so that the plastic encapsulation layer and the chip 10 can be more closely connected without delamination or cracking.
[0061] In one embodiment, the material of the plastic encapsulation layer 30 may be a polymer resin, a resin composite material, a polymer composite material, etc. For example, the plastic encapsulation layer 30 may be a resin with a filler, wherein the filler may be an inorganic particle. The plastic encapsulation layer 30 may be formed by injection molding, compression molding, or transfer molding.
[0062] Then, the substrate is peeled off to obtain a structure to be wired.
[0063] Through this step, we can obtain Figure 5 The structure to be wired 40 is shown. Figure 5 As shown, the pad 11 of the chip 10 is exposed. When the adhesive layer 31 is a thermal release film layer, the substrate can be peeled off by heating.
[0064] In step 120, the plurality of structures to be wired are mounted on the same carrier, with the electrodes facing away from the carrier.
[0065] Through step 120, the following can be obtained: Figure 6 and Figure 7 The third intermediate structure shown. Figure 6 and Figure 7 As shown, a plurality of structures to be wired 40 are mounted on the same carrier 24 via an adhesive layer 23 , and the pads 11 of the chips 10 face away from the carrier 24 . Figure 6In the illustrated embodiment, four structures to be wired 40 are mounted on the same carrier board 24. In other embodiments, the number of structures to be wired 40 mounted on the same carrier board 24 may be two or three, or five or more.
[0066] In one embodiment, after step 120 and before step 130 of forming a rewiring layer on a side of the plurality of structures to be wired away from the carrier, the method for manufacturing the semiconductor structure further comprises the following steps:
[0067] First, an insulating layer is formed on a side of the plurality of structures to be wired away from the carrier, and the insulating layer fills the gaps between adjacent structures to be wired.
[0068] Through this step, we can obtain Figure 8 and Fig. 9 The fourth intermediate structure shown. Figure 8 and Fig. 9 As shown, the insulating layer 50 covers the surface of the structure to be wired 40 facing away from the carrier 24 , the opening 121 of the protection layer 12 is filled with the insulating layer 50 , and the gaps between adjacent structures to be wired 40 are filled with the insulating layer 50 .
[0069] Subsequently, a plurality of openings are formed on the insulating layer, and at least a portion of a surface of each of the electrodes is exposed by the openings.
[0070] Through the above steps, we can get Fig.10 and Fig.11 The fifth intermediate structure shown. Fig.10 and Fig.11 As shown, a plurality of openings 51 are formed on the insulating layer 50, and the openings 51 expose the pads 11 of the chip 10. The openings 51 penetrate the portion of the insulating layer 50 located in the opening 121 of the protective layer 12 and the portion of the protective layer 12 located on the side away from the carrier 24. The openings 51 and the pads 11 may correspond one to one, and each opening 51 exposes the corresponding pad 11.
[0071] In one embodiment, the distance between adjacent structures to be wired 40 is less than or equal to 100 μm. This arrangement can avoid the gap between adjacent structures to be wired 40 being too large, resulting in the insulation layer 50 not being able to fill the gap, thereby making the surface of the insulation layer 50 away from the carrier 24 uneven, affecting the quality of the rewiring layer formed subsequently.
[0072] In one embodiment, the surface of the insulating layer 50 away from the carrier 24 is flush at all places. When the rewiring layer is subsequently formed, a seed layer is first formed on the surface of the insulating layer 50 away from the carrier 24. When the surface of the insulating layer 50 away from the carrier 24 is flush at all places, the problem of the seed layer being broken due to height differences in different regions of the insulating layer 50 can be avoided, and the thickness of the formed seed layer can be made more uniform. Furthermore, when the electroplating process is used, the current size at all places of the seed layer is more consistent, and the thickness of the metal layer formed on the seed layer is more uniform at all places, which helps to improve the quality of the formed rewiring layer.
[0073] In one embodiment, the material of the insulating layer 50 may include at least one of resin, polyisoprene, polyimide and synthetic rubber, so that the material used to prepare the insulating layer 50 has better fluidity and is more helpful to fill the gap between adjacent structures 40 to be wired.
[0074] In one embodiment, the thickness of each of the structures to be wired 40 is the same. With such a configuration, it is easier to make the surface of the insulating layer 50 away from the carrier 24 flush at all locations when preparing the insulating layer 50. In other embodiments, the thickness of each of the structures to be wired 40 may not be the same. When preparing the insulating layer 50, a smaller amount of insulating material may be applied to the surface of the thicker structure to be wired 40 away from the carrier 24, and a larger amount of insulating material may be applied to the surface of the thicker structure to be wired 40 away from the carrier 24, so that the surface of the insulating layer 50 away from the carrier 24 is flush at all locations.
[0075] In one embodiment, the structures to be wired 40 are in a cubic shape. With this arrangement, after each structure to be wired 40 is mounted on the carrier 24, the adjacent sides of any two adjacent structures to be wired 40 are parallel to each other, which helps to reduce the gap between any two adjacent structures to be wired 40.
[0076] In one embodiment, the cross-sections of the structures to be wired 40 are all the same in size. The cross-section of each structure to be wired refers to the cross-section of the structure to be wired 40 parallel to the carrier 24. With such a configuration, after each structure to be wired 40 is mounted on the carrier 24, when each structure to be wired 40 is arranged regularly, the surface of the insulating layer 50 located on each structure to be wired 40 can be in a regular shape, which helps to reduce the difficulty of preparing a rewiring layer later.
[0077] In one embodiment, the area range of the cross section of each of the structures to be wired 40 is 100mm*100mm to 300mm*300mm. When the area of the cross section of each structure to be wired 40 is within the range of 100mm*100mm to 300mm*300mm, each structure to be wired 40 can be prepared using the currently relatively mature process equipment, without the need to develop new process equipment, and can reduce the manufacturing cost while ensuring the efficiency of manufacturing semiconductor structures. In some embodiments, the area of the cross section of the structure to be wired 40 can be 100mm*100mm, 150mm*150mm, 200mm*200mm, 250mm*250mm, 300mm*300mm. The area of the cross section of the structure to be wired 40 is Xmm*Ymm, which means that the cross section of the structure to be wired 40 is rectangular, and the lengths of the two adjacent sides of the rectangle are Xmm and Ymm respectively. For example, the cross-sectional area of the structure to be wired 40 being 100mm*100mm means that the cross-sectional area of the structure to be wired 40 is a square with a side length of 100mm; the cross-sectional area of the structure to be wired 40 being 300mm*300mm means that the cross-sectional area of the structure to be wired 40 is a square with a side length of 300mm.
[0078] In step 130, a rewiring layer is formed on a side of the plurality of structures to be wired that is away from the carrier, and the rewiring layer is electrically connected to the electrodes of each of the electrical components.
[0079] Through this step, we can obtain Fig.12 The sixth intermediate structure shown. Fig.12 As shown, the rewiring layer 60 is electrically connected to the pad 11 of the chip 10 through the opening 51 of the insulating layer 50. The rewiring layer 61 includes a plurality of trace structures 61, and each trace structure 61 is electrically connected to the pad 11 respectively.
[0080] In one embodiment, the step of forming a rewiring layer on a side of the plurality of structures to be wired away from the carrier board may include the following process:
[0081] Firstly, a conductive material layer is simultaneously formed on a side of the plurality of structures to be wired away from the carrier.
[0082] The preparation process of the conductive material layer can be as follows: using sputtering to form a seed layer on the surface of the insulating layer 50 away from the carrier 24, the seed layer can cover the insulating layer 50; forming a photoresist layer covering the seed layer on the seed layer; using an exposure and development process to pattern the photoresist layer; using an electroplating process to form a metal layer in the exposed area of the seed layer; removing the patterned photoresist layer. In this way, a conductive material layer including a seed layer and a metal layer can be obtained.
[0083] Then, the conductive material layer is patterned to form a rewiring layer.
[0084] In this step, a wet etching process may be used to etch away the region of the seed layer that is not covered by the metal layer, and the remaining portion of the seed layer and the metal layer is the rewiring layer.
[0085] In one embodiment, the electrical components in each of the structures to be wired 40 are the same, and the step of forming a rewiring layer on the side of the multiple structures to be wired away from the carrier includes the following process: forming a rewiring layer simultaneously on the side of the multiple structures to be wired away from the carrier. When the electrical components are the same, the shapes of the trace structures connected to the pads of each electrical component can be the same, and corresponding trace structures can be formed on each structure to be wired at the same time, that is, the same mask is used to perform patterning on the photoresist layer, which helps to simplify the preparation process of the semiconductor structure and save preparation time.
[0086] In another embodiment, the electrical components in at least two structures to be wired 40 are different, and forming a rewiring layer on a side of the plurality of structures to be wired facing away from the carrier board comprises the following process:
[0087] First, a seed layer is simultaneously formed on the surfaces of the plurality of structures to be wired that are away from the carrier.
[0088] In this step, the seed layer formed on the insulating layer 50 is a continuous film layer, that is, the seed layers on the surfaces of the structures to be wired away from the carrier are connected.
[0089] Subsequently, a photoresist layer covering the seed layer is simultaneously formed in regions of the seed layer opposite to the plurality of structures to be packaged.
[0090] Subsequently, patterning is sequentially performed on portions of the photoresist layer that are opposite to the at least two structures to be wired.
[0091] Subsequently, a metal layer is simultaneously formed in the region of the seed layer that is opposite to each of the structures to be wired and is not covered by the photoresist layer. In this step, the metal layer may be formed by an electroplating process.
[0092] Subsequently, the seed layer and the regions not covered by the metal layer are etched simultaneously to obtain a rewiring layer including the retained portion of the seed layer and the metal layer.
[0093] In this embodiment, when the electrical components in the structure to be wired 40 are different, the shapes of the trace structures connected to the different electrical components may be different. When preparing the rewiring layer, the steps of forming the seed layer, the photoresist layer and the metal layer, and the step of patterning the seed layer may be formed at the same time. When patterning the photoresist layer, different masks are required for the parts of the photoresist layer corresponding to the structure to be wired where the different electrical components are located. Therefore, they are not performed at the same time.
[0094] In one embodiment, after step 130, the method for manufacturing a semiconductor structure further includes the following steps:
[0095] First, an insulating film layer covering the rewiring layer is formed, and through holes are opened on the insulating film layer, each of which exposes a partial surface of the trace structure.
[0096] Through this step, we can obtain Fig.13 The seventh intermediate structure shown. Fig.13 As shown, the insulating film layer covers the side surface of the trace structure 61 and a portion of the surface facing away from the carrier 24, and each through hole 71 exposes a portion of the surface of a trace structure 61. One trace structure 61 may be opposite to one through hole 71, or one trace structure 61 may be opposite to two or more through holes 71.
[0097] Subsequently, a plurality of conductive parts are formed, each of which is partially located in the through hole of the insulating film layer, and is away from the surface of the carrier board to expose the insulating film layer, and is electrically connected to the trace structure.
[0098] Through this step, we can obtain Fig.14 The eighth intermediate structure shown. Fig.14 As shown, the conductive portion 80 is partially located in the through hole 71 of the insulating film layer 70 , and partially exposed from the through hole 71 . Fig.14 The conductive part 80 shown is a conductive ball. In other embodiments, the conductive part may be a columnar structure. The resulting semiconductor structure can be soldered on a circuit board through the conductive part 80 to facilitate the connection between the semiconductor structure and the circuit board. The material of the conductive part 80 can be solder paste, metal tin, tin alloy or nickel gold.
[0099] In one embodiment, the method for manufacturing the semiconductor structure further includes: removing the carrier, and cutting the obtained structure to obtain a plurality of semiconductor structures after cutting.
[0100] Through this step, we can obtain Fig.15 The semiconductor structure shown in FIG. 1 includes at least one electrical element.
[0101] It should be noted that in the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It is also understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on the other element, or there may be an intermediate layer. In addition, it is understood that when an element or layer is referred to as being "under" another element or layer, it may be directly under the other element, or there may be more than one intermediate layer or element. In addition, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it may be the only layer between the two layers or two elements, or there may also be more than one intermediate layer or element. Similar reference numerals throughout the text indicate similar elements.
[0102] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the disclosure disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.
[0103] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.
Claims
1. A method for manufacturing a semiconductor structure, characterized in that: The method for manufacturing the semiconductor structure comprises: Providing a plurality of structures to be wired, the structures to be wired comprising a plurality of packaging structures and a plastic packaging layer, the packaging structure comprising at least one electrical component, the electrical component comprising an electrode, and the plastic packaging layer at least encapsulating a side surface of the packaging structure; Mounting the plurality of structures to be wired on the same carrier, with the electrodes facing away from the carrier; A rewiring layer is formed on a side of the plurality of structures to be wired that is away from the carrier, and the rewiring layer is electrically connected to the electrodes of each of the electrical components.
2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: Before forming a rewiring layer on a side of the plurality of structures to be wired away from the carrier, the method for manufacturing the semiconductor structure further comprises: forming an insulating layer on a side of the plurality of structures to be wired away from the carrier, wherein the insulating layer fills gaps between adjacent structures to be wired; forming a plurality of openings on the insulating layer, wherein at least a portion of a surface of each of the electrodes is exposed by the openings; The redistribution layer is electrically connected to the electrode through the opening.
3. The method for manufacturing a semiconductor structure according to claim 2, characterized in that: The distance between adjacent structures to be wired is less than or equal to 100 μm.
4. The method for manufacturing a semiconductor structure according to claim 2, characterized in that: The surface of the insulating layer facing away from the carrier is flush at all locations.
5. The method for manufacturing a semiconductor structure according to claim 1, wherein: The electrical components in each of the structures to be wired are the same, and the rewiring layer is formed on a side of the plurality of structures to be wired away from the carrier board, comprising: A rewiring layer is simultaneously formed on a side of the plurality of structures to be wired that is away from the carrier.
6. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The electrical components in at least two structures to be wired are different, and the forming of a rewiring layer on a side of the plurality of structures to be wired away from the carrier board comprises: Simultaneously forming a seed layer on the surfaces of the plurality of structures to be wired away from the carrier; Subsequently, a photoresist layer covering the seed layer is simultaneously formed in the region of the seed layer opposite to the plurality of structures to be packaged; Subsequently, patterning is sequentially performed on the portions of the photoresist layer that are opposite to the at least two structures to be wired; Simultaneously forming a metal layer in the region of the seed layer that is opposite to each of the structures to be wired and is not covered by the photoresist layer; The seed layer and the regions not covered by the metal layer are etched simultaneously to obtain a rewiring layer including a retained portion of the seed layer and the metal layer.
7. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The thicknesses of the structures to be wired are all the same.
8. The method for manufacturing a semiconductor structure according to claim 1, wherein: The structure to be wired is in a cubic shape.
9. The method for manufacturing a semiconductor structure according to claim 8, characterized in that: The cross-section area of each of the structures to be wired ranges from 100 mm*100 mm to 300 mm*300 mm.
10. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The electrical component includes at least one of a chip and a passive device, and the passive device includes at least one of an inductor, a resistor and a capacitor.