Method for realizing multi-stack flash memory packaging

Abstract

The invention relates to the technical field of chip packaging, in particular to a method for realizing multi-stack flash memory packaging. Comprising the following steps that S1, a plurality of chips are stacked on a substrate or a PCB, and the adjacent chips are bonded through bonding wires; s2, pasting a water-soluble film on the upper side of the uppermost chip, wherein the water-soluble film wraps the surface of one side of the uppermost chip and the bonding wire of the uppermost chip; s3, plastic packaging: wrapping the chip, the bonding wire and the water-soluble film with a plastic packaging material; s4, grinding the surface of a formed packaging body after plastic packaging is completed, and exposing the surface of the water-soluble film; s5, the water-soluble film is dissolved through water cleaning, and a cavity is formed in the surface of the packaging body; s6, continuously stacking a plurality of chips on the surface of the chip exposed in the cavity; and S7, repeating the steps S2 to S5 until all the chips are stacked, and performing plastic package on the cavity. Compared with the prior art, more than 16 layers of 3D flash memory chips can be stacked, and more memory chips can be integrated by a single packaging body.

Description

Technical Field

[0001] The invention relates to the technical field of chip packaging, in particular to a method for implementing multi-layer flash memory packaging. Background Art

[0002] At present, 3D flash memory packaging is to stack multiple flash memory chips and bond them on a substrate or PCB, and then complete the electrical connection between each layer of flash memory chips and between the chips and the substrate or PCB pads through welding wires, and finally perform plastic sealing, and then carry out subsequent processes to complete the entire packaging process. The current industry generally stacks 16 layers. When stacking more layers, the chip will bend and collapse, and the current stacking layer capacity limits the integration of higher storage capacity in a single package. Summary of the invention

[0003] The present invention overcomes the deficiencies of the prior art and provides a method for implementing multi-layer flash memory packaging.

[0004] To achieve the above object, a method for implementing multi-layer flash memory packaging is designed, comprising the following steps: S1, stacking several chips on a substrate or PCB, and bonding adjacent chips by wire bonding; S2, pasting a water-soluble film on the upper side of the uppermost chip, the water-soluble film wrapping the surface of one side of the uppermost chip and the bonding wire of the uppermost chip; S3, plastic encapsulation, the plastic encapsulation material wraps the chip, bonding wires, and water-soluble film; S4, grinding the surface of the formed package body after the plastic packaging is completed to expose the surface of the water-soluble film; S5, washing with water to dissolve the water-soluble film and form a cavity on the surface of the package; S6, stacking a plurality of chips on the chip surface exposed in the cavity, and bonding adjacent chips by wire bonding; S7, repeating step S2 to step S5 until all chips are stacked, and the cavity is plastic-sealed to obtain a final package.

[0005] The number of chip layers stacked each time is 1-16.

[0006] The upper and lower adjacent chips are bonded together by DAF film.

[0007] The chip is a flash memory chip.

[0008] Compared with the prior art, the present invention realizes stacking of more than 16 layers of 3D flash memory chips and integrates more storage chips into a single package. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 Schematic diagram of step S1 of an embodiment of the present invention.

[0010] Figure 2 Schematic diagram of step S2 of an embodiment of the present invention.

[0011] Figure 3 Schematic diagram of step S3 of an embodiment of the present invention.

[0012] Figure 4 Schematic diagram of step S4 of an embodiment of the present invention.

[0013] Figure 5 Schematic diagram of step S5 of an embodiment of the present invention.

[0014] Figure 6 Schematic diagram of step S6 of an embodiment of the present invention.

[0015] Figure 7 Schematic diagram of step S7 of an embodiment of the present invention.

[0016] Figure 8 Schematic diagram of step S8 of an embodiment of the present invention.

[0017] Fig. 9 Schematic diagram of step S9 of an embodiment of the present invention.

[0018] Fig.10 Schematic diagram of step S10 of an embodiment of the present invention.

[0019] Fig.11 Schematic diagram of step S11 of an embodiment of the present invention. DETAILED DESCRIPTION

[0020] The present invention will be further described below with reference to the accompanying drawings.

[0021] The method for implementing multi-layer flash memory packaging in this embodiment includes the following steps: S1, such as Figure 1 As shown, several layers of chips 3 are stacked on a substrate or PCB board 1, and adjacent chips 3 are bonded by bonding wires 6; S2, a water-soluble film 5 is attached to the upper side of the uppermost chip 3, and the water-soluble film 5 covers the surface of one side of the uppermost chip 3 and the bonding wire 6 of the uppermost chip 3; S3, plastic encapsulation, the plastic encapsulation material 4 wraps the chip 3, the bonding wire 6, and the water-soluble film 5; S4, after the plastic packaging is completed, the surface of the formed package body is ground to expose the surface of the water-soluble film 5; S5, washing with water to dissolve the water-soluble film 5 and form a cavity on the surface of the package; S6, continue to stack several layers of chips 3 on the surface of the chip 3 exposed in the cavity, and bond adjacent chips 3 by bonding wires 6; S7, a water-soluble film 5 is attached to the upper side of the uppermost chip 3, and the water-soluble film 5 covers the surface of one side of the uppermost chip 3 and the bonding wire 6 of the uppermost chip 3; S8, plastic sealing, the plastic sealing material 4 wraps the chip 3, the bonding wire 6, and the water-soluble film 5; S9, grinding the surface of the formed package body to expose the surface of the water-soluble film 5; S10, washing with water to dissolve the water-soluble film 5 and form a cavity on the surface of the package; S11, after all chips 3 are stacked, the cavity is plastic-sealed to obtain a final package.

[0022] When used specifically, the number of layers of chips 3 stacked each time is 1-16 layers. In this embodiment, the final package is formed by stacking twice. When used specifically, the number of stacking times and the number of chip layers stacked each time can be determined according to the number of chips to be stacked. After each stacking is completed, plastic sealing is first performed, and the plastic sealing material 4 is wrapped around the chip 3 and the outer side of the welding wire 6 to play a supporting role, preventing the chip from bending and collapsing when the number of chip stacking layers is large.

[0023] In this embodiment, the upper and lower adjacent chips 3 are bonded together by DAF films 2. The chip 3 is a flash memory chip.

[0024] The present invention utilizes the easy-to-remove property of water-soluble film to improve the existing process of single stacking and plastic sealing into multiple stacking and plastic sealing. Each plastic sealing wraps and supports the previously stacked chips to prevent the stacked chips from bending or collapsing, ultimately achieving the maximum number of stacking layers of a single package and integrating the maximum number of storage chips.

Claims

1. A method for implementing multi-layer flash memory packaging, characterized in that: The steps include: S1, stacking a plurality of chips (3) on a substrate or a PCB (1), and bonding adjacent chips (3) via bonding wires (6); S2, affixing a water-soluble film (5) to the upper side of the uppermost chip (3), wherein the water-soluble film (5) wraps the surface of one side of the uppermost chip (3) and the bonding wire (6) of the uppermost chip (3); S3, plastic encapsulation, the plastic encapsulation material (4) wraps the chip (3), the bonding wire (6), and the water-soluble film (5); S4, after the plastic encapsulation is completed, the surface of the formed package body is ground to expose the surface of the water-soluble film (5); S5, washing with water to dissolve the water-soluble film (5) and form a cavity on the surface of the package; S6, stacking a plurality of chips (3) on the surface of the chip (3) exposed in the cavity, and bonding adjacent chips (3) via bonding wires (6); S7, repeating steps S2 to S5 until all chips (3) are stacked, and the cavity is plastic-sealed to obtain a final package.

2. A method for implementing multi-layer flash memory packaging according to claim 1, characterized in that: The number of chips (3) stacked each time is 1 to 16 layers.

3. The method for implementing multi-layer flash memory packaging according to claim 1, characterized in that: The upper and lower adjacent chips (3) are bonded together via a DAF film (2).

4. The method for implementing multi-layer flash memory packaging according to claim 1, characterized in that: The chip (3) is a flash memory chip.

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