Semiconductor structure and forming method thereof
By forming and repairing the dielectric layer in steps in the formation method of semiconductor structures, the problems of conductive stack damage and circuit short circuit in the cleaning process are solved, and the requirements for smooth formation of conductive components in the surrounding area are achieved and additional processes are avoided.
Patent Information
- Application Number
- CN202311518141.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-08-28
- Filing Date
- 2023-11-15
- Publication Date
- 2025-02-28
AI Technical Summary
In the cleaning process of semiconductor structures, the dielectric layer and side walls of the conductive stack are often damaged, which may cause circuit short circuits. In traditional processes, an over-thick repair dielectric layer needs to be formed to prevent short circuits, resulting in the failure of conductive components in the surrounding area to form smoothly, and additional lithography and etching processes are required to remove part of the repair dielectric layer.
In the method of forming the semiconductor structure, the dielectric layer is formed and repaired in steps, the specific steps include forming the bottom dielectric layer on the substrate, the first and second stacking structures, patterning the conductive stack, performing a cleaning process, forming the first and second patch dielectric layers, ensuring that the thickness of the patch dielectric layer on the side wall of the conductive stack is different, to prevent circuit short circuits and avoid additional lithography and etching processes.
The circuit short circuit caused by the cleaning process is effectively prevented, and the conductive parts located in the substrate are successfully formed in the surrounding area, and no additional lithography and etching processes are required to handle the repair dielectric layer.
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Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductors, and in particular to a semiconductor structure and a method for forming the same. Background Art
[0002] As the size and process of semiconductor structures (e.g., dynamic random access memory (DRAM)) are miniaturized, in the semiconductor structure process, the dielectric layer at the bottom of the conductive stack (e.g., the gate stack in the cell area) and / or the sidewall of the conductive structure are often damaged during the cleaning process. Therefore, a repair dielectric layer is needed for repair.
[0003] In traditional processes, in order to prevent these damages from causing circuit short circuits, an overly thick repair dielectric layer is often formed, which results in the inability to smoothly form conductive components in the substrate in the peripheral area (for example, the source and drain buried in the substrate), or requires additional photolithography and etching processes to remove part of the overly thick repair dielectric layer. Summary of the invention
[0004] The embodiment of the present application proposes a semiconductor structure and a method for forming the same. The formation method of the embodiment of the present application can effectively prevent damage caused by the cleaning process from causing circuit short circuits, and can also smoothly form conductive components located in the substrate in the peripheral area without the need for additional photolithography and etching processes.
[0005] Some embodiments of the present application include a method for forming a semiconductor structure, and the method for forming a semiconductor structure includes the following steps:
[0006] A substrate is provided, wherein the substrate is divided into a unit area and a peripheral area, and the peripheral area is adjacent to the unit area. A bottom dielectric layer is formed on the substrate. A first stacking structure and a second stacking structure are formed on the bottom dielectric layer, wherein the first stacking structure is located in the unit area, and the second stacking structure is located in the peripheral area. The first stacking structure is patterned to form a plurality of first conductive stacks. A first cleaning process is performed. A first repair dielectric layer is formed on the first conductive stack, the second stacking structure, and the bottom dielectric layer. The second stacking structure is patterned to form a plurality of second conductive stacks. A second cleaning process is performed. A second repair dielectric layer is formed on the first conductive stack, the second conductive stack, and the bottom dielectric layer.
[0007] Some embodiments of the present application include a semiconductor structure, the semiconductor structure includes a substrate, the substrate has a unit area and a peripheral area, and the peripheral area is adjacent to the unit area. The semiconductor structure includes a bottom dielectric layer, and the bottom dielectric layer is disposed on the substrate. The semiconductor structure further includes a plurality of first conductive stacks and a plurality of second conductive stacks, the first conductive stacks are disposed on the bottom dielectric layer and located in the unit area, and the second conductive stacks are disposed on the bottom dielectric layer and located in the peripheral area. In addition, the semiconductor structure includes a repair dielectric layer, and the repair dielectric layer is disposed on the first conductive stack and the second conductive stack. The repair dielectric layer has a first thickness on the sidewall of each first conductive stack, and the repair dielectric layer has a second thickness on the sidewall of each second conductive stack, and the first thickness is greater than the second thickness. BRIEF DESCRIPTION OF THE DRAWINGS
[0008] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0009] Figures 1 to 5 A partial cross-sectional view of a corresponding semiconductor structure in an embodiment of the present application Figures 1 to 5 ;
[0010] [Explanation of symbols]
[0011] 100:Semiconductor structure
[0012] 10:Substrate
[0013] 12: Bottom dielectric layer
[0014] 14,16,18: Insulation layer
[0015] 20,22,24: Semiconductor layer
[0016] 31: First repair dielectric layer
[0017] 32: Second repair dielectric layer
[0018] CG: First Conductive Stack
[0019] PG: Second conductive stack
[0020] R1: Unit area
[0021] R2: Surrounding area
[0022] S: Gap
[0023] TC: First Thickness
[0024] TP: Second thickness DETAILED DESCRIPTION
[0025] Figures 1 to 5 1 is a partial cross-sectional view showing various stages of forming a semiconductor structure 100 according to some embodiments of the present application. It should be noted that, for the sake of simplicity, Figures 1 to 5 Some components of the semiconductor structure 100 have been omitted.
[0026] Reference Figure 1 In some embodiments, a substrate 10 is provided, and the substrate 10 is divided into a unit region R1 and a peripheral region R2, and the peripheral region R2 is adjacent to the unit region R1. For example, the peripheral region R2 of the substrate 10 may surround the unit region R1, but the embodiments of the present application are not limited thereto.
[0027] Reference Figure 1 In some embodiments, a bottom dielectric layer 12 is formed on the substrate 10. For example, the bottom dielectric layer 12 may include an insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride, the like, or a combination of the foregoing materials, but the embodiments of the present application are not limited thereto. The bottom dielectric layer 12 may be formed by a deposition process, such as chemical vapor deposition, atomic layer deposition, molecular beam epitaxy, liquid phase epitaxy, the like, or a combination of the foregoing, but the embodiments of the present application are not limited thereto.
[0028] Reference Figure 1 In some embodiments, a first stack structure ST1 and a second stack structure ST2 are formed on the bottom dielectric layer 12. Figure 1 As shown, the first stacked structure ST1 is located in the unit region R1 of the substrate 10, and the second stacked structure ST2 is located in the peripheral region R2 of the substrate 10. For example, the first stacked structure ST1 may include semiconductor layers 20, 22 and an insulating layer 14, wherein the insulating layer 14 is disposed between the semiconductor layer 20 and the semiconductor layer 22; the second stacked structure ST2 may include a semiconductor layer 24 and an insulating layer 18, wherein the insulating layer 18 is disposed on the semiconductor layer 24, but the embodiment of the present application is not limited thereto. In addition, the first stacked structure ST1 may further include an insulating layer 16, wherein the insulating layer 16 is disposed on the semiconductor layer 22.
[0029] The semiconductor layers 20, 22 and 24 may include silicon or germanium, and the insulating layers 14, 16 and 18 may include silicon oxide, silicon nitride, silicon oxynitride, the like or a combination of the above materials, and the above materials may be formed by a deposition process, but the embodiment of the present application is not limited thereto. The examples of the deposition process are described above and will not be repeated here.
[0030] It should be noted that although Figure 1The semiconductor layers 20 and 24 are shown to be directly formed on the bottom dielectric layer 12 (i.e., the semiconductor layers 20 and 24 are in direct contact with the bottom dielectric layer 12), but the present invention is not limited thereto. Other components may exist between the semiconductor layer 20 and the bottom dielectric layer 12 or between the semiconductor layer 24 and the bottom dielectric layer 12.
[0031] Reference Figure 2 , patterning the first stack structure ST1 to form a plurality of first conductive stacks CG. A patterning process may be performed to process the first stack structure ST1 according to a predetermined position of the first conductive stack CG. For example, a mask layer (not shown) is disposed on the first stack structure ST1 (the insulating layer 16), and then an etching process is performed using the mask layer as an etching mask to etch a groove in the first stack structure ST1. The mask layer may include a photoresist, such as a positive photoresist or a negative photoresist. In addition, the mask layer may include a hard mask, and may be formed of silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), silicon carbide nitride (SiCN), similar materials, or a combination thereof, but the embodiments of the present application are not limited thereto.
[0032] The mask layer may be a single layer or a multi-layer structure. The formation of the mask layer may include a deposition process, a photolithography process, other appropriate processes or a combination thereof, but the embodiments of the present application are not limited thereto.
[0033] Next, refer to Figure 2 In some embodiments, a first cleaning process W1 is performed. The first cleaning process W1 can be used to remove the excess components remaining after the above process. In some embodiments, the first cleaning process W1 is a wet cleaning process, and the wet cleaning process uses diluted hydrofluoric acid (HF) as a cleaning agent, but the embodiments of the present application are not limited thereto.
[0034] like Figure 2 As shown, in some embodiments, the bottom dielectric layer 12 forms a plurality of gaps S during the first cleaning process W1. In some embodiments, the gaps S are close to the corners of the bottom of the first conductive stack CG, but the present invention is not limited thereto. For example, the semiconductor layer 20 or other stacked layers in the first conductive stack CG may also form gaps S during the first cleaning process W1 (not shown). Figure 2 ).
[0035] Next, refer to Figure 3In some embodiments, a first repair dielectric layer 31 is formed on the first conductive stack CG, the second stack structure ST2 and the bottom dielectric layer 12. The first repair dielectric layer 31 may include an insulating material, and examples of the insulating material are described above and will not be repeated here. In some embodiments, the first repair dielectric layer 31 fills the gap S. The first repair dielectric layer 31 can be used to prevent the gap S from causing a subsequent circuit short circuit.
[0036] In some embodiments, a thermal treatment process is performed to form the first repair dielectric layer 31. In some embodiments, the thermal treatment process includes in-situ steam generation (ISSG) oxidation, rapid thermal oxidation (RTO), and rapid thermal nitridation (RTN), but the embodiments of the present application are not limited thereto.
[0037] Next, refer to Figure 4 In some embodiments, the second stack structure ST2 is patterned to form a plurality of second conductive stacks PG (in Figure 4 Only one is shown in the figure). A patterning process may be performed to process the second stack structure ST2 according to a predetermined location of the second conductive stack PG. Examples of the patterning process are described above and will not be repeated here.
[0038] Next, refer to Figure 4 In some embodiments, a second cleaning process W2 is performed. The second cleaning process W2 can be used to remove the excess components remaining after the above process. Similarly, the second cleaning process W2 is a wet cleaning process, and the wet cleaning process uses diluted hydrofluoric acid (HF) as a cleaning agent, but the embodiments of the present application are not limited thereto.
[0039] Next, refer to Figure 5 In some embodiments, a second repair dielectric layer 32 is formed on the first conductive stack CG, the second conductive stack PG and the bottom dielectric layer 12 to form the semiconductor structure 100. The material of the second repair dielectric layer 32 may be the same as or similar to that of the first repair dielectric layer 31. In addition, in some embodiments, a heat treatment process is performed to form the second repair dielectric layer 32. The examples of the heat treatment process are described above and will not be repeated here, but the embodiments of the present application are not limited thereto.
[0040] The bottom dielectric layer 12, the first conductive stack CG or the second conductive stack PG are Figure 4During the second cleaning process W2 shown, multiple gaps (not shown) may still be formed. The second repair dielectric layer 32 can be filled in these gaps to prevent the gaps from causing subsequent circuit short circuits. In other words, the first repair dielectric layer 31 and the second repair dielectric layer 32 can be regarded as the repair dielectric layer of the bottom dielectric layer 12 and the first conductive stack CG, and the second repair dielectric layer 32 can be regarded as the repair dielectric layer of the second conductive stack PG.
[0041] like Figure 5 As shown, in some embodiments, the semiconductor structure 100 includes a substrate 10, the substrate 10 has a unit region R1 and a peripheral region R2, and the peripheral region R2 is adjacent to the unit region R1. The semiconductor structure 100 also includes a bottom dielectric layer 12, and the bottom dielectric layer 12 is disposed on the substrate 10. The semiconductor structure 100 further includes a plurality of first conductive stacks CG and a plurality of second conductive stacks PG, the first conductive stacks CG are disposed on the bottom dielectric layer 12 and located in the unit region R1, and the second conductive stacks PG are disposed on the bottom dielectric layer 12 and located in the peripheral region R2.
[0042] In the present embodiment, the semiconductor structure 100 includes a repair dielectric layer, which is disposed on the first conductive stack CG and the second conductive stack PG. The repair dielectric layer has a first thickness TC on the sidewall of each first conductive stack CG, and has a second thickness TP on the sidewall of each second conductive stack PG, and the first thickness TC is greater than the second thickness TP. In addition, in some embodiments, the repair dielectric layer includes oxide or nitride.
[0043] In some embodiments, the bottom dielectric layer 12 (or the first conductive stack CG and / or the second conductive stack PG) has a plurality of gaps S, and the repair dielectric layer is filled in the gaps S. Since the repair dielectric layer is filled in the gaps S, it can be used to prevent the gaps S from causing subsequent circuit short circuits.
[0044] In addition, the thickness (e.g., second thickness TP) of the repair dielectric layer (e.g., second repair dielectric layer 32) in the peripheral region R2 (e.g., on the side wall of each second conductive stack PG) is less than the thickness (e.g., first thickness TC) in the unit region R1 (e.g., on the side wall of each first conductive stack PG). Therefore, no additional photolithography and etching processes are required to remove a portion of the repair dielectric layer, so that a conductive component located within the substrate 10 can be successfully formed in the peripheral region R2.
[0045] The above summarizes the components of several embodiments so that those with ordinary knowledge in the technical field to which this application belongs can understand the viewpoints of the embodiments of this application, and can design or modify other processes and structures based on the embodiments of this application to achieve the same purpose and / or advantages of the embodiments introduced here, and such equivalent structures do not deviate from the spirit and scope of this application, and they can make various changes, substitutions and replacements without violating the spirit and scope of this application. Therefore, the scope of protection of this application shall be determined by the definition of the claims. In addition, although this application has been invented as above with several preferred embodiments, it is not used to limit this application.
Claims
1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, wherein the substrate is divided into a unit area and a peripheral area, wherein the peripheral area is adjacent to the unit area; forming a bottom dielectric layer over the substrate; forming a first stacking structure and a second stacking structure on the bottom dielectric layer, wherein the first stacking structure is located in the cell region, and the second stacking structure is located in the peripheral region; patterning the first stack structure to form a plurality of first conductive stacks; performing a first cleaning process; forming a first repair dielectric layer on the first conductive stack, the second stack structure and the bottom dielectric layer; patterning the second stack structure to form a plurality of second conductive stacks; performing a second cleaning process; as well as A second repair dielectric layer is formed on the first conductive stack, the second conductive stack and the bottom dielectric layer.
2. The method for forming a semiconductor structure according to claim 1, wherein: The bottom dielectric layer forms a plurality of gaps during the first cleaning process, and the first repair dielectric layer fills the gaps.
3. The method for forming a semiconductor structure according to claim 2, wherein: The gap is close to a corner of the bottom of the first conductive stack.
4. The method for forming a semiconductor structure according to claim 1, wherein: The first cleaning process or the second cleaning process is a wet cleaning process.
5. The method for forming a semiconductor structure according to claim 4, characterized in that: The wet cleaning process uses hydrofluoric acid as a cleaning agent.
6. The method for forming a semiconductor structure according to claim 1, wherein: A thermal treatment process is performed to form the first repair dielectric layer or the second repair dielectric layer.
7. The method for forming a semiconductor structure according to claim 6, wherein: The heat treatment process includes in-situ steam oxidation, rapid thermal oxidation, and rapid thermal nitridation.
8. A semiconductor structure, characterized in that: include: A substrate having a unit region and a peripheral region, wherein the peripheral region is adjacent to the unit region; a bottom dielectric layer disposed on the substrate; A plurality of first conductive stacks are disposed on the bottom dielectric layer and located in the cell region; A plurality of second conductive stacks are disposed on the bottom dielectric layer and located in the peripheral area; A repair dielectric layer is disposed on the multiple first conductive stacks and the multiple second conductive stacks, wherein the repair dielectric layer has a first thickness on the sidewall of each of the first conductive stacks, the repair dielectric layer has a second thickness on the sidewall of each of the second conductive stacks, and the first thickness is greater than the second thickness.
9. The semiconductor structure according to claim 8, characterized in that: The bottom dielectric layer has a plurality of gaps, and the repair dielectric layer is filled in the plurality of gaps.
10. The semiconductor structure according to claim 8, characterized in that The repair dielectric layer includes oxide or nitride.