Substrate for semiconductor package and semiconductor package including same

Abstract

The present invention provides a substrate for a semiconductor package on which a fine pitch corresponding electroless palladium gold (EPIG) plating layer is formed, and a semiconductor package including the same.

Description

Technical Field

[0001] The present invention relates to a semiconductor package substrate having a fine pitch corresponding chemical palladium gold (EPIG) plating layer and a semiconductor package including the substrate. Background Art

[0002] In the manufacture of electronic components, the step of forming a circuit on a semiconductor wafer is called a front-end process, and the step of assembling the wafer into a state that can be used in an actual product is called a back-end process, or a packaging process.

[0003] In the field of semiconductor packaging, new packaging technologies that are thinner, lighter and shorter have been developed and replaced by wire bonding technology or flip chip bonding technology.

[0004] Among them, wire bonding technology is a method of bonding thin metal wires to pads. That is, it is a technology for connecting the internal chip and the outside. Structurally, the wire acts as a bridge connecting the bonding pads of the chip (primary bonding) and the pads of the carrier (secondary bonding). Currently, the substrate used as the carrier is mainly a printed circuit board (PCB).

[0005] Moreover, there are three ways to connect the lead to the pad, namely, a thermal compression method that uses heat to heat and press to connect the bonding pad and a capillary (capillary, a capillary-shaped lead moving tool), a method of applying ultrasound to the capillary for bonding without using heat, and a composite method that uses both heat and ultrasound.

[0006] First, the thermal compression method is as follows, that is, the temperature of the chip bonding pad is raised to about 200°C in advance, and the temperature of the tip (Tip, end) of the splitter is also raised to make the lead into a ball shape, so that the splitter applies pressure to the bonding pad to attach the lead.

[0007] The ultrasonic method is a method in which the lead is punched onto the pad and ultrasonic waves are applied to a wedge (a lead moving tool similar to a wedge, which does not form a ball) to attach the lead to the pad. It has the advantage of low cost in terms of process and material. However, since ultrasonic waves are used instead of heat and pressure, it has the disadvantage of being easy to operate but poor in tensile strength after bonding (the force that the lead can withstand when it is pulled after wiring).

[0008] The most commonly used method in semiconductor processes is the thermosonic method, which combines the advantages of the thermocompression method and the ultrasonic method. Heat, pressure, and ultrasonic waves are applied to the splitter to perform bonding under optimal conditions. Compared with cost, the semiconductor back-end process attaches more importance to the bonding strength, so even though it is expensive, the thermosonic method using gold wire is mainly used.

[0009] In addition, the flip chip bonding technology is a form in which the semiconductor chip is facing downward and the metal protrusions that carry electricity are connected to the pads. Since the flip chip bonding is directed to the substrate without leads, it has the following characteristics, namely, reduced volume, reduced power consumption, reduced peripheral noise influence, fast speed due to the small signal movement distance, and high fixing strength.

[0010] Among them, the materials of metal protrusions mainly use solder (Solder) and gold (Au). Metal protrusions refer to conductive metal protrusions used to connect chips to circuit substrates through tape automated bonding (TAB) and flip chip (FC) methods, or conductive metal protrusions used to directly connect ball grid arrays (BGA) and chip scale packages (CSP) to circuit substrates.

[0011] The solder bumps are formed into spherical shapes by surface tension after the reflow process, and the gold bumps, which are one type of metal bumps, are formed into rectangular shapes with length, width, and height by gold electroplating.

[0012] The wafers with gold bumps will be used for TCP (tape carrier package), COG (Chip on Glass) packaging, and COF (chip on Film) packaging, and will be used in products such as televisions (TV), monitors, networks, mobile devices, tablets, and automotive DIC (Digital Image Correlation).

[0013] Since gold plating is excellent in physical and chemical properties such as conductivity, oxidation resistance, and chemical resistance, it is used for a variety of purposes in microelectronics and optoelectronics fields such as RDL (redistribution layer), pattern plating, conformal via coating, X-ray mask, MEMS (micro-electromechanical system), and gold bumping.

[0014] Currently, although nickel plating is formed on the semiconductor package substrate as described above, nickel plating is difficult to use for fine pitches due to its high plating thickness, cracks may occur due to the poor flexibility of nickel metal, and there is a lot of signal loss at high frequencies due to its magnetic nature.

[0015] Therefore, the applicant has obtained a semiconductor package substrate having a fine pitch corresponding chemical palladium gold plating layer and a semiconductor package including the same after hard work and many studies, thereby completing the present invention.

[0016] Prior art literature

[0017] Patent Literature

[0018] Korean Patent No. 10-1852658 (Patent Announcement Date: April 26, 2018) Summary of the invention

[0019] Therefore, an object of the present invention is to provide a semiconductor package substrate having a fine pitch-compatible chemical palladium-gold plating layer formed thereon.

[0020] Another object of the present invention is to provide a semiconductor package including a semiconductor package substrate on which a fine-pitch compatible chemical palladium-gold plating layer is formed.

[0021] The purpose of the present invention is not limited to the above-mentioned purpose, and other purposes not mentioned can be clearly understood by those skilled in the art through the following description.

[0022] In order to achieve the above-mentioned purpose, according to one embodiment of the present invention, a substrate for semiconductor packaging will be provided, characterized in that it includes: a copper substrate; a strike gold plating film formed on the above-mentioned copper substrate; a palladium plating film formed on the above-mentioned strike gold plating film; and a gold plating film formed on the above-mentioned palladium plating film. In the above-mentioned semiconductor packaging substrate, the spacing is the sum of the circuit width and the spacing width. When used for fine circuits with a spacing level of 4 to 50 μm, the diffusion of the gold plating film of the above-mentioned semiconductor packaging substrate is 0.001 to 10 volume percent.

[0023] Furthermore, according to another embodiment of the present invention, a substrate for semiconductor packaging is provided, characterized in that it includes: a copper substrate; a gold impact film formed on the copper substrate; a palladium film formed on the gold impact film; and a gold film formed on the palladium film. When the semiconductor packaging substrate is measured by the high-speed ball shear strength evaluation condition of the following evaluation condition 1, the high-speed ball shear strength is 1000 to 1600 gf.

[0024] [Evaluation Condition 1]

[0025] High-speed shearing equipment: Dage 4000HS

[0026] Shear speed: 1m / s

[0027] Shear height: 50μm

[0028] Ball grid array (BGA) pad diameter: 350μm

[0029] Solder Ball Diameter: 450μm

[0030] Solder ball type: SAC 305 (solder ball containing 96.5 weight percent of tin (Sn), 3 weight percent of silver (Ag) and 0.5 weight percent of copper (Cu))

[0031] Measurement points: n = 25

[0032] In addition, according to another embodiment of the present invention, a substrate for semiconductor packaging is provided, characterized in that it includes: a copper substrate; a strike gold plating film formed on the above-mentioned copper substrate; a palladium plating film formed on the above-mentioned strike gold plating film; and a gold plating film formed on the above-mentioned palladium plating film. When the above-mentioned semiconductor packaging substrate is measured by the lead pull strength evaluation condition of the following evaluation condition 2, the lead pull strength is 6 to 14 gf.

[0033] [Evaluation Condition 2]

[0034] Wire Bonder: Wire Bonder-HB16

[0035] Pull Tester: Dage 4000

[0036] Au wire: 1mil

[0037] Bonding conditions: 1st Bond – 300 Hz (US), 250 ms (Time), force 250 mN;

[0038] 2nd Bond – 400Hz (US), 350mls (time), pressure 250mN

[0039] Heat treatment conditions: 175°C, 6 hours

[0040] Furthermore, according to another embodiment of the present invention, a substrate for semiconductor packaging is provided, characterized in that it includes: a copper substrate; a strike gold plating film formed on the above copper substrate; a palladium plating film formed on the above strike gold plating film; and a gold plating film formed on the above palladium plating film, and the thickness of the above gold plating film is 20 to 1000 nm.

[0041] Furthermore, according to another embodiment of the present invention, a substrate for semiconductor packaging is provided, characterized in that it includes: a copper substrate; a strike gold plating film formed on the above copper substrate; a palladium plating film formed on the above strike gold plating film; and a gold plating film formed on the above palladium plating film.

[0042] Furthermore, according to another embodiment of the present invention, a substrate for semiconductor packaging is provided, characterized in that it includes: a copper substrate; a strike gold plating film formed on the above-mentioned copper substrate; a palladium plating film formed on the above-mentioned strike gold plating film; and a gold plating film formed on the above-mentioned palladium plating film, and the thickness of the above-mentioned strike gold plating film is 2 to 30 nm.

[0043] Furthermore, according to another embodiment of the present invention, a substrate for semiconductor packaging is provided, characterized in that it includes: a copper substrate; a strike gold plating film formed on the above-mentioned copper substrate; a palladium plating film formed on the above-mentioned strike gold plating film; and a gold plating film formed on the above-mentioned palladium plating film, and the thickness of the above-mentioned palladium plating film is 20 to 500 nm.

[0044] Furthermore, according to another embodiment of the present invention, a substrate for semiconductor packaging is provided, characterized in that it includes: a copper substrate; a strike gold plating film formed on the above-mentioned copper substrate; a palladium plating film formed on the above-mentioned strike gold plating film; and a gold plating film formed on the above-mentioned palladium plating film. When the above-mentioned semiconductor packaging substrate is evaluated by the solder diffusion evaluation condition of the following evaluation condition 3, the solder ball diffusion is the solder ball diffusion diameter / solder ball diameter (N), and the diffusion multiple N is 1.2 to 6.

[0045] [Evaluation Condition 3]

[0046] Evaluation by reflowing the solder balls

[0047] Solder ball diameter: 300μm

[0048] Solder ball type: SAC 305 (solder ball containing 96.5 weight percent Sn, 3 weight percent Ag and 0.5 weight percent Cu)

[0049] Reflow conditions: preheat at 130-200°C for 80-120 seconds, then perform bonding (soldering) at 240-260°C for 20-60 seconds

[0050] Furthermore, according to another embodiment of the present invention, a substrate for semiconductor packaging is provided, characterized in that it includes: a copper substrate; a strike gold plating film formed on the above-mentioned copper substrate; a palladium plating film formed on the above-mentioned strike gold plating film; and a gold plating film formed on the above-mentioned palladium plating film. When the bendability of the above-mentioned semiconductor packaging substrate is evaluated by the crack (MIT) evaluation condition of the following evaluation condition 4, the bendability reaches 50 to 180 times after reflow soldering 2 to 5 times.

[0051] [Evaluation Condition 4]

[0052] Bendability testing equipment: MIT-DA / TOYOSEIKI

[0053] Loading: 500g

[0054] Bending speed: 175 times / min

[0055] Bending angle: 135°

[0056] Reflow conditions: preheat at 130-200°C for 80-120 seconds, then perform irreversible thermal aging (heat aging) at 240-260°C for 20-60 seconds.

[0057] Furthermore, according to still another embodiment of the present invention, a semiconductor package including the semiconductor package substrate is provided.

[0058] According to the present invention, since a semiconductor package substrate having a fine pitch-compatible chemical palladium-gold plating layer formed thereon can be provided, fine circuit diffusion is reduced, fine pitches can be easily handled, and cracks are not generated.

[0059] Furthermore, since the present invention provides a semiconductor package including a semiconductor package substrate having a fine pitch-compatible chemical palladium-gold plating layer formed thereon, the semiconductor package has excellent physical properties and is economical.

[0060] The effects of the present invention are not limited to the above effects, and should be understood to include all effects that can be derived from the structure of the invention described in the detailed description of the present invention or the scope of the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] Figure 1 FIG. 4 is a cross-sectional view of a semiconductor package substrate according to an embodiment of the present invention.

[0062] Figure 2FIG. 1 is a scanning electron microscope (SEM) image showing a cross section of a semiconductor package substrate according to an embodiment of the present invention.

[0063] Figure 3 The depth graph of X-ray photoelectron spectroscopy (XPS) is shown to show the cross-sectional analysis and composition analysis of the impact gold plating film of the semiconductor package substrate according to one embodiment of the present invention.

[0064] Figure 4 This is a scanning electron microscope image showing whether or not there is diffusion of the gold plating film when the semiconductor package substrate according to one embodiment of the present invention is used for a fine pitch.

[0065] Figure 5 This is a graph showing the high-speed ball shear strength of a semiconductor package substrate according to an embodiment of the present invention.

[0066] Figure 6 This is a graph showing the lead pull strength of a semiconductor package substrate according to an embodiment of the present invention.

[0067] Figure 7 This is a graph showing solder diffusion properties of a semiconductor package substrate according to an embodiment of the present invention.

[0068] Figure 8 This is a graph showing the bending properties of a semiconductor package substrate according to an embodiment of the present invention, indicating whether or not there are cracks. DETAILED DESCRIPTION

[0069] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0070] References and Attachments Figure 1 The advantages, features and methods of achieving the same will be apparent from the various embodiments described in detail below.

[0071] However, the present invention is not limited to the multiple embodiments disclosed below, and may form a variety of different implementation methods. These embodiments only make the disclosure of the present invention complete, and the purpose is to enable ordinary technicians in the technical field to which the present invention belongs to fully understand the scope of the present invention. The present invention is only defined by the scope of the invention protection claims.

[0072] Furthermore, if it is determined during the description of the present invention that a related known technology or the like may obscure the gist of the present invention, the detailed description thereof will be omitted.

[0073] Hereinafter, the present invention will be described in detail.

[0074] Semiconductor packaging substrate

[0075] The present invention provides a semiconductor packaging substrate having a fine pitch corresponding chemical palladium-gold plating layer.

[0076] The semiconductor packaging substrate of the present invention may include: a copper substrate; a strike gold plating film formed on the copper substrate; a palladium plating film formed on the strike gold plating film; and a gold plating film formed on the palladium plating film. In the semiconductor packaging substrate, the spacing is the sum of the circuit width and the spacing width. When used for fine circuits with a spacing level of 4 to 50 μm, the diffusion of the gold plating film of the semiconductor packaging substrate can be 0.001 to 10 volume percent.

[0077] Since the present invention provides a semiconductor packaging substrate having a fine pitch-compatible chemical palladium-gold plating layer, the fine circuit has less diffusion, is easy to handle fine pitches, and does not generate cracks.

[0078] In the manufacture of electronic components, the step of forming a circuit on a semiconductor wafer is called a front-end process, and the step of assembling the wafer into a state that can be used in an actual product is called a back-end process, or a packaging process.

[0079] In the field of semiconductor packaging, new packaging technologies that are thinner, lighter and shorter have been developed and replaced by wire bonding technology or flip chip bonding technology.

[0080] Among them, wire bonding technology is a method of bonding thin metal wires to pads. That is, it is a technology for connecting the internal chip and the outside. Structurally, the wire acts as a bridge connecting the bonding pads of the chip (primary bonding) and the pads of the carrier (secondary bonding). Currently, the substrate used as the carrier is mainly a printed circuit board.

[0081] Moreover, there are three ways to connect the lead to the pad, namely, a thermal compression method that uses heat to heat and press to connect the bonding pad and a capillary (capillary, a capillary-shaped lead moving tool), a method of applying ultrasound to the capillary for bonding without using heat, and a composite method that uses both heat and ultrasound.

[0082] First, the thermal compression method is as follows, that is, the temperature of the chip bonding pad is raised to about 200°C in advance, and the temperature of the tip (Tip, end) of the splitter is also raised to make the lead into a ball shape, so that the splitter applies pressure to the bonding pad to attach the lead.

[0083] The ultrasonic method is a method in which the lead is punched onto the pad and ultrasonic waves are applied to a wedge (a lead moving tool similar to a wedge, which does not form a ball) to attach the lead to the pad. It has the advantage of low cost in terms of process and material. However, since ultrasonic waves are used instead of heat and pressure, it has the disadvantage of being easy to operate but poor in tensile strength after bonding (the force that the lead can withstand when it is pulled after wiring).

[0084] The most commonly used method in semiconductor processes is the thermosonic method, which combines the advantages of the thermocompression method and the ultrasonic method. Heat, pressure, and ultrasonic waves are applied to the splitter to perform bonding under optimal conditions. Compared with cost, the semiconductor back-end process attaches more importance to the bonding strength, so even though it is expensive, the thermosonic method using gold wire is mainly used.

[0085] In addition, the flip chip bonding technology is a form in which the semiconductor chip is facing downward and the metal protrusions that carry electricity are connected to the pads. Since the flip chip bonding is directed to the substrate without leads, it has the following characteristics, namely, reduced volume, reduced power consumption, reduced peripheral noise influence, fast speed due to the small signal movement distance, and high fixing strength.

[0086] Among them, the materials of metal protrusions mainly use solder (Solder) and gold (Au). Metal protrusions refer to conductive metal protrusions used to connect chips to circuit substrates through tape automated bonding (TAB) and flip chip (FC) methods, or conductive metal protrusions used to directly connect ball grid arrays (BGA) and chip scale packages (CSP) to circuit substrates.

[0087] The solder bumps are formed into spherical shapes by surface tension after the reflow process, and the gold bumps, which are one type of metal bumps, are formed into rectangular shapes with length, width, and height by gold electroplating.

[0088] The wafers with gold bumps will be used for TCP (tape carrier package), COG (Chip on Glass) packaging, and COF (chip on Film) packaging, and will be used in products such as televisions (TV), monitors, networks, mobile devices, tablets, and automotive DIC (Digital Image Correlation).

[0089] Since gold plating is excellent in physical and chemical properties such as conductivity, oxidation resistance, and chemical resistance, it is used for a variety of purposes in microelectronics and optoelectronics fields such as RDL (redistribution layer), pattern plating, conformal via coating, X-ray mask, MEMS (micro-electromechanical system), and gold bumping.

[0090] Currently, although nickel plating is formed on the semiconductor package substrate as described above, nickel plating is difficult to use for fine pitches due to its high plating thickness, cracks may occur due to the poor flexibility of nickel metal, and there is a lot of signal loss at high frequencies due to its magnetic nature.

[0091] Therefore, the applicant has obtained a semiconductor package substrate having a fine pitch corresponding chemical palladium gold plating layer and a semiconductor package including the same after hard work and many studies, thereby completing the present invention.

[0092] In this case, the semiconductor package substrate of the present invention may be a semiconductor package substrate on which no nickel plating layer is formed.

[0093] Therefore, since the semiconductor package substrate does not form a nickel plating layer as a post-film, signal loss is small in high-frequency communication, fine circuit diffusion is small, and it is easy to cope with fine pitches without generating cracks.

[0094] Furthermore, the copper substrate may be a copper metal substrate selected on a printed circuit board.

[0095] In this case, the copper metal substrate selected on the above-mentioned printed circuit board may include copper circuits.

[0096] Furthermore, the oxide film on the surface of the copper substrate can be appropriately removed by a reducing agent.

[0097] Furthermore, the copper substrate may have a thickness of 2 to 30 μm.

[0098] Among them, if the thickness of the above-mentioned copper base material is within the above-mentioned range, it can facilitate the transmission of electrical signals of the above-mentioned semiconductor package substrate.

[0099] In this case, the thickness of the copper substrate may preferably be 5 to 25 μm, and more preferably 5 to 20 μm.

[0100] Furthermore, the thickness of the copper substrate may be the thickness of the copper metal substrate selected on the printed circuit board.

[0101] Furthermore, the thickness of the copper substrate may be the copper thickness of the copper circuit.

[0102] Furthermore, the strike gold plating film formed on the copper substrate may be formed from a strike gold plating composition.

[0103] The above-mentioned strike gold plating composition may be a chemical strike gold plating composition.

[0104] In this case, the above-mentioned electroless strike gold plating composition may include a cyanide gold compound or a non-cyanide gold compound and a purine or pyrimidine compound having a carbonyl oxygen group.

[0105] Furthermore, the strike gold plating film formed on the copper substrate can act as a catalyst for the subsequent formation of a palladium plating film.

[0106] Furthermore, the strike gold plating film formed on the copper substrate can suppress corrosion or voids (microscopic pores between plating layers) of the copper substrate.

[0107] Furthermore, the thickness of the strike gold plating film formed on the copper substrate may be 2 to 30 nm.

[0108] However, if the thickness of the strike gold plating film formed on the copper substrate exceeds the above range, corrosion or voids (microscopic pores between plating layers) of the copper substrate of the semiconductor package substrate may occur.

[0109] In this case, the thickness of the strike gold plating film formed on the copper substrate may preferably be 2 to 28 nm, and more preferably 2 to 25 nm.

[0110] Furthermore, the palladium plating film formed on the strike gold plating film may be formed from a palladium plating composition.

[0111] Wherein, the above palladium plating composition can be a chemical palladium plating composition.

[0112] In this case, the electroless palladium plating composition may include an amine palladium compound, an organic carboxylic acid, and a pyrimidinone compound.

[0113] Furthermore, the palladium plating film formed on the strike gold plating film can suppress erosion or dissolution of the copper substrate, thereby suppressing corrosion.

[0114] Furthermore, the thickness of the palladium plating film formed on the strike gold plating film may be 20 to 500 nm.

[0115] However, if the thickness of the palladium plating film formed on the strike gold plating film exceeds the above range, the copper base material of the semiconductor package substrate may be eroded or dissolved, and corrosion may occur.

[0116] In this case, the thickness of the palladium plating formed on the above-mentioned impact gold plating may preferably be 20 to 450 nm, more preferably 20 to 400 nm, even more preferably 20 to 350 nm, further preferably 20 to 300 nm, further preferably 20 to 250 nm, further preferably 20 to 200 nm, further preferably 20 to 150 nm, and most preferably 20 to 100 nm.

[0117] Furthermore, the gold plating film formed on the palladium plating film may be formed from a gold plating composition.

[0118] The gold plating composition may be a chemical gold plating composition.

[0119] In this case, the electroless gold plating composition may include a cyanide gold compound or a non-cyanide gold compound, a carbonyl amide compound, and a nitrogen-containing heterocarboxylic acid.

[0120] Furthermore, the gold plating film formed on the palladium plating film can play a role in electrically connecting the semiconductor chip to the copper substrate by a wire bonding process or a flip chip bonding process.

[0121] Furthermore, the gold plating film formed on the palladium plating film can suppress erosion or dissolution of the copper substrate, thereby suppressing corrosion.

[0122] Furthermore, the thickness of the gold plating film formed on the palladium plating film may be 20 to 1000 nm.

[0123] However, if the thickness of the gold plating film formed on the palladium plating film exceeds the above range, the copper base material of the semiconductor package substrate may be eroded or dissolved, and corrosion may occur.

[0124] In this case, the thickness of the gold plating film formed on the above-mentioned palladium plating film may preferably be 20 to 950 nm, more preferably 20 to 900 nm, even more preferably 20 to 800 nm, further preferably 20 to 700 nm, further preferably 20 to 600 nm, further preferably 20 to 500 nm, further preferably 20 to 400 nm, further preferably 20 to 300 nm, further preferably 20 to 200 nm, further preferably 20 to 150 nm, and most preferably 20 to 100 nm.

[0125] Figure 1 FIG. 4 is a cross-sectional view of a semiconductor package substrate according to an embodiment of the present invention.

[0126] Reference Figure 1The semiconductor package substrate 100 includes: a strike gold plated film 130 formed on a copper substrate 110; a palladium plated film 150 formed on the strike gold plated film 130; and a gold plated film 170 formed on the palladium plated film.

[0127] Figure 2 FIG. 1 is a scanning electron microscope image showing a cross section of a semiconductor package substrate according to an embodiment of the present invention.

[0128] Reference Figure 2 The semiconductor packaging substrate includes: a strike gold plated film (marked with white between the upper part of Cu and the palladium plated film), formed on a copper substrate (marked as Cu); a palladium plated film (marked as Pd), formed on the above strike gold plated film; and a gold plated film (marked as Au), formed on the above palladium plated film.

[0129] Figure 3 The depth curve diagram of X-ray photoelectron spectroscopy is shown for cross-sectional analysis and composition analysis of an impact gold plating film of a semiconductor package substrate according to an embodiment of the present invention.

[0130] Reference Figure 3 An example of the thickness of the strike gold plating film of the semiconductor package substrate may be 5 to 15 nm.

[0131] Furthermore, in the semiconductor package substrate, the pitch is the sum of the circuit width and the spacing width. When used for fine circuits of 4 to 50 μm pitch level, the diffusion of the gold plating film of the semiconductor package substrate can be 0.001 to 10 volume percent.

[0132] The above-mentioned diffusibility of the gold plating film can be obtained by measuring the diffusion volume in a scanning electron microscope measurement.

[0133] When the diffusibility of the gold plating film is within the above range, the semiconductor package substrate can be used for fine pitches.

[0134] In this case, the diffusivity of the gold plating film may preferably be 0.001 to 9.8 volume percent, and more preferably 0.001 to 9.5 volume percent.

[0135] Figure 4 This is a scanning electron microscope image showing whether or not there is diffusion of the gold plating film when the semiconductor package substrate according to one embodiment of the present invention is used for a fine pitch.

[0136] Reference Figure 4 Flexible chemical nickel gold (ENIG, Electroless Nikel / Immersion Gold; Ni-P 3.0μm / Au 0.05μm) semiconductor packaging substrate with nickel plating can be nickel plated on the PI (polyimide) surface in fine circuits with a pitch of 4 to 50μm.

[0137] On the other hand, the chemical palladium-gold substrate of the present invention, in which the thickness of the palladium plated film formed on the impact gold plated film is 0.1 μm and the thickness of the gold plated film formed on the above palladium plated film is 0.1 μm, can completely eliminate the diffusion of the gold plated film in a fine circuit of 4 to 50 μm pitch level.

[0138] Furthermore, the semiconductor packaging substrate of the present invention may include: a copper substrate; a strike gold plating film formed on the copper substrate; a palladium plating film formed on the strike gold plating film; and a gold plating film formed on the palladium plating film. When the semiconductor packaging substrate is measured by the high-speed ball shear strength evaluation condition 1 below, the high-speed ball shear strength can be 1000 to 1600 gf.

[0139] [Evaluation Condition 1]

[0140] High-speed shearing equipment: Dage 4000HS

[0141] Shear speed: 1m / s

[0142] Shear height: 50μm

[0143] Ball grid array pad diameter: 350μm

[0144] Solder ball diameter: 450μm

[0145] Solder ball type: SAC 305 (solder ball containing 96.5 weight percent Sn, 3 weight percent Ag and 0.5 weight percent Cu)

[0146] Measurement points: n = 25

[0147] The high-speed ball shear strength is used in flip chip bonding technology to evaluate the bonding strength between a semiconductor package substrate and a solder bump.

[0148] Among them, when the above-mentioned semiconductor packaging substrate is measured by the high-speed ball shear strength evaluation condition of the above-mentioned evaluation condition 1, if the above-mentioned high-speed ball shear strength is within the above-mentioned range, the bonding strength between the semiconductor packaging substrate and the solder bump is excellent, so that a good packaging process can be carried out.

[0149] In this case, the high-speed ball shear strength may preferably be 1000 to 1550 gf, more preferably 1000 to 1500 gf, even more preferably 1000 to 1400 gf, and even more preferably 1000 to 1350 gf.

[0150] Figure 5 This is a graph showing the high-speed ball shear strength of a semiconductor package substrate according to an embodiment of the present invention.

[0151] Reference Figure 5 In the above-mentioned evaluation condition 1, the thickness of the palladium plating film formed on the above-mentioned impact gold plating film is 0.05μm and the thickness of the gold plating film formed on the above-mentioned palladium plating film is 0.05μm. The bonding strength between the substrate for semiconductor packaging and the solder protrusion of the chemical palladium gold (EPIG, Electroless Palladium Immersion Gold)-0.05 of the present invention can be 1250~1350gf of high-speed ball shear strength.

[0152] Furthermore, in the above-mentioned evaluation condition 1, the thickness of the palladium plated film formed on the above-mentioned impact gold plated film is 0.10μm and the thickness of the gold plated film formed on the above-mentioned palladium plated film is 0.10μm. The bonding strength between the chemical palladium gold-0.10 semiconductor package substrate of the present invention and the solder protrusion can be a high-speed ball shear strength of 1200 to 1400gf.

[0153] On the other hand, in the evaluation condition 1, the bonding strength between the flexible electroless nickel gold (ENIG, Electroless Nikel Immersion Gold; Ni—P 3.0 μm / Au 0.05 μm) semiconductor package substrate with nickel plating and the solder bump can be a high-speed ball shear strength of 1050 to 1150 gf.

[0154] Furthermore, in the evaluation condition 1, the bonding strength between the organic solderability preservative (OSP, Organic Solderability Preservative; 0.1-0.5 μm) semiconductor package substrate and the solder bump can be a high-speed ball shear strength of 1150-1400 gf.

[0155] Therefore, when the above-mentioned semiconductor packaging substrate of the present invention is measured by the high-speed ball shear strength evaluation condition of the above-mentioned evaluation condition 1, the high-speed ball shear strength is greater than the high-speed ball shear strength of the flexible chemical nickel gold (ENIG, Electroless Nikel Immersion Gold; Ni-P 3.0μm / Au 0.05μm) semiconductor packaging substrate with nickel plating, so the bonding strength between the solder bumps can be better.

[0156] Furthermore, the semiconductor packaging substrate of the present invention may include: a copper substrate; a strike gold plating film formed on the copper substrate; a palladium plating film formed on the strike gold plating film; and a gold plating film formed on the palladium plating film. When the semiconductor packaging substrate is measured by the lead pull strength evaluation condition of the following evaluation condition 2, the lead pull strength is 6 to 14 gf.

[0157] [Evaluation Condition 2]

[0158] Wire Bonder: Wire Bonder—HB16

[0159] Tensile tester: Dage 4000

[0160] Gold wire: 1mil

[0161] Bonding conditions: First bonding point – 300Hz (US), 250ms (time), pressure 250mN; second bonding point – 400Hz (US), 350mls (time), pressure 250mN

[0162] Heat treatment conditions: 175°C, 6 hours

[0163] The wire pull strength is used in wire bonding technology to evaluate the bonding strength between a semiconductor package substrate and a wire.

[0164] Among them, when the above-mentioned semiconductor packaging substrate is measured by the lead pull strength evaluation condition of the above-mentioned evaluation condition 2, after aging heat treatment at a temperature of 175°C for 6 hours, if the above-mentioned lead pull strength is within the above-mentioned range, the bonding strength between the semiconductor packaging substrate and the lead is excellent, and thus a good packaging process can be carried out.

[0165] In this case, the wire pulling strength may preferably be 6 to 13.8 gf, more preferably 6 to 13.5 gf, even more preferably 7 to 13 gf, and even more preferably 7 to 12 gf.

[0166] Figure 6 This is a graph showing the lead pull strength of a semiconductor package substrate according to an embodiment of the present invention.

[0167] Reference Figure 6 In the above evaluation condition 2, the thickness of the gold plating formed on the above impact gold plating is 0.3μm direct chemical gold (DEG, Direct Electroless Gold) -0.3 The bonding strength between the semiconductor packaging substrate and the lead can be 8~12gf of lead pulling strength.

[0168] Furthermore, in the above evaluation condition 2, the bonding strength between the thin film chemical nickel palladium gold (ENEPIG, Electroless Nickel Electroless Palladium Immersion Gold; Ni 0.1-0.3μm / Pd 0.03-0.15μm / Au0.03-0.15μm) semiconductor package substrate and the lead can be 8.5-12gf of lead pull strength.

[0169] Moreover, in the above-mentioned evaluation condition 2, the thickness of the palladium plating film formed on the above-mentioned impact gold plating film is 0.05μm and the thickness of the gold plating film formed on the above-mentioned palladium plating film is 0.05μm. The bonding strength between the chemical palladium gold-0.05 semiconductor packaging substrate and the lead of the present invention can be 8.0~11gf of lead pulling strength.

[0170] Furthermore, in the above-mentioned evaluation condition 2, the thickness of the palladium plating film formed on the above-mentioned impact gold plating film is 0.10μm and the thickness of the gold plating film formed on the above-mentioned palladium plating film is 0.10μm. The bonding strength between the chemical palladium gold-0.10 semiconductor packaging substrate and the lead of the present invention can be a lead pull strength of 9 to 11.5gf.

[0171] Moreover, in the above-mentioned evaluation condition 2, the thickness of the palladium plating film formed on the above-mentioned impact gold plating film is 0.15μm and the thickness of the gold plating film formed on the above-mentioned palladium plating film is 0.15μm. The bonding strength between the chemical palladium gold-0.15 semiconductor packaging substrate and the lead of the present invention can be a lead pull strength of 9.5 to 12gf.

[0172] Therefore, the bonding strength between the semiconductor packaging substrate and the lead of the chemical palladium gold semiconductor packaging substrate of the present invention can be similar to that of direct chemical gold plating and thin film chemical nickel palladium gold, and the bonding strength between the semiconductor packaging substrate and the lead of the chemical palladium gold-0.15 semiconductor packaging substrate of the present invention can be better than that of direct chemical gold plating and thin film chemical nickel palladium gold.

[0173] Furthermore, the semiconductor packaging substrate of the present invention may include: a copper substrate; a strike gold plating film formed on the copper substrate; a palladium plating film formed on the strike gold plating film; and a gold plating film formed on the palladium plating film, and the thickness of the gold plating film may be 20 to 1000 nm.

[0174] Furthermore, the semiconductor package substrate of the present invention may include: a copper substrate; a gold strike plated film formed on the copper substrate; a palladium plated film formed on the gold strike plated film; and a gold plated film formed on the palladium plated film.

[0175] Furthermore, the semiconductor packaging substrate of the present invention may include: a copper substrate; a strike gold plating film formed on the copper substrate; a palladium plating film formed on the strike gold plating film; and a gold plating film formed on the palladium plating film, and the thickness of the strike gold plating film may be 2 to 30 nm.

[0176] The semiconductor packaging substrate of the present invention may include: a copper substrate; a gold strike film formed on the copper substrate; a palladium film formed on the gold strike film; and a gold film formed on the palladium film. The palladium film may have a thickness of 20 to 500 nm.

[0177] In this case, the semiconductor package substrate of the present invention may be a semiconductor package substrate on which no nickel plating layer is formed.

[0178] Therefore, since the semiconductor package substrate does not form a nickel plating layer as a post-film, signal loss is small in high-frequency communication, fine circuit diffusion is small, and it is easy to cope with fine pitches without generating cracks.

[0179] Furthermore, the copper substrate may be a copper metal substrate selected on a printed circuit board.

[0180] In this case, the copper metal substrate selected on the above-mentioned printed circuit board may include copper circuits.

[0181] Furthermore, the oxide film on the surface of the copper substrate can be appropriately removed by a reducing agent.

[0182] Furthermore, the copper substrate may have a thickness of 2 to 30 μm.

[0183] Among them, if the thickness of the above-mentioned copper base material is within the above-mentioned range, it can facilitate the transmission of electrical signals of the above-mentioned semiconductor package substrate.

[0184] In this case, the thickness of the copper substrate may preferably be 5 to 25 μm, and more preferably 5 to 20 μm.

[0185] Furthermore, the thickness of the copper substrate may be the thickness of the copper metal substrate selected on the printed circuit board.

[0186] Furthermore, the thickness of the copper substrate may be the copper thickness of the copper circuit.

[0187] Furthermore, the strike gold plating film formed on the copper substrate may be formed from a strike gold plating composition.

[0188] The above-mentioned strike gold plating composition may be a chemical strike gold plating composition.

[0189] In this case, the above-mentioned electroless strike gold plating composition may include a cyanide gold compound or a non-cyanide gold compound and a purine or pyrimidine compound having a carbonyl oxygen group.

[0190] Furthermore, the strike gold plating film formed on the copper substrate can act as a catalyst for the subsequent formation of a palladium plating film.

[0191] Furthermore, the strike gold plating film formed on the copper substrate can suppress corrosion or voids (fine pores between plating layers) of the copper substrate.

[0192] Furthermore, the thickness of the strike gold plating film formed on the copper substrate may be 2 to 30 nm.

[0193] However, if the thickness of the strike gold plating film formed on the copper base material exceeds the above range, corrosion or voids (microscopic pores between plating layers) of the copper base material of the semiconductor package substrate may occur.

[0194] In this case, the thickness of the strike gold plating film formed on the copper substrate may preferably be 2 to 28 nm, and more preferably 2 to 25 nm.

[0195] Furthermore, the palladium plating film formed on the strike gold plating film may be formed from a palladium plating composition.

[0196] Wherein, the above palladium plating composition can be a chemical palladium plating composition.

[0197] In this case, the electroless palladium plating composition may include an amine palladium compound, an organic carboxylic acid, and a pyrimidinone compound.

[0198] Furthermore, the palladium plating film formed on the strike gold plating film can suppress erosion or dissolution of the copper substrate, thereby suppressing corrosion.

[0199] Furthermore, the thickness of the palladium plating film formed on the strike gold plating film may be 20 to 500 nm.

[0200] However, if the thickness of the palladium plating film formed on the strike gold plating film exceeds the above range, the copper base material of the semiconductor package substrate may be eroded or dissolved, and corrosion may occur.

[0201] In this case, the thickness of the palladium plating formed on the above-mentioned impact gold plating may preferably be 20 to 450 nm, more preferably 20 to 400 nm, even more preferably 20 to 350 nm, further preferably 20 to 300 nm, further preferably 20 to 250 nm, further preferably 20 to 200 nm, further preferably 20 to 150 nm, and most preferably 20 to 100 nm.

[0202] Furthermore, the gold plating film formed on the palladium plating film may be formed from a gold plating composition.

[0203] The gold plating composition may be a chemical gold plating composition.

[0204] In this case, the electroless gold plating composition may include a cyanide gold compound or a non-cyanide gold compound, a carbonyl amide compound, and a nitrogen-containing heterocarboxylic acid.

[0205] Furthermore, the gold plating film formed on the palladium plating film can play a role in electrically connecting the semiconductor chip to the copper substrate by a wire bonding process or a flip chip bonding process.

[0206] Furthermore, the gold plating film formed on the palladium plating film can suppress erosion or dissolution of the copper substrate, thereby suppressing corrosion.

[0207] Furthermore, the thickness of the gold plating film formed on the palladium plating film may be 20 to 1000 nm.

[0208] However, if the thickness of the gold plating film formed on the palladium plating film exceeds the above range, the copper base material of the semiconductor package substrate may be eroded or dissolved, and corrosion may occur.

[0209] In this case, the thickness of the gold plating film formed on the above-mentioned palladium plating film may preferably be 20 to 950 nm, more preferably 20 to 900 nm, even more preferably 20 to 800 nm, further preferably 20 to 700 nm, further preferably 20 to 600 nm, further preferably 20 to 500 nm, further preferably 20 to 400 nm, further preferably 20 to 300 nm, further preferably 20 to 200 nm, further preferably 20 to 150 nm, and most preferably 20 to 100 nm.

[0210] Moreover, the semiconductor packaging substrate of the present invention may include: a copper substrate; a strike gold plating film formed on the above-mentioned copper substrate; a palladium plating film formed on the above-mentioned strike gold plating film; and a gold plating film formed on the above-mentioned palladium plating film. When the above-mentioned semiconductor packaging substrate is evaluated under the solder diffusion evaluation conditions of the following evaluation condition 3, the solder ball diffusion is the solder ball diffusion diameter / solder ball diameter (N), and the diffusion multiple N is 1.2 to 6.

[0211] [Evaluation Condition 3]

[0212] Evaluation by reflowing the solder balls

[0213] Solder ball diameter: 300μm

[0214] Solder ball type: SAC 305 (solder ball containing 96.5 weight percent Sn, 3 weight percent Ag and 0.5 weight percent Cu)

[0215] Reflow conditions: preheat at 130-200°C for 80-120 seconds, then perform bonding (soldering) at 240-260°C for 20-60 seconds

[0216] Furthermore, the above-mentioned solder ball diffusion is used in flip chip bonding technology to evaluate the degree of bonding between a semiconductor package substrate and a solder bump.

[0217] Among them, when the above-mentioned semiconductor packaging substrate is evaluated by the solder diffusion evaluation condition of the above-mentioned evaluation condition 3, the above-mentioned solder ball diffusion is the solder ball diffusion diameter / solder ball diameter (N). If it is within the above-mentioned range, the degree of bonding between the semiconductor packaging substrate and the solder protrusion is excellent, and thus a good packaging process can be carried out.

[0218] In this case, the above-mentioned solder ball diffusion is solder ball diffusion diameter / solder ball diameter (N), the diffusion factor N may preferably be 1.2 to 5.8, the diffusion factor N may more preferably be 1.2 to 5.5, the diffusion factor N may more preferably be 1.2 to 5.3, and the diffusion factor N may further preferably be 1.2 to 5.

[0219] Figure 7 This is a graph showing solder diffusion properties of a semiconductor package substrate according to an embodiment of the present invention.

[0220] Reference Figure 7 In the above evaluation condition 3, the degree of bonding between the organic solderability protective layer (OSP, Organic Solderability Preservative; 0.1~0.5μm) semiconductor package substrate and the solder bump can make the diffusion multiples after 3 reflows. is 2.

[0221] Furthermore, in the evaluation condition 3, the thickness of the gold plating film formed on the above-mentioned impact gold plating film is 0.03 μm, and the degree of bonding between the semiconductor package substrate and the solder bump can be made to diffuse multiples after 3 reflows. is 2.8.

[0222] Furthermore, in the evaluation condition 3, the bonding degree between the common chemical nickel gold (ENIG, Electroless Nikel Immersion Gold; Ni 2.5μm / Au 0.05μm) semiconductor package substrate and the solder bump can be made to diffuse multiples after three reflows. It is 5.2.

[0223] Moreover, in the evaluation condition 3, the bonding degree between the thin film chemical nickel palladium gold (ENEPIG, Electroless Nickel Electroless Palladium Immersion Gold; Ni 0.1~0.3μm / Pd 0.03~0.15μm / Au0.03~0.15μm) semiconductor package substrate and the solder bump can be made to diffuse multiples after 3 reflows. is 4.

[0224] Furthermore, in the evaluation condition 3, the thickness of the palladium plated film formed on the above-mentioned gold plated film is 0.03 μm and the thickness of the gold plated film formed on the above-mentioned palladium plated film is 0.03 μm. The bonding degree between the chemical palladium gold-0.03 semiconductor package substrate of the present invention and the solder bump can be made to diffuse multiples after three reflows. is 4.8.

[0225] Furthermore, in the evaluation condition 3, the thickness of the palladium plated film formed on the above-mentioned strike gold plated film is 0.06 μm and the thickness of the gold plated film formed on the above-mentioned palladium plated film is 0.06 μm. The bonding degree between the chemical palladium gold-0.06 semiconductor package substrate of the present invention and the solder bump can be made to diffuse multiples after 3 reflow soldering. is 4.6.

[0226] Furthermore, in the evaluation condition 3, the thickness of the palladium plated film formed on the above-mentioned gold plated film is 0.10 μm and the thickness of the gold plated film formed on the above-mentioned palladium plated film is 0.10 μm. The bonding degree between the chemical palladium gold-0.10 semiconductor package substrate of the present invention and the solder bump can be made to diffuse multiples after 3 reflows. is 4.4.

[0227] Therefore, before and after reflow, the above-mentioned semiconductor package substrate of the present invention has a diffusion factor of Both aspects show excellent results of diffusion to more than twice the diameter of the solder ball.

[0228] Therefore, when the semiconductor package substrate of the present invention is evaluated under the solder diffusion evaluation condition of the evaluation condition 3, the diffusion factor after three reflows is Greater than the diffusion multiple of organic solderability resist semiconductor package substrate after 3 reflows The bonding degree with the solder bump can be improved.

[0229] Moreover, the semiconductor packaging substrate of the present invention may include: a copper substrate; a strike gold plating film formed on the above copper substrate; a palladium plating film formed on the above strike gold plating film; and a gold plating film formed on the above palladium plating film. When the bendability of the above semiconductor packaging substrate is evaluated by the crack (MIT) evaluation condition of the following evaluation condition 4, the bendability can reach 50 to 180 times after reflow soldering 2 to 5 times.

[0230] [Evaluation Condition 4]

[0231] Bendability testing equipment: MIT-DA / TOYOSEIKI

[0232] Loading: 500g

[0233] Bending speed: 175 times / minute

[0234] Bending angle: 135°

[0235] Reflow conditions: preheat at 130-200°C for 80-120 seconds, then perform irreversible thermal aging (heat aging) at 240-260°C for 20-60 seconds.

[0236] Furthermore, the above-mentioned bendability may be a method of evaluating the presence or absence of cracks by repeatedly bending the semiconductor package substrate.

[0237] When the bendability of the semiconductor package substrate is evaluated by the crack evaluation condition of the evaluation condition 4, if the bendability is within the above range after the reflow process 2 to 5 times, the occurrence of cracks in the semiconductor package substrate can be suppressed.

[0238] In this case, the bendability after the reflow process 2 to 5 times may be preferably 50 to 170 times, more preferably 50 to 160 times, even more preferably 50 to 150 times, and most preferably 50 to 140 times.

[0239] Figure 8 This is a graph showing the bending properties of a semiconductor package substrate according to an embodiment of the present invention, indicating whether or not there are cracks.

[0240] Reference Figure 8 In the above evaluation condition 4, the copper substrate can make the bendability reach 156 times after 5 reflows.

[0241] Furthermore, in the evaluation condition 4, the flexible electroless nickel gold (ENIG, Electroless Nikel Immersion Gold; Ni—P 3.0 μm / Au 0.05 μm) semiconductor package substrate with nickel plating can achieve a bendability of 76 times after 5 reflow cycles.

[0242] Furthermore, in the evaluation condition 4, the direct chemical gold-plated-0.1 semiconductor package substrate of the present invention having a gold plating film having a thickness of 0.1 μm formed on the impact gold plating film can achieve a bendability of 158 times after 5 reflow cycles.

[0243] Moreover, in the above-mentioned evaluation condition 4, the chemical palladium-gold-0.05 semiconductor packaging substrate of the present invention, in which the thickness of the palladium plated film formed on the impact gold plated film is 0.05 μm and the thickness of the gold plated film formed on the above-mentioned palladium plated film is 0.05 μm, can achieve a bendability of 143 times after 5 reflow soldering times.

[0244] Furthermore, in the above-mentioned evaluation condition 4, the chemical palladium-gold-0.10 semiconductor packaging substrate of the present invention, in which the thickness of the palladium plated film formed on the impact gold plated film is 0.10 μm and the thickness of the gold plated film formed on the above-mentioned palladium plated film is 0.10 μm, can achieve a flexibility of 156 times after 5 reflow soldering times.

[0245] Moreover, in the above-mentioned evaluation condition 4, the chemical palladium-gold-0.15 semiconductor packaging substrate of the present invention, in which the thickness of the palladium plated film formed on the impact gold plated film is 0.15 μm and the thickness of the gold plated film formed on the above-mentioned palladium plated film is 0.15 μm, can achieve a flexibility of 157 times after 5 reflow soldering times.

[0246] Therefore, the semiconductor package substrate of the present invention can exhibit extremely soft and crack-free properties.

[0247] Therefore, when the above-mentioned semiconductor packaging substrate of the present invention is evaluated by the crack (MIT) evaluation condition of the above-mentioned evaluation condition 4, the flexibility is greater than that of the flexible chemical nickel gold (ENIG, Electroless Nikel Immersion Gold; Ni-P 2.0μm / Au 0.05μm) semiconductor packaging substrate with nickel plating, and thus the physical properties of the semiconductor packaging substrate of the present invention can be better.

[0248] Semiconductor package including substrate for semiconductor package

[0249] The present invention provides a semiconductor package including a semiconductor package substrate having a fine pitch corresponding chemical palladium-gold plating layer formed therein.

[0250] The present invention provides a semiconductor package including the semiconductor package substrate.

[0251] Since the present invention provides a semiconductor package including a semiconductor package substrate having a fine pitch corresponding chemical palladium gold plating layer, the semiconductor package has excellent physical properties and is economical.

[0252] Hereinafter, the present invention will be described in detail by way of examples. However, the following examples are used to more specifically describe the present invention, and the scope of the present invention is not limited to the following examples. The following examples can be appropriately modified and changed by those skilled in the art within the scope of the present invention.

[0253] Example

[0254] Example 1: Manufacturing a semiconductor packaging substrate having a chemical palladium-gold plating layer

[0255] After degreasing a copper substrate having a thickness of 10 μm (circuit spacing of 25 μm) at a temperature of 45°C for 5 minutes using ACIDCLEAN 620 of MK Chem&Tech as a degreasing liquid, the degreased copper substrate was etched at a temperature of 27°C for 2 minutes using MKS-3000 of MK Chem&Tech as an etching liquid.

[0256] Then, the etched copper substrate was subjected to chemical strike gold plating with a thickness of 6 nm at 80° C. for 3 minutes using a strike gold plating composition containing a cyanide gold compound and a purine compound having carbonyl oxygen (NEOZEN SG from MK Chem&Tech).

[0257] Next, the strike gold plated film was subjected to chemical palladium plating using a palladium plating composition for semiconductor package substrates containing an amine palladium compound, an organic carboxylic acid, and a pyrimidinone compound (NEOZEN EPD from MK Chem & Tech) to form a palladium plated film with a thickness of 0.10 μm.

[0258] The palladium plated film was then electrolessly plated with gold using a gold plating composition for semiconductor package substrates containing a semiconductor cyanide gold compound, a carbonyl amide compound, and a nitrogen-containing heterocarboxylic acid (NEOZEN TG from MK Chem&Tech), thereby manufacturing a semiconductor package substrate having a gold plated film with a thickness of 0.10 μm.

[0259] Example 2-Example 9 Manufacturing a semiconductor packaging substrate having a chemical palladium-gold plating layer

[0260] As shown in Table 1, a semiconductor package substrate having a chemical palladium-gold plating layer was manufactured in the same manner as in Example 1 except for the thickness of the palladium plating film and the thickness of the gold plating film.

[0261] Table 1

[0262]

[0263] Comparative Example

[0264] Comparative Example 1: Manufacturing Highly Flexible Chemical Nickel Gold (ENIG) Semiconductor Packaging Substrate

[0265] A copper substrate having a thickness of 10 μm was degreased at 45° C. for 5 minutes using ACIDCLEAN 620 of MK CHEM&TECH as a degreasing liquid, and then the degreased copper substrate was etched at 27° C. for 2 minutes using MKS-3000 of MK CHEM&TECH as an etching liquid.

[0266] In order to remove the surface residue of the copper substrate after etching, an acid treatment was performed using a 10 wt % sulfuric acid aqueous solution at a temperature of 25° C. for 1 minute.

[0267] Thereafter, palladium catalysis was performed at 27° C. for 2 minutes using CATA-NC20 catalyst produced by MK CHEM&TECH, and post-treatment was performed at 27° C. for 2 minutes using POST-DIP PR produced by MK CHEM&TECH.

[0268] Next, NEOZEN SPF-K, a highly flexible chemical nickel plating chemical produced by MK CHEM&TECH, was used to perform a treatment at 83°C for 20 minutes to increase the Ni thickness to 2 to 4 μm. IG-10, an alternative gold plating chemical produced by MK CHEM&TECH, was used to perform a treatment at 80°C for 7 minutes to produce a highly flexible chemical nickel-gold semiconductor packaging substrate with an Au (gold) thickness of 0.03 to 0.05 μm.

[0269] Comparative Example 2: Manufacturing of an Organic Solderability Preservative (OSP) Semiconductor Packaging Substrate

[0270] A copper substrate having a thickness of 10 μm was degreased at 45° C. for 20 seconds using ACIDCLEAN LF-T from MK CHEM&TECH as a degreasing liquid, and then the degreased copper substrate was etched at 27° C. for 30 seconds using MKS-1200 from MK CHEM&TECH as an etching liquid.

[0271] In order to remove the surface residue of the copper substrate after etching, an acid treatment was performed at a temperature of 25° C. for 30 seconds using a 5 wt % sulfuric acid aqueous solution.

[0272] Then, the substrate was treated at 40° C. for 2 minutes using Glicoat SMD F2 (LX) manufactured by Shikoku Chemical Co., Ltd., Japan, to manufacture an organic solderability resist (OSP) semiconductor package substrate having a thickness of 0.1 to 0.4 μm.

[0273] Comparative Example 3: Manufacturing of Thin Film Chemical Nickel Palladium Gold (ENEPIG) Semiconductor Packaging Substrate

[0274] A copper substrate having a thickness of 10 μm was degreased at 45° C. for 5 minutes using ACIDCLEAN 620 of MK CHEM&TECH as a degreasing liquid, and then the degreased copper substrate was etched at 27° C. for 2 minutes using MKS-3000 of MK CHEM&TECH as an etching liquid.

[0275] In order to remove the surface residue of the etched copper substrate, an acid treatment was performed using a 10 wt % sulfuric acid aqueous solution at a temperature of 25° C. for 1 minute.

[0276] Thereafter, palladium catalysis was performed at 27° C. for 2 minutes using CATA-NC20 catalyst produced by MK CHEM&TECH, and post-treatment was performed at 27° C. for 2 minutes using POST-DIP PR produced by MK CHEM&TECH.

[0277] Next, NEOZEN MP-K, an electroless nickel plating chemical of MK CHEM&TECH, was used to perform a treatment at 83°C for 1 minute to increase the Ni thickness to 0.15 to 0.3 μm, and FLASH GOLD IG-10, an alternative gold plating chemical of MK CHEM&TECH, was used to perform a treatment at 80°C for 7 minutes to manufacture a thin film electroless nickel palladium gold (ENEPIG) semiconductor packaging substrate with an Au thickness of 0.03 to 0.05 μm.

[0278] Comparative Example 4: Manufacturing of a Conventional Electroless Nickel-Gold (ENIG) Semiconductor Packaging Substrate

[0279] A copper substrate having a thickness of 10 μm was degreased at 45° C. for 5 minutes using ACIDCLEAN 620 of MK CHEM&TECH as a degreasing liquid, and then the degreased copper substrate was etched at 27° C. for 2 minutes using MKS-3000 of MK CHEM&TECH as an etching liquid.

[0280] In order to remove the surface residue of the copper substrate after etching, an acid treatment was performed using a 10 wt % sulfuric acid aqueous solution at a temperature of 25° C. for 1 minute.

[0281] Thereafter, palladium catalysis was performed at 27° C. for 2 minutes using CATA-NC20 catalyst produced by MK CHEM&TECH, and post-treatment was performed at 27° C. for 2 minutes using POST-DIP PR produced by MK CHEM&TECH.

[0282] Next, NEOZEN MP-K, a rigid chemical nickel plating chemical of MK CHEM&TECH, was used to perform a treatment at 83°C for 20 minutes to increase the Ni thickness to 2 to 4 μm, and FLASH GOLD IG-10, an alternative gold plating chemical of MK CHEM&TECH, was used to perform a treatment at 80°C for 7 minutes to manufacture a conventional chemical nickel-gold semiconductor packaging substrate with an Au thickness of 0.03 to 0.05 μm.

[0283] Experimental example

[0284] Experimental Example 1: Cross-sectional analysis of a semiconductor package substrate having a chemical palladium-gold plating layer

[0285] like Figure 2 As shown, the cross section of the semiconductor package substrate on which the chemical palladium-gold plating layer was formed in Example 1 was measured by a scanning electron microscope (SEM).

[0286] The thickness of the palladium plated film was measured to be 0.10 μm, and the thickness of the gold plated film was measured to be 0.10 μm.

[0287] Furthermore, it is shown that no nickel plating is used.

[0288] Experimental Example 2 Measurement of the Thickness of the Impact Plating Film on a Semiconductor Package Substrate with a Chemical Palladium-Gold Plating Layer

[0289] like Figure 3 As shown, in the semiconductor package substrates having the chemical palladium gold plating layer formed thereon in Examples 1 to 9, the thickness of the impact gold plating film was measured by X-ray photoelectron spectroscopy (XPS).

[0290] The thickness of the strike gold plating film was measured to be 0.004 to 0.010 μm.

[0291] Experimental Example 3: Diffusion Measurement

[0292] In order to determine the diffusion properties of the gold coating, Figure 4 As shown, the surface of the semiconductor package substrate on which the chemical palladium-gold plating layer was formed in Example 1 was measured by a scanning electron microscope (SEM).

[0293] Among them, the above-mentioned Example 1 has no diffusivity at all.

[0294] And, if Figure 4 As shown, the surface of the highly flexible chemical nickel gold (ENIG) semiconductor package substrate of the above-mentioned Comparative Example 1 was measured by a scanning electron microscope (SEM).

[0295] The comparative example 1 exhibits a diffusivity of 70 to 100 volume percent.

[0296] Therefore, unlike the highly flexible ENIG semiconductor package substrate of Comparative Example 1, the semiconductor package substrate having the chemical palladium gold plating layer formed thereon according to Example 1 of the present invention exhibits almost no diffusibility.

[0297] Experimental Example 4 High-speed ball shear strength measurement

[0298] In order to determine the high-speed ball shear strength of semiconductor packaging substrates, such as Figure 5As shown, the semiconductor package substrates having the chemical palladium-gold plating layer formed thereon in Examples 1 and 3 were measured under the high-speed ball shear strength evaluation condition of the following evaluation condition 1.

[0299] [Evaluation Condition 1]

[0300] High-speed shearing equipment: Dage 4000HS

[0301] Shear speed: 1m / s

[0302] Shear height: 50μm

[0303] Ball grid array (BGA) pad diameter: 350μm

[0304] Solder Ball Diameter: 450μm

[0305] Solder ball type: SAC 305 (solder ball containing 96.5 weight percent Sn, 3 weight percent Ag and 0.5 weight percent Cu)

[0306] Measurement points: n = 25

[0307] The high-speed ball shear strength of the semiconductor package substrates having the chemical palladium-gold plating layer formed thereon in the above-mentioned Examples 1 and 3 is 1150 to 1450 gf.

[0308] On the other hand, when measured under the same high-speed ball shear strength evaluation condition of the above-mentioned evaluation condition 1, the high-speed ball shear strength of the high-flexibility chemical nickel gold (ENIG) semiconductor package substrate of the above-mentioned comparative example 1 was reduced to 900 to 1250 gf.

[0309] Furthermore, when measured under the same high-speed ball shear strength evaluation condition of the evaluation condition 1, the high-speed ball shear strength of the organic solderability resist (OSP) semiconductor package substrate of the comparative example 2 was reduced to 1150 to 1500 gf.

[0310] Experimental Example 5: Measurement of Lead Pull Strength

[0311] In order to determine the lead pull strength of semiconductor packaging substrates, such as Figure 6 As shown, the semiconductor package substrates having the chemical palladium-gold plating layer formed thereon in Examples 1, 3, and 6 were measured under the following evaluation condition 2 for lead pull strength evaluation.

[0312] [Evaluation Condition 2]

[0313] Wire Bonder: Wire Bonder-HB16

[0314] Tensile tester: Dage 4000

[0315] Gold wire: 1mil

[0316] Bonding conditions: first bonding point – 300 Hz (US), 250 ms (time), pressure 250 mN;

[0317] Second bond point – 400Hz (US), 350mls (time), pressure 250mN

[0318] Heat treatment conditions: 175°C, 6 hours

[0319] The lead pull strength of the semiconductor package substrates having the chemical palladium-gold plating layer formed thereon in the above-mentioned Examples 1, 3 and 6 was 7.5 to 12 gf after aging at a temperature of 150° C. for 12 hours.

[0320] On the other hand, when measured by the same lead pull strength evaluation condition of the above-mentioned evaluation condition 2, the lead pull strength of the thin film chemical nickel palladium gold (ENEPIG) semiconductor package substrate of the above-mentioned comparative example 3 was 8.5 to 11.8 gf after aging for 12 hours.

[0321] Experimental Example 6: Measurement of solder diffusion

[0322] In order to determine the solder diffusion properties of semiconductor packaging substrates, such as Figure 7 As shown, the semiconductor package substrates having the chemical palladium-gold plating layer formed thereon in Examples 1, 2, and 4 were evaluated under the solder diffusibility evaluation condition of the following evaluation condition 3.

[0323] [Evaluation Condition 3]

[0324] Evaluation by reflowing the solder balls

[0325] Solder ball diameter: 300μm

[0326] Solder ball type: SAC 305 (solder ball containing 96.5 weight percent Sn, 3 weight percent Ag and 0.5 weight percent Cu)

[0327] Reflow conditions: preheat at 130-200°C for 80-120 seconds, then perform bonding (soldering) at 240-260°C for 20-60 seconds

[0328] The solder diffusivity of the semiconductor package substrate with chemical palladium-gold plating in Example 1 is solder ball diffusion diameter / solder ball diameter (N). Before reflow, the diffusion factor N is 4.7, and after reflow 3 times, the diffusion factor N is 4.5.

[0329] Moreover, the solder diffusivity of the semiconductor package substrate formed with the chemical palladium gold plating layer in the above-mentioned Example 2 is solder ball diffusion diameter / solder ball diameter (N). Before reflow, the diffusion factor N is 4.9, and after reflow 3 times, the diffusion factor N is 4.8.

[0330] Furthermore, the solder diffusivity of the semiconductor package substrate having the chemical palladium-gold plating layer in the fourth embodiment is solder ball diffusion diameter / solder ball diameter (N). Before reflow, the diffusion factor N is 4.8, and after reflow 3 times, the diffusion factor N is 4.6.

[0331] That is, the semiconductor package substrates on which the chemical palladium-gold plating layer is formed in the above-mentioned Examples 1, 2, and 4 have excellent solder diffusivity.

[0332] On the other hand, when evaluated under the same solder diffusion evaluation conditions of the above-mentioned evaluation condition 3, the solder diffusion of the organic solderability protective layer (OSP) semiconductor packaging substrate of the above-mentioned comparison example 2 is the solder ball diffusion diameter / solder ball diameter (N). Before reflow soldering, the diffusion factor N is 2.0. After reflow soldering 3 times, the diffusion factor N is greatly reduced to 2.0.

[0333] Moreover, when evaluated by the same solder diffusion evaluation conditions of the above-mentioned evaluation condition 3, the solder diffusion of the thin film chemical nickel palladium gold (ENEPIG) semiconductor packaging substrate of the above-mentioned comparison example 3 is the solder ball diffusion diameter / solder ball diameter (N). Before reflow soldering, the diffusion factor N is 4.0, and after reflow soldering 3 times, the diffusion factor N is 3.8.

[0334] Furthermore, when evaluated using the same solder diffusion evaluation conditions of the above-mentioned evaluation condition 3, the solder diffusion of the ordinary chemical nickel gold (ENIG) semiconductor packaging substrate of the above-mentioned comparison example 4 is solder ball diffusion diameter / solder ball diameter (N). Before reflow soldering, the diffusion factor N is 5.4, and after reflow soldering 3 times, the diffusion factor N is 5.2.

[0335] Experimental Example 7: Bendability Measurement

[0336] In order to measure the bending property of semiconductor packaging substrates, Figure 8 As shown, the bendability of the semiconductor package substrates having the chemical palladium-gold plating layer formed thereon in Examples 1, 3, and 6 was evaluated under the following evaluation condition 4 for crack (MIT) evaluation.

[0337] [Evaluation Condition 4]

[0338] Bendability testing equipment: MIT-DA / TOYOSEIKI

[0339] Loading: 500g

[0340] Bending speed: 175 times / minute

[0341] Bending angle: 135°

[0342] Reflow conditions: preheat at 130-200°C for 80-120 seconds, then perform irreversible thermal aging (heat aging) at 240-260°C for 20-60 seconds.

[0343] The bendability of the semiconductor package substrate having the chemical palladium-gold plating layer in the first embodiment was 138 times before reflow, but increased to 158 times after reflow.

[0344] The bendability of the semiconductor package substrate on which the chemical palladium-gold plating layer was formed in the above-mentioned Example 3 reached 137 times before reflow soldering, but increased to 143 times after reflow soldering.

[0345] The bendability of the semiconductor package substrate on which the chemical palladium-gold plating layer was formed in Example 6 was 140 times before reflow, but increased to 159 times after reflow.

[0346] Therefore, the semiconductor package substrates on which the chemical palladium-gold plating layer is formed in the above-mentioned Examples 1, 3, and 6 have very excellent bendability.

[0347] On the other hand, the bendability of the highly flexible ENIG semiconductor package substrate of Comparative Example 1 reached 134 times before reflow, but sharply decreased to 74 times after reflow.

[0348] Although specific embodiments of the semiconductor package substrate and the semiconductor package including the same according to the present invention have been described above, it is needless to say that various modifications may be made without departing from the scope of the present invention.

[0349] Therefore, the scope of the present invention is not limited to the described embodiments, but should be determined by the appended claims and the scope equivalent to the claims.

[0350] That is, the described embodiments are illustrative at all levels and should be understood as non-restrictive. The scope of the present invention is presented by the attached invention protection scope rather than detailed description, and should be interpreted as all changes or modified embodiments derived from the meaning, scope and equivalent concepts of the invention protection scope are included in the scope of the present invention.

Claims

1. A semiconductor packaging substrate, characterized in that: include: Copper substrate; impact gold plating, formed on the copper substrate; A palladium coating formed on the above-mentioned impact gold coating; as well as The gold plating film is formed on the above-mentioned palladium plating film.

2. The semiconductor package substrate according to claim 1, wherein: In the above semiconductor package substrate, the pitch is the sum of the circuit width and the spacing width. When used for fine circuits at a pitch level of 4 to 50 μm, the gold plating film diffusivity of the semiconductor packaging substrate is 0.001 to 10 volume percent.

3. The semiconductor package substrate according to claim 1, wherein: When the semiconductor package substrate is measured under the high-speed ball shear strength evaluation condition of the following evaluation condition 1, the high-speed ball shear strength is 1000 to 1600 gf. Evaluation Condition 1: High-speed shearing equipment: Dage 4000HS Shear speed: 1m / s Shear height: 50μm Ball grid array pad diameter: 350μm Solder ball diameter: 450μm Solder ball type: SAC 305, a solder ball containing 96.5 weight percent tin, 3 weight percent silver, and 0.5 weight percent copper Measurement points: n=25.

4. The semiconductor package substrate according to claim 1, wherein: When the semiconductor package substrate is measured under the following evaluation condition 2 for lead pull strength, the lead pull strength is 6 to 14 gf. Evaluation condition 2: Wire Bonder: Wire Bonder-HB16 Tensile tester: Dage 4000 Gold wire: 1mil Bonding conditions: First bonding point – frequency 300Hz, time 250ms, pressure 250mN; second bonding point – frequency 400Hz, time 350mls, pressure 250mN Heat treatment conditions: 175°C, 6 hours.

5. The semiconductor package substrate according to claim 1, wherein: The thickness of the gold plating film is 20 to 1000 nm.

6. The semiconductor package substrate according to claim 1, wherein: The thickness of the above-mentioned impact gold plating film is 2 to 30 nm.

7. The semiconductor package substrate according to claim 1, wherein: The thickness of the palladium plated film is 20 to 500 nm.

8. The semiconductor package substrate according to claim 1, wherein: When the semiconductor package substrate is evaluated under the solder diffusion evaluation condition of the following evaluation condition 3, the solder ball diffusion is solder ball diffusion diameter / solder ball diameter (N), and the diffusion factor N is 1.2 to 6. Evaluation Condition 3: Evaluation by reflowing the solder balls Solder ball diameter: 300μm Solder ball type: SAC 305, a solder ball containing 96.5 weight percent tin, 3 weight percent silver and 0.5 weight percent copper Reflow conditions: preheat at 130-200°C for 80-120 seconds, then perform bonding, i.e. soldering, at 240-260°C for 20-60 seconds.

9. The semiconductor package substrate according to claim 1, wherein: When the bendability of the semiconductor package substrate is evaluated by the crack evaluation condition of the following evaluation condition 4, the bendability reaches 50 to 180 times after 2 to 5 reflows. Evaluation Condition 4: Bendability testing equipment: MIT-DA / Toyo Seiki Loading: 500g Bending speed: 175 times / minute Bending angle: 135° Reflow conditions: preheat at 130-200°C for 80-120 seconds, followed by irreversible thermal aging at 240-260°C for 20-60 seconds.

10. A semiconductor package, characterized in that: A semiconductor package substrate according to any one of claims 1 to 9 is included.

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