Heat dissipation control method and device for triode packaging and storage medium

By setting up a multi-layer independently controlled heat dissipation structure outside the transistor and actively regulating heat dissipation based on heat prediction and mode analysis, the problem of poor heat dissipation efficiency and balance of the transistor is solved, and efficient and balanced heat dissipation control is achieved.

CN119542284AActive Publication Date: 2025-02-28SHENZHEN CHANGHAO MICROELECTRONICS CO LTD
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Patent Information

Application Number
CN202411778147.3
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2024-12-05
Publication Date
2025-02-28
Estimated Expiration
2044-12-05

AI Technical Summary

Technical Problem

In the prior art, the thermal efficiency and balance of transistors are poor, and lack active regulation, making it difficult to meet the complex thermal management needs of high-power and high-density integrated circuits.

Method used

A multi-layer heat dissipation structure is provided outside the transistor, including a heat sink layer, a first heat dissipation channel layer and a second heat dissipation channel layer, each heat dissipation layer being independently controlled. By collecting package control parameters to predict heat, determine whether it exceeds the preset heat index, start the joint channel heat dissipation command, conduct joint heat dissipation mode analysis, obtain the joint heat dissipation mode, and perform heat dissipation control according to the mode.

Benefits of technology

It has achieved improvement of heat dissipation efficiency, ensured balanced heat dissipation, and provided active heat dissipation regulation, solving the problem of poor efficiency and balance of traditional heat dissipation methods.

✦ Generated by Eureka AI based on patent content.

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Abstract

The invention discloses a heat dissipation control method and device for triode packaging and a storage medium, and relates to the technical field of semiconductors, and the method comprises the steps: arranging a multi-layer heat dissipation structure composed of a heat dissipation fin layer, a first heat dissipation channel layer and a second heat dissipation channel layer outside a triode, and enabling each heat dissipation layer to be independently controlled; collecting packaging control parameters of the triode; performing heat prediction according to the packaging control parameter, and outputting a first predicted heat index; judging whether the first predicted heat index is greater than or equal to a preset heat index, and if yes, starting a combined channel heat dissipation instruction; performing heat dissipation mode conjoint analysis on the first predicted heat index in the multi-layer heat dissipation structure according to the joint channel heat dissipation instruction to obtain a joint heat dissipation mode; and performing heat dissipation control on the triodes according to the combined heat dissipation mode. Therefore, the technical effects of improving heat dissipation efficiency, ensuring heat dissipation balance and providing active heat dissipation regulation and control are achieved.
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Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a heat dissipation control method, device and storage medium for transistor packaging. Background Art

[0002] As a commonly used semiconductor device, the transistor generates a lot of heat when it is working. If the heat dissipation is not timely or uniform, it will cause the transistor to overheat, thus affecting its performance and lifespan and even causing damage.

[0003] Traditional heat dissipation technology mainly relies on simple heat sinks and heat dissipation channels. However, as the power of transistors increases and the working environment becomes more complicated, traditional heat dissipation methods gradually show their limitations, especially in high-power, high-density integrated circuits. A single heat dissipation path often cannot meet complex heat management requirements. There are technical problems such as poor heat dissipation efficiency and balance, and lack of active regulation. Summary of the invention

[0004] The present invention provides a heat dissipation control method, device and storage medium for transistor packaging to solve the technical problems of poor heat dissipation efficiency and balance and lack of active regulation in the prior art, and achieve the technical effects of improving heat dissipation efficiency, ensuring heat dissipation balance and providing active heat dissipation regulation.

[0005] In a first aspect, the present invention provides a heat dissipation control method for a transistor package, wherein the method comprises: A multi-layer heat dissipation structure is arranged outside the triode, wherein the multi-layer heat dissipation structure comprises a heat sink layer, a first heat dissipation channel layer and a second heat dissipation channel layer, and each heat dissipation layer is independently controlled.

[0006] The packaging control parameters of the transistor are collected.

[0007] Heat prediction is performed according to the packaging control parameters, and a first predicted heat index is output.

[0008] It is determined whether the first predicted heat index is greater than or equal to a preset heat index, and if the first predicted heat index is greater than or equal to the preset heat index, a joint channel heat dissipation instruction is started.

[0009] According to the joint channel heat dissipation instruction, a heat dissipation mode joint analysis is performed on the first predicted heat index in the multi-layer heat dissipation structure to obtain a joint heat dissipation mode.

[0010] Heat dissipation of the transistor is controlled according to the combined heat dissipation mode.

[0011] In a second aspect, the present invention further provides a heat dissipation control device for a transistor package, wherein the device comprises: A multi-layer heat dissipation configuration module is used to set a multi-layer heat dissipation structure outside the triode, wherein the multi-layer heat dissipation structure includes a heat sink layer, a first heat dissipation channel layer and a second heat dissipation channel layer, and each heat dissipation layer is independently controlled.

[0012] A packaging control parameter acquisition module, wherein the packaging control parameter acquisition module is used to acquire packaging control parameters of the transistor.

[0013] A heat generation prediction module is used to perform heat generation prediction according to the packaging control parameters and output a first predicted heat index.

[0014] A heat determination module is used to determine whether the first predicted heat index is greater than or equal to a preset heat index, and if the first predicted heat index is greater than or equal to the preset heat index, a joint channel heat dissipation instruction is started.

[0015] A heat dissipation mode analysis module is used to perform a heat dissipation mode joint analysis on the first predicted heat index in the multi-layer heat dissipation structure according to the joint channel heat dissipation instruction to obtain a joint heat dissipation mode.

[0016] A heat dissipation control module is used to control the heat dissipation of the transistor according to the combined heat dissipation mode.

[0017] In a third aspect, the present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the data security management method based on privacy computing provided by the present invention.

[0018] The present invention discloses a heat dissipation control method, device and storage medium for transistor packaging, including: arranging a multi-layer heat dissipation structure outside the transistor, including a heat sink layer, a first heat dissipation channel layer and a second heat dissipation channel layer, wherein each heat dissipation layer can be independently controlled; collecting packaging control parameters of the transistor; performing heat prediction according to the packaging control parameters, and outputting a first predicted heat index; judging whether the first predicted heat index is greater than or equal to a preset heat index, and if so, starting a joint channel heat dissipation instruction; performing a heat dissipation mode joint analysis on the first predicted heat index in the multi-layer heat dissipation structure according to the joint channel heat dissipation instruction, and obtaining a joint heat dissipation mode; and controlling the heat dissipation of the transistor according to the joint heat dissipation mode. The heat dissipation control method, device and storage medium for transistor packaging disclosed by the present invention solve the technical problems of poor heat dissipation efficiency and balance, and lack of active regulation, and achieve the technical effects of improving heat dissipation efficiency, ensuring heat dissipation balance, and providing active heat dissipation regulation. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a flow chart of the heat dissipation control method of the triode package of the present invention; Figure 2 It is a structural schematic diagram of the heat dissipation control device of the triode package of the present invention; Figure 3 A schematic diagram of the structure of a computer-readable storage medium provided by the present invention.

[0020] Explanation of the reference numerals: multi-layer heat dissipation configuration module 11 , packaging control parameter acquisition module 12 , heat generation prediction module 13 , heat determination module 14 , heat dissipation mode analysis module 15 , heat dissipation control module 16 , computer readable storage medium 600 , computer program 611 . DETAILED DESCRIPTION

[0021] The technical solution provided in the embodiments of the present invention is to solve the technical problems of poor heat dissipation efficiency and balance and lack of active regulation in the prior art. The overall idea adopted is as follows: First, a multi-layer heat dissipation structure is arranged outside the triode, wherein the multi-layer heat dissipation structure includes a heat sink layer, a first heat dissipation channel layer and a second heat dissipation channel layer, and each heat dissipation layer is independently controlled; then, the packaging control parameters of the triode are collected; then, heat prediction is performed according to the packaging control parameters, and a first predicted heat index is output; then, it is determined whether the first predicted heat index is greater than or equal to a preset heat index, and if the first predicted heat index is greater than or equal to the preset heat index, a joint channel heat dissipation instruction is started; then, according to the joint channel heat dissipation instruction, a heat dissipation mode joint analysis is performed on the first predicted heat index in the multi-layer heat dissipation structure to obtain a joint heat dissipation mode; finally, heat dissipation control of the triode is performed according to the joint heat dissipation mode.

[0022] The above technical solution will be described in detail below in conjunction with the accompanying drawings and specific implementation methods of the specification to better understand the above technical solution. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments of the present invention. It should be understood that the present invention is not limited to the example embodiments used only to explain the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. In addition, it should be noted that, for the convenience of description, only the parts related to the present invention are shown in the drawings, rather than all of them. Example 1

[0023] Figure 1 The figure is a flow chart of a heat dissipation control method for a transistor package according to the present invention, wherein the method comprises: A multi-layer heat dissipation structure is arranged outside the triode, wherein the multi-layer heat dissipation structure comprises a heat sink layer, a first heat dissipation channel layer and a second heat dissipation channel layer, and each heat dissipation layer is independently controlled.

[0024] Specifically, a multi-layer heat dissipation structure is first configured for the target transistor, and the multi-layer heat dissipation structure is arranged on the outer surface of the transistor or on the package, and includes a heat sink layer, a first heat dissipation channel layer and a second heat dissipation channel layer.

[0025] In some embodiments, the heat dissipation efficiency of the heat sink layer is lower than the heat dissipation efficiency of the first heat dissipation channel layer, and the heat dissipation efficiency of the first heat dissipation channel layer is lower than the heat dissipation efficiency of the second heat dissipation channel layer.

[0026] Specifically, the heat sink layer, the first heat dissipation channel layer and the second heat dissipation channel layer have a stepped configuration of heat dissipation capabilities, wherein the heat dissipation efficiency of the heat sink layer is the lowest, the heat dissipation efficiency of the second heat dissipation channel layer is the highest, and the heat dissipation efficiency of the first heat dissipation channel layer is between the above two. The multi-layer heat dissipation structure with the above stepped configuration helps to provide sufficient control space for flexible heat dissipation control of the target transistor.

[0027] Specifically, each level of heat dissipation channel has different characteristic parameters, corresponding to different heat dissipation efficiencies, wherein the characteristic parameters of the heat dissipation channel include material, shape and area, channel width and height, surface roughness, convection velocity, etc. Exemplarily, each level of heat dissipation channel corresponds to heat dissipation parameters of different dimensions. For the heat sink layer, it mainly involves material (thermal conductivity and heat capacity), shape, area, surface roughness, etc.; while for the first heat dissipation channel layer and the second heat dissipation channel layer, it includes material thermal conductivity, heat capacity, channel width, height, designed convection velocity, etc., and the first heat dissipation channel layer and the second heat dissipation channel layer have different configurations (such as different working fluid convection velocities, different channel designs, different material selections, etc.).

[0028] The packaging control parameters of the transistor are collected.

[0029] Specifically, the packaging control parameters of the transistor involve specific quantitative parameters of the target transistor in dimensions such as packaging form, packaging material, and electrical performance; by collecting the packaging control parameters, an important basis is provided for the subsequent accurate prediction of the heat generation of the transistor under different working conditions.

[0030] Exemplarily, the packaging control parameters include: thermal conductivity of the packaging material, which affects the efficiency of heat conduction through the packaging material; thermal expansion coefficient, that is, the expansion characteristics of the material when the temperature changes, which affects thermal stress and packaging integrity; packaging structure parameters, such as size and shape (affecting the heat dissipation area and path), number of layers and thickness (affecting the heat conduction path), etc.; thermal conductivity of the thermal interface material (affecting the heat conduction efficiency between the chip and the heat sink), thickness and uniformity (affecting thermal resistance and heat dissipation performance), etc.; electrical properties of the transistor, such as power consumption, heat density, heat distribution, etc.

[0031] Heat prediction is performed according to the packaging control parameters, and a first predicted heat index is output.

[0032] Specifically, the packaging control parameters are combined with the existing mathematical model of physical properties related to heat conduction to conduct heat generation and heat distribution of the target transistor to obtain a first predicted heat index, which is the basis for subsequent heat dissipation decisions.

[0033] In some embodiments, performing heat prediction according to the packaging control parameter and outputting a first predicted heat index comprises: Construct a thermal conduction model based on the transistor; collect the real-time working status of the transistor; input the packaging control parameter and the real-time working status into the thermal conduction model to simulate the thermal conduction loss, and output a thermal conduction simulation data set; predict the heat loss based on the thermal conduction simulation data set, and output a first predicted heat index.

[0034] Specifically, first, a heat conduction model is constructed based on the finite element analysis (FEA) method; then, the real-time working status of the target transistor is obtained, including the working voltage, current, characteristic frequency, base parameters, etc.; then, according to the packaging material, structural parameters and thermal interface material characteristics in the packaging control parameters, combined with the real-time working status of the transistor, the model parameters of the above heat conduction model are set, and boundary conditions such as ambient temperature and airflow conditions are defined to ensure that the heat conduction model can accurately reflect the real-time status of the target transistor; then, the heat conduction model is run to simulate the loss in the heat conduction process and generate a heat conduction simulation data set.

[0035] Specifically, the heat conduction simulation data set is analyzed to identify the main sources of heat loss, that is, which parts of the transistor (such as contact surfaces and internal structures) generate the most heat, and the heat loss mode is determined, such as the load mode, frequency mode, time mode, etc. corresponding to the heat loss; the identification result is defined as the first predicted heat index. In other words, the heat loss of the target transistor corresponds to the heat generation of the target transistor. Preferably, the first predicted heat index is the average heat loss of the target transistor package.

[0036] It is determined whether the first predicted heat index is greater than or equal to a preset heat index, and if the first predicted heat index is greater than or equal to the preset heat index, a joint channel heat dissipation instruction is started.

[0037] Specifically, the first predicted thermal index is compared with the preset thermal index, which is determined based on the maximum heat dissipation capacity of a single heat dissipation channel of the target transistor package. In other words, the preset thermal index defines the maximum thermal index of a single heat dissipation channel of the target transistor package while ensuring the safe operation of the transistor, wherein the passive heat dissipation capacity can be determined through experiments or simulations, and the preset thermal index corresponds to the most unfavorable environment.

[0038] In some embodiments, determining whether the first predicted heat index is greater than or equal to a preset heat index, the method further includes: If the first predicted heat index is less than the preset heat index, a single-channel heat dissipation instruction is started; according to the single-channel heat dissipation instruction, a heat dissipation pattern matching analysis is performed on the first predicted heat index in the multi-layer heat dissipation structure to obtain a heat sink layer or a first heat dissipation channel layer or a second heat dissipation channel layer; heat dissipation of the transistor is controlled according to the heat sink layer or the first heat dissipation channel layer or the second heat dissipation channel layer.

[0039] Specifically, the first predicted heat index is compared with the preset heat index. If the first predicted heat index is less than the preset heat index, it can be considered that single-channel heat dissipation is sufficient to meet the heat dissipation requirements and ensure the safe operation of the transistor, and the single-channel heat dissipation instruction can be started.

[0040] Specifically, through a single-channel heat dissipation instruction, a heat dissipation pattern matching analysis is performed in the multi-layer heat dissipation structure, and the heat dissipation efficiency of the multi-layer heat dissipation structure is matched according to the first predicted heat index, and the one of the heat sink layer, the first heat dissipation channel layer or the second heat dissipation channel layer that meets the first predicted heat index and has the lowest heat dissipation efficiency is determined as the most suitable heat dissipation layer, and the heat dissipation of the transistor is effectively controlled through the selected heat sink layer or heat dissipation channel layer.

[0041] According to the joint channel heat dissipation instruction, a heat dissipation mode joint analysis is performed on the first predicted heat index in the multi-layer heat dissipation structure to obtain a joint heat dissipation mode.

[0042] Specifically, if the first predicted heat index is greater than or equal to the preset heat index, it means that the current heat generation of the transistor is relatively high, and the single-channel heat dissipation cannot meet the heat dissipation requirements. To ensure the safe operation of the transistor, the joint channel heat dissipation instruction is started, and the heat dissipation decision analysis is performed through the joint channel heat dissipation instruction to obtain the corresponding joint heat dissipation mode.

[0043] Exemplarily, the joint heat dissipation mode is used to define a specific heat dissipation strategy for the joint heat dissipation, such as selecting a heat dissipation layer for the joint heat dissipation, specific heat dissipation control parameters, and the like.

[0044] In some embodiments, according to the joint channel heat dissipation instruction, a heat dissipation mode joint analysis is performed on the first predicted heat index in the multi-layer heat dissipation structure to obtain a joint heat dissipation mode, and the method includes: Calculate the heat dissipation performance index of each heat dissipation layer in the multi-layer heat dissipation structure; obtain a first thermal coupling coefficient and a second thermal coupling coefficient in the multi-layer heat dissipation structure, wherein the first thermal coupling coefficient is the degree of mutual influence between the heat sink layer and the first heat dissipation channel layer, and the second thermal coupling coefficient is the degree of mutual influence between the first heat dissipation channel layer and the second heat dissipation channel layer; construct a joint heat dissipation mode optimization model according to the heat dissipation performance index of each heat dissipation layer, the first thermal coupling coefficient and the second thermal coupling coefficient; perform a joint heat dissipation mode joint analysis on the first predicted heat index according to the joint heat dissipation mode optimization model to obtain a joint heat dissipation mode.

[0045] Specifically, joint heat dissipation analysis and decision-making are performed according to the joint channel heat dissipation instructions. First, the heat dissipation performance indicators of multiple heat dissipation layers are evaluated and calculated through the characteristic parameters of each heat dissipation layer, such as surface heat dissipation coefficient, thermal resistance, thermal conductivity, etc.

[0046] Specifically, since multiple heat dissipation layers work together on the same transistor package, when multiple heat dissipation layers in different combinations are used together, the internal temperature field of the target transistor will cause different changes, such as temperature distribution, temperature gradients of various interfaces, etc.; therefore, it is necessary to analyze the degree of mutual influence between the heat sink layer and the first heat dissipation channel layer, and the degree of mutual influence between the first heat dissipation channel layer and the second heat dissipation channel layer, respectively, to determine the first thermal coupling coefficient and the second thermal coupling coefficient.

[0047] For example, when multiple heat dissipation layers are used in combination, the improvement in heat dissipation capacity will cause the temperature gradient of each heat transfer interface of the transistor package to change, thereby causing a change in the heat transfer gradient force, and thus resulting in a difference in heat dissipation efficiency and heat dissipation characteristics between the combined use of multiple heat dissipation layers and the use of a single heat dissipation layer under the same predicted thermal index. For example, when multiple heat dissipation layers are used in combination, the heat dissipation capacity is improved, and the surface temperature of the transistor package decreases, resulting in a smaller temperature gradient and a smaller heat transfer gradient force, thereby reducing the heat flux when the multiple heat dissipation layers are used in combination. At this time, it can be considered that the heat dissipation capacity per unit area of ​​the multiple heat dissipation layers used in combination is reduced compared to when used alone; at the same time, different combinations of heat dissipation layers have different effects on each other when used in combination.

[0048] Optionally, the first thermal coupling coefficient and the second thermal coupling coefficient are obtained by experimental measurement or simulation calculation, such as by modeling through thermal network analysis or finite element method to evaluate the heat transfer path and thermal coupling strength between each layer.

[0049] Furthermore, based on the heat dissipation performance index and the thermal coupling coefficient, an optimization model is constructed to find the optimal heat dissipation mode, wherein, exemplarily, the input variables are the heat dissipation performance index of each heat dissipation layer, the first thermal coupling coefficient and the second thermal coupling coefficient, and the first predicted thermal index; the optimization goal is to minimize the total thermal resistance of the model system or to maximize the total heat dissipation efficiency of the model system; the constraints are the physical limitations of each heat dissipation layer (such as material properties, geometric dimensions) and the heat balance equation of the model system.

[0050] Specifically, the first predicted heat index is used as input and substituted into the joint heat dissipation mode optimization model, and then the synergy between different heat dissipation layers is analyzed through the optimization algorithm to determine the optimal joint heat dissipation mode, and the output is the optimization result, wherein the specific strategy of the joint heat dissipation mode includes the combination method of each heat dissipation layer, the corresponding working state (such as the surface treatment method of the heat sink layer, the fluid flow rate distribution of the first channel and the second channel, etc.), the heat flux distribution of the heat dissipation path, etc.

[0051] Through the above method, based on the heat dissipation performance index and thermal coupling coefficient of the multi-layer heat dissipation structure, a joint heat dissipation mode optimization model is constructed, and the first predicted heat index is jointly analyzed to obtain the optimal heat dissipation mode, effectively improve the heat dissipation efficiency under complex heat load conditions, and ensure the stable operation of the transistor.

[0052] In some implementations, performing a joint analysis of the cooling modes on the first predicted heat index according to the joint cooling mode optimization model to obtain a joint cooling mode includes: According to the multi-layer heat dissipation structure, a combination is performed to output a joint heat dissipation mode solution space, wherein the joint heat dissipation mode solution space includes multiple solutions, and each solution corresponds to a joint heat dissipation mode; minimizing the first predicted heat index is taken as the first optimization goal, and minimizing the sum of energy consumption of the joint heat dissipation mode is taken as the second optimization goal, optimization is performed in the joint heat dissipation mode solution space, an optimal solution that meets the first optimization goal and the second optimization goal is obtained, and a joint heat dissipation mode is output.

[0053] Specifically, first, a joint heat dissipation mode solution space is generated according to all possible combinations of multi-layer heat dissipation structures. Each solution of the joint heat dissipation mode solution space corresponds to a specific heat dissipation mode and contains combination information of the multi-layer heat dissipation structure, such as the working status and parameter configuration of the heat sink layer, the first heat dissipation channel layer and the second heat dissipation channel layer; wherein the scale of the joint heat dissipation mode solution space depends on the number of heat dissipation layers and the parameter degrees of freedom of each layer.

[0054] Specifically, the first optimization goal is to minimize the first predicted heat index, so as to ensure that the heat distribution of the transistor package meets the heat dissipation requirements and reduce the heat load of key nodes; at the same time, the second optimization goal is to minimize the energy consumption, which is secondary, that is, under the premise of ensuring that the heat dissipation requirements are met, the total energy consumption of the heat dissipation system is reduced as much as possible, including the surface treatment or active cooling power consumption of the heat sink, and the pumping power consumption of the fluid in the heat dissipation channel; through the combination of the first optimization goal and the second optimization goal, the comprehensive optimization of the heat dissipation effect is ensured.

[0055] Optionally, the first optimization objective and the second optimization objective are combined in the following ways: assigning a weight to each objective through a weighted summation method, and combining the two objectives into a comprehensive optimization objective; and finding an optimal solution set that satisfies both objectives through a Pareto optimization method.

[0056] Specifically, based on the size of the solution space of the joint cooling mode, different optimization algorithms are selected. Exemplarily, exhaustive search is suitable for situations where the solution space is small, that is, traversing all possible solutions to find the optimal solution; heuristic algorithms are suitable for situations where the solution space is large, such as genetic algorithms, particle swarm optimization or simulated annealing algorithms.

[0057] By constructing a solution space for joint cooling modes, and taking minimizing the first predicted heat index and minimizing energy consumption as the optimization goals, and performing multi-objective optimization in the solution space, we can find a joint cooling mode that meets the cooling requirements and has the lowest energy consumption, and achieve efficient cooling control decisions.

[0058] Heat dissipation of the transistor is controlled according to the combined heat dissipation mode.

[0059] Furthermore, according to the joint heat dissipation mode, the corresponding multiple heat dissipation layers are activated for joint heat dissipation, and heat dissipation control is performed, including adjusting the fluid flow rate in the first heat dissipation channel and / or the second heat dissipation channel, increasing or decreasing the circulation rate of the coolant, and selecting a suitable coolant type (such as water or thermal oil) to match the current heat demand.

[0060] Preferably, temperature sensors and other monitoring devices are used to collect temperature data of the transistors in real time, and the operating status of the cooling system is monitored, including fan speed, coolant flow rate and power consumption; if the heat load of the transistor changes, such as an increase in workload or an increase in ambient temperature, or the transistor temperature approaches the allowable upper limit, a more efficient cooling mode is dynamically switched, and in the case of low load, when the transistor temperature is below the target range or the energy consumption is too high, a low energy consumption mode is switched to save resources, and a low power cooling mode is switched to reduce unnecessary energy consumption.

[0061] By controlling the heat dissipation of the transistors through the combined heat dissipation mode, the heat dissipation requirements of the transistors can be efficiently met in a complex working environment, while achieving energy saving and reliability goals.

[0062] In some embodiments, a gas isolation layer is provided between the heat sink layer and the first heat dissipation channel layer, and the method further comprises: Determine whether the combined heat dissipation mode is the combined heat dissipation of the heat sink layer and the first heat dissipation channel layer; if the combined heat dissipation mode is the combined heat dissipation of the heat sink layer and the first heat dissipation channel layer, perform heat dissipation control on the transistor according to the combined heat dissipation mode while starting the gas isolation layer for auxiliary heat dissipation control.

[0063] Specifically, the gas isolation layer is arranged between the heat sink layer and the first heat dissipation channel layer. The heat transfer efficiency between the heat sink layer and the first heat dissipation channel layer can be adjusted through the gas isolation layer. Then, in the high heat demand scenario, the gas isolation layer is used as an auxiliary heat dissipation control means to further improve the heat dissipation efficiency.

[0064] Specifically, when it is determined that the heat sink layer and the first heat dissipation channel layer are in a joint heat dissipation mode, the gas isolation layer is started to perform auxiliary heat dissipation control, wherein the start conditions include: the transistor temperature is close to a preset threshold (for example, exceeding 80% of the safe temperature range), the synergistic heat dissipation effect of the heat sink layer and the first heat dissipation channel layer is not sufficient to quickly reduce the temperature, and environmental factors (such as high temperature or decreased efficiency of the heat dissipation channel fluid) cause the heat dissipation capacity to decrease.

[0065] Specifically, the control method of the gas isolation layer includes adjusting the flow rate of the gas, adjusting the pressure of the gas isolation layer, etc.

[0066] By setting a gas isolation layer between the heat sink layer and the first heat dissipation channel layer, and starting the gas isolation layer in the combined heat dissipation mode for auxiliary heat dissipation control, the heat dissipation regulation range and control flexibility of the transistor can be significantly improved, thereby ensuring that the transistor temperature is always within a safe range and improving the reliability of heat dissipation.

[0067] In summary, the heat dissipation control method for transistor packaging provided by the present invention has the following technical effects: By setting a multi-layer heat dissipation structure outside the triode, including a heat sink layer, a first heat dissipation channel layer and a second heat dissipation channel layer, each heat dissipation layer can be independently controlled; collecting the packaging control parameters of the triode; performing heat prediction according to the packaging control parameters, and outputting a first predicted heat index; judging whether the first predicted heat index is greater than or equal to the preset heat index, if so, starting the joint channel heat dissipation instruction; performing a joint analysis of the heat dissipation mode of the first predicted heat index in the multi-layer heat dissipation structure according to the joint channel heat dissipation instruction, and obtaining a joint heat dissipation mode; and controlling the heat dissipation of the triode according to the joint heat dissipation mode. Thus, the technical effects of improving heat dissipation efficiency, ensuring heat dissipation balance, and providing active heat dissipation regulation are achieved. Example 2

[0068] Figure 2 Schematic diagram of the heat dissipation control device of the triode package of the present invention. Figure 1 The flow chart of the heat dissipation control method of the transistor package of the present invention can be shown as follows: Figure 2 The structure shown is implemented.

[0069] Based on the same concept as the heat dissipation control method of the transistor package in the above embodiment, the present invention also provides a heat dissipation control device for the transistor package, including: The multi-layer heat dissipation configuration module 11 is used to set a multi-layer heat dissipation structure outside the triode, wherein the multi-layer heat dissipation structure includes a heat sink layer, a first heat dissipation channel layer and a second heat dissipation channel layer, and each heat dissipation layer is independently controlled.

[0070] The packaging control parameter acquisition module 12 is used to acquire the packaging control parameters of the transistor.

[0071] The heat generation prediction module 13 is used to perform heat generation prediction according to the packaging control parameters and output a first predicted heat index.

[0072] The heat determination module 14 is used to determine whether the first predicted heat index is greater than or equal to a preset heat index, and if the first predicted heat index is greater than or equal to the preset heat index, start a joint channel heat dissipation instruction.

[0073] The heat dissipation mode analysis module 15 is used to perform a heat dissipation mode joint analysis on the first predicted heat index in the multi-layer heat dissipation structure according to the joint channel heat dissipation instruction to obtain a joint heat dissipation mode.

[0074] The heat dissipation control module 16 is used to control the heat dissipation of the transistor according to the combined heat dissipation mode.

[0075] The heat generation prediction module 13 includes: The heat conduction model building unit is used to build a heat conduction model based on the transistor.

[0076] The real-time working status acquisition unit is used to acquire the real-time working status of the transistor.

[0077] The heat conduction loss simulation unit is used to input the packaging control parameters and the real-time working status into the heat conduction model to simulate the heat conduction loss and output a heat conduction simulation data set.

[0078] The heat loss prediction unit is used to predict heat loss based on the heat conduction simulation data set and output a first predicted heat index.

[0079] In some embodiments, the heat determination module 14 includes: The monitoring and comparing unit is used to start a single-channel heat dissipation instruction if the first predicted heat index is less than the preset heat index.

[0080] A startup instruction unit is used to perform a heat dissipation pattern matching analysis on the first predicted heat index in the multi-layer heat dissipation structure according to the single-channel heat dissipation instruction to obtain a heat sink layer or a first heat dissipation channel layer or a second heat dissipation channel layer.

[0081] A heat dissipation mode matching analysis unit is used to control the heat dissipation of the triode according to the heat sink layer or the first heat dissipation channel layer or the second heat dissipation channel layer.

[0082] Furthermore, the heat dissipation efficiency of the heat sink layer is less than the heat dissipation efficiency of the first heat dissipation channel layer, and the heat dissipation efficiency of the first heat dissipation channel layer is less than the heat dissipation efficiency of the second heat dissipation channel layer. In some embodiments, the heat dissipation mode analysis module 15 includes: The heat dissipation performance index calculation unit is used to calculate the heat dissipation performance index of each heat dissipation layer in the multi-layer heat dissipation structure.

[0083] A thermal coupling coefficient acquisition unit is used to acquire a first thermal coupling coefficient and a second thermal coupling coefficient in the multi-layer heat dissipation structure, wherein the first thermal coupling coefficient is the degree of mutual influence between the heat sink layer and the first heat dissipation channel layer, and the second thermal coupling coefficient is the degree of mutual influence between the first heat dissipation channel layer and the second heat dissipation channel layer.

[0084] The joint heat dissipation mode optimization model construction unit is used to construct a joint heat dissipation mode optimization model according to the heat dissipation performance index of each heat dissipation layer, the first thermal coupling coefficient and the second thermal coupling coefficient.

[0085] The joint heat dissipation mode analysis unit is used to perform a joint heat dissipation mode analysis on the first predicted heat index according to the joint heat dissipation mode optimization model to obtain a joint heat dissipation mode.

[0086] In some implementations, the joint heat dissipation mode analysis unit in the heat dissipation mode analysis module 15 includes: The joint heat dissipation mode solution space output unit is used to combine the multi-layer heat dissipation structure and output the joint heat dissipation mode solution space, wherein the joint heat dissipation mode solution space includes multiple solutions, each solution corresponds to a joint heat dissipation mode.

[0087] An optimization target setting and execution unit is used to minimize the first predicted heat index as the first optimization target, minimize the sum of the energy consumption of the joint cooling mode as the second optimization target, perform optimization in the joint cooling mode solution space, obtain an optimal solution that meets the first optimization target and the second optimization target, and output the joint cooling mode.

[0088] In some embodiments, a gas isolation layer is provided between the heat sink layer and the first heat dissipation channel layer, and the device further comprises: The combined heat dissipation mode judging unit is used to judge whether the combined heat dissipation mode is the combined heat dissipation of the heat sink layer and the first heat dissipation channel layer.

[0089] The auxiliary heat dissipation control start unit is used to start the gas isolation layer to perform auxiliary heat dissipation control while controlling the heat dissipation of the transistor according to the joint heat dissipation mode if the heat sink layer and the first heat dissipation channel layer jointly dissipate heat. Example 3

[0090] Figure 3 Schematic diagram of an embodiment of a computer-readable storage medium provided by the present invention. Figure 3 As shown, this embodiment provides a computer-readable storage medium 600, on which a computer program 611 is stored. When the computer program 611 is executed by a processor, the following steps are implemented: a multi-layer heat dissipation structure is set outside the triode, wherein the multi-layer heat dissipation structure includes a heat sink layer, a first heat dissipation channel layer, and a second heat dissipation channel layer, and each heat dissipation layer is independently controlled; the packaging control parameters of the triode are collected; heat prediction is performed according to the packaging control parameters, and a first predicted heat index is output; it is determined whether the first predicted heat index is greater than or equal to a preset heat index, and if the first predicted heat index is greater than or equal to the preset heat index, a joint channel heat dissipation instruction is started; according to the joint channel heat dissipation instruction, a heat dissipation mode joint analysis is performed on the first predicted heat index in the multi-layer heat dissipation structure to obtain a joint heat dissipation mode; and heat dissipation control of the triode is performed according to the joint heat dissipation mode.

[0091] It should be understood that the embodiments mentioned in this specification focus on their differences from other embodiments. The specific embodiments in the aforementioned embodiment one are also applicable to the heat dissipation control device for transistor package described in embodiment two. For the sake of brevity of the specification, they will not be further expanded here.

[0092] It should be understood that the embodiments disclosed in the present invention and the above description can enable those skilled in the art to use the present invention to implement the present invention. At the same time, the present invention is not limited to the above-mentioned embodiments. It should be understood that those skilled in the art can still modify the technical solutions recorded in the above-mentioned embodiments, or replace some of the technical features therein by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the protection scope of the present invention.

Claims

1. A heat dissipation control method for transistor packaging, characterized in that: The method comprises: A multi-layer heat dissipation structure is arranged outside the triode, wherein the multi-layer heat dissipation structure includes a heat sink layer, a first heat dissipation channel layer and a second heat dissipation channel layer, and each heat dissipation layer is independently controlled; Collecting packaging control parameters of the transistor; Perform heat prediction according to the packaging control parameter and output a first predicted heat index; Determining whether the first predicted heat index is greater than or equal to a preset heat index, and if the first predicted heat index is greater than or equal to the preset heat index, starting a joint channel heat dissipation instruction; According to the joint channel heat dissipation instruction, performing a heat dissipation mode joint analysis on the first predicted heat index in the multi-layer heat dissipation structure to obtain a joint heat dissipation mode; Heat dissipation of the transistor is controlled according to the combined heat dissipation mode.

2. The method according to claim 1, characterized in that Determining whether the first predicted heat index is greater than or equal to a preset heat index, the method further includes: If the first predicted heat index is less than the preset heat index, starting a single-channel cooling instruction; According to the single-channel heat dissipation instruction, a heat dissipation pattern matching analysis is performed on the first predicted heat index in the multi-layer heat dissipation structure to obtain a heat sink layer or a first heat dissipation channel layer or a second heat dissipation channel layer; Heat dissipation of the transistor is controlled according to the heat sink layer or the first heat dissipation channel layer or the second heat dissipation channel layer.

3. The method according to claim 1, characterized in that The heat dissipation efficiency of the heat sink layer is lower than that of the first heat dissipation channel layer, and the heat dissipation efficiency of the first heat dissipation channel layer is lower than that of the second heat dissipation channel layer.

4. The method according to claim 1, characterized in that Performing heat prediction according to the packaging control parameter and outputting a first predicted heat index, the method includes: Constructing a heat conduction model based on the triode; Collecting the real-time working status of the triode; Inputting the packaging control parameters and the real-time working status into the heat conduction model to simulate heat conduction loss, and outputting a heat conduction simulation data set; Heat loss prediction is performed based on the heat conduction simulation data set, and a first predicted heat index is output.

5. The method according to claim 1, characterized in that According to the joint channel heat dissipation instruction, a heat dissipation mode joint analysis is performed on the first predicted heat index in the multi-layer heat dissipation structure to obtain a joint heat dissipation mode, the method comprising: Calculating the heat dissipation performance index of each heat dissipation layer in the multi-layer heat dissipation structure; Obtaining a first thermal coupling coefficient and a second thermal coupling coefficient in the multi-layer heat dissipation structure, wherein the first thermal coupling coefficient is the degree of mutual influence between the heat sink layer and the first heat dissipation channel layer, and the second thermal coupling coefficient is the degree of mutual influence between the first heat dissipation channel layer and the second heat dissipation channel layer; Constructing a joint heat dissipation mode optimization model according to the heat dissipation performance index of each heat dissipation layer, the first thermal coupling coefficient and the second thermal coupling coefficient; A joint heat dissipation mode joint analysis is performed on the first predicted heat index according to the joint heat dissipation mode optimization model to obtain a joint heat dissipation mode.

6. The method according to claim 5, characterized in that The method includes: performing a joint analysis of the heat dissipation mode on the first predicted heat index according to the joint heat dissipation mode optimization model to obtain a joint heat dissipation mode. Combining the multi-layer heat dissipation structure, outputting a joint heat dissipation mode solution space, wherein the joint heat dissipation mode solution space includes multiple solutions, each solution corresponding to a joint heat dissipation mode; Taking minimizing the first predicted heat index as the first optimization goal and minimizing the sum of the energy consumption of the joint cooling mode as the second optimization goal, optimization is performed in the joint cooling mode solution space to obtain an optimal solution that meets the first optimization goal and the second optimization goal, and the joint cooling mode is output.

7. The method according to claim 1, characterized in that A gas isolation layer is provided between the heat sink layer and the first heat dissipation channel layer; Determine whether the combined heat dissipation mode is combined heat dissipation of the heat sink layer and the first heat dissipation channel layer; If the heat sink layer and the first heat dissipation channel layer jointly dissipate heat, the heat dissipation of the transistor is controlled according to the joint heat dissipation mode, and at the same time, the gas isolation layer is started to perform auxiliary heat dissipation control.

8. A heat dissipation control device for transistor packaging, characterized in that: The device is used to execute the heat dissipation control method of the transistor package according to any one of claims 1 to 7, and the device comprises: A multi-layer heat dissipation configuration module, which is used to set a multi-layer heat dissipation structure outside the triode, wherein the multi-layer heat dissipation structure includes a heat sink layer, a first heat dissipation channel layer and a second heat dissipation channel layer, and each heat dissipation layer is independently controlled; A packaging control parameter acquisition module, wherein the packaging control parameter acquisition module is used to acquire packaging control parameters of the transistor; A heat generation prediction module, the heat generation prediction module is used to perform heat generation prediction according to the packaging control parameter and output a first predicted heat index; a heat determination module, the heat determination module being used to determine whether the first predicted heat index is greater than or equal to a preset heat index, and if the first predicted heat index is greater than or equal to the preset heat index, starting a joint channel heat dissipation instruction; a heat dissipation mode analysis module, the heat dissipation mode analysis module being used to perform a heat dissipation mode joint analysis on the first predicted heat index in the multi-layer heat dissipation structure according to the joint channel heat dissipation instruction to obtain a joint heat dissipation mode; A heat dissipation control module is used to control the heat dissipation of the transistor according to the combined heat dissipation mode.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the heat dissipation control method for a transistor package according to any one of claims 1 to 7 is implemented.

Citation Information

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