Semiconductor device, high-frequency device, and method for manufacturing same

Abstract

The invention relates to a semiconductor device, a high-frequency device and a manufacturing method thereof. The invention provides a semiconductor device capable of realizing adjustment of characteristics. A semiconductor device (100) is provided with: a conductive base (11); a first chip and a second chip mounted on the base; and a first bonding wire (32) that electrically connects the first chip and the second chip and transmits a high-frequency signal, the susceptor having a first opening (15) that passes through the susceptor in the thickness direction and that overlaps at least a portion of the first bonding wire without interposing a conductor layer when viewed from the thickness direction of the susceptor.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, a high-frequency device, and a method for manufacturing the same. Background Art

[0002] It is known that a plurality of chips including a semiconductor chip are mounted on a conductive base, and the plurality of chips are electrically connected to each other using bonding wires (for example, Patent Document 1).

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2018-113284

[0006] Patent Document 2: Japanese Patent Application Publication No. 2003-318329

[0007] Patent Document 3: Japanese Patent Application Publication No. 2012-104792

[0008] The characteristics may be different due to the difference in height and length of the bonding wires that electrically connect the chips to each other. In this case, it is difficult to adjust the characteristics. Summary of the invention

[0009] The present disclosure has been made in view of the above-mentioned problems, and an object of the present disclosure is to enable adjustment of characteristics.

[0010] One embodiment of the present disclosure is a semiconductor device comprising: a conductive base; a first chip and a second chip mounted on the base; and a first bonding wire electrically connecting the first chip and the second chip to transmit a high-frequency signal, wherein the base has a first opening that penetrates in the thickness direction and overlaps with at least a portion of the first bonding wire without a conductive layer when viewed from the thickness direction of the base.

[0011] Effects of the Invention

[0012] According to the present disclosure, adjustment of characteristics can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is a top view of the semiconductor device of Example 1.

[0014] Figure 2 yes Figure 1 A-A section view.

[0015] Figure 3 This is a circuit diagram of a set of semiconductor devices in the first embodiment.

[0016] Figure 4This is a top view of the high-frequency device of Example 1.

[0017] Figure 5 yes Figure 4 A-A section view.

[0018] Figure 6 4 is a cross-sectional view of a high-frequency device of Comparative Example 1.

[0019] Figure 7 This is a cross-sectional view showing Example 1 of the high-frequency device of Example 1.

[0020] Figure 8 It is a cross-sectional view showing Example 2 of the high-frequency device of Example 1.

[0021] Fig. 9 1 is a flowchart showing a method for manufacturing a high-frequency device according to the first embodiment.

[0022] Fig.10 It is a top view of the semiconductor device of Example 2.

[0023] Fig.11 This is a circuit diagram of a set of semiconductor devices in Example 2.

[0024] Fig.12 It is a top view of the semiconductor device of Example 3.

[0025] Fig.13 It is a cross-sectional view of the high-frequency device of Example 3.

[0026] Fig.14 This is a circuit diagram of a set of semiconductor devices in Example 3.

[0027] Description of reference numerals:

[0028] 10: Lead frame

[0029] 11: Base

[0030] 11a, 11b, 11c, 11d, 11e: Partial

[0031] 12, 13: Terminal

[0032] 14: Resin layer

[0033] 15, 15a, 45, 45a: Open

[0034] 16: Set

[0035] 18: Matching circuit

[0036] 20: Semiconductor chips

[0037] 21, 26, 26a: substrate

[0038] 22, 23, 24, 27, 27a, 28, 28a: Electrodes

[0039] 25, 25a: Passive component chips

[0040] 31, 32, 33, 34: Bonding line

[0041] 35, 36: Bonding layer

[0042] 39: Reference potential surface

[0043] 40, 48, 49, 49a: Conductor layer

[0044] 41, 41a, 41b: Ground layer

[0045] 42, 43: Signal line

[0046] 50a, 50b, 50c: mounting substrate

[0047] 100, 101, 102, 110: Semiconductor devices

[0048] 105, 106, 107, 108, 112: high frequency devices. DETAILED DESCRIPTION

[0049] [Description of Embodiments of the Present Disclosure]

[0050] First, the contents of the embodiments of the present disclosure will be listed and described.

[0051] (1) One embodiment of the present disclosure is a semiconductor device comprising: a conductive base; a first chip and a second chip mounted on the base; and a first bonding wire electrically connecting the first chip and the second chip to transmit a high-frequency signal, wherein the base has a first opening that penetrates in the thickness direction and overlaps with at least a portion of the first bonding wire without a conductive layer when viewed from the thickness direction of the base. Thus, the characteristics of the first bonding wire can be adjusted, and the characteristics of the semiconductor device can be adjusted.

[0052] (2) In the above (1), the semiconductor device may include: a first terminal provided outside the base; a second terminal provided outside the base; a second bonding wire electrically connecting the first terminal to the first chip; and a third bonding wire electrically connecting the second terminal to the second chip. Thus, the characteristics of the first bonding wire provided between the first terminal and the second terminal can be adjusted.

[0053] (3) In the above (2), the first chip may be a semiconductor chip having a transistor, and the transistor amplifies a high-frequency signal input to the first terminal or the second terminal and outputs the amplified high-frequency signal to the second terminal or the first terminal. Thus, the characteristics of the inductor connected to the transistor can be adjusted.

[0054] (4) In the above (3), the second chip may include a dielectric substrate and an electrode provided on the dielectric substrate, a capacitor is formed between the electrode and the base, and the first bonding wire and the third bonding wire are connected to the electrode. Thus, the characteristics of the inductor connected to the semiconductor chip in the T-type circuit of the LCL can be adjusted.

[0055] (5) In the above (4), the second chip, the first bonding wire, and the third bonding wire may form a matching circuit that matches the impedance when the second terminal looks at the third bonding wire with the impedance when the first bonding wire looks at the semiconductor chip. This allows the characteristics of the matching circuit of the transistor to be adjusted.

[0056] (6) In the above (1), the semiconductor device may include a third chip mounted on the base, the semiconductor device having: a first terminal provided outside the base; a second terminal provided outside the base; a second bonding wire electrically connecting the first terminal to the first chip; a third bonding wire electrically connecting the second chip to the third chip; and a fourth bonding wire electrically connecting the second terminal to the third chip, the base having a second opening that penetrates in the thickness direction and overlaps with at least a portion of the third bonding wire without a conductive layer when viewed from the thickness direction of the base. Thus, the characteristics of the first bonding wire and the third bonding wire can be independently adjusted.

[0057] (7) In the above (6), the first chip may be a semiconductor chip having a transistor that amplifies a high-frequency signal input to the first terminal or the second terminal and outputs the amplified high-frequency signal to the second terminal or the first terminal, the second chip may include a first dielectric substrate and a first electrode provided on the first dielectric substrate, a first capacitor is formed between the first electrode and the base, the first bonding wire and the third bonding wire are connected to the first electrode, and the third chip may include a second dielectric substrate and a second electrode provided on the second dielectric substrate, a second capacitor is formed between the second electrode and the base, and the third bonding wire and the fourth bonding wire are connected to the second electrode. Thus, the characteristics of the first bonding wire and the third bonding wire can be adjusted independently.

[0058] (8) In any one of the above (1) to (7), the semiconductor device may include a resin layer provided on the base to seal the first chip, the second chip, and the first bonding wire. This allows the shape characteristics of the first bonding wire, which cannot be finely adjusted, to be adjusted.

[0059] (9) One embodiment of the present disclosure is a high-frequency device comprising: the semiconductor device of any one of (1) to (8); and a mounting substrate comprising an insulating substrate and a first conductive layer, the first conductive layer being provided on the insulating substrate and carrying the semiconductor device, and the first conductive layer having a third opening, at least a portion of the third opening overlapping at least a portion of the first opening without interposing the conductive layer when viewed in the thickness direction of the insulating substrate. Thus, the characteristics of the first bonding wire can be adjusted.

[0060] (10) In the above (9), the high-frequency device may include: a second conductive layer provided on a surface of the insulating substrate opposite to the first conductive layer, and overlapping the third opening without interposing the conductive layer when viewed in the thickness direction of the insulating substrate. This allows the characteristics of the first bonding wire to be adjusted.

[0061] (11) In the above (9), the high-frequency device may include: a third conductive layer provided inside the insulating substrate and overlapping the third opening without interposing the conductive layer when viewed in the thickness direction of the insulating substrate. This allows the characteristics of the first bonding wire to be adjusted.

[0062] (12) One embodiment of the present disclosure is a method for manufacturing a high-frequency device, comprising the following steps: preparing a semiconductor device according to any one of (1) to (8); preparing a plurality of mounting substrates having different reference potential plane heights, wherein when the semiconductor device is mounted on the upper surface of the mounting substrate, at least a portion of the reference potential plane overlaps with at least a portion of the first opening when viewed from the thickness direction of the mounting substrate; obtaining information related to the high-frequency characteristics of the semiconductor device; selecting a mounting substrate from the plurality of mounting substrates based on the obtained information; and mounting the semiconductor device on the selected mounting substrate. In this way, the characteristics of the high-frequency device can be adjusted.

[0063] [Details of the embodiments of the present disclosure]

[0064] Hereinafter, specific examples of semiconductor devices, high frequency devices and methods for manufacturing the same according to embodiments of the present disclosure are described with reference to the accompanying drawings. It should be noted that the present disclosure is not limited to these examples, but is indicated by the claims, and is intended to include all changes within the meaning and scope equivalent to the claims.

[0065] [Example 1]

[0066] Figure 1 This is a top view of the semiconductor device of Example 1. Figure 2 yes Figure 1 The thickness direction of the base 11 is defined as the Z direction, the extending direction of the straight line connecting the terminal 13 and the terminal 12 is defined as the X direction, and the direction perpendicular to the X direction and the Z direction is defined as the Y direction.

[0067] like Figure 1 and Figure 2 As shown, the semiconductor device 100 of the first embodiment has a structure in which a semiconductor chip 20 and a passive component chip 25 mounted on a base 11 of a conductive lead frame 10 are sealed by a resin layer 14. The lead frame 10 has a base 11, a terminal 12, and a terminal 13. The base 11, the terminal 12, and the terminal 13 are not in contact with each other. The base 11 is a die pad, and the terminal 12 and the terminal 13 are leads. The connecting strip that connects the base 11, the terminal 12, and the terminal 13 before cutting is omitted from the illustration. The lower surface of the base 11, the terminal 12, and the terminal 13 is exposed from the lower surface of the resin layer 14.

[0068] The base 11 includes parts 11a to 11c and has an H-shaped top view. Part 11a is closer to the terminal 12 than part 11b, and part 11b is closer to the terminal 13 than part 11a. The terminal 12, the semiconductor chip 20, the passive component chip 25, and the terminal 13 are arranged in the - direction of the X direction. Two sets 16 of the terminal 12, the semiconductor chip 20, the passive component chip 25, and the terminal 13 are provided, and the two sets 16 are arranged in the Y direction. The set 16 can be one, or three or more.

[0069] The semiconductor chip 20 is mounted on the portion 11a, and the passive element chip 25 is mounted on the portion 11b. The semiconductor chip 20 includes a substrate 21 and electrodes 22 to 24. The substrate 21 is, for example, a semiconductor substrate. The electrodes 22 and 23 are provided on the upper surface of the substrate 21. The electrode 24 is provided on the lower surface of the substrate 21.

[0070] The passive element chip 25 includes a substrate 26, an electrode 27, and an electrode 28. The substrate 26 is, for example, a dielectric substrate. The electrode 27 is provided on the upper surface of the substrate 26, and the electrode 28 is provided on the lower surface of the substrate 26. The conductive bonding layer 35 bonds the base 11 with the electrode 24 and the electrode 28. The electrode 24 and the electrode 28 are electrically connected to the base 11 to cause a short circuit. The bonding wire 31 electrically connects the terminal 12 with the electrode 23. The bonding wire 32 electrically connects the electrode 22 with the electrode 27. The bonding wire 33 electrically connects the electrode 27 with the terminal 13.

[0071] The opening 15 of the base 11 is formed between the portion 11a and the portion 11b, and the resin layer 14 is provided without the base 11. When viewed from the Z direction, a portion of the bonding wire 32 overlaps with the opening 15. No conductive layer is provided between the bonding wire 32 and the opening 15.

[0072] Figure 3 FIG. 1 is a circuit diagram of a set of semiconductor devices in Example 1. Figure 3 As shown, the set 16 includes a terminal 12, a terminal 13, a transistor Q, inductors L1 to L3, and a capacitor C1. The transistor Q is, for example, a FET (Field Effect Transistor), and has a source S, a gate G, and a drain D. The inductor L3 and the inductor L2 are connected in series between the terminal 13 and the gate G. The capacitor C1 is connected in shunt to a node between the inductor L3 and the inductor L2. The source S is grounded. The inductor L1 is connected between the drain D and the terminal 12. The inductor L3, the inductor L2, and the capacitor C1 are a T-type circuit of LCL, forming a matching circuit 18. The matching circuit 18 matches the impedance when the terminal 13 looks at the matching circuit 18 with the impedance when the matching circuit 18 looks at the transistor Q.

[0073] The transistor Q is provided in the semiconductor chip 20. The source S, the gate G and the drain D correspond to the electrode 24, the electrode 22 and the electrode 23, respectively. The electrode 22 is an input electrode for inputting a high-frequency signal, and the electrode 23 is an output electrode for outputting a high-frequency signal. The capacitor C1 is provided in the passive element chip 25, and corresponds to the substrate 26 and the electrode 27 and the electrode 28 across the substrate 26. The inductor L1, the inductor L2 and the inductor L3 correspond to the bonding wire 31, the bonding wire 32 and the bonding wire 33, respectively.

[0074] The high-frequency signal input to the terminal 13 is input to the gate G through the matching circuit 18. The high-frequency signal amplified by the transistor Q is output from the drain D to the terminal 12 through the inductor L1. The inductor L1 may also form a part of the matching circuit. When the semiconductor device 100 is used for an amplifier circuit for a base station of mobile communication, the frequency of the high-frequency signal is, for example, 0.5 GHz to 10 GHz. The frequency of the high-frequency signal may also be above 10 GHz.

[0075] The transistor Q is, for example, a GaN HEMT (Gallium Nitride High Electron Mobility Transistor) or a LDMOS (Laterally Diffused Metal Oxide Semiconductor). When the transistor Q is a GaN HEMT, the substrate 21 is, for example, a silicon carbide substrate or a gallium nitride substrate. The electrodes 22 to 24 are, for example, metal layers such as a gold layer.

[0076] When the passive element chip 25 has the capacitor C1, the substrate 26 is, for example, a dielectric substrate, such as an alumina substrate, a high dielectric ceramic substrate having a relative dielectric constant greater than that of the alumina substrate, a silicon substrate, or a gallium arsenide substrate. The electrodes 27 and 28 are, for example, metal layers such as gold layers.

[0077] Figure 4 This is a top view of the high-frequency device of Example 1. Figure 5 yes Figure 4 AA cross-sectional view. In the high-frequency device 105 of Example 1, the semiconductor device 100 is mounted on the mounting substrate 50a. The mounting substrate 50a includes an insulating substrate 46, a conductive layer 40, a conductive layer 48, and a via 47. The conductive layer 40 is provided on the upper surface of the insulating substrate 46, and the conductive layer 48 is provided on the lower surface of the insulating substrate 46. The conductive layer 40 includes a ground layer 41, a signal line 42, and a signal line 43. The ground layer 41 includes a ground layer 41a and a ground layer 41b, and there is an opening 45 between the ground layer 41a and the ground layer 41b without the conductive layer 40. The conductive layer 48 is electrically connected to the ground layer 41a and the ground layer 41b through the via 47, resulting in a short circuit.

[0078] The base 11 of the semiconductor device 100 is electrically connected to the ground layer 41 using the bonding layer 36 to cause a short circuit. When viewed from the Z direction, at least a portion of the opening 15 of the base 11 overlaps with at least a portion of the opening 45 of the ground layer 41. The terminals 12 and 13 of the semiconductor device 100 are electrically connected to the signal line 42 and the signal line 43 respectively using the bonding layer 36 to cause a short circuit. The reference potential such as the ground potential supplied to the conductor layer 48 is supplied to the base 11 via the via 47, the ground layer 41, and the bonding layer 36. As a result, the conductor layer 48 and the base 11 have the same potential. The high-frequency signal is input from the signal line 43 to the terminal 13 via the bonding layer 36. The high-frequency signal is output from the terminal 12 to the signal line 42 via the bonding layer 36. The insulating substrate 46 is, for example, an organic insulating substrate such as a glass epoxy substrate. The conductor layer 40, the conductor layer 48, and the via 47 are, for example, metal layers such as copper layers.

[0079] [Comparative Example 1]

[0080] Figure 6 1 is a cross-sectional view of a high-frequency device of Comparative Example 1. In the high-frequency device 112 of Comparative Example 1, the opening 15 is not provided in the base 11 of the semiconductor device 110. The opening 45 is not provided in the ground layer 41 of the mounting substrate 50b. If the height H1 of the bonding wire 32 from the base 11 and the length of the bonding wire 32 are changed, the high-frequency characteristics (e.g., impedance) of the bonding wire 32 will change. As a result, the high-frequency characteristics of the matching circuit 18 will change, and the high-frequency characteristics of the semiconductor device 110 will change.

[0081] When the high frequency characteristics of the bonding wires 31 and 33 change, the high frequency characteristics of the high frequency device 112 can be adjusted in the mounting substrate 50b outside the semiconductor device 110. However, when the high frequency characteristics of the bonding wires 32 change, it is difficult to adjust the high frequency characteristics in the mounting substrate 50b.

[0082] [Description of Example 1]

[0083] Figure 7 1 is a cross-sectional view showing Example 1 of the high-frequency device of Example 1. Figure 7 As shown, in the high frequency device 106 of the first embodiment, the mounting substrate 50b is used, and the opening 45 is not provided in the ground layer 41. Figure 5 The same and the description are omitted.

[0084] Figure 8 1 is a cross-sectional view showing Example 2 of the high-frequency device of Example 1. Figure 8 As shown, in the high frequency device 107 of the first embodiment, a mounting substrate 50c is used, and an opening 45 is provided in the ground layer 41. The conductor layer 49 inside the mounting substrate 50c is provided below the opening 45. The conductor layer 49 is electrically connected to the conductor layer 48 through the via 47, thereby short-circuiting.

[0085] like Figure 5 Thus, in the high-frequency device 105, the conductive layer 48 below the bonding wire 32 serves as the reference potential plane 39. The distance between the bonding wire 32 and the reference potential plane 39 is H2.

[0086] like Figure 7 Thus, in the high-frequency device 106, the ground layer 41 below the bonding wire 32 becomes the reference potential plane 39. The distance between the bonding wire 32 and the reference potential plane 39 is H2a.

[0087] like Figure 8 Thus, in the high-frequency device 107, the conductive layer 49 below the bonding wire 32 serves as the reference potential plane 39. The distance between the bonding wire 32 and the reference potential plane 39 is H2b.

[0088] The height H1 is, for example, 100 μm to 300 μm, the thickness of the base 11 is, for example, 100 μm to 300 μm, and the thickness of the mounting substrates 50 a to 50 c is, for example, 200 μm to 1000 μm. Therefore, the distances H2 , H2a , and H2b can be changed within a range of, for example, about 200 μm to 2000 μm.

[0089] Fig. 9 FIG. 1 is a flow chart showing a method for manufacturing a high-frequency device according to Embodiment 1. Fig. 9 As shown, a plurality of mounting substrates 50a to 50c having different heights from the upper surfaces of the mounting substrates 50a to 50c to the reference potential plane 39 are prepared (step S10). Next, the semiconductor device 100 of the first embodiment is prepared (step S12).

[0090] Next, information related to the high-frequency characteristics of the semiconductor device 100 is obtained (step S14). The information related to the high-frequency characteristics can be obtained, for example, by measuring the high-frequency characteristics of the semiconductor device 100. The high-frequency characteristics can be measured, for example, by measuring small signal characteristics such as S parameters between the terminal 13 and the terminal 12 and large signal characteristics such as output power relative to input power when a large signal with a large amplitude is input to the semiconductor device 100. The information related to the high-frequency characteristics may also be information related to the shape of the bonding wire 32, for example.

[0091] Next, based on the measurement result of step S14, one mounting substrate is selected from the plurality of mounting substrates 50a to 50c (step S16). For example, the mounting substrate 50a, the mounting substrate 50b, or the mounting substrate 50c is selected so that the high-frequency characteristics when the semiconductor device 100 is mounted on the mounting substrates 50a to 50c become the desired characteristics. Next, the semiconductor device 100 is mounted on the selected mounting substrate 50a, the mounting substrate 50b, or the mounting substrate 50c (step S18). Through the above steps, the high-frequency device 105, the high-frequency device 106, or the high-frequency device 107 is manufactured.

[0092] Thus, in the first embodiment, the distance H2, the distance H2a, and the distance H2b between the bonding wire 32 and the reference potential plane 39 can be changed by changing the mounting substrate 50a to the mounting substrate 50c. If the distance H2, the distance H2a, and the distance H2b are changed, the capacitance between the bonding wire 32 and the reference potential plane 39 will change. As a result, the high-frequency characteristics of the bonding wire 32 will change. Even in the case where the characteristics of the semiconductor device 100 are different from the expected values ​​due to the high-frequency characteristics of the bonding wire 32 being different from the expected values ​​due to the height H1 or the length of the bonding wire 32 being different from the expected values, the high-frequency characteristics of the bonding wire 32 can be made close to the expected values. Therefore, the high-frequency characteristics of the high-frequency device can be made close to the expected values.

[0093] [Example 2]

[0094] Fig.10 FIG. 2 is a top view of the semiconductor device of Example 2. Fig.10 As shown in FIG. 1 , in the semiconductor device 101 of the second embodiment, an electrode 27a and an electrode 27b are provided on the upper surface of the passive element chip 25. An inductor L4 is connected between the electrode 27a and the electrode 27b. The inductor L4 is, for example, a spiral inductor. Fig.10 The inductor symbol is used in the figure. The bonding wire 32 electrically connects the electrode 22 and the electrode 27a. The bonding wire 33 electrically connects the electrode 27b and the terminal 13. Figure 1 The same and the description are omitted.

[0095] Fig.11 FIG. 1 is a circuit diagram of a set of semiconductor devices in Example 2. Fig.11 As shown, the inductor L4 is connected in series between the inductor L2 and the inductor L3. The capacitor C1 is connected in shunt between the inductor L2 and the inductor L4. The capacitor C2 is connected in shunt between the inductor L4 and the inductor L3. The inductors L2 to L4, the capacitor C1 and the capacitor C2 form a matching circuit 18. The inductor L4, the capacitor C1 and the capacitor C2 are provided on the passive component chip 25. The inductor L4 is a spiral inductor formed on the substrate 26. The capacitor C1 corresponds to the substrate 26 and the electrode 27a and the electrode 28 across the substrate 26. The capacitor C2 corresponds to the substrate 26 and the electrode 27b and the electrode 28 across the substrate 26. The other structures are the same as Figure 3 The same and the description are omitted.

[0096] [simulation]

[0097] The resonance frequency of the matching circuit 18 was simulated using the circuit A without the openings 15 and the openings 45 and the circuit B with the openings 15 but without providing a conductive layer overlapping the openings 15 on the mounting substrate 50 a .

[0098] The simulation conditions are as follows.

[0099] L1: 0.5nH, L2: 0.5nH, L3: 1nH, L4: 0.5nH

[0100] C1: 2pF, C2: 4pF

[0101] Q: GaN-HEMT, saturation power of 15W

[0102] H1: 400μm

[0103] H2: 1400μm

[0104] Two resonant frequencies of the reflection characteristic S11 from the terminal 13 to the matching circuit 18 are formed. The two resonant frequencies are as follows.

[0105] Circuit A: 3.64GHz, 7.82GHz

[0106] Circuit B: 3.36GHz, 7.38GHz

[0107] As described above, the high frequency characteristics of the matching circuit 18 can be changed by changing the distance between the bonding wire 32 and the reference potential surface 39. Therefore, it can be seen that the high frequency characteristics of the matching circuit 18 can be adjusted by selecting the mounting substrates 50a to 50c.

[0108] [Example 3]

[0109] Fig.12 It is a top view of the semiconductor device of Example 3. Fig.13 1 is a cross-sectional view of a high-frequency device according to Embodiment 3. In the high-frequency device 108 according to Embodiment 3, a semiconductor device 102 is mounted on a mounting substrate 50c. Fig.12 and Fig.13 As shown, in the semiconductor device 102 and the high-frequency device 108, the base 11 has a portion 11d and a portion 11e in addition to the portions 11a to 11c. The portion 11d is closer to the terminal 13 than the portion 11b. The portion 11e connects the portion 11b to the portion 11d. An opening 15a is provided between the portion 11b and the portion 11d. The passive element chip 25a is mounted on the portion 11d. The passive element chip 25a has a substrate 26a, an electrode 27a, and an electrode 28a. The bonding wire 34 electrically connects the electrode 27 to the electrode 27a. The bonding wire 33 electrically connects the electrode 27a to the terminal 13.

[0110] In the mounting substrate 50c, the conductor layer 40 may be provided so as to overlap with the opening 15 when viewed from the Z direction, or the opening 45 may be provided so as to overlap with the opening 15 when viewed from the Z direction. In the case where the opening 45 is provided, the conductor layer 49 may be provided, or the conductor layer 49 may not be provided. In addition, in the mounting substrate 50c, the conductor layer 40 may be provided so as to overlap with the opening 15a when viewed from the Z direction, or the opening 45a may be provided so as to overlap with the opening 15a when viewed from the Z direction. In the case where the opening 45a is provided, the conductor layer 49a may be provided, or the conductor layer 49a may not be provided.

[0111] Fig.14 FIG. 1 is a circuit diagram of a set of semiconductor devices in Embodiment 3. Fig.14 As shown in FIG. 1 , capacitor C1 is provided in passive component chip 25, and capacitor C2 is provided in passive component chip 25a. Inductor L4 corresponds to bonding wire 34. Other configurations are similar to Fig.11 The same and the description are omitted.

[0112] In the third embodiment, a plurality of mounting substrates 50c are prepared, which are different in both the height of the reference potential plane overlapping the opening 15 and the height of the reference potential plane overlapping the opening 15a when viewed from the Z direction. One mounting substrate 50c is selected from the plurality of mounting substrates 50c based on information related to the high-frequency characteristics of the semiconductor device 102. Thus, the high-frequency characteristics of the bonding wires 32 and 34 can be adjusted independently. Therefore, the characteristics of the matching circuit 18 can be further adjusted.

[0113] According to Embodiments 1 to 3, the semiconductor chip 20 (first chip) and the passive component chip 25 (second chip) are mounted on a conductive base 11. The bonding wire 32 (first bonding wire) of Embodiments 1 to 3 electrically connects the semiconductor chip 20 and the passive component chip 25 to transmit a high-frequency signal. The base 11 has an opening 15 (first opening) that penetrates in the thickness direction and overlaps with at least a portion of the bonding wire 32 when viewed from the thickness direction of the base 11. A conductive layer is not provided between the bonding wire 32 and the opening 15. That is, when viewed from the Z direction, the bonding wire 32 and the opening 15 overlap without a conductive layer.

[0114] like Fig. 9 As in step S14, information related to the high-frequency characteristics of the semiconductor device is obtained, and as in step S16, a mounting substrate on which the semiconductor device is to be mounted is selected. As in step S18, the semiconductor device is mounted on the selected mounting substrate. Thus, the high-frequency characteristics of the bonding wire 32 in the semiconductor device can be adjusted. Therefore, the characteristics of the semiconductor device can be adjusted.

[0115] The first chip and the second chip may also both be passive component chips. As the opening 15, an example in which the outline of the base 11 observed from the Z direction is a notch is described. It is also possible that part 11c is not provided and the opening 15 is between part 11a and part 11b. The opening 15 may also be a closed space surrounded by the base 11. If part 11a of the base 11 is separated from part 11b and part 11c is not provided, the parasitic inductance between the reference potential of the semiconductor chip 20 and the reference potential of the passive component chip 25 will increase. Therefore, part 11c may also connect part 11a to part 11b.

[0116] The terminal 12 (first terminal) is provided outside the base 11 for high-frequency signal output. The terminal 13 (second terminal) is provided outside the base 11 for high-frequency signal input. The bonding wire 31 (second bonding wire) electrically connects the terminal 12 to the semiconductor chip 20. The bonding wire 33 (third bonding wire) electrically connects the terminal 13 to the passive element chip 25. Thus, the high-frequency characteristics of the bonding wire 32 provided between the terminal 13 for signal input and the terminal 12 for signal output can be adjusted.

[0117] The semiconductor chip 20 includes a transistor Q that amplifies a high-frequency signal input to a terminal 13 and outputs the amplified high-frequency signal to a terminal 12. Thus, the high-frequency characteristics of the inductor connected to the transistor Q for amplification can be adjusted.

[0118] The passive element chip 25 includes a substrate 26 as a dielectric and an electrode 27 provided on the substrate 26, and a capacitor C1 is formed between the electrode 27 and the base 11. The bonding wires 32 and 33 are connected to the electrode 27. Thus, the high-frequency characteristics of the inductor connected to the semiconductor chip 20 in the T-type circuit of the LCL formed by the passive element chip 25, the bonding wires 32, and the bonding wires 33 can be adjusted.

[0119] Passive element chip 25, bonding wire 32, and bonding wire 33 form matching circuit 18 that matches impedance when viewed from terminal 13 toward bonding wire 33 with impedance when viewed from bonding wire 32 toward semiconductor chip 20. Thus, high frequency characteristics of matching circuit 18 of transistor Q can be adjusted.

[0120] The resin layer 14 is provided on the base 11 to seal the semiconductor chip 20, the passive element chip 25, and the bonding wires 31 to 33. In this case, the bonding wires 32 are located in the resin layer 14, so it is impossible to finely adjust the shape of the bonding wires 32. However, by providing the openings 15, the high-frequency characteristics of the bonding wires 32 can be adjusted.

[0121] In the mounting substrate 50 b , the conductor layer 40 (first conductor layer) is provided on the insulating substrate 46 , the semiconductor device 100 or the semiconductor device 101 is mounted thereon, and the opening 15 overlaps the conductor layer 40 without interposing the conductor layer therebetween when viewed from the Z direction.

[0122] In the mounting substrates 50a and 50c, the conductor layer 40 (first conductor layer) has an opening 45 (third opening), at least a portion of which overlaps with at least a portion of the opening 15 without interposing the conductor layer when viewed from the Z direction.

[0123] In the mounting substrate 50 a , the conductor layer 48 (second conductor layer) is provided on the surface of the insulating substrate 46 opposite to the conductor layer 40 , and overlaps with the opening 45 without the conductor layer interposed therebetween when viewed from the Z direction.

[0124] In the mounting substrate 50c, the conductor layer 49 (third conductor layer) is provided inside the insulating substrate 46 and overlaps with the opening 45 without the conductor layer interposed therebetween when viewed in the Z direction. A plurality of mounting substrates 50c having conductor layers 49 of different heights in the Z direction may be prepared.

[0125] In this manner, a mounting substrate on which the semiconductor device 100 and the semiconductor device 101 are to be mounted is selected from the mounting substrate 50 a and the mounting substrate 50 c . This makes it possible to adjust the high frequency characteristics of the bonding wire 32 .

[0126] The opening 45 has been described as an example of a portion between the separated ground layer 41a and the ground layer 41b. The opening 45 may be a notch in the outline of the ground layer 41. The opening 45 may be a closed space surrounded by the ground layer 41.

[0127] In Example 3, the bonding wire 31 (second bonding wire) electrically connects the terminal 12 to the semiconductor chip 20. The bonding wire 32 (first bonding wire) electrically connects the semiconductor chip 20 to the passive component chip 25. The bonding wire 34 (third bonding wire) electrically connects the passive component chip 25 to the passive component chip 25a (third chip). The bonding wire 33 (fourth bonding wire) electrically connects the passive component chip 25a to the terminal 13. The base 11 has: an opening 15, which overlaps with at least a portion of the bonding wire 32 without a conductive layer in between when viewed from the Z direction; and an opening 15a (second opening), which overlaps with at least a portion of the bonding wire 34 without a conductive layer in between. As a result, the high-frequency characteristics of both the bonding wire 32 and the bonding wire 34 can be adjusted independently.

[0128] The semiconductor chip 20 has a transistor Q that amplifies a high-frequency signal input to the terminal 13 and outputs the amplified high-frequency signal to the terminal 12. The passive element chip 25 has a substrate 26 (a first dielectric substrate) and an electrode 27 (a first electrode) provided on the substrate 26, and a capacitor C1 (a first capacitor) is formed between the electrode 27 and the base 11. The passive element chip 25a has a substrate 26a (a second dielectric substrate) and an electrode 27a (a second electrode) provided on the substrate 26a, and a capacitor C2 (a second capacitor) is formed between the electrode 27a and the base 11. Thus, the high-frequency characteristics of the bonding wire 32 and the bonding wire 34, which correspond to the inductor L2 and the inductor L4 in the matching circuit 18, can be independently adjusted.

[0129] As the matching circuit 18, an example of an input matching circuit has been described, but a passive component chip may be provided between the semiconductor chip 20 and the terminal 13, and the opening 15 of the base 11 may be provided in a manner overlapping with the bonding wire that electrically connects the semiconductor chip 20 and the passive component chip. In this way, the transistor Q may also amplify the high-frequency signal input to the terminal 12 and output the amplified high-frequency signal to the terminal 13. As the bonding wire 32, an example provided in the matching circuit 18 has been described, but the bonding wire 32 that electrically connects the semiconductor chip 20 (first chip) and the passive component chip 25 (second chip) may be any bonding wire for propagation of the high-frequency signal.

[0130] The embodiments disclosed herein are illustrative in all aspects and should not be considered restrictive. The scope of the present disclosure is indicated by the claims rather than the above meaning, and is intended to include all modifications within the meaning and scope equivalent to the claims.

Claims

1. A semiconductor device comprising: Conductive base; A first chip and a second chip are mounted on the base; and A first bonding wire electrically connects the first chip and the second chip to transmit a high-frequency signal. The base has a first opening that penetrates in a thickness direction and overlaps with at least a portion of the first bonding wire without interposing a conductive layer when viewed in the thickness direction of the base.

2. The semiconductor device according to claim 1, comprising: A first terminal, disposed outside the base; A second terminal is disposed outside the base; a second bonding wire electrically connecting the first terminal to the first chip; as well as The third bonding wire electrically connects the second terminal and the second chip.

3. The semiconductor device according to claim 2, wherein: The first chip is a semiconductor chip including a transistor that amplifies a high-frequency signal input to the first terminal or the second terminal and outputs the amplified high-frequency signal to the second terminal or the first terminal.

4. The semiconductor device according to claim 3, wherein: The second chip includes a dielectric substrate and an electrode provided on the dielectric substrate, a capacitor is formed between the electrode and the base, and the first bonding wire and the third bonding wire are connected to the electrode.

5. The semiconductor device according to claim 4, wherein: The second chip, the first bonding wire, and the third bonding wire form a matching circuit that matches an impedance when the third bonding wire is viewed from the second terminal with an impedance when the semiconductor chip is viewed from the first bonding wire.

6. The semiconductor device according to claim 1, comprising A third chip is mounted on the base. The semiconductor device comprises: A first terminal, disposed outside the base; A second terminal is disposed outside the base; a second bonding wire electrically connecting the first terminal to the first chip; a third bonding wire, electrically connecting the second chip to the third chip; as well as a fourth bonding wire electrically connecting the second terminal to the third chip, The base has a second opening that penetrates in the thickness direction and overlaps with at least a portion of the third bonding wire without interposing a conductive layer when viewed in the thickness direction of the base.

7. The semiconductor device according to claim 6, wherein: The first chip is a semiconductor chip having a transistor, the transistor amplifies a high-frequency signal input to the first terminal or the second terminal and outputs the amplified high-frequency signal to the second terminal or the first terminal, The second chip includes a first dielectric substrate and a first electrode provided on the first dielectric substrate, a first capacitor is formed between the first electrode and the base, the first bonding wire and the third bonding wire are connected to the first electrode, The third chip includes a second dielectric substrate and a second electrode provided on the second dielectric substrate, a second capacitor is formed between the second electrode and the base, and the third bonding wire and the fourth bonding wire are connected to the second electrode.

8. The semiconductor device according to any one of claims 1 to 7, comprising: The resin layer is disposed on the base and seals the first chip, the second chip and the first bonding wire.

9. A high frequency device comprising: The semiconductor device according to any one of claims 1 to 7; and A mounting substrate comprises an insulating substrate and a first conductive layer, wherein the first conductive layer is arranged on the insulating substrate and carries the semiconductor device, and the first conductive layer has a third opening, and when observed from the thickness direction of the insulating substrate, at least a portion of the third opening overlaps with at least a portion of the first opening without the conductive layer in between.

10. The high frequency device according to claim 9, comprising: The second conductive layer is provided on a surface of the insulating substrate opposite to the first conductive layer, and overlaps with the third opening without interposing a conductive layer therebetween when viewed in the thickness direction of the insulating substrate.

11. The high frequency device according to claim 9, comprising: The third conductive layer is provided inside the insulating substrate and overlaps with the third opening without interposing the conductive layer therebetween when viewed in the thickness direction of the insulating substrate.

12. A method for manufacturing a high frequency device, comprising the following steps: Preparing a semiconductor device according to any one of claims 1 to 7; A plurality of mounting substrates having different reference potential surface heights are prepared, wherein: When the semiconductor device is mounted on the upper surface of the mounting substrate, at least a portion of the reference potential surface overlaps with at least a portion of the first opening when viewed in the thickness direction of the mounting substrate; acquiring information related to high frequency characteristics of the semiconductor device; Based on the acquired information, selecting a mounting substrate from the plurality of mounting substrates; as well as The semiconductor device is mounted on the selected one mounting substrate.

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