Time modulation for DC-DC analog current sensing

Abstract

The invention relates to time modulation for DC-DC analog current sensing. A load is powered between the positive rail and the negative rail. The switching converter generates a negative rail voltage based on the input voltage, wherein the power transistor involves generation of the negative rail voltage. The replica generator generates a replica voltage that mirrors a drain-to-source voltage of the power transistor. The buffer buffers the replica voltage. The first switch selectively connects the buffer voltage to the output node in response to a control signal having a duty cycle proportional to the input voltage divided by the negative rail voltage. The second switch selectively connects the buffer voltage to ground according to an inverted signal of the control signal, thereby generating a PWM signal at the output node. The output filter filters the PWM signal to generate a sense voltage indicative of an output current flowing from the load device. The processing circuit determines an input current from the positive rail to the load device based on the sensed voltage.

Description

Technical Field

[0001] The present invention relates to continuous time input and output current sensing in DC-DC converters, such as in an inverting buck-boost converter used to generate a negative rail voltage in a display panel. Background Art

[0002] Power management is a concerning aspect of modern electronic systems, especially in portable devices such as smartphones, tablets, and laptops. These devices rely on efficient and accurate voltage regulation to optimize power consumption and extend battery life. A significant power-consuming component in such devices is their display panel. Display technologies such as liquid crystal displays (LCDs) and organic light-emitting diodes (OLEDs) require precise control of input and output currents to ensure optimal performance, brightness, and energy efficiency.

[0003] DC-DC converters such as buck-boost converters are often used in power management integrated circuits (PMICs) to regulate the voltage supplied to the display panel. In a typical PMIC, the converter generates and regulates positive and negative rail voltages based on the input voltage. The display panel consumes power by drawing input and output currents from these rails. Accurately determining and controlling these currents is important to maintain optimal display performance, energy efficiency, and extend battery life.

[0004] Traditional methods of monitoring and controlling the operation of a DC-DC converter involve directly measuring the drain-to-source voltage (VDS) of the high side transistor, which can be challenging and can introduce inaccuracies in the control loop. In addition, determining the display input current generally involves complex circuitry, increasing complexity and reducing reliability. An improved method and apparatus is needed for determining the input and output currents of a display panel and controlling the operation of a DC-DC converter with greater accuracy and minimal complexity. In particular, it is of interest to measure the output current through the negative rail. In view of this, further developments in this area are needed. Summary of the invention

[0005] An electronic device is disclosed herein, the electronic device including a positive rail and a negative rail, a switching converter, a replica voltage generating circuit, and an amplifier circuit, the positive rail and the negative rail are at a positive rail voltage and a negative rail voltage, and are configured to power a load device between the positive rail and the negative rail, the switching converter is configured to generate a negative rail voltage based on an input voltage, the switching converter includes a power transistor involved in the generation of the negative rail voltage, the replica voltage generating circuit is configured to generate a replica voltage, the replica voltage is a replica of the drain-to-source voltage of the power transistor, and the amplifier circuit is configured to amplify the replica voltage to generate an amplified voltage. The electronic device also includes a first switch and a second switch, the first switch is configured to selectively couple the amplified voltage to an output filter node based on a control signal having a duty cycle proportional to the input voltage divided by the negative rail voltage, and the second switch is configured to selectively couple the amplified voltage to ground based on an inverted signal of the control signal, thereby generating a pulse width modulated signal at the output filter node. The output filter is configured to filter the pulse width modulated signal to generate a sense voltage representing an output current flowing from the load device to the switching converter. The processing circuit is configured to determine an input current from the positive rail to the load device based on the sense voltage.

[0006] The replica voltage generating circuit may include a replica transistor and a first resistor, the replica transistor may be a replica of the power transistor, the first resistor is coupled between the input voltage and the replica transistor, wherein the replica transistor may be in a mirror relationship with the power transistor, thereby generating a first voltage that may be proportional to a drain current of the power transistor across the first resistor. The output transistor may be coupled to the replica voltage node. The second resistor may be coupled between the input voltage and the output transistor. The regulating circuit may be configured to control the output transistor to keep the first voltage and the second voltage across the second resistor equal, thereby generating a replica voltage at the replica voltage node.

[0007] The regulation circuit may include an amplifier having a non-inverting input terminal coupled to receive the first voltage, an inverting input terminal coupled to receive the second voltage, and an output coupled to a control terminal of the output transistor.

[0008] The output transistor may have a first conduction terminal coupled to receive the second voltage, a second conduction terminal coupled to the replica voltage node, and a control terminal coupled to the output of the amplifier.

[0009] The output transistor may be a p-channel transistor having a source coupled to receive the second voltage, a drain coupled to the replica voltage, and a gate coupled to the output of the amplifier.

[0010] The power transistor may be an n-channel transistor. The replica transistor may be an n-channel transistor having a drain connected to the first resistor, a source coupled to the converter output node, and a gate coupled to receive the same control signal as the gate of the power transistor.

[0011] The control signal generator may be configured to generate a control signal based on the negative rail voltage.

[0012] The control signal generator may include a ramp signal generator, a comparator, and an output circuit, wherein the ramp signal generator is configured to generate a ramp signal having a ramp rate related to a negative rail voltage, the comparator is configured to compare the ramp signal with a reference voltage, and the output circuit is configured to generate a control signal based on an output of the comparator.

[0013] The output circuit may include a first inverter configured to invert the output of the comparator to generate the control signal, and a second inverter configured to invert the control signal to generate an inverted signal of the control signal.

[0014] The processing circuit may determine the input current based on the sense voltage by determining an output current from the load device to the negative rail based on the sense voltage, and determining the input current based on the output current and a resistance of the load device.

[0015] The load device may be a display panel.

[0016] The switching converter may be an inverting buck-boost converter.

[0017] The amplifier circuit may be configured as a buffer configured to buffer the replica voltage at unity gain to generate an amplified voltage as the buffered voltage.

[0018] The amplifier circuit may include an amplifier having a non-inverting input coupled to receive a reference voltage, an inverting input coupled to a resistor, and an output, and an integrating capacitor coupled between the non-inverting input of the amplifier and the output of the amplifier, wherein the resistor is coupled between the inverting input of the amplifier and the replica voltage.

[0019] The present invention also discloses an electronic device, which includes a first converter circuit and a second converter circuit, wherein the first converter circuit is configured to generate an input current to be applied to a load device, and the second converter circuit is configured to absorb an output current from the load device based on an input voltage, wherein the second converter circuit includes a power transistor. The replica voltage generation circuit is configured to generate a replica voltage, which is a replica of the drain-to-source voltage of the power transistor. The sampling and filtering circuit is configured to sample the replica voltage in response to a pulse width modulated sampling signal, and filter the sampled replica voltage to generate an output voltage. The processing circuit is configured to determine the input current based on the output voltage.

[0020] The second converter circuit may sink an output current through the negative voltage rail, and the second converter circuit may generate a negative voltage on the negative voltage rail.

[0021] The control circuit may be configured to generate a pulse width modulated sampling signal having a duty cycle proportional to the input voltage divided by the negative voltage.

[0022] The control circuit may include a ramp generator configured to generate a periodic ramp signal having a slope depending on a negative voltage and a comparator configured to compare the periodic ramp signal with a reference voltage, wherein the pulse width modulated sampling signal is derived from an output of the comparator.

[0023] A method for determining an input current from a positive rail to a load device is also disclosed herein. The method may include generating a negative rail voltage on a negative rail using a switching converter including a power transistor; generating a replica voltage of a drain-to-source voltage of the power transistor; generating a pulse width modulated signal based on the replica voltage in response to a control signal; filtering the pulse width modulated signal to generate a sense voltage representing an output current from the load device to the negative rail; and determining the input current based on the sense voltage.

[0024] The method may include generating a control signal based on the negative rail voltage using a control signal generator by: generating a voltage proportional to the negative rail voltage; generating a reference voltage corresponding to the input voltage; comparing the proportional voltage and the reference voltage to generate an error signal; and generating a control signal having a duty cycle proportional to the input voltage divided by the negative rail voltage based on the error signal.

[0025] Further disclosed herein is a method for determining an input current from a positive rail to a load device in an electronic device. The method includes generating a negative rail voltage at a negative rail based on an input voltage using a switching converter, the switching converter including a power transistor involved in the generation of the negative rail voltage; generating a replica voltage using a replica voltage generating circuit, the replica voltage being a replica of a drain-to-source voltage of the power transistor; amplifying the replica voltage to generate an amplified voltage; selectively coupling the amplified voltage to an output filter node using a first switch based on a control signal, and selectively coupling the amplified voltage to ground using a second switch based on an inverted signal of the control signal, thereby generating a pulse width modulated signal at the output filter node; filtering the pulse width modulated signal using an output filter to generate a sense voltage representing an output current flowing from the negative rail to the load device; and determining the input current from the positive rail to the load device based on the sense voltage.

[0026] The control signal may have a duty cycle that is proportional to the input voltage divided by the negative rail voltage.

[0027] The method may include generating a control signal by: generating a voltage proportional to a negative rail voltage; generating a reference voltage corresponding to an input voltage; comparing the voltage proportional to the negative rail voltage with the reference voltage and generating an error signal; and generating a control signal having a duty cycle proportional to the input voltage divided by the negative rail voltage based on the error signal using a pulse width modulation (PWM) circuit.

[0028] The PWM circuit may generate a control signal by comparing a ramp signal generated by a ramp generator with an error signal, generating a control signal when the ramp signal is smaller than the error signal, and generating an inverted signal of the control signal when the ramp signal is larger than the error signal.

[0029] The amplification of the replica voltage can be performed as a buffer with unity gain.

[0030] Amplification of the replica voltage may be performed by a non-inverting operational amplifier integrator. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a block diagram of the display system described in this article;

[0032] Figure 2 is a schematic diagram of the inverting buck-boost converter described in this article;

[0033] Figure 2A is a schematic diagram of an alternative embodiment of an inverting buck-boost converter described herein;

[0034] Figure 3 is generated for Figure 2Schematic diagram of a control signal generator for a control signal of a switch of an inverting buck-boost converter;

[0035] Figure 4 is shown during operation Figure 3 A graph of the generation of a control signal; and

[0036] Figure 5 is a schematic diagram of another alternative embodiment of the inverting buck-boost converter described herein. DETAILED DESCRIPTION

[0037] The following disclosure enables those skilled in the art to make and use the subject matter described herein. The general principles outlined in this disclosure may be applied to embodiments and applications other than those described in detail above without departing from the spirit and scope of the disclosure. The purpose is not to limit the disclosure to the embodiments shown, but to give it the widest scope consistent with the principles and features disclosed or suggested herein.

[0038] Note that in the following description, unless otherwise specified, any resistor or resistance mentioned is a discrete device, not just an electrical wire between two points. Therefore, any resistor or resistance connected between two points has a higher resistance than the wire between the two points, and such a resistor or resistance cannot be interpreted as a wire. Similarly, unless otherwise specified, any capacitor or capacitance mentioned is a discrete device, and is not a parasitic element unless otherwise specified. Furthermore, unless otherwise specified, any inductor or inductance mentioned is a discrete device, and is not a parasitic element unless otherwise specified.

[0039] First reference Figure 1 , the display system 10 includes an active matrix organic light emitting diode (AMOLED) display panel 30 powered between a positive rail VO1 and a negative rail VOT2. A power management integrated circuit (PMIC) 11 has a boost fixed frequency continuous mode (boost FCCM) converter 12 designed to generate and regulate the positive rail voltage VO1. The PMIC 11 also includes an inverting buck-boost converter 20 for generating and regulating the negative rail voltage VO2.

[0040] The PMIC 11 also includes a boost converter 13 that generates a regulated pre-drive voltage VO3 that is used by row and column drivers 15. These drivers 15 are used to activate and deactivate display elements within the AMOLED display panel 30. An input current, denoted as I_display_in, flows out of the boost FCCM converter 12 through the positive rail VO1 and into the display panel 30. An output current, denoted as I_display_out, flows out of the display panel 30 through the negative rail VO2 and into the inverting buck-boost converter 20, which in this case is configured to act as a current sink. As will be explained in more detail below, the inverting buck-boost converter 20 receives an input current I_buckboost_in and, based thereon, sinks an output current I_display_out from the display.

[0041] The purpose is to estimate the display output current I_display_out by measuring the input current I_buckboost_in of the buck boost converter, rather than measuring the display input current I_display_in from the boost FCCM converter 12. From the display output current I_display_out, the display input current I_display_in can be calculated by treating the display as a resistor.

[0042] Use the relation: And remembering that the display output current I_display_out is the output current of (eg, the current sunk by) the inverting buck-boost converter 20 , the processing circuitry 19 within the PMIC 11 may calculate the display output current I_display_out as:

[0043]

[0044] According to the display output current I_display_out, the processing circuit 19 can calculate the display input current I_display_in.

[0045] Therefore, a determination of the input current I_buckboost_in of the buck-boost converter will be performed as described below.

[0046] refer to Figure 2The inverting buck-boost converter 20 is described in more detail. The converter 20 includes an inverting buck-boost circuit 21 coupled between an input voltage VIN and a negative rail VO2. In addition, a sensing circuit 22 is coupled to the output of the inverting buck-boost circuit 21. A filter 24 is implemented at the output of the sensing circuit 22, and the output of the filter 24 is connected to the input of an amplifier 25 configured as a unity gain buffer. A first switch S1 selectively connects the output of the buffer 25 to an output filter 26 in response to a control signal TOCL having a duty cycle proportional to Vin / VO2, and a second switch S2 selectively connects the output of the buffer 25 to an output filter 26 in response to an inverted signal of the control signal TOCL. The connection point between the switch S1 and the output filter 26 is selectively connected to ground.

[0047] Examining the inverting buck-boost circuit 21 in more detail, it includes a first n-channel transistor MN1, the drain of MN1 is connected to the input voltage VIN, its source is connected to the node N1, and its gate receives the high-side control signal HS. The circuit 21 also has a second n-channel transistor MN2, the drain of MN2 is connected to the node N1, its source is connected to the negative rail VO2, and its gate receives the low-side control signal LS. An inductor L is connected between the node N1 and ground.

[0048] As for the sensing circuit 22, it includes a resistor R1 connected between the input voltage VIN and the node N2, and an n-channel transistor MN3 connected between the nodes N2 and N1. Specifically, the drain of MN3 is connected to the node N2, the source of MN3 is connected to the node N1, and the gate of MN3 receives the high-voltage side control signal HS. The resistor R2 is connected between the input voltage VIN and the node N3. The source of the p-channel transistor MP1 is connected to the node N3, the drain is connected to the node N4, and the gate is connected to receive the output of the amplifier 23. The resistor R3 is connected between the node N4 and the ground. The non-inverting input terminal of the amplifier 23 is connected to the node N2, the inverting input terminal is connected to the node N3, and the output is connected to the gate of the p-channel transistor MP1. The filter 24 is formed by a resistor R4 connected between the node N4 and the node N5 and a capacitor C1 connected between the node N5 and the ground.

[0049] The buffer 25 is formed by an amplifier whose non-inverting input terminal is connected to the node N5, whose output is connected to the switch S1, and whose inverting input terminal is connected to its output.

[0050] The switch S1 is connected between the output of the amplifier 25 and the node N6, and is controlled by the control signal TOCL as described above. The switch S2 is connected between the node N6 and the ground, and is controlled by the inverted signal of the control signal TOCL as described above. control.

[0051] Finally, the output filter 26 is formed by a resistor R5 connected between the node N6 and a first terminal of a capacitor C2, while the second terminal of the capacitor C2 is connected to ground.

[0052] There are alternative versions of the inverting buck-boost converter 20. For example, Figure 2A In the version of the inverting buck-boost converter 20' shown, the filter 24 and the amplifier 25 can be rearranged as a non-inverting operational amplifier integrator 24', wherein the inverting input terminal of the amplifier 25 is connected to the node N5, the capacitor C1 is connected between the inverting input terminal and the output of the amplifier 25, and the non-inverting input terminal of the amplifier 25 is coupled to the reference voltage. In addition, here, the resistor R3 is connected between the node N4 and the reference voltage. In addition, as an example, the sense voltage VOCL generated by the output filter 26 is buffered here by the amplifier 27 configured as a unity gain buffer, but it should be understood that such a buffering arrangement can be added to any embodiment of the inverting buck-boost converter 20.

[0053] The operation is as follows. The inverting buck-boost converter 20 as part of the PMIC 11 operates in both buck and boost modes to generate and regulate the negative rail voltage VO2 based on the input voltage VIN. In buck mode, the input voltage VIN is bucked, while in boost mode, it is boosted. This is achieved by controlling the switching of transistors MN1 and MN2 using a high-side control signal HS and a low-side control signal LS, which in turn regulates the current through the inductor L for energy storage and release, ultimately generating the negative rail voltage VO2.

[0054] The sensing circuit 22 creates a replica of the drain-to-source voltage (VDS) of the high-side transistor MN1, called VDS_Replica, through a combination of components and feedback mechanisms. Transistor MN3 is a replica of transistor MN1. Here, transistor MN3 acts as a switch. During the high-side conduction when transistors MN1 and MN3 are turned on, since the resistance of resistor R1 is much greater than the on-resistance of MN3, it can be assumed that when MN3 is turned on, node N2 is at the same voltage as node N1, but since resistor R1 acts as a pull-up, node N2 is at VIN. The sensing circuit 22 uses amplifier 23 to maintain equal voltages at nodes N2 and N3. The feedback mechanism involving amplifier 23 and transistor MP1 adjusts the gate voltage of MP1 to keep the voltage across resistor R2 at node N3 equal to the voltage across resistor R1 at node N2. Therefore, the voltage VDS_Replica at node N4 is proportional to the drain-to-source voltage VDS of transistor MN1.

[0055] It is observed that the combination of resistors R1, R2 and R3 produces a voltage divider that scales the voltage at node N4 to match the actual VDS of MN1, thereby enabling the sensing circuit to accurately replicate the drain-to-source voltage VDS of transistor MN1. Thus, through the generation of VDS_Replica, the design enables accurate monitoring and control of the operation of the inverting buck-boost converter 20 without directly measuring the drain-to-source voltage of the high-side transistor MN1.

[0056] Continuing to describe the operation, VDS_Replica generated at node N4 passes through filter 24. This results in a voltage representing input current I_buckboost_in being generated at the non-inverting input terminal of amplifier 25 and, after buffering, this voltage is sent to output filter 26 through switch circuits S1, S2.

[0057] The switch S1 is operated synchronously with the control signal TOCL, and as previously described, the duty cycle of the TOCL is proportional to Vin / VO2. When TOCL is high, the switch S1 is closed to connect the output of the amplifier 25 to the node N6. Conversely, when TOCL is low, the switch S1 is opened to disconnect the buffer from the node N6. At the same time, the switch S2 is connected to the inverted signal of the control signal TOCL (expressed as ) synchronous operation. When is high, switch S2 is closed to connect node N6 to ground, and when When is low, switch S2 is turned off to disconnect node N6 from ground.

[0058] This synchronous operation of switches S1 and S2 combined with the duty cycle of TOCL produces a pulse width modulated (PWM) signal at node N6, where the pulse width is proportional to Vin / VO2. The PWM signal then passes through output filter 26, which filters out high frequency components to generate a sense voltage VOCL.

[0059] Since the duty cycle of TOCL is proportional to Vin / VO2, and the voltage at the non-inverting input terminal of the amplifier 25 represents the input current I_buckboost_in, the sense voltage VOCL generated at the output of the output filter 26 is proportional to the absolute value of the display output current I_display_out. Therefore, at this time, the processing circuit 19 can calculate the display output current I_display_out as:

[0060]

[0061] This calculation will now be fully explained. At node N4, the instantaneous voltage across transistor MN1 is:

[0062] V N4 =VDS_Replica(t)=RON MN1 I L (t)

[0063] Here, V N4 is the voltage at node N4, RON MN1 is the on-resistance of transistor MN1, I L (t) is the current through the inductor L.

[0064] The filter 24' averages its input signal. In this way, at the node N5, there is the average value of the node N4, expressed as:

[0065]

[0066] Here, V N5 is the voltage at node N5. MN1 is almost constant, the equation can be rewritten as:

[0067]

[0068] Therefore, the voltage V N5 includes information about the average current in transistor MN1, which is also the input current of the inverting buck-boost 20. Therefore:

[0069]

[0070] Due to the action of switches S1 and S2 and filter 26, the following operation is effectively performed:

[0071] V N5 Vin / VO2

[0072] We can write:

[0073]

[0074] But recalling:

[0075] I_buckboost_in·Vin=I_buckboost_out·VO2

[0076] It can be said that:

[0077]

[0078] Therefore, it can be said that:

[0079] VOCL=RON MN1 I_buckboost_out = RON MN1 I_display_out

[0080] therefore,

[0081]

[0082] Continuing to describe the operation, in order to determine the display input current I_display_in from the display output current I_display_out, the resistance of the current path through the display 30 is considered. The display panel 30 can be considered as a resistive element through which the input current I_display_in flows to generate a voltage drop across the resistive element. The voltage drop is equal to the difference between the positive rail voltage VO1 and the negative rail voltage VO2.

[0083] According to Ohm's law, the voltage across a resistive element is equal to the product of the current flowing through it and its resistance (V=I×R). In this case, the voltage across the display panel 30 can be expressed as the product of the display input current I_display_in and the resistance R_display of the current path through the display, which can be expressed as:

[0084] VO1-VO2=I_display_in×R_display

[0085] Assuming that the display output current I_display_out, and the relationship between the display input current and the display output current are now known, the above equation can be rearranged to find the display input current I_display_in:

[0086]

[0087] By knowing the resistance R_display of the current path through the display, processing circuitry 19 can calculate the display input current I_display_in using the voltage difference between positive rail VO1 and negative rail VO2. This approach allows the display input current I_display_in and thereby I_buckboost_out to be determined based on the previously calculated display output current I_display_out and the known resistance of display panel 30.

[0088] Control signal TOCL and its inverted signal By reference Figure 3 The control signal generator 40 described in further detail generates the control signal. The control signal generator 40 includes a ramp generator 41 and a comparator circuit 43.

[0089] The ramp generator 41 includes a resistor R6 connected between the voltage VDAC and the node N7 and a resistor R7 connected between the node N7 and the ground. The non-inverting input terminal of the amplifier 42 is connected to the node N7, the inverting input terminal is connected to the node N8, and the output is connected to the gate of the n-channel transistor MN4. The drain of MN4 is connected to the node N9, and its source is connected to the node N8. The resistor R8 is connected between the node N8 and the ground. The current mirror is connected between the nodes N9 and N10 and is formed by the p-channel transistor MP2, the source of MP2 is connected to the voltage V1V8, the drain is connected to the node N9, and the gate is connected to the node N9. The current mirror also includes a p-channel transistor MP3, the source of MP3 is connected to the voltage V1V8, the drain is connected to the node N10, and the gate is connected to the node N9. The switch S3 selectively connects the node N10 to the ground and is controlled by the reset signal RESET. The capacitor C3 is connected between the node N10 and the ground.

[0090] The comparator circuit 43 includes an amplifier 43 configured as a comparator, the non-inverting input terminal of the amplifier is connected to the node N10, the inverting input terminal thereof is connected to the node N11, and the output thereof is connected to the input of the inverter 44. The resistor R9 is connected between the voltage VINSW and the node N11. The input of the inverter 45 is connected to the output of the inverter 44.

[0091] In operation, the ramp generator 41 generates a ramp signal at node N10 by charging and discharging capacitor C3 through a current mirror formed by transistors MP2 and MP3. In more detail, the operation of amplifier 42 and transistor MN4 converts voltage VO2P (proportional to negative rail voltage VO2) into a current flowing on the left side of the current mirror. When switch S3 is turned off due to deassertion of the reset signal, the mirror current flowing on the right side of the current mirror charges capacitor C3, where the charging rate and ramp slope are set by the value of the mirror current and the capacitance of capacitor C3.

[0092] The amplifier 43 configured as a comparator compares the ramp signal at the node N10 with the reference voltage at the node N11, and outputs a high or low signal depending on whether the ramp signal is higher or lower than the voltage at the node N11. The output signal is then sent to the input of the inverter 44, which inverts the signal to generate the control signal TOCL. Finally, the control signal TOCL is inverted again by the inverter 45 to generate an inverted signal of the control signal TOCL.

[0093] exist Figure 4The generation of TOCL and the ramp signal (denoted as RAMP) at node N10 can be seen in FIG. Just before time T1, the reset signal RESET has been asserted to close switch S3, thereby causing the charge on capacitor C3 to discharge to ground. Therefore, at time T1, RAMP is at ground potential. This means that RAMP is less than the reference voltage at node N11, causing the output of amplifier 43 to be disabled and thus causing the control signal TOCL to be asserted.

[0094] Then, the reset signal RESET is deactivated and RAMP begins to ramp up as described above. It is observed that the ramp rate of RAMP varies depending on the value of the input voltage VIN because the mirror current amplitude depends on the voltage VO2P. At time T2, RAMP has exceeded the reference voltage at the node N11, and as a result, the output of the amplifier 43 is validated and thus the control signal TOCL is deactivated, as shown at time T2.

[0095] The sensing circuit described above can be used with other types of converters besides an inverting buck-boost converter. For example, a non-inverting buck-boost converter, Converters, or other DC-DC converters involving precise control and regulation of output voltage can benefit from the method of the present invention. One noteworthy aspect of the above is the ability to determine the display output current by measuring the converter input current and calculating the display input current accordingly. This principle can be applied to any converter used as a current sink and used in conjunction with a display panel or any other load that can be considered a resistive element.

[0096] The overall advantages are numerous. First, the sensing circuit described in this article allows for precise control and monitoring of the converter's operation without having to directly measure the high-side transistor drain-to-source voltage, which can be challenging and can introduce inaccuracies in the control loop. By generating a replica of this voltage and utilizing the generated control signal (TOCL), precise control and regulation of the converter output voltage is achieved.

[0097] Second, the sensing circuit simplifies the process of determining the display input current by allowing the display input current to be calculated based on the display output current and the known resistance of the display panel. This approach eliminates the need to directly measure the display input current, reduces complexity and improves reliability. By accurately controlling and regulating the output voltage, the efficiency and performance of the display system can be improved, resulting in better energy management, longer battery life and an enhanced user experience.

[0098] Finally, this approach is general and can be applied to various types of converters and power management systems. For example, this approach can be applied to a buck converter, a non-inverting buck-boost controller, or a boost controller.

[0099] Finally, it is evident that modifications and variations may be made to what is described and illustrated herein without departing from the scope of the present disclosure. Figure 5 An embodiment of an inverting buck-boost converter 20" is shown. Here, a filter 24" formed by resistors R1 and C1 is placed before the amplifier 23, wherein a resistor R4 is connected between nodes N2 and N5, a capacitor C1 is connected between node N5 and a reference voltage VREF_A, and the non-inverting input terminal of the amplifier 23 is connected to node N5. In addition, a resistor R2 is connected between node N3 and a reference voltage VREF_B to provide an offset, and a resistor R3 is connected between node N4 and a reference voltage VREF_C. The reference voltages VREF_A and VREF_B may be equal. The operation of the inverting buck-boost converter 20" is as described above.

[0100] Although the present disclosure has been described with a limited number of embodiments, those skilled in the art, with the benefit of this disclosure, may conceive of other embodiments that do not depart from the disclosed scope. In addition, those skilled in the art may conceive of embodiments that can represent various combinations of the embodiments disclosed herein in various ways.

Claims

1. An electronic device, comprising: A positive rail and a negative rail, at a positive rail voltage and a negative rail voltage, and configured to power a load device between the positive rail and the negative rail; a switching converter configured to generate the negative rail voltage based on an input voltage, the switching converter comprising a power transistor involved in the generation of the negative rail voltage; a replica voltage generating circuit configured to generate a replica voltage, the replica voltage being a replica of a drain-to-source voltage of the power transistor; an amplifier circuit configured to amplify the replica voltage to generate an amplified voltage; a first switch configured to selectively couple the amplified voltage to an output filter node based on a control signal having a duty cycle proportional to the input voltage divided by the negative rail voltage, and a second switch configured to selectively couple the amplified voltage to ground based on an inverted version of the control signal to generate a pulse width modulated signal at the output filter node; an output filter configured to filter the pulse width modulated signal to generate a sense voltage representative of an output current flowing from the load device to the switching converter; as well as A processing circuit is configured to determine an input current from the positive rail to the load device based on the sense voltage.

2. The electronic device according to claim 1, wherein the replica voltage generating circuit comprises: a replica transistor, the replica transistor being a replica of the power transistor; a first resistor coupled between the input voltage and the replica transistor; wherein the replica transistor is in a mirror relationship with the power transistor so as to generate a first voltage across the first resistor, the first voltage being proportional to a drain current of the power transistor; an output transistor coupled to the replica voltage node; a second resistor coupled between the input voltage and the output transistor; as well as A regulation circuit is configured to control the output transistor to maintain the first voltage and a second voltage across the second resistor equal to generate the replica voltage at the replica voltage node.

3. An electronic device according to claim 2, wherein the regulation circuit includes an amplifier having: a non-inverting input terminal coupled to receive the first voltage; an inverting input terminal coupled to receive the second voltage; and an output coupled to a control terminal of the output transistor.

4. The electronic device of claim 3, wherein the output transistor has: a first conduction terminal coupled to receive the second voltage; a second conduction terminal coupled to the replica voltage node; and a control terminal coupled to the output of the amplifier.

5. The electronic device of claim 4, wherein the output transistor is a p-channel transistor having: a source coupled to receive the second voltage; a drain coupled to the replica voltage; and a gate coupled to the output of the amplifier.

6. An electronic device according to claim 2, wherein the power transistor is an n-channel transistor; wherein the replica transistor is an n-channel transistor, the drain of the n-channel transistor is connected to the first resistor, the source of the n-channel transistor is coupled to the converter output node, and the gate is coupled to receive the same control signal as the gate of the power transistor.

7. The electronic device according to claim 1, further comprising: A control signal generator is configured to generate the control signal based on the negative rail voltage.

8. The electronic device according to claim 7, wherein the control signal generator comprises: a ramp signal generator configured to generate a ramp signal having a ramp rate related to the negative rail voltage; a comparator configured to compare the ramp signal with a reference voltage; as well as The output circuit is configured to generate the control signal based on the output of the comparator.

9. The electronic device according to claim 8, wherein the output circuit comprises: a first inverter configured to invert the output of the comparator to generate the control signal; as well as The second inverter is configured to invert the control signal to generate the inverted signal of the control signal.

10. The electronic device of claim 1, wherein the processing circuit determines the input current according to the sense voltage in the following manner: determining an output current from the load device to the negative rail based on the sense voltage; and The input current is determined based on the output current and the resistance of the load device. The electronic device according to claim 1 , wherein the load device is a display panel.

12. The electronic device of claim 1, wherein the switching converter comprises an inverting buck-boost converter. 13 . The electronic device of claim 1 , wherein the amplifier circuit is configured as a buffer configured to buffer the replica voltage at unity gain to generate the amplified voltage as a buffered voltage.

14. The electronic device of claim 1, wherein the amplifier circuit comprises: an amplifier having: a non-inverting input coupled to receive a reference voltage; The inverting input is coupled to a resistor; and output; as well as an integrating capacitor coupled between the non-inverting input of the amplifier and the output of the amplifier; Wherein the resistor is coupled between the inverting input of the amplifier and the replica voltage.

15. An electronic device, comprising: a first converter circuit configured to generate an input current to be applied to a load device; a second converter circuit configured to sink an output current from the load device based on an input voltage; wherein the second converter circuit comprises a power transistor; a replica voltage generating circuit configured to generate a replica voltage, the replica voltage being a replica of a drain-to-source voltage of the power transistor; a sampling and filtering circuit configured to sample the replica voltage in response to a pulse width modulation sampling signal and filter the sampled replica voltage to generate an output voltage; as well as The processing circuit is configured to determine the input current according to the output voltage. 16 . The apparatus of claim 15 , wherein the second converter circuit sinks the output current through a negative voltage rail, and the second converter circuit generates a negative voltage on the negative voltage rail.

17. The device of claim 16, further comprising a control circuit configured to generate the pulse width modulated sampling signal, the pulse width modulated sampling signal having a duty cycle proportional to the input voltage divided by the negative voltage.

18. The apparatus of claim 17, wherein the control circuit comprises: a ramp generator configured to generate a periodic ramp signal having a slope depending on the negative voltage; as well as A comparator is configured to compare the periodic ramp signal with a reference voltage, wherein the pulse width modulated sampling signal is derived from an output of the comparator.

19. A method for determining an input current from a positive rail to a load device, the method comprising: generating a negative rail voltage on the negative rail using a switching converter including a power transistor; generating a replica voltage of a drain-to-source voltage of the power transistor; generating a pulse width modulation signal based on the replica voltage in response to a control signal; filtering the pulse width modulated signal to produce a sense voltage representative of an output current from the load device to the negative rail; as well as The input current is determined based on the sense voltage.

20. The method of claim 19, further comprising generating the control signal based on the negative rail voltage using a control signal generator by: generating a voltage proportional to the negative rail voltage; generating a reference voltage corresponding to the input voltage; comparing the proportional voltage with the reference voltage to generate an error signal; as well as The control signal having a duty cycle proportional to the input voltage divided by the negative rail voltage is generated based on the error signal.

21. A method for determining input current from a positive rail to a load device in an electronic device, the method comprising: generating a negative rail voltage at a negative rail based on an input voltage using a switching converter, the switching converter including a power transistor involved in generating the negative rail voltage; generating a replica voltage using a replica voltage generating circuit, the replica voltage being a replica of a drain-to-source voltage of the power transistor; amplifying the replica voltage to generate an amplified voltage; selectively coupling the amplified voltage to an output filter node using a first switch based on a control signal, and selectively coupling the amplified voltage to ground using a second switch based on an inverted version of the control signal, thereby generating a pulse width modulated signal at the output filter node; filtering the pulse width modulated signal using an output filter to generate a sense voltage representative of an output current flowing from the negative rail to the load device; as well as The input current from the positive rail to the load device is determined based on the sense voltage.

22. The method of claim 21, wherein the control signal has a duty cycle that is proportional to the input voltage divided by the negative rail voltage.

23. The method of claim 21 , further comprising generating the control signal by: generating a voltage proportional to the negative rail voltage; generating a reference voltage corresponding to the input voltage; comparing the voltage proportional to the negative rail voltage to the reference voltage and generating an error signal; and The control signal having a duty cycle proportional to the input voltage divided by the negative rail voltage is generated based on the error signal using a pulse width modulation (PWM) circuit.

24. The method according to claim 23, wherein the PWM circuit generates the control signal by comparing a ramp signal generated by a ramp generator with the error signal, generating the control signal when the ramp signal is smaller than the error signal, and generating the inverted signal of the control signal when the ramp signal is larger than the error signal.

25. The method of claim 21, wherein the amplifying of the replica voltage is performed as a buffer with unity gain.

26. The method of claim 21, wherein the amplification of the replica voltage is performed by a non-inverting operational amplifier integrator.

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