Power-on reset circuit with hysteresis effect

Abstract

The invention discloses a power-on reset circuit with a hysteresis effect, and the power-on reset circuit with the hysteresis effect can achieve the hysteresis effect through the setting of a front-end circuit, a comparison inverting circuit and the conduction voltage of an NMOS tube in a control circuit, and through the control circuit, in the power-on process, along with the gradual increase of the power supply voltage, the hysteresis effect is achieved, and the hysteresis effect is achieved. Enabling the output power supply of the first phase inverter to be gradually boosted through the conduction of the first phase inverter and the conduction of a PMOS (P-channel Metal Oxide Semiconductor) tube of the first phase inverter until the output voltage of the first phase inverter is greater than the conduction voltage of an NMOS (N-channel Metal Oxide Semiconductor) tube of the second phase inverter, and completing power-on; and in the power-off process, along with gradual reduction of the power supply voltage, the output voltage of the second phase inverter is gradually increased, and the output voltage of the first phase inverter is gradually reduced until the output voltage of the first phase inverter is smaller than the conduction voltage of the NMOS tube of the second phase inverter, and power-off is completed.

Description

Technical Field

[0001] The invention relates to the field of electronic technology, and in particular to a power-on reset circuit with hysteresis effect. Background Art

[0002] The power-on reset circuit generally plays the role of a low-effective global reset in integrated circuits and systems. The circuit generates a low-effective logic signal affected by the power supply voltage (VDD) of the circuit system, namely, the reset signal (RSTN), and controls other modules in the circuit system to perform a global reset.

[0003] The power-on reset circuit can set its upper and lower thresholds so that other modules of the circuit system always operate within the normal range of the power supply voltage, avoiding the problem of abnormal operation of the circuit system caused by too low power supply voltage.

[0004] Therefore, how to design and use a power-on reset circuit has become an important research direction for those skilled in the art in the field of electronic technology. Summary of the invention

[0005] The present invention provides a power-on reset circuit with hysteresis effect. Specifically, the present invention provides the following technical solutions:

[0006] A power-on reset circuit with hysteresis effect, comprising: a preamplifier circuit, a comparison inversion circuit, and a control circuit;

[0007] The input end of the preamplifier circuit is connected to a power supply, and the output end of the preamplifier circuit is connected to the comparison inversion circuit, so as to provide an output voltage to the comparison inversion circuit;

[0008] The comparison inverting circuit comprises a first inverter and a second inverter, wherein the first input terminal of the first inverter is connected to the output terminal of the preamplifier circuit; the second input terminal of the first inverter is connected to the power supply; the output terminal of the first inverter is connected to the first input terminal of the second inverter; the second input terminal of the second inverter is connected to the power supply; the comparison inverting circuit is used to output a first reset signal based on the voltage output by the preamplifier circuit and the power supply voltage;

[0009] The first input terminal of the control circuit is connected to the output terminal of the preamplifier circuit; the second input terminal of the control circuit is connected to the output terminal of the first inverter; the third input terminal of the control circuit is connected to the output terminal of the second inverter;

[0010] The control circuit is used to gradually increase the output power of the first inverter during a power-on process as the power supply voltage gradually increases and the PMOS tube of the first inverter is turned on, until the output voltage of the first inverter is greater than the turn-on voltage of the NMOS tube of the second inverter, thereby completing power-on; and to gradually increase the output voltage of the second inverter and gradually decrease the output voltage of the first inverter during a power-off process as the power supply voltage gradually decreases, until the output voltage of the first inverter is less than the turn-on voltage of the NMOS tube of the second inverter, thereby completing power-off.

[0011] In an optional implementation manner of the present application, the front-end circuit includes: a first NMOS tube and a first resistor;

[0012] The drain of the first NMOS tube is respectively connected to one end of the first resistor and the gate of the first NMOS tube; the other end of the first resistor is connected to the power supply; the source of the first NMOS tube is grounded; wherein the drain of the first NMOS tube serves as an output end to provide an output voltage to the comparison inverting circuit.

[0013] In an optional implementation manner of the present application, the first inverter includes a first PMOS tube and a second NMOS tube;

[0014] The gate of the first PMOS tube is connected to the gate of the second NMOS tube, and is connected to the output end of the preamplifier circuit as the first input end of the first inverter;

[0015] The source of the first PMOS tube is connected to the power supply as the second input end of the first PMOS tube;

[0016] The drain of the first PMOS tube is connected to the drain of the second NMOS tube, and is connected to the input of the second inverter as the output of the first inverter; the source of the second NMOS tube is grounded.

[0017] In an optional implementation manner of the present application, the second inverter includes: a second PMOS tube and a fifth NMOS tube;

[0018] The gate of the second PMOS tube is connected to the gate of the fifth NMOS tube, and is connected to the output end of the first inverter as the first input end of the second inverter;

[0019] The source of the second PMOS tube is connected to the power supply as the second input end of the second PMOS tube;

[0020] The drain of the second PMOS tube is connected to the drain of the fifth NMOS tube and serves as the output end of the second inverter; the source of the fifth NMOS tube is grounded.

[0021] In an optional implementation manner of the present application, the control circuit includes: a third NMOS tube and a fourth NMOS tube;

[0022] The source of the third NMOS tube is connected to the drain of the fourth NMOS tube; the gate of the third NMOS tube is respectively connected to the first input end of the first inverter and the output end of the preamplifier circuit; the drain of the third NMOS tube is respectively connected to the output end of the first inverter and the first input end of the second inverter;

[0023] The gate of the fourth NMOS tube is connected to the output end of the second inverter; the source of the fourth NMOS tube is grounded.

[0024] In an optional implementation manner of the present application, the front-end circuit includes a first NMOS tube;

[0025] The relationship between the on-state voltages of the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, and the fifth NMOS transistor is:

[0026] V TH4 <V TH3 <V TH1 <V TH2 < <V TH5 ;

[0027] Among them, V TH4 represents the on-state voltage of the fourth NMOS tube; V TH3 Represents the on-state voltage of the third NMOS tube; V TH1 Represents the on-state voltage of the first NMOS tube; V TH2 Represents the conduction voltage of the second NMOS tube; V TH5 Represents the on-state voltage of the fifth NMOS tube.

[0028] In an optional implementation of the present application, it also includes:

[0029] Output filtering circuit;

[0030] The input end of the output filtering circuit is connected to the output end of the comparison inversion circuit, and is used for receiving the first reset signal and performing hysteresis output on the first reset signal.

[0031] In an optional implementation manner of the present application, the output filtering circuit includes:

[0032] A third inverter, a fourth inverter, a fifth inverter, a first capacitor and an AND operation module;

[0033] The input end of the third inverter is connected to the output end of the second inverter as the input end of the output filter circuit; the output end of the third inverter is connected to the first input end of the AND operation module and the input end of the fourth inverter respectively;

[0034] The output end of the fourth inverter is connected to the input end of the fifth inverter and one end of the first capacitor respectively; the other end of the first capacitor is grounded;

[0035] The output terminal of the fifth inverter is connected to the second input terminal of the AND operation module.

[0036] Compared with the prior art, the power-on reset circuit with hysteresis effect provided by the present invention can be set by setting the conduction voltage of the NMOS tube in the pre-circuit, the comparison inverting circuit and the control circuit, and through the control circuit, in the power-on process, as the power supply voltage gradually increases and the PMOS tube of the first inverter is turned on, the output power of the first inverter gradually increases until the output voltage of the first inverter is greater than the conduction voltage of the NMOS tube of the second inverter, and the power-on is completed; and in the power-off process, as the power supply voltage gradually decreases, the output voltage of the second inverter gradually increases, and the output voltage of the first inverter gradually decreases until the output voltage of the first inverter is less than the conduction voltage of the NMOS tube of the second inverter, and the power-off is completed. The power-on reset circuit with hysteresis effect can realize the hysteresis effect of the power-on reset circuit in the power-on process and the power-off process, and can provide a new research idea of ​​the power-on reset circuit in the field of electronic technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0038] Figure 1 A power-on reset circuit structure with hysteresis effect provided in an embodiment of the present application Figure 1 ;

[0039] Figure 2 A power-on reset circuit structure with hysteresis effect provided in an embodiment of the present application Figure 2 ;

[0040] Figure 3 A schematic diagram of the behavior of the reset signal during the power-on and power-off processes provided in an embodiment of the present application. DETAILED DESCRIPTION

[0041] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0042] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0043] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. The meaning of "several" is one or more, unless otherwise clearly and specifically defined.

[0044] In the description of the present invention, it is necessary to understand that the directions or positional relationships indicated by the terms "up", "down", "front", "back", "left", "right", etc. are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the present invention.

[0045] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0046] The power-on reset circuit generally plays the role of a low-effective global reset in integrated circuits and systems. The circuit generates a low-effective logic signal affected by the power supply voltage (VDD) of the circuit system, namely, the reset signal (RSTN), and controls other modules in the circuit system to perform a global reset.

[0047] The power-on reset circuit can set its upper and lower thresholds so that other modules of the circuit system always operate within the normal range of the power supply voltage, avoiding the problem of abnormal operation of the circuit system caused by too low power supply voltage.

[0048] Therefore, how to design and use a power-on reset circuit has become an important research direction for those skilled in the art in the field of electronic technology.

[0049] In order to solve the above technical problems, the present application provides a power-on reset circuit with hysteresis effect, please refer to Figure 1 , Figure 1 A power-on reset circuit structure with hysteresis effect provided in an embodiment of the present application Figure 1 .

[0050] like Figure 1 As shown, the power-on reset circuit with hysteresis effect includes: a preamplifier circuit 101, a comparison inversion circuit 102, a control circuit 103 and an output filter circuit 104;

[0051] The input end of the preamplifier circuit 101 is connected to a power supply, and the output end is connected to the comparison inversion circuit 102 , so as to provide an output voltage to the comparison inversion circuit 102 .

[0052] The comparison inversion circuit 102 includes a first inverter 1021 and a second inverter 1022 .

[0053] Wherein, the first input end of the first inverter 1021 is connected to the output end of the preamplifier circuit 101; the second input end of the first inverter 1021 is connected to the power supply; the output end of the first inverter 1021 is connected to the first input end of the second inverter 1022; the second input end of the second inverter 1022 is connected to the power supply; the output end of the second inverter 1022 is connected to the output filtering circuit; the comparison inverting circuit is used to output a first reset signal based on the voltage output by the preamplifier circuit and the power supply voltage;

[0054] The first input terminal of the control circuit 103 is connected to the output terminal of the preamplifier circuit 101 ; the second input terminal of the control circuit 103 is connected to the output terminal of the first inverter 1021 ; and the third input terminal of the control circuit 103 is connected to the output terminal of the second inverter 1022 .

[0055] The control circuit 103 is used to gradually increase the output power of the first inverter 1021 during the power-on process as the power supply voltage gradually increases and the PMOS tube of the first inverter 1021 is turned on, until the output voltage of the first inverter 1021 is greater than the turn-on voltage of the NMOS tube of the second inverter 1022, and the power-on is completed; and during the power-off process, gradually increase the output voltage of the second inverter 1022 and gradually decrease the output voltage of the first inverter 1021 as the power supply voltage gradually decreases, until the output voltage of the first inverter 1021 is less than the turn-on voltage of the NMOS tube of the second inverter 1022, and the power-off is completed.

[0056] An input end of the output filtering circuit 104 is connected to an output end of the comparison inversion circuit 102 , and is used to receive the first reset signal and filter and output the first reset signal.

[0057] For details, please refer to Figure 2 , Figure 2 A power-on reset circuit structure with hysteresis effect provided in an embodiment of the present application Figure 2 .

[0058] like Figure 2 As shown, the preamplifier circuit 101 includes: a first NMOS transistor (hereinafter referred to as NMOS1) and a first resistor R1.

[0059] The drain of NMOS1 is connected to one end of the first resistor R1 and the gate of NMOS1 respectively; the other end of the first resistor R1 is connected to the power supply VDD; the source of NMOS1 is grounded; the drain of NMOS1 serves as an output end to provide an output voltage to the comparison inverting circuit.

[0060] The first inverter 1021 includes a first PMOS transistor (hereinafter referred to as PMOS1) and a second NMOS transistor (hereinafter referred to as NMOS2).

[0061] The gate of the PMOS1 is connected to the gate of the NMOS2, and is connected to the output end of the preamplifier circuit as the first input end of the first inverter 1021;

[0062] The source of the PMOS 1 is connected to the power supply (VDD) as the second input terminal of the PMOS 1 .

[0063] The drain of PMOS1 is connected to the drain of NMOS2 and is connected to the input of the second inverter 1022 as the output of the first inverter 1021 ; the source of NMOS2 is grounded.

[0064] Similar to the first inverter 1021 , the second inverter includes: a second PMOS transistor (hereinafter referred to as PMOS2 ) and a fifth NMOS transistor (hereinafter referred to as NMOS5 ).

[0065] The gate of the PMOS2 is connected to the gate of the NMOS5, and is connected to the output end of the first inverter 1021 as the first input end of the second inverter;

[0066] The source of PMOS2 is connected to the power supply (VDD) as the second input terminal of PMOS2;

[0067] The drain of PMOS2 is connected to the drain of NMOS5 and is connected to the input of the output filter circuit as the output end of the second inverter 1022; the source of NMOS5 is grounded.

[0068] Furthermore, the control circuit includes: a third NMOS transistor (hereinafter referred to as NMOS3) and a fourth NMOS transistor (hereinafter referred to as NMOS4).

[0069] Among them, the source of NMOS3 is connected to the drain of NMOS4; the gate of NMOS3 is connected to the first input end of the first inverter 1021 and the output end of the preamplifier circuit respectively; the drain of NMOS3 is connected to the output end of the first inverter 1021 and the input end of the first inverter 1021 respectively.

[0070] The gate of NMOS4 is connected to the output terminal of the second inverter 1022 (ie, the drain of PMOS2 and the drain of NMOS2) and the input terminal of the output filter circuit 104 respectively; the source of NMOS4 is grounded.

[0071] Output filter circuit 104: includes a third inverter (such as Figure 2 INV1 shown), the fourth inverter (such as Figure 2 INV2 shown), the fifth inverter (such as Figure 2 INV3 shown), the first capacitor C1 and the AND operation model (such as Figure 2 AND as shown).

[0072] Among them, the input end of the third inverter is connected to the output end of the second inverter (that is, the drain of PMOS2 and the drain of NMOS2) as the input end of the output filtering circuit; the output end of the third inverter is respectively connected to the input end of the fourth inverter and the first input end of the operation module.

[0073] The output end of the fourth inverter is connected to the input end of the fifth inverter and one end of the first capacitor C1 respectively; the other end of the first capacitor C1 is grounded.

[0074] The output terminal of the fifth inverter is connected to the second input terminal of the operation module.

[0075] Furthermore, the on-state voltages of NMOS1, NMOS2, NMOS3, NMOS4, and NMOS5 are as follows:

[0076] V TH4 <V TH3 <V TH1 <V TH2 < <V TH5 ;

[0077] Among them, V TH4 represents the on-state voltage of the fourth NMOS tube; V TH3 Represents the on-state voltage of the third NMOS tube; V TH1 Represents the on-state voltage of the first NMOS tube; V TH2 Represents the conduction voltage of the second NMOS tube; V TH5 Represents the on-state voltage of the fifth NMOS tube.

[0078] First, in order to facilitate understanding of the working principle of the power-on reset circuit with hysteresis effect provided in the embodiment of the present application, first, the power-on process and the power-off process of the power-on reset circuit are described in detail.

[0079] Please refer to Figure 3 , Figure 3 A schematic diagram of the behavior of the reset signal during the power-on and power-off processes provided in an embodiment of the present application.

[0080] like Figure 3 As shown, for the power-on reset circuit, as time goes by, in the process of the power supply voltage VDD rising from 0 to the normal working voltage of the circuit system, the power-on reset circuit is reset only when the power supply voltage VDD is higher than the power-on threshold V PORR When the reset signal RSTN changes from logic 0 (Logic0) to logic 1 (Logic1), other modules of the circuit system end the global reset after receiving the signal and start working normally.

[0081] When the power supply voltage VDD drops from the normal voltage to 0, the power-on reset circuit will be turned off only when the power supply voltage VDD is lower than the power-down threshold V PORF When the reset signal RSTN changes from logic 1 to logic 0, other modules in the circuit system perform a global reset after receiving this signal.

[0082] For Figure 2 In the power-on reset circuit shown, the output voltage of the preamplifier circuit is set to V1, the output voltage of the first inverter is set to V2, the voltage of the second inverter is set to V4, the voltage between the drain of NMOS4 and the source of NMOS3 is set to V3, the output voltage of the third inverter is set to V5 (that is, the input voltage of the first input terminal of the AND operation module is set to V5), and the input voltage of the second input terminal of the AND operation module is set to V6.

[0083] During the power-on process, when the power supply voltage VDD is greater than 0 and less than V TH4 When , NMOS1 to NMOS4 are all in the off state, and at this time, the node voltage of V1 is equal to VDD.

[0084] In this case, since the voltage value of VDD is too small to turn on PMOS1, but there is a small amount of leakage current in NMOS2. Therefore, the node voltage of V2 is between 0 and VDD, and is closer to 0. Furthermore, for PMOS2 and NMOS5, the two form an inverter, so the leakage current of PMOS2 makes the node voltage of V4 between 0 and VDD, and is closer to VDD.

[0085] In this process, in order to prevent the V2 node voltage from affecting the subsequent circuit reset, the fourth inverter, the fifth inverter and the capacitor C1 are used to delay the generation of V6 (the potential of V6 is 0), and the potential of V6 (0) and the potential of V5 (0) are input into the AND operation module together, so that the reset signal of the AND operation module data is 0.

[0086] As the power supply voltage VDD continues to increase, when VDD is at V TH4 To V TH2 In the process between, since the gate and drain of NMOS1 are connected, in this case, the node voltage of V1 is equal to the on-voltage of NMOS1, that is, V1 = V TH1 During this process, the leakage current of NMOS2 gradually increases, and PMOS1 is not turned on, and the node voltage of V2 is pulled down to ground by NMOS2. In this state, the node voltage of V2 is 0. For PMOS2 and NMOS5, when the node voltage of V2 is 0, PMOS2 is turned on, NMOS5 is turned off, and the node voltage of V4 is pulled up to the power supply voltage VDD by PMOS2. Furthermore, for NMOS4, at this time, the gate voltage of NMOS4 is equal to the node voltage of V4, that is, the gate voltage of NMOS4 is equal to the power supply voltage VDD, which is greater than the on-state voltage V TH4 , NMOS4 is turned on, and the node voltage of V3 is pulled down to ground; for NMOS3, NMOS3 is turned on, but the node voltage of V2 is always 0.

[0087] In this process, the node voltage of V4 is VDD, the potentials of V5 and V6 received by the AND operation module are both 0, and the reset signal output by the AND operation is still 0.

[0088] As the power supply voltage VDD continues to increase, the node voltage of V1 is always equal to V TH1 (That is, the gate voltage of NMOS2 and PMOS1 is always equal to V TH1), and because VTH4 is less than VTH3. Therefore, the pull-down current flowing through NMOS3 and NMOS4 will no longer increase with the increase of VDD. In this process, the leakage current of POMS1 is gradually turned on with the increase of power supply voltage VDD, and the node voltage of V2 gradually increases.

[0089] When the node voltage of V2 gradually increases to V2 greater than V TH5 In the case of NMOS5 being turned on, the node voltage of V4 will be pulled down as NMOS5 is turned on until the node voltage of V4 is less than V TH4 , NMOS4 is turned off. In this case, the voltage of V3 will increase, and NMOS3 will remain in a weak on state until the power supply voltage VDD equals the power-on threshold V of the power-on reset circuit. PORR In this state, the node voltage of V2 is equal to the power supply voltage VDD, the node voltage of V4 is equal to 0, and the node voltage of V4 is input into the output filter circuit, so that the potentials of the first input terminal and the second input terminal of the AND operation module of the output filter circuit are both 1, and finally a reset signal with a potential of 1 is output to complete the power-on process of the reset circuit.

[0090] For the power-off process of the power-on reset circuit:

[0091] When the power supply voltage VDD drops from the normal value, the node voltage of V2 decreases with the decrease of the power supply voltage VDD until the node voltage of V2 is less than V TH5 When the voltage at the node of V4 increases, NMOS4 and NMOS3 are turned on, and the voltage at the node of V2 is pulled down to 0. At this time, the power supply voltage VDD is equal to the power-down threshold V of the power-on reset circuit. PORF After that, the node voltage of V2 is 0, the node voltage of V4 is equal to the power supply voltage VDD, the current IPD flowing through NMOS3 and NMOS4 is approximately equal to 0, and the reset signal finally output by the power-on reset circuit remains 0.

[0092] Based on the above description of the power-on process and the power-off process of the power-on reset circuit with hysteresis effect, it can be known that the reset voltage of the power-on reset circuit is V1, V2 and V TH5 The power consumption of the power-on reset circuit when working is determined by the first resistor R1 of the preamplifier circuit and V TH1 In an optional implementation manner of the present application, the resistance value of R1 is about 10 Mohm, and in a typical application scenario of VDD=3.3V, the quiescent current of the power-on reset circuit is less than 0.5 μA.

[0093] Furthermore, the hysteresis function of the power-on reset circuit is activated when the node voltage of V2 reaches the power-on threshold V PORR and power-down threshold V PORFDuring the power-on process, the voltage at the V2 node is equal to V TH5 When the power is turned off, the current flowing through NMOS3 and NMOS4 is limited to a constant pull-down current (IPD); and during the power-off process, if the node voltage of V2 is equal to V TH5 When , the pull-down current flowing through NMOS3 and NMOS4 is approximately equal to 0.

[0094] Therefore, when the pull-up capability of PMOS1 remains unchanged, the node voltage of V2 is equal to V TH5 The corresponding power supply voltage is greater than the V2 node voltage during power-off, which is equal to V TH5 The corresponding power supply voltage is V PORR >V PORF .

[0095] In the embodiment of the present application, the hysteresis of the power-on reset circuit is mainly affected by the current size of IPD, that is, V1=V TH1 and the size of NMOS3; the larger the IPD, the more obvious the hysteresis. Therefore, IPD should not be too large. If it exceeds the pull-up capability of PM1, V2 will always be pulled down to 0, RSTN will be locked at 0, and the function will fail. When IPD is within a reasonable range and the size of NMOS3 is increased to increase the hysteresis, NMOS3 and NMOS4 should be adjusted in proportion so that IPD is always limited by NMOS3 to prevent the current determined by NMOS4 from being too large when VDD is too high, causing V2 to always be pulled down.

[0096] In summary, the power-on reset circuit with hysteresis effect provided in the present application can be set by setting the conduction voltage of the NMOS tube in the pre-circuit, the comparison inverting circuit and the control circuit, and through the control circuit, during the power-on process, as the power supply voltage gradually increases and the PMOS tube of the first inverter is turned on, the output power of the first inverter gradually increases until the output voltage of the first inverter is greater than the conduction voltage of the NMOS tube of the second inverter, and the power-on is completed; and during the power-off process, as the power supply voltage gradually decreases, the output voltage of the second inverter gradually increases, and the output voltage of the first inverter gradually decreases until the output voltage of the first inverter is less than the conduction voltage of the NMOS tube of the second inverter, and the power-off is completed. The power-on reset circuit with hysteresis effect can realize the hysteresis effect of the power-on reset circuit in the power-on process and the power-off process, and can provide a new research idea of ​​the power-on reset circuit in the field of electronic technology.

[0097] The embodiments of the present disclosure are described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, a person skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A power-on reset circuit with hysteresis effect, characterized in that: include: Preamplifier circuit, comparison inversion circuit, control circuit; The input end of the preamplifier circuit is connected to a power supply, and the output end of the preamplifier circuit is connected to the comparison inversion circuit, so as to provide an output voltage to the comparison inversion circuit; The comparison inverting circuit comprises a first inverter and a second inverter, wherein the first input end of the first inverter is connected to the output end of the preamplifier circuit; the second input end of the first inverter is connected to the power supply; the output end of the first inverter is connected to the first input end of the second inverter; and the second input end of the second inverter is connected to the power supply; The comparison inversion circuit is used to output a first reset signal based on the voltage output by the preamplifier circuit and the power supply voltage; The first input terminal of the control circuit is connected to the output terminal of the preamplifier circuit; the second input terminal of the control circuit is connected to the output terminal of the first inverter; the third input terminal of the control circuit is connected to the output terminal of the second inverter; The control circuit is used for gradually increasing the output voltage of the first inverter during the power-on process as the power supply voltage gradually increases and the PMOS tube of the first inverter is turned on, until the output voltage of the first inverter is greater than the turn-on voltage of the NMOS tube of the second inverter, thereby completing the power-on process; And during the power-off process, as the power supply voltage gradually decreases, the output voltage of the second inverter gradually increases, and the output voltage of the first inverter gradually decreases, until the output voltage of the first inverter is less than the conduction voltage of the NMOS tube of the second inverter, and the power-off is completed.

2. The power-on reset circuit with hysteresis effect according to claim 1, characterized in that: The front-end circuit includes: a first NMOS tube and a first resistor; The drain of the first NMOS tube is respectively connected to one end of the first resistor and the gate of the first NMOS tube; the other end of the first resistor is connected to the power supply; the source of the first NMOS tube is grounded; wherein the drain of the first NMOS tube serves as an output end to provide an output voltage to the comparison inverting circuit.

3. The power-on reset circuit with hysteresis effect according to claim 1, characterized in that: The first inverter includes a first PMOS tube and a second NMOS tube; The gate of the first PMOS tube is connected to the gate of the second NMOS tube, and is connected to the output end of the preamplifier circuit as the first input end of the first inverter; The source of the first PMOS tube is connected to the power supply as the second input end of the first PMOS tube; The drain of the first PMOS tube is connected to the drain of the second NMOS tube, and is connected to the input of the second inverter as the output of the first inverter; the source of the second NMOS tube is grounded.

4. The power-on reset circuit with hysteresis effect according to claim 3, characterized in that: The second inverter includes: a second PMOS tube and a fifth NMOS tube; The gate of the second PMOS tube is connected to the gate of the fifth NMOS tube, and is connected to the output end of the first inverter as the first input end of the second inverter; The source of the second PMOS tube is connected to the power supply as the second input end of the second PMOS tube; The drain of the second PMOS tube is connected to the drain of the fifth NMOS tube and serves as the output end of the second inverter; the source of the fifth NMOS tube is grounded.

5. The power-on reset circuit with hysteresis effect according to claim 4, characterized in that: The control circuit comprises: a third NMOS tube and a fourth NMOS tube; The source of the third NMOS tube is connected to the drain of the fourth NMOS tube; the gate of the third NMOS tube is respectively connected to the first input end of the first inverter and the output end of the preamplifier circuit; the drain of the third NMOS tube is respectively connected to the output end of the first inverter and the first input end of the second inverter; The gate of the fourth NMOS tube is connected to the output end of the second inverter; the source of the fourth NMOS tube is grounded.

6. The power-on reset circuit with hysteresis effect according to claim 5, characterized in that: The front circuit includes a first NMOS tube; The relationship between the on-state voltages of the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, and the fifth NMOS transistor is: In TH4 <V TH3 <V TH1 <V TH2 < <V TH5 ; Among them, V TH4 represents the on-state voltage of the fourth NMOS tube; V TH3 Represents the on-state voltage of the third NMOS tube; V TH1 Represents the on-state voltage of the first NMOS tube; V TH2 Represents the conduction voltage of the second NMOS tube; V TH5 Represents the on-state voltage of the fifth NMOS tube.

7. The power-on reset circuit with hysteresis effect according to claim 1, characterized in that: Also includes: Output filtering circuit; The input end of the output filtering circuit is connected to the output end of the comparison inversion circuit, and is used to receive the first reset signal and filter and output the first reset signal.

8. The power-on reset circuit with hysteresis effect according to claim 7, characterized in that: The output filtering circuit comprises: A third inverter, a fourth inverter, a fifth inverter, a first capacitor and an AND operation module; The input end of the third inverter is connected to the output end of the second inverter as the input end of the output filter circuit; the output end of the third inverter is connected to the first input end of the AND operation module and the input end of the fourth inverter respectively; The output end of the fourth inverter is connected to the input end of the fifth inverter and one end of the first capacitor respectively; the other end of the first capacitor is grounded; The output terminal of the fifth inverter is connected to the second input terminal of the AND operation module.

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