Reference voltage buffer with low power consumption and strong driving capability applied to SAR ADC (Synthetic Aperture Radar Analog to Digital Converter)

Abstract

The invention discloses a low-power-consumption and strong-driving-capacity reference voltage buffer applied to an SAR ADC, and belongs to the technical field of reference voltage buffers.The reference voltage buffer is composed of three parts of circuits, the first part is a two-stage operational amplifier circuit of an output source follower, the second part is an output buffer circuit, and the third part is a second-stage operational amplifier circuit of an output source follower. The third part is a dynamic current enhancement circuit; wherein the output of the two-stage operational amplifier circuit is used for providing bias voltage for the output buffer circuit; the output buffer circuit is an open-loop source follower, and the output of the output buffer circuit is used for providing reference voltage for the ADC; the dynamic current enhancement circuit generates current pulses with adjustable size and pulse width through control signals of an ADC sampling clock and a conversion clock. According to the invention, the power consumption is reduced, the driving capability of the buffer is enhanced, the output ripple of the reference voltage is reduced, and the circuit has very strong engineering significance in the design of a fully-integrated high-speed high-precision SAR ADC (Synthetic Aperture Radar Analog to Digital Converter).

Description

Technical Field

[0001] The invention belongs to the technical field of reference voltage buffers, and in particular relates to a reference voltage buffer with low power consumption and strong driving capability applied to SAR ADC. Background Art

[0002] At present, the highly integrated SAR ADC module requires the ADC to have a built-in high-performance reference voltage buffer, which puts forward higher requirements for accuracy, speed and low power consumption in the design of the reference voltage buffer. In order to meet the requirements of faster settling time and smaller ripple of the reference voltage buffer under high-speed clock operation, the design of the buffer often uses large-area filter capacitors and high-current source followers as the output stage. This design undoubtedly increases the chip area and power consumption. Summary of the invention

[0003] The purpose of the present invention is to provide a reference voltage buffer with low power consumption and strong driving capability for use in a SAR ADC. An improved circuit is proposed for the design of a traditional reference voltage buffer in a SAR ADC that sacrifices power consumption and area in order to obtain strong driving capability. A new reference voltage buffer for use in a SAR ADC is designed, which increases its strong driving capability, shortens the reference voltage establishment time, reduces the ripple, and also reduces the power consumption of the buffer, thereby effectively solving the problems raised in the above-mentioned background technology.

[0004] To achieve the above object, the present invention provides the following technical solution: a reference voltage buffer with low power consumption and strong driving capability applied to SAR ADC, the reference voltage buffer is composed of three circuit parts, the first part is a two-stage operational amplifier circuit of an output source follower, the second part is an output buffer circuit, and the third part is a dynamic current enhancement circuit;

[0005] Among them, the output of the two-stage operational amplifier circuit is used to provide a bias voltage for the output buffer circuit; the output buffer circuit is an open-loop source follower, and its output is used to provide a reference voltage for the ADC; the dynamic current enhancement circuit generates a current pulse with adjustable size and pulse width through the control signals of the ADC sampling clock and the conversion clock. When there is a momentary large load change, the reference voltage buffer is supplemented with driving current in time to maintain the stability of the output voltage and reduce the output ripple when the load changes.

[0006] Preferably, the output stage of the two-stage operational amplifier is in the core power domain, and the core device is used as the output source follower of the operational amplifier to increase the transconductance of the source follower; and the output buffer circuit is also designed in the core power domain so as to achieve mirror replication with the output stage of the two-stage operational amplifier.

[0007] Preferably, the two-stage operational amplifier circuit includes a differential amplifier and a source follower; wherein the differential amplifier is an operational amplifier, serving as the first working stage, and the source follower is composed of MN0 and I0, serving as the second working stage; the source of MN0 is connected to the negative electrode of the operational amplifier to form negative feedback, so that the voltages of the positive and negative electrodes of the operational amplifier are both equal to VREF_IN; at the same time, the operational amplifier operates in the VDD_IO power domain, while MN0 operates in the VDD_CORE power domain, so that the source follower has a larger transconductance and smaller power consumption.

[0008] Preferably, the output buffer circuit is a source follower with strong driving capability, the gate of MN1 in the output buffer circuit is connected to the gate of MN0 in the two-stage operational amplifier circuit, and MN1 also operates in the power domain of VDD_CORE to achieve mirror replication with the output stage of the two-stage operational amplifier.

[0009] Preferably, the dynamic current enhancement circuit is a switch-controlled dynamic current enhancement circuit, in which the gate of MP0 is controlled by the clock of the ADC core through a control module. When a large load is switched on the ADC core causing the VREF_OUT voltage on the capacitor CL to jitter, MP0 is turned on and the current of I2 is directly supplemented to CL to reduce the jitter of VREF_OUT.

[0010] Compared with the prior art, the present invention has the following beneficial effects:

[0011] The present invention reduces power consumption while enhancing the driving capability of the buffer and reducing the output ripple of the reference voltage, and has great engineering significance in the design of a fully integrated high-speed and high-precision SAR ADC. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 The present invention is a circuit structure block diagram of a reference voltage buffer with low power consumption and strong driving capability applied to SAR ADC.

[0013] Figure 2 FIG. 4 is a circuit diagram of an operational amplifier in a reference voltage buffer of the present invention.

[0014] Figure 3 FIG. 4 is a structural diagram of a current source in a reference voltage buffer of the present invention.

[0015] Figure 4A The figure is a comparison diagram of the transient characteristics of VREF_OUT of the reference voltage buffer of the present invention and the traditional reference voltage buffer when the same load jumps.

[0016] Figure 4BThe figure is a comparison diagram of power consumption of the reference voltage buffer of the present invention and the VREF_OUT of the traditional reference voltage buffer when the two structures have the same load jump. DETAILED DESCRIPTION

[0017] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0018] The specific implementation part of the present invention provides a reference voltage buffer with low power consumption and strong driving capability for SAR ADC, which is composed of three circuit parts. The first part is a two-stage operational amplifier circuit with an output source follower, the second part is an output buffer stage circuit, and the third part is a dynamic current enhancement circuit. Compared with the traditional design scheme, the output stage of the two-stage operational amplifier in the first part of this design is replaced with the core power domain, and the core device is used as the output source follower of the operational amplifier, which increases the transconductance of the source follower. The output of the two-stage operational amplifier in the first part only provides a bias voltage for the output buffer of the second part, so the main pole of the operational amplifier can be designed inside to ensure the stability of the operational amplifier, and the design of the amplifier does not require a large gain-bandwidth product, which effectively reduces power consumption compared with the traditional operational amplifier. The output buffer of the second part is an open-loop source follower, and the output provides a reference voltage VREF for the ADC. In order to reduce power consumption, this part is also designed in the core power domain, which can achieve mirror replication with the output stage of the previous part. In traditional circuit design, the power consumption of this part needs to be large enough to meet the driving requirements of the ADC during the sampling and conversion period of the capacitor charging and discharging. The third part is a switch-controlled dynamic current enhancement circuit, which can generate current pulses with adjustable size and pulse width through the control of the ADC sampling clock and the conversion clock. When there is a momentary large load change, the reference voltage buffer is promptly supplemented with driving current to maintain the stability of the output voltage and reduce the output ripple when the load changes. In the application of high-speed ADC, the power loss caused by this dynamic current is much smaller than the power loss caused by the traditional static current, and the required filter capacitor can be effectively reduced. In addition, the dynamic current enhancement circuit acts on the open-loop output buffer of the second part, and will not affect the stability of the operational amplifier of the first part.

[0019] Furthermore, the embodiment section of the present application specifically describes three embodiments. Of course, the protection scope of the present application is not limited to the following three embodiments.

[0020] Example 1 Figure 1 As shown, Figure 1The structural block diagram of the new reference voltage buffer is described. The reference voltage buffer can be divided into three parts a, b, and c in the figure. Part a is a two-stage operational amplifier, in which the operational amplifier (amp) is a differential amplifier of the first stage, MN0 and I0 constitute a source follower of the second stage, and the source of MN0 is connected to the negative electrode of the operational amplifier (amp) to form negative feedback, so that the voltage of the positive and negative electrodes of the operational amplifier (amp) is the same, equal to VREF_IN. In order to obtain a larger voltage margin and improve the gain of the operational amplifier, the operational amplifier (amp) works in the power domain of VDD_IO, and MN0 works in the power domain of VDD_CORE, so that the source follower of the second stage has a larger transconductance and smaller power consumption. Part b of the reference voltage buffer is a source follower with strong driving capability. The gate of MN1 is connected to the gate of MN0, and MN1 and MN0 work under the power supply of VDD_CORE at the same time. In order to make the output voltage VREF_OUT=VREF_IN, when I1=m*I0, the number of MN1s in parallel needs to be equal to m times the number of MN0s in parallel. Part c of the reference voltage buffer is a switch-controlled dynamic current enhancement circuit. The gate of MP0 is controlled by the clock of the ADC core through the control module. When a large load is switched on the ADC core causing the VREF_OUT voltage on the capacitor CL to jitter, MP0 is turned on and the current of I2 is directly supplemented to CL to reduce the jitter of VREF_OUT. The current of I2 can be designed artificially. It has been verified that this current is much smaller than the static current added by the traditional structure to improve the driving capability of MN1.

[0021] Example 2 Figure 2 As shown, this is Figure 1 An amp circuit in.

[0022] Example 3 Figure 3 As shown, this is a current source circuit.

[0023] Figure 4A and Figure 4B The transient characteristics of VREF_OUT of the proposed reference voltage buffer and the traditional reference voltage buffer under the same load jump and the power consumption comparison of the two structures are shown. It can be seen that the output ripple of the new reference voltage buffer VREF_OUT is significantly smaller, the driving capability is stronger, and the power consumption is only about half of that of the traditional structure.

[0024] The present invention reduces power consumption while enhancing the driving capability of the buffer and reducing the output ripple of the reference voltage, and has great engineering significance in the design of a fully integrated high-speed and high-precision SAR ADC.

[0025] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0026] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A reference voltage buffer with low power consumption and strong driving capability applied to SAR ADC, characterized in that: The reference voltage buffer is composed of three circuit parts, the first part is a two-stage operational amplifier circuit of an output source follower, the second part is an output buffer circuit, and the third part is a dynamic current enhancement circuit; Among them, the output of the two-stage operational amplifier circuit is used to provide a bias voltage for the output buffer circuit; the output buffer circuit is an open-loop source follower, and its output is used to provide a reference voltage for the ADC; the dynamic current enhancement circuit generates a current pulse with adjustable size and pulse width through the control signals of the ADC sampling clock and the conversion clock. When there is a momentary large load change, the reference voltage buffer is supplemented with driving current in time to maintain the stability of the output voltage and reduce the output ripple when the load changes.

2. A reference voltage buffer with low power consumption and strong driving capability applied to SAR ADC according to claim 1, characterized in that: The output stage of the two-stage operational amplifier is in the core power domain, and the core device is used as the output source follower of the operational amplifier to increase the transconductance of the source follower; and the output buffer circuit is also designed in the core power domain so as to achieve mirror replication with the output stage of the two-stage operational amplifier.

3. A reference voltage buffer with low power consumption and strong driving capability applied to SAR ADC according to claim 2, characterized in that: The two-stage operational amplifier circuit includes a differential amplifier and a source follower; wherein the differential amplifier is an operational amplifier, serving as the first working stage, and the source follower is composed of MN0 and I0, serving as the second working stage; the source of MN0 is connected to the negative electrode of the operational amplifier to form negative feedback, so that the voltages of the positive and negative electrodes of the operational amplifier are both equal to VREF_IN; at the same time, the operational amplifier operates in the VDD_IO power domain, while MN0 operates in the VDD_CORE power domain, so that the source follower has a larger transconductance and smaller power consumption.

4. The reference voltage buffer with low power consumption and strong driving capability used in SAR ADC according to claim 3, characterized in that: The output buffer circuit is a source follower with strong driving capability. The gate of MN1 in the output buffer circuit is connected to the gate of MN0 in the two-stage operational amplifier circuit, and MN1 also works in the power domain of VDD_CORE to achieve mirror replication with the output stage of the two-stage operational amplifier.

5. A reference voltage buffer with low power consumption and strong driving capability applied to SAR ADC according to claim 4, characterized in that: The dynamic current enhancement circuit is a switch-controlled dynamic current enhancement circuit. The gate of MP0 in the dynamic current enhancement circuit is controlled by the clock of the ADC core through the control module. When the ADC core has a large load switching causing the VREF_OUT voltage on the capacitor CL to jitter, MP0 is turned on and the current of I2 is directly supplemented to CL to reduce the jitter of VREF_OUT.

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