USB data transmission circuit and transmission method

Abstract

The invention discloses a USB data transmission circuit and a USB data transmission method. The USB data transmission circuit comprises a physical layer interface unit, a data sending unit and a data receiving unit, wherein the data sending unit counts a synchronization domain of a data packet by using a system clock to obtain a standard value of a sending signal bit width, and parses sending data according to the standard value of the sending signal bit width to complete USB data sending; and the data receiving unit counts the synchronization domain of the data packet by using the system clock to obtain a standard value of the bit width of the received signal, and analyzes the received data according to the standard value of the bit width of the received signal to complete USB data receiving. According to the invention, the USB host end and the USB equipment end can directly utilize the internal system clocks of the respective chips to realize the normal transmission of USB data.

Description

Technical Field

[0001] The invention relates to a USB data transmission circuit and also to a USB data transmission method, belonging to the technical field of data communication. Background Art

[0002] USB (Universal Serial Bus) is a communication protocol that supports data exchange between USB hosts and USB devices. It is widely used for its high speed, hot-swap capability, scalability and support for multiple devices. USB data transmission uses this protocol and corresponding transmission circuits to allow personal computers to communicate and power external devices such as printers, scanners, keyboards, mice, and storage. In addition, USB technology is also widely used in different types of electronic devices and embedded systems to achieve communication between chips and chips, and between modules.

[0003] In the prior art, USB data transmission usually uses a 48Mhz clock as a sampling clock to sample the data signal sent by the USB host, and the USB bus protocol defines a set of characteristic signal sequences, such as the synchronization domain SYNC, the packet identifier PID, and the packet end mark EOP, etc., to synchronize the local 48Mhz clock of the device end. Therefore, when designing the USB system, both the USB host end and the USB device end need to provide an accurate 48Mhz sampling clock to ensure normal decoding, and the sampling clock cannot directly use the internal clock of the chip, but needs to be used in conjunction with an external crystal oscillator. Furthermore, when the device operates at different temperatures, the internal clock of the chip will change with the temperature. In this case, the difficulty and cost of providing an accurate 48Mhz sampling clock will increase.

[0004] In the Chinese invention patent with patent number ZL 201810328409.4, a digital implementation method for USB data transmission is disclosed. The method comprises the following steps: sending a SOF packet and extracting the middle four bits in the SOF packet and obtaining a counter value through the middle four bits; setting a sending mode according to the counter value and a preset first algorithm, and sending a DATA packet according to the sending mode; receiving a DATA packet according to the sending mode and extracting a special sampling point in the DATA packet according to a preset second algorithm to parse the DATA packet. However, the method still has the following problems: first, only the DP signal in the differential signal is detected, which will cause communication errors in the case of large interference; second, the host provides a SOF learning packet, and subsequent transmissions need to be based on this learning packet, which will not work when the system frequency changes; third, only counting is performed on the SOF learning packet, and when the high level and the low level are inconsistent, communication errors will occur; fourth, the use of SOF learning packets for synchronization will cause the current SOF data to be lost, thereby affecting communication. Summary of the invention

[0005] The primary technical problem to be solved by the present invention is to provide a USB data transmission circuit.

[0006] Another technical problem to be solved by the present invention is to provide a transmission method for USB data transmission.

[0007] Another technical problem to be solved by the present invention is to provide a transmission method for USB data reception.

[0008] In order to achieve the above object, the present invention adopts the following technical solutions:

[0009] According to a first aspect of an embodiment of the present invention, there is provided a USB data transmission circuit, comprising a physical layer interface unit, a data sending unit and a data receiving unit; wherein:

[0010] The external differential signal bus is connected to the physical layer interface unit, the physical layer interface unit is connected to the data sending unit and the data receiving unit respectively through the internal differential signal bus and the single-ended signal line, and the data sending unit is connected to the physical layer interface unit through two data lines;

[0011] The data transmission unit is used to transmit USB data, and it uses the system clock to count the synchronization domain of the data packet to obtain the standard value of the bit width of the transmission signal, and parses the transmission data according to the standard value of the bit width of the transmission signal to complete the USB data transmission;

[0012] The data receiving unit is used to receive USB data, and it uses the system clock to count the synchronization domain of the data packet to obtain the standard value of the bit width of the received signal, and parses the received data with the standard value of the bit width of the received signal to complete the USB data reception;

[0013] The physical layer interface unit is used to implement the physical layer function of the USB protocol.

[0014] Preferably, the data sending unit includes a first reset counter, a first EOP counter, a first high level counter, a first low level counter, a first decoding state machine, a first data receiving module and a sending counting module, as well as a first register, a second register, a third register, a fourth register, a fifth register and a sixth register, a first inverter, a second inverter, a first AND gate and a second AND gate; wherein,

[0015] The first decoding state machine is used to logically control the working state of each functional module in the data sending unit;

[0016] The first data receiving module is used to receive USB control data, and uses the standard value of the bit width of the sending signal to extract the received data;

[0017] The sending counting module is used for sending data, and uses the standard value of the sending signal bit width to parse and transmit the sending data.

[0018] Preferably, in the data sending unit, the positive signal line of the internal differential signal bus is connected to the input end of the first register, the output end of the first register is connected to the input end of the second register, and the output end of the second register is connected to the first input end of the first AND gate and the first input end of the second AND gate respectively through the first inverter;

[0019] The negative signal line of the internal differential signal bus is connected to the input end of the third register, the output end of the third register is connected to the input end of the fourth register, and the output end of the fourth register is connected to the second input end of the first AND gate and the second input end of the second AND gate respectively through the second inverter;

[0020] The output end of the first AND gate is connected to the input end of the first reset counter, and the output end of the first reset counter is connected to the bus reset end of the first decoding state machine;

[0021] The output end of the second AND gate is connected to the input end of the first EOP counter, the output end of the first EOP counter is connected to the EOP identification end of the first decoding state machine, and the control end of the first EOP counter is connected to the counting cycle configuration end of the first decoding state machine;

[0022] The clock ends of the first register, the second register, the third register and the fourth register are all connected to the system clock signal end.

[0023] Preferably, in the data sending unit, the single-ended signal line is connected to the input end of the fifth register, the output end of the fifth register is connected to the input end of the sixth register, the output end of the sixth register is connected to the input ends of the first high level counter and the first low level counter respectively, and the output ends of the first high level counter and the first low level counter are connected to the first counting end and the second counting end of the first decoding state machine respectively;

[0024] The clock terminals of the fifth register and the sixth register are both connected to the system clock signal terminal.

[0025] Preferably, during the bus reset phase of sending data packets, both the positive signal and the negative signal are at low levels, the first reset counter starts counting, and when the count value reaches a reset preset value, a reset signal is generated to start the first decoding state machine to perform a state jump and enter the synchronization domain detection phase.

[0026] Preferably, in the synchronization domain stage of sending a data packet, the first high-level counter and the first low-level counter respectively count the high-level bits and low-level bits of the single-ended signal to obtain N high-level count values ​​and N low-level count values, and the first decoding state machine averages the counting results to obtain a standard value of the bit width of the transmitted signal; wherein N is a positive integer.

[0027] Preferably, during the EOP phase of sending a data packet, the first EOP counter starts counting, and when the count value reaches an EOP preset value, an end-of-packet symbol EOP is sent, and the first decoding state machine performs a state jump to enter a data packet sending end state.

[0028] Preferably, the data receiving unit includes a second reset counter, a second EOP counter, a second high level counter, a second low level counter, a second decoding state machine and a second data receiving module, as well as a seventh register, an eighth register, a ninth register, a tenth register, an eleventh register, a twelfth register, a third inverter, a fourth inverter, a third AND gate and a fourth AND gate; wherein,

[0029] The second decoding state machine is used to logically control the working state of each functional module in the data receiving unit;

[0030] The second data receiving module is used to receive data, and uses the standard value of the bit width of the received signal to parse and extract the received data;

[0031] The clock ends of the seventh register, the eighth register, the ninth register, the tenth register, the eleventh register and the twelfth register are all connected to the system clock signal end.

[0032] Preferably, in the synchronization domain stage of receiving the data packet, the second high-level counter and the second low-level counter respectively count the high-level bits and low-level bits of the single-ended signal to obtain N high-level count values ​​and N low-level count values, and the second decoding state machine averages the counting results to obtain a standard value of the bit width of the received signal; wherein N is a positive integer.

[0033] According to a second aspect of an embodiment of the present invention, a transmission method for USB data transmission is provided, which is implemented based on the above-mentioned USB data transmission circuit and includes the following steps:

[0034] (11) The reset counter uses the system clock signal to count the positive and negative signals of the differential signal at the same time when they are at a low level, and generates a reset signal when the count value reaches a reset preset value;

[0035] (12) The decoding state machine enters the synchronization domain detection stage;

[0036] (13) In the synchronization domain stage, the high level counter and the low level counter respectively count the high level bits and the low level bits of the single-ended signal using the system clock signal to obtain N high level count values ​​and N low level count values; wherein N is a positive integer;

[0037] (14) averaging the N high-level count values ​​and the N low-level count values, and using the obtained average value as a standard value of the bit width of the transmitted signal;

[0038] (15) parsing the subsequent logical domain of the USB data packet using the standard value of the bit width of the transmission signal and then sending the corresponding data;

[0039] (16) The EOP counter uses the system clock signal to count the positive and negative signals of the differential signal at low levels, and sends an end-of-packet symbol EOP when the count value reaches an EOP preset value;

[0040] (17) Go to step (12) and loop through steps (12) to (16) to send the next data packet; or, end USB data transmission;

[0041] According to a third aspect of an embodiment of the present invention, a transmission method for USB data reception is provided, which is implemented based on the above-mentioned USB data transmission circuit and includes the following steps:

[0042] (21) The reset counter uses the system clock signal to count the positive and negative signals of the differential signal at the same time when they are at a low level, and generates a reset signal when the count value reaches a reset preset value;

[0043] (22) The decoding state machine enters the synchronization domain detection stage;

[0044] (23) In the synchronization domain stage, the high level counter and the low level counter respectively count the high level bits and the low level bits of the single-ended signal using the system clock signal to obtain N high level count values ​​and N low level count values, where N is a positive integer;

[0045] (24) averaging the N high-level count values ​​and the N low-level count values, and using the obtained average value as a standard value of the received signal bit width;

[0046] (25) parsing the subsequent logical domain of the USB data packet using the standard value of the bit width of the received signal to obtain corresponding data;

[0047] (26) The EOP counter uses the system clock signal to count the positive and negative signals of the differential signal, both of which are low level, and when the count value reaches the EOP preset value, it is determined that the packet end character EOP is received;

[0048] (27) Go to step (21) and loop through steps (21) to (26) to receive the next data packet; or, end USB data reception.

[0049] Compared with the prior art, in the USB data transmission circuit provided by the present invention, during the data transmission process, both the USB host end and the USB device end can directly use the internal system clock of their respective chips to count the high and low levels of the synchronization domain SYNC in the data packet, and obtain the standard value of the Bit width of the sending signal or the standard value of the Bit width of the receiving signal after average calculation, and use the standard value of the Bit width to parse the subsequent logical domain of the data packet to achieve normal transmission of USB data. Therefore, the USB data transmission circuit provided by the present invention has the beneficial effects of low design difficulty, low circuit cost, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 A structural block diagram of a USB data transmission circuit provided by an embodiment of the present invention;

[0051] Figure 2 A circuit schematic diagram of a data sending unit in an embodiment of the present invention;

[0052] Figure 3 A schematic diagram of the domain structure of a typical data packet of USB data in the prior art;

[0053] Figure 4 A key timing comparison diagram of a data sending unit in an embodiment of the present invention;

[0054] Figure 5 A circuit schematic diagram of a data receiving unit in an embodiment of the present invention;

[0055] Figure 6 A key timing comparison diagram of a data receiving unit in an embodiment of the present invention;

[0056] Figure 7 The process of the USB data transmission method in the embodiment of the present invention is as follows Figure 1 ;

[0057] Figure 8 The process of the USB data transmission method in the embodiment of the present invention is as follows Figure 2 . DETAILED DESCRIPTION

[0058] The technical content of the present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0059] like Figure 1 As shown, the USB data transmission circuit provided by the embodiment of the present invention includes a data sending unit, a data receiving unit and a physical layer (PHY) interface unit. Among them, the external differential signal bus (DP, DM) is connected to the PHY interface unit, and the PHY interface unit is connected to the data sending unit and the data receiving unit respectively through the internal differential signal bus (DP, DM) and the single-ended signal line (RCV), and the data sending unit is connected to the PHY interface unit through two data lines (TX_SEO, TX_DATA). Among them, the differential signal bus includes a positive signal line DP and a negative signal line DM.

[0060] The data transmission unit is used to transmit USB data. It uses the system clock to count the synchronization field SYNC of the data packet to obtain the standard value of the bit width of the transmission signal, and uses the standard value of the bit width of the transmission signal to parse the transmission data and complete the USB data transmission.

[0061] The data receiving unit is used to receive USB data. It uses the system clock to count the synchronization field SYNC of the data packet to obtain the standard value of the bit width of the received signal, and uses the standard value of the bit width of the received signal to parse the received data and complete the USB data reception.

[0062] The PHY interface unit is used to implement the physical layer functions of the USB protocol, including converting external differential signals (DP, DM) into single-ended signals (RCV).

[0063] The USB data transmission circuit provided by the embodiment of the present invention does not need to use the same and accurate sampling clock when sending or receiving data, but can complete the USB data transmission by using the internal system clock of the chip.

[0064] In one embodiment of the present invention, Figure 2As shown, the data sending unit includes a first reset counter, a first EOP (End of Operation Phase) counter, a first high level counter, a first low level counter, a first decoding state machine, a first data receiving module and a sending counting module, as well as a first register DP_R0, a second register DP_R1, a third register DM_R0, a fourth register DM_R1, a fifth register RCV_R0 and a sixth register RCV_R1, a first inverter IN1, a second inverter IN2, a first AND gate AND1 and a second AND gate AND2. Among them, the positive signal line DP of the internal differential signal bus is connected to the input end of the first register DP_R0, the output end of the first register DP_R0 is connected to the input end of the second register DP_R1, and the output end of the second register DP_R1 is connected to the first input end of the first AND gate AND1 and the first input end of the second AND gate AND2 through the first inverter IN1; the negative signal line DM of the internal differential signal bus is connected to the input end of the third register DM_R0, the output end of the third register DM_R0 is connected to the input end of the fourth register DM_R1, and the output end of the fourth register DM_R1 is connected to the second input end of the first AND gate AND1 and the second input end of the second AND gate AND2 through the second inverter IN2; the first AND gate AND The output end of the second AND gate AND2 is connected to the input end of the first EOP counter, and the output end of the first EOP counter is connected to the EOP identification end of the first decoding state machine. At the same time, the control end of the first EOP counter is connected to the counting cycle configuration end of the first decoding state machine. The single-ended signal line RCV is connected to the input end of the fifth register RCV_R0, the output end of the fifth register RCV_R0 is connected to the input end of the sixth register RCV_R1, and the output end of the sixth register RCV_R1 is connected to the first high level counter. The six registers are connected to the input end of the first decoding state machine and the first low-level counter, and the output ends of the first high-level counter and the first low-level counter are connected to the first counting end and the second counting end of the first decoding state machine respectively; the clock ends of the six registers are connected to the system clock signal end; the first enable end and the data end of the first decoding state machine are connected to the first data receiving module, and the second enable end of the first decoding state machine is connected to the sending counting module; the control end of the first data receiving module is connected to the control end of the sending counting module; the input end of the sending counting module is connected to the data signal sending end, and the first output end TX_SE0 and the second output end TX_DATA of the sending counting module are both connected to the PHY interface unit.

[0065] The first decoding state machine is used to perform logical control on the working state of each functional module in the data sending unit.

[0066] The first data receiving module is used to receive USB control data, and it uses the standard value of the bit width of the sending signal to extract the received data. USB control data includes token packets, port numbers and other data.

[0067] The sending counting module is used to send data, and it uses the standard value of the bit width of the sending signal to parse and transmit the sending data.

[0068] The working principle of the data sending unit in this embodiment is described in detail below.

[0069] The basic unit of USB data transmission is packet. Figure 3 As shown in the figure, a data packet is composed of different fields. Different types of data packets contain different fields, but they all start with the synchronization field SYNC, followed by a packet identifier PID, and end with the packet end mark EOP. For full-speed or low-speed devices, the data length of the synchronization field SYNC is usually 8 bits; for high-speed devices, the data length of the synchronization field SYNC is usually 32 bits.

[0070] The first reset counter and the first EOP counter use the system clock signal to count each bit of the positive signal DP and the negative signal DM respectively; when the count value of the first reset counter reaches the reset preset value, a reply signal is generated, and the first decoding state machine performs a state jump to enter the synchronization domain SYNC detection stage; when the count value of the first EOP counter reaches the EOP preset value, a packet end character EOP is sent, and the first decoding state machine performs a state jump to enter the data packet sending end state.

[0071] In the synchronization domain SYNC stage, the first high-level counter and the first low-level counter use the system clock signal to count the high-level bits and low-level bits of the single-ended signal RCV respectively, and obtain N high-level count values ​​and N low-level count values ​​(N is a positive integer). The counting results are averaged by the first decoding state machine to obtain the average bit width of the synchronization domain, and the average bit width of the synchronization domain is used as the standard value of the bit width of the sending signal, which is used to parse the packet identifier PID and data DATA after the synchronization domain to realize the sending of USB data packets.

[0072] In one embodiment of the present invention, the key timing of the data transmission unit is as follows: Figure 4 Therefore, the sending process of a data packet includes the bus reset phase, idle phase, SYNC phase, PID phase, DATD phase, CRC5 phase and EOP phase in sequence. The working process of each phase is as follows.

[0073] In the bus reset phase, the positive signal DP and the negative signal DM are both at low level, the first reset counter starts counting, and when the count value reaches the reset preset value, a reset signal is generated to start the first decoding state machine to perform state jump and enter the synchronization domain SYNC detection phase;

[0074] In the idle stage, the positive signal DP is at a high level, the negative signal DM is at a low level, all counters do not work, and the count value remains at 0.

[0075] In the SYNC stage, if Figure 4 As shown, the single-ended signal RCV first has a falling edge, and the first low-level counter starts counting until a rising edge appears. In the first low-level bit, the low-level count value is 5; after the first rising edge appears, the first high-level counter starts counting until a falling edge appears again. In the first high-level bit, the high-level count value is 5. Similarly, in the SYNC stage, the first high-level counter and the first low-level counter use the system clock signal to count the high-level bits and low-level bits of the single-ended signal RCV in turn, and the count values ​​obtained are arranged in the following order: low 5, high 5, low 5, high 5, low 5, high 5;

[0076] The counting result shows that each bit width of the synchronization domain SYNC is 5. After average calculation, the average bit width of the synchronization domain is 5. The technical solution of the present invention uses the average bit width 5 of the synchronization domain as the standard value of the bit width of the sending signal to parse the packet identifier PID and data DATA after the synchronization domain to realize the sending of USB data packets.

[0077] In the PID stage, the first high-level counter and the first low-level counter use the system clock signal to count the high-level bits and low-level bits of the single-ended signal RCV in turn, and the count values ​​obtained are arranged in the following order: low 20, high 10, low 5, high 10, low 5;

[0078] The counting result of the above PID stage can be parsed according to the standard value of the bit width of the transmitted signal of 5. After parsing the synchronization field SYNC and the packet identifier PID, each bit data is arranged as follows: 01010100 00110110

[0080] After conversion according to the encoding format of non-return-to-zero encoding, the NRZI encoding of the synchronization field SYNC and the packet identifier PID is finally obtained as follows:

[0081] Little endian: 00000001 11010010;

[0082] Big endian: 10000000 01001011;

[0083] After parsing the NRZI encoding according to the USB protocol, the hexadecimal data of SYNC+PID is 0x800x4b, indicating the data DATA1 packet.

[0084] In the DATD stage, the data to be sent in this embodiment is 0x40 0x04 0x00..., and its corresponding binary data is:

[0085] Big endian: 01000000 00000100 00000000;

[0086] Little endian: 00000010 00100000 00000000;

[0087] After conversion according to the encoding format of non-return-to-zero encoding, the final NRZI encoding is: 10101001 01101010101010101;

[0089] Finally, according to the standard value of the signal bit width of 5, the NRZI encoding in the DATD stage is used to send data. That is to say, in the NRZI encoding, a high level or low level of a bit width is sent using the duration of 5 system clock signals.

[0090] The data transmission process in the CRC5 stage and the EOP stage is similar to that in the above-mentioned DATD stage, so it will not be repeated here.

[0091] In one embodiment of the present invention, Figure 5As shown, the data receiving unit includes a second reset counter, a second EOP counter, a second high level counter, a second low level counter, a second decoding state machine and a second data receiving module, as well as a seventh register DP_R2, an eighth register DP_R3, a ninth register DM_R2, a tenth register DM_R3, an eleventh register RCV_R2 and a twelfth register RCV_R3, a third inverter IN3, a fourth inverter IN4, a third AND gate AND3 and a fourth AND gate AND4. Among them, the positive signal line DP of the internal differential signal bus is connected to the input end of the seventh register DP_R2, the output end of the seventh register DP_R2 is connected to the input end of the eighth register DP_R3, and the output end of the eighth register DP_R3 is respectively connected to the first input end of the third AND gate AND3 and the first input end of the fourth AND gate AND4 through the third inverter IN3; the negative signal line DM of the internal differential signal bus is connected to the input end of the ninth register DM_R2, the output end of the ninth register DM_R2 is connected to the input end of the tenth register DM_R3, and the output end of the tenth register DM_R3 is respectively connected to the second input end of the third AND gate AND3 and the second input end of the fourth AND gate AND4 through the fourth inverter IN4; the output end of the third AND gate AND3 is connected to the input end of the second reset counter, and the output end of the second reset counter is connected to the bus reset end of the second decoding state machine; the fourth AND gate A The output end of ND4 is connected to the input end of the second EOP counter, the output end of the second EOP counter is connected to the EOP identification end of the second decoding state machine, and at the same time, the control end of the second EOP counter is connected to the counting cycle configuration end of the second decoding state machine; the single-ended signal line RCV is connected to the input end of the eleventh register RCV_R2, the output end of the eleventh register RCV_R2 is connected to the input end of the twelfth register RCV_R3, the output end of the twelfth register RCV_R3 is respectively connected to the input ends of the second high level counter and the second low level counter, and the output ends of the second high level counter and the second low level counter are correspondingly connected to the first counting end and the second counting end of the second decoding state machine; the clock ends of the six registers are all connected to the system clock signal end; the enable end and the data end of the second decoding state machine are connected to the second data receiving module, and the output end of the second data receiving module is connected to the data signal receiving end.

[0092] The second decoding state machine is used to perform logical control on the working state of each functional module in the data receiving unit.

[0093] The second data receiving module is used to receive data, and uses the standard value of the Bit width of the received signal to parse and extract the received data.

[0094] The working principle of the data receiving unit in this embodiment is described in detail below.

[0095] The second reset counter and the second EOP counter use the system clock signal to count each bit of the positive signal DP and the negative signal DM respectively; when the count value of the second reset counter reaches the reset preset value, a reset signal is generated, and the second decoding state machine performs a state jump to enter the synchronization domain SYNC detection stage; when the count value of the second EOP counter reaches the EOP preset value, it is determined that the packet end character EOP is received, and the second decoding state machine performs a state jump to enter the data packet reception end state.

[0096] In the synchronization domain SYNC stage, the second high-level counter and the second low-level counter use the system clock signal to count the high-level bits and low-level bits of the single-ended signal RCV respectively. The counting results are averaged by the second decoding state machine to obtain the average bit width of the synchronization domain. The average bit width of the synchronization domain is used as the standard value of the bit width of the received signal, which is used to parse the packet identifier PID and data DATA after the synchronization domain to realize the reception of USB data packets.

[0097] In one embodiment of the present invention, the key timing of the data receiving unit is compared as follows: Figure 6 Therefore, the receiving process of a data packet includes the bus reset stage, idle stage, SYNC stage, PID stage, FRAME stage, CRC5 stage and EOP stage in sequence. The working process of each stage is as follows.

[0098] In the bus reset phase, the positive signal DP and the negative signal DM are both low level, the second reset counter starts counting, and when the count value reaches the reset preset value, a reset signal is generated to start the second decoding state machine to perform state jump and enter the synchronization domain SYNC detection phase.

[0099] In the idle stage, the positive signal DP is at a high level, the negative signal DM is at a low level, all counters do not work, and the count value remains at 0.

[0100] In the SYNC stage, if Figure 6 As shown, the single-ended signal RCV first has a falling edge, and the second low-level counter starts counting until a rising edge appears. In the first low-level bit, the low-level count value is 5; after the first rising edge appears, the second high-level counter starts counting until a falling edge appears again. In the first high-level bit, the high-level count value is 5. Similarly, in the SYNC stage, the second high-level counter and the second low-level counter use the system clock signal to count the high-level bits and low-level bits of the single-ended signal RCV in turn, and the count values ​​obtained are arranged in the following order: low 5, high 5, low 5, high 5, low 5, high 5;

[0101] The counting result shows that each bit width of the synchronization domain SYNC is 5. After average calculation, the average bit width of the synchronization domain is 5. The technical solution of the present invention uses the average bit width 5 of the synchronization domain as the standard value of the bit width of the received signal to parse the packet identifier PID and FRAME and other domain data after the synchronization domain to realize the reception of USB data packets.

[0102] In the PID stage, the second high-level counter and the second low-level counter use the system clock signal to count the high-level bits and low-level bits of the single-ended signal RCV in turn, and the count values ​​obtained are arranged in the following order: low 15, high 10, low 5, high 10, low 10;

[0103] Similarly, in the FRAME stage and the CRC5 stage, the counting results of the second high-level counter and the second low-level counter are arranged in the following order: high 5, low 15, high 10, low 20, high 15, low 5, high 5, low 5;

[0104] The counting results of the synchronization field SYNC, packet identifier PID, FRAME field and CRC5 field are analyzed according to the standard value of the received signal bit width of 5, and each bit data is arranged as follows: 01010100 01101100 10001100001 11010;

[0106] After conversion according to the encoding format of non-return-to-zero encoding, the NRZI encoding of the synchronization field SYNC, packet identifier PID, FRAME field and CRC5 field is finally obtained as follows:

[0107] Little endian: 00000001 10100101 00110101110 11000;

[0108] Big endian: 10000000 10100101 01110101100 00011;

[0109] After parsing the NRZI encoding according to the USB protocol, the hexadecimal data is as follows:

[0110] SYNC+PID+FRAME+CRC5

[0111] 0x80 0xa5 0x3ac 0x03

[0112] The analysis result shows that the received data is a synchronization frame, and the frame data is 0x3ac.

[0113] In the EOP stage, the positive signal DP and the negative signal DM are both low level, the second EOP counter starts counting, and the final counting result is 10. After parsing according to the standard value of the received signal Bit width of 5, it means that two bits of 0 are received. According to the USB protocol, the parsing result is a packet end mark EOP, indicating that a data packet has been received.

[0114] It can be seen from the detailed description of the above embodiments that in the process of data transmission and reception, the USB data transmission circuit provided by the embodiment of the present invention does not need to provide an accurate 48Mhz sampling clock for decoding on the USB host side and the USB device side, but directly uses the internal system clock of the chip to count the high and low levels of the synchronization domain SYNC in the data packet, and obtains the standard value of the Bit width of the transmission signal or the standard value of the Bit width of the reception signal after average calculation, and uses this standard value of the Bit width to parse the subsequent logical domain of the data packet to achieve normal transmission of USB data. In addition, the system clocks of the USB host side and the USB device side are not required to be the same, so when the device operates at different temperatures, the internal clock of the chip changes with the temperature, which will not affect the USB data transmission, thus greatly reducing the difficulty and cost of USB system design.

[0115] Based on the working principle of the above USB data transmission circuit, the embodiment of the present invention further provides a USB data transmission method, wherein the data transmission and data reception processes are respectively as follows: Figure 7 and Figure 8 The transmission method comprises the following steps:

[0116] S1: The USB data sending method includes the following sub-steps:

[0117] S11: The reset counter uses the system clock signal to count the positive signal DP and the negative signal DM of the differential signal when both are at low level, and generates a reset signal when the count value reaches a reset preset value.

[0118] S12: The decoding state machine enters the synchronization domain SYNC detection stage.

[0119] S13: In the synchronization domain SYNC stage, the high level counter and the low level counter use the system clock signal to count the high level bits and low level bits of the single-ended signal RCV respectively, and obtain N high level count values ​​and N low level count values; wherein N is a positive integer.

[0120] S14: averaging the N high-level count values ​​and the N low-level count values ​​of the synchronization field SYNC, and using the obtained average value as a standard value of the Bit width of the transmission signal.

[0121] S15: parse the subsequent logical domain of the USB data packet using the standard value of the bit width of the sending signal and then send the corresponding data.

[0122] S16: The EOP counter uses the system clock signal to count the positive signal DP and the negative signal DM of the differential signal, both of which are low level, and sends the packet end character EOP when the count value reaches the EOP preset value.

[0123] S17: Go to step S12, and execute steps S12-S16 in a loop to send the next data packet; or, end USB data sending.

[0124] S2: The USB data receiving method includes the following sub-steps:

[0125] S21: The reset counter uses the system clock signal to count the positive signal DP and the negative signal DM of the differential signal at the low level at the same time, and generates a reset signal when the count value reaches the reset preset value;

[0126] S22: The decoding state machine enters the phase of detecting the synchronization domain SYNC.

[0127] S23: In the synchronization domain SYNC stage, the high level counter and the low level counter respectively count the high level bits and low level bits of the single-ended signal RCV using the system clock signal to obtain N high level count values ​​and N low level count values.

[0128] S24: averaging the N high-level count values ​​and the N low-level count values ​​of the synchronization field SYNC, and using the obtained average value as a standard value of the Bit width of the received signal.

[0129] S25: Analyze the subsequent logic domain of the USB data packet using the standard value of the bit width of the received signal to obtain corresponding data.

[0130] S26: The EOP counter uses the system clock signal to count the positive signal DP and the negative signal DM of the differential signal, both of which are low level, and when the count value reaches the EOP preset value, it is determined that the packet end character EOP is received.

[0131] S27: Go to step S21, and loop through steps S21-S26 to receive the next data packet; or, end USB data reception.

[0132] In summary, compared with the prior art, in the USB data transmission circuit provided by the embodiment of the present invention, during the data transmission process, neither the USB host end nor the USB device end needs to provide an accurate 48Mhz sampling clock for decoding, but directly uses the internal system clock of the chip to count the high and low levels of the synchronization domain SYNC in the data packet, and obtains the standard value of the Bit width of the sending signal or the standard value of the Bit width of the receiving signal after average calculation, and uses the standard value of the Bit width to parse the subsequent logical domain of the data packet to achieve normal transmission of USB data. Therefore, the USB data transmission circuit provided by the embodiment of the present invention has the beneficial effects of low design difficulty, low circuit cost, etc.

[0133] It should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0134] The USB data transmission circuit and transmission method provided by the present invention are described in detail above. For those skilled in the art, any obvious changes made to the present invention without departing from the essence of the present invention will constitute an infringement of the patent right of the present invention and will bear corresponding legal responsibilities.

Claims

1. A USB data transmission circuit, comprising a physical layer interface unit, characterized in that It also includes a data sending unit and a data receiving unit; wherein, The external differential signal bus is connected to the physical layer interface unit, the physical layer interface unit is connected to the data sending unit and the data receiving unit respectively through the internal differential signal bus and the single-ended signal line, and the data sending unit is connected to the physical layer interface unit through two data lines; The data sending unit is used to send USB data. The data sending unit uses the system clock to count the synchronization domain of the data packet to obtain a standard value of the bit width of the sending signal, and parses the sending data according to the standard value of the bit width of the sending signal to complete the USB data sending; The data receiving unit is used to receive USB data. The data receiving unit counts the synchronization domain of the data packet using the system clock to obtain a standard value of the bit width of the received signal, and parses the received data according to the standard value of the bit width of the received signal to complete the USB data reception. The physical layer interface unit is used to implement the physical layer function of the USB protocol.

2. The USB data transmission circuit according to claim 1, characterized in that: The data sending unit includes a first reset counter, a first EOP counter, a first high level counter, a first low level counter, a first decoding state machine, a first data receiving module and a sending counting module, as well as a first register, a second register, a third register, a fourth register, a fifth register and a sixth register, a first inverter, a second inverter, a first AND gate and a second AND gate; wherein, The first decoding state machine is used to logically control the working state of each functional module in the data sending unit; The first data receiving module is used to receive USB control data, and uses the standard value of the bit width of the sending signal to extract the received data; The sending counting module is used for sending data, and uses the standard value of the sending signal bit width to parse and transmit the sending data.

3. The USB data transmission circuit as claimed in claim 2, characterized in that In the data sending unit, The positive signal line of the internal differential signal bus is connected to the input end of the first register, the output end of the first register is connected to the input end of the second register, and the output end of the second register is connected to the first input end of the first AND gate and the first input end of the second AND gate respectively through the first inverter; The negative signal line of the internal differential signal bus is connected to the input end of the third register, the output end of the third register is connected to the input end of the fourth register, and the output end of the fourth register is connected to the second input end of the first AND gate and the second input end of the second AND gate respectively through the second inverter; The output end of the first AND gate is connected to the input end of the first reset counter, and the output end of the first reset counter is connected to the bus reset end of the first decoding state machine; The output end of the second AND gate is connected to the input end of the first EOP counter, the output end of the first EOP counter is connected to the EOP identification end of the first decoding state machine, and the control end of the first EOP counter is connected to the counting cycle configuration end of the first decoding state machine; The clock ends of the first register, the second register, the third register and the fourth register are all connected to the system clock signal end.

4. The USB data transmission circuit as claimed in claim 2, characterized in that In the data sending unit, The single-ended signal line is connected to the input end of the fifth register, the output end of the fifth register is connected to the input end of the sixth register, the output end of the sixth register is connected to the input ends of the first high level counter and the first low level counter respectively, and the output ends of the first high level counter and the first low level counter are connected to the first counting end and the second counting end of the first decoding state machine respectively; The clock terminals of the fifth register and the sixth register are both connected to the system clock signal terminal.

5. The USB data transmission circuit as claimed in claim 2, characterized in that: During the bus reset phase of sending data packets, both the positive signal and the negative signal are at low level, the first reset counter starts counting, and when the count value reaches the reset preset value, a reset signal is generated to start the first decoding state machine to perform a state jump and enter the synchronization domain detection phase.

6. The USB data transmission circuit as claimed in claim 2, characterized in that: In the synchronization domain stage of sending a data packet, the first high-level counter and the first low-level counter respectively count the high-level bits and low-level bits of the single-ended signal to obtain N high-level count values ​​and N low-level count values, and the first decoding state machine averages the counting results to obtain a standard value of the bit width of the transmitted signal; wherein N is a positive integer.

7. The USB data transmission circuit according to claim 2, characterized in that: In the EOP phase of sending a data packet, the first EOP counter starts counting, and when the count value reaches the EOP preset value, a packet end character EOP is sent, and the first decoding state machine performs a state jump to enter the data packet sending end state.

8. The USB data transmission circuit according to claim 1, characterized in that: The data receiving unit includes a second reset counter, a second EOP counter, a second high level counter, a second low level counter, a second decoding state machine, a second data receiving module, and a seventh register, an eighth register, a ninth register, a tenth register, an eleventh register, a twelfth register, a third inverter, a fourth inverter, a third AND gate, and a fourth AND gate; wherein, The second decoding state machine is used to logically control the working state of each functional module in the data receiving unit; The second data receiving module is used to receive data, and uses the standard value of the bit width of the received signal to parse and extract the received data; The clock ends of the seventh register, the eighth register, the ninth register, the tenth register, the eleventh register and the twelfth register are all connected to the system clock signal end.

9. The USB data transmission circuit according to claim 8, characterized in that: In the synchronization domain stage of receiving the data packet, the second high-level counter and the second low-level counter respectively count the high-level bits and low-level bits of the single-ended signal to obtain N high-level count values ​​and N low-level count values, and the second decoding state machine averages the counting results to obtain a standard value of the bit width of the received signal; wherein N is a positive integer.

10. A transmission method for USB data transmission, implemented based on any one of claims 1 to 9, characterized in that The steps include: (11) The reset counter uses the system clock signal to count the positive and negative signals of the differential signal at the same time when they are at a low level, and generates a reset signal when the count value reaches a reset preset value; (12) The decoding state machine enters the synchronization domain detection stage; (13) In the synchronization domain stage, the high level counter and the low level counter respectively count the high level bits and the low level bits of the single-ended signal using the system clock signal to obtain N high level count values ​​and N low level count values; wherein N is a positive integer; (14) averaging the N high-level count values ​​and the N low-level count values, and using the obtained average value as a standard value of the bit width of the transmitted signal; (15) parsing the subsequent logical domain of the USB data packet using the standard value of the bit width of the transmission signal and then sending the corresponding data; (16) The EOP counter uses the system clock signal to count the positive and negative signals of the differential signal at low levels, and sends an end-of-packet symbol EOP when the count value reaches an EOP preset value; (17) Go to step (12) and loop through steps (12) to (16) to send the next data packet; or, end USB data transmission.

11. A transmission method for USB data reception, implemented based on the USB data transmission circuit according to any one of claims 1 to 9, characterized in that The steps include: (21) The reset counter uses the system clock signal to count the positive and negative signals of the differential signal at the same time when they are at a low level, and generates a reset signal when the count value reaches a reset preset value; (22) The decoding state machine enters the synchronization domain detection stage; (23) In the synchronization domain stage, the high level counter and the low level counter respectively count the high level bits and the low level bits of the single-ended signal using the system clock signal to obtain N high level count values ​​and N low level count values, where N is a positive integer; (24) averaging the N high-level count values ​​and the N low-level count values, and using the obtained average value as a standard value of the received signal bit width; (25) parsing the subsequent logical domain of the USB data packet using the standard value of the bit width of the received signal to obtain corresponding data; (26) The EOP counter uses the system clock signal to count the positive and negative signals of the differential signal, both of which are low level, and when the count value reaches the EOP preset value, it is determined that the packet end character EOP is received; (27) Go to step (21) and loop through steps (21) to (26) to receive the next data packet; or, end USB data reception.

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