Parallel timing synchronization method for satellite-ground high-speed data transmission

Abstract

The invention discloses a parallel timing synchronization method for satellite-ground high-speed data transmission, and belongs to the technical field of satellite communication. The method comprises the following six processing steps: interpolation, interpolation point marking, data rearrangement, clock error extraction, loop filtering, numerical control oscillation and the like. The method is suitable for satellite-ground high-speed data transmission, has the capability of realizing timing synchronization under the condition that the symbol rate is far higher than the working frequency of a chip, and is low in resource overhead, low in implementation difficulty of whole-process processing, high in flexibility, high in processing speed and efficiency and small in residual error after compensation.

Description

Technical Field

[0001] The invention relates to a parallel timing synchronization method for satellite-to-ground high-speed data transmission, belonging to the technical field of satellite communications. Background Art

[0002] In satellite communication systems, the receiver needs to perform periodic sampling and judgment according to the symbol rate in order to recover data from the received signal. Since the local oscillators of the receiver and transmitter are independent of each other, there must be a deviation between the clocks generated by the two. The receiver needs to compensate for this deviation through timing synchronization to ensure the best sampling of the demodulated output signal.

[0003] With the rapid development of aerospace technology, the data rate generated by the payload is getting higher and higher, and the bandwidth and capacity of the satellite-to-ground link transmission channel are also getting larger and larger. In order to meet the transmission needs of massive data, the receiver must achieve parallel timing synchronization under the condition that the symbol rate is much higher than the chip operating frequency.

[0004] When the existing timing synchronization method is implemented in full digital parallel, a data reordering module is usually added to the input end to adjust the relative order of the sampled data by controlling the read cache. This process requires each channel to have a set of cache space, resulting in large resource overhead and increasing the difficulty of the internal control process of timing synchronization. Summary of the invention

[0005] The purpose of the present invention is to provide a parallel timing synchronization method for satellite-to-ground high-speed data transmission. The method is suitable for satellite-to-ground high-speed data transmission, has the ability to achieve timing synchronization under the condition that the symbol rate is much higher than the chip operating frequency, has low resource overhead, low difficulty in implementing the full-process processing, high flexibility, high processing speed and efficiency, small residual after compensation, and supports self-synchronization.

[0006] The technical solution adopted by the present invention is:

[0007] A parallel timing synchronization method for satellite-to-ground high-speed data transmission comprises the following steps:

[0008] (1) Interpolation: Input a signal including 2 × L components, obtain interpolation coefficients according to the fractional interval of the current iteration, combine the input signal with the last 4 components of the interpolation signal of the previous iteration to obtain a temporary signal, and interpolate the temporary signal in groups according to the interpolation coefficients to obtain the interpolation signal of the current iteration;

[0009] (2) Interpolation signal marker: The interpolation signal marker sequence of the current iteration is obtained according to the offset of the current iteration and the interpolation signal marker sequence obtained in the previous iteration;

[0010] (3) Data rearrangement: The interpolation signal components corresponding to the components of the interpolation signal flag sequence obtained in the current iteration whose value is 1 are placed into a first-in-first-out storage buffer queue; when the number of signals in the first-in-first-out storage buffer queue is greater than or equal to the parallel output symbol number L0, the first L0 data in the first-in-first-out storage buffer queue are taken out as the output signal; otherwise, no operation is performed;

[0011] (4) Clock error extraction: According to the interpolation signal marker sequence of the current iteration, the three adjacent components of the interpolation signal are grouped into one group, each group includes two peak points and one non-peak point, and the final L-2 sets of peak points and non-peak points are taken; the Gardner timing error detection formula is used to extract L-2 clock errors from the set, and the average value of the extracted L-2 clock errors is calculated as the error mean value of the current iteration;

[0012] (5) Loop filtering: Based on the error mean value obtained in the current iteration, the error mean value obtained in the previous iteration, the control word obtained in the previous iteration, and the filter coefficient, a second-order active proportional integral filter is used to filter the output control word;

[0013] (6) Numerical control oscillation: Based on the control word and the oscillator register value obtained in the previous iteration, the fractional interval and offset of the next iteration are obtained as the fractional interval and offset of the current iteration, and the process returns to step (1).

[0014] Furthermore, the specific process of step (1) is as follows:

[0015] (101) converting the fractional interval of the current iteration into a cubic or piecewise parabola-based Lagrangian coefficient, i.e., an interpolation coefficient, according to the interpolation selection;

[0016] (102) The last 4 components of the interpolation signal obtained in the previous iteration and the input signal of 2×L components are combined to form a temporary signal with 2×L+4 components;

[0017] (103) Every 4 adjacent components of the temporary signal are grouped into a group, for a total of 2×L+1 groups. Each group is interpolated once using the same interpolation coefficient to obtain an interpolated signal with 2×L+1 components.

[0018] Furthermore, the specific process of step (2) is as follows:

[0019] When the offset is 1, if the last component of the interpolation signal marker sequence obtained in the previous iteration is 0, then the first five components from the left of the interpolation signal marker sequence of the current iteration are 00101, and the following 2L-4 components are L-2 01 sequences; otherwise, the first five components from the left of the interpolation signal marker sequence of the current iteration are 00010, and the following 2L-4 components are L-2 10 sequences;

[0020] When the offset is -1, if the last component of the interpolation signal marker sequence obtained in the previous iteration is 0, then the first five components from the left of the interpolation signal marker sequence of the current iteration are 10101, and the following 2L-4 components are L-2 01 sequences; otherwise, the first five components from the left of the interpolation signal marker sequence of the current iteration are 01010, and the following 2L-4 components are L-2 10 sequences;

[0021] When the offset is 0, if the last component of the interpolation signal marker sequence obtained in the previous iteration is 0, then the first five components from the left of the interpolation signal marker sequence of the current iteration are 01010, and the following 2L-4 components are L-2 10 sequences; otherwise, the first five components from the left of the interpolation signal marker sequence of the current iteration are 00101, and the following 2L-4 components are L-2 01 sequences.

[0022] Furthermore, the specific process of step (6) is as follows:

[0023] (601) Calculate the difference between the oscillator register value obtained in the previous iteration and twice the control word;

[0024] (602) If the difference is greater than -1, the oscillator register value of the current iteration is set equal to the oscillator register value obtained in the previous iteration minus 3 times the control word plus 2, and the offset is set to 1; if the difference is less than -2, the oscillator register value of the current iteration is set equal to the oscillator register value obtained in the previous iteration minus 2 times the control word plus 3, and the offset is set to -1; if the difference is greater than -1, the oscillator register value of the current iteration is set equal to the oscillator register value obtained in the previous iteration minus 2 times the control word plus 2, and the offset is set to 0;

[0025] (603) Let the fractional interval be equal to the oscillator register value obtained in the current iteration, and use the obtained fractional interval and offset as the fractional interval and offset of the current iteration, and return to step (1).

[0026] Compared with the prior art, the present invention has the following advantages:

[0027] 1) The present invention supports full digital parallel implementation and places data rearrangement processing at the output end, which can reduce resource overhead while lowering the difficulty of the internal control process and is easy to implement.

[0028] 2) The present invention adopts 2 times oversampling, and the baseband signal satisfies the Nyquist sampling theorem, which reduces the requirements of the sampling rate index of the analog-to-digital conversion device under the high symbol rate condition.

[0029] 3) The present invention supports external signal control to select interpolation coefficients, and supports outputting data according to a set number of parallel symbols without increasing resource overhead, and has high flexibility.

[0030] 4) When the loop filter coefficient of the present invention takes a specific value, the multiplication operation can be replaced by a shift operation, thereby improving the processing speed and efficiency.

[0031] 5) The present invention reduces the residual after clock error compensation by correcting the branch judgment condition of the numerically controlled oscillation.

[0032] 6) The present invention does not require training data and supports self-synchronization. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is a flow chart of the method involved in the embodiment of the present invention.

[0034] Figure 2 4 are possible state diagrams of the interpolation signal marker sequence according to an embodiment of the present invention.

[0035] Figure 3 It is a state transition diagram of an interpolation signal marker sequence according to an embodiment of the present invention. DETAILED DESCRIPTION

[0036] The present invention is further described in detail below.

[0037] A parallel timing synchronization method for satellite-to-ground high-speed data transmission comprises the following steps:

[0038] (1) Interpolation

[0039] Let k be the number of iterations, k ≥ 1. L is the number of parallel input symbols, L ≥ 2, and it is recommended to take a positive integer power of 2, but it is not mandatory. N is the oversampling multiple per symbol, N = 2. The input signal X(k) = {x N×L-1 (k),…,x0(k)}. Interpolation signal Y(k)={y N×L (k),…,y0(k)}, especially Y(0)={0,…,0}. Each component of the input signal X(k) and the interpolation signal Y(k) is a complex number, and the subscript high digit comes first and the low digit comes last. s is the interpolation selection, s∈{0,1}. μ(k) is the fractional interval, indicating the fractional part of the clock deviation, μ(k)∈[0,1), especially μ(1)=0. {C -2 (k),C -1 (k), C0(k), C1(k)} are interpolation coefficients.

[0040] The input of this step includes the input signal X(k) of the current iteration, the last four components {y3(k-1),…,y0(k-1)} of the interpolation signal Y(k-1) obtained in the previous iteration, the interpolation selection s and the fractional interval μ(k), and the output includes the interpolation signal Y(k).

[0041] The input signal X(k) and the last four interpolation signals {y3(k-1),…,y0(k-1)} obtained in the previous iteration are combined into a temporary signal T(k)={t N×L+3 (k),…,t0(k)}, that is

[0042]

[0043] In particular, if k = 1, that is, the first iteration, the temporary signal T(1) is {0,0,0,0,x N×L-1 (1),…,x0(1)}.

[0044] Each component of the interpolation signal Y(k) is obtained by interpolating every 4 adjacent components of the temporary signal T(k), that is,

[0045] y i (k) = C1(k) × t i+3 (k)+C0(k)×t i+2 (k)+C -1 (k)×t i+1 (k)+C -2 (k)×t i (k)

[0046] A total of N×L+1 interpolation operations are performed in each iteration.

[0047] Interpolation coefficient {C -2 (k),C -1 (k), C0(k), C1(k)} is determined by the interpolation selection s and the fractional interval μ(k). The interpolation selection s is used to select the interpolation coefficients. When s = 1, the interpolation uses the Lagrange coefficients based on cubic interpolation.

[0048]

[0049] When s = 0, the interpolation uses the Lagrange coefficients based on piecewise parabolic interpolation.

[0050]

[0051] In order to simplify the operation and save resources, the N×L+1 interpolation operation performed in each iteration adopts an equal fractional interval μ(k).

[0052] In the specific implementation, the parallel number of input symbols L=16, and the interpolation selection s=1. The input signal of the current iteration has 32 components, and each component corresponds to a sampling point. The last 4 components of the interpolation signal obtained in the previous iteration and the 32 components of the input signal form a temporary signal with 36 components. The fractional interval of the current iteration is converted into the Lagrange coefficient suitable for cubic interpolation, that is, the interpolation coefficient according to the formula. Every 4 adjacent components of the temporary signal are divided into a group, for a total of 33 groups, and each group is interpolated once, for a total of 33 interpolations, to obtain an interpolation signal with 33 components. The same Lagrange coefficient is used for all 33 interpolations.

[0053] (2) Interpolation signal marker

[0054] Let m(k) be the offset, which represents the integer part of the clock deviation, m(k)∈{-1,0,1}, especially m(1)=0. F(k)={f N×L (k),…,f0(k)} is the interpolation signal label sequence, and each component f i (k)∈{0,1},f i (k) = 1 means y i (k) is the peak point, and f i (k) = 0 means y i (k) is a non-peak point. The interpolation signal marker sequence F(k) has four possible states, see Figure 2 , there is a non-peak point between every two adjacent peak points. In particular, F(0) = F2. Other symbols are consistent with the above.

[0055] The input of this step includes the offset m(k) and the last component f0(k-1) of the interpolation signal label sequence F(k-1) obtained in the previous iteration, and the output includes the interpolation signal label sequence F(k).

[0056] When the offset m(k)=1, if f0(k-1)=0, then F(k)=F3; if f0(k-1)=1, then F(k)=F4.

[0057] When the offset m(k)=-1, if f0(k-1)=0, then F(k)=F1; if f0(k-1)=1, then F(k)=F2.

[0058] When the offset m(k)=0, if f0(k-1)=0, then F(k)=F2; if f0(k-1)=1, then F(k)=F3.

[0059] Figure 3 The state transition diagram of the interpolation signal tag sequence F(k) is given. Figure 2 and Figure 3It can be seen that the interpolation signal Y(k) may contain three cases, namely, L-1, L, and L+1 peak points. When the offset m(k)=0, the interpolation signal Y(k) must contain L peak points, and the other two cases will only occur when m(k)≠0.

[0060] In specific implementation, the interpolation signal of the next iteration may contain 15, 16 or 17 peak points, and there is an intermediate point between every two adjacent peak points. The number of peak points is based on the offset and the interpolation signal marker sequence obtained in the previous iteration, according to Figure 3 The state transition diagram shown is used to determine. When the offset is 1, if the interpolation signal tag sequence obtained in the previous iteration is F2 or F4, the interpolation signal tag sequence becomes F3, otherwise it is F4. When the offset is -1, if the interpolation signal tag sequence obtained in the previous iteration is F2 or F4, the interpolation signal tag sequence becomes F1, otherwise it is F2. When the offset is 0, if the interpolation signal tag sequence obtained in the previous iteration is F2 or F4, the interpolation signal tag sequence becomes F2, otherwise it is F3.

[0061] (3) Data Rearrangement

[0062] Let L0 be the number of parallel output symbols, L0 ≥ L. Output signal Z(k) = {z L0-1 (k),…,z0(k)}, each component is a complex number, and the high-order subscript comes first and the low-order subscript comes last. Other symbols are the same as above.

[0063] The input of this step includes the parallel output symbol number L0, the interpolation signal Y(k) and the interpolation signal label sequence F(k), and the output includes the output signal Z(k).

[0064] Traverse each component y of the interpolation signal Y(k) from high to low i (k). If the corresponding component f of the interpolation signal marker sequence F(k) i (k)=1, then y i (k) Put it into the first-in-first-out storage buffer queue; otherwise, do not put it into the first-in-first-out storage buffer queue.

[0065] When the number of signals in the FIFO storage buffer queue is greater than or equal to the parallel output symbol number L0, the first L0 data in the FIFO storage buffer queue are assigned to the output signal Z(k)={z L0-1 (k),…,z0(k)}.

[0066] In the specific implementation, the parallel number of output symbols L0=16. The interpolation signal tag sequence corresponds to the components of the interpolation signal one by one. The interpolation signal components corresponding to the components of the interpolation signal tag sequence obtained in the current iteration with a value of 1 are placed into the first-in-first-out storage buffer queue. When the number of signals in the first-in-first-out storage buffer queue is greater than or equal to 16, the first 16 data in the first-in-first-out storage buffer queue are taken out as the output signal; otherwise, no operation is performed.

[0067] (4) Clock error extraction

[0068] Let E(k) = {e L-2 (k),…,e0(k)} is the extracted clock error sequence. is the mean error, especially Re represents the real part of a complex number, and Im represents the imaginary part of a complex number. Other symbols are the same as above.

[0069] The input of this step includes the interpolation signal Y(k) and the interpolation signal label sequence F(k), and the output includes the error mean

[0070] Considering that the number of peak points contained in the interpolation signal Y(k) is not constant, the design is based on the minimum peak point situation. Each iteration can ensure that at least L-1 clock errors are extracted. Therefore, the clock error sequence E(k) has only L-1 components. Each component is calculated by the two adjacent peak points and the non-peak point in the middle of the interpolation signal Y(k) according to the Gardner timing error detection formula.

[0071]

[0072] Mean Error is the average value of the clock error sequence E(k). In order to simplify the calculation, the denominator can be replaced by a positive integer power of 2 close to L-1 when calculating the average value. In this way, shifting can be used instead of division.

[0073] In the specific implementation, the clock error extraction adopts the Gardner timing error detection formula, which requires the calculation of the three adjacent components of the interpolated signal, including two peak points and one non-peak point. Since the interpolated signal has at least 15 peak points, at least 14 clock errors can be obtained. The output error mean is the sum of these 14 clock errors divided by 16. 16 is a positive integer power of 2, and the shift operation can be used instead of the division operation.

[0074] (5) Loop Filter

[0075] Assume w(k) is the control word, especially w(0) = 1. K1 and K2 are filter coefficients. Other symbols are consistent with the above.

[0076] The input of this step includes the error mean obtained in the current iteration The mean error obtained in the previous iteration The control word w(k-1), filter coefficients K1 and K2 obtained in the previous iteration, and the output includes the control word w(k).

[0077] The loop filter uses a second-order active proportional integral filter. The time domain recursive equation of the entire loop filter is:

[0078]

[0079] In order to simplify the calculation, it is recommended that the filter coefficients K1 and K2 be taken as negative integer powers of 2, so that the multiplication operation can be replaced by the shift operation. In the specific implementation, the filter coefficient K1 = 2 -6 and K2=2 -16 .

[0080] (6) CNC oscillation

[0081] Let η(k) be the oscillator register value, specifically η(1) = 1 / N. Other symbols are the same as above.

[0082] The input of this step includes the control word w(k) and the oscillator register value η(k) obtained in the previous iteration, and the output includes the fractional interval μ(k+1) and the offset m(k+1).

[0083] If η(k)-2×w(k)>-1, then the oscillator register value η(k+1)=η(k)-3×w(k)+2 and the offset m(k+1)=1; if η(k)-2×w(k)<-2, then the oscillator register value η(k+1)=η(k)-2×w(k)+3 and the offset m(k+1)=-1; otherwise, the oscillator register value η(k+1)=η(k)-2×w(k)+2 and the offset m(k+1)=0. The branch judgment condition here is different from the conventional serial timing synchronization numerical control oscillation branch judgment condition, which uses the value of η(k)-w(k) for judgment, and the thresholds are 1 and 0.

[0084] The fractional interval μ(k+1)=η(k+1).

[0085] In the specific implementation, according to the control word and the oscillator register value obtained in the previous iteration, the fractional interval and offset of the next iteration are updated according to the branch judgment condition of the corrected numerical control oscillation. Calculate the difference between the oscillator register value obtained in the previous iteration and the 2 times control word. If the difference is greater than -1, the oscillator register value of the current iteration is equal to the oscillator register value obtained in the previous iteration minus 3 times the control word plus 2, and the offset is 1; if the difference is less than -2, the oscillator register value of the current iteration is equal to the oscillator register value obtained in the previous iteration minus 2 times the control word plus 3, and the offset is -1; if the difference is greater than -1, the oscillator register value of the current iteration is equal to the oscillator register value obtained in the previous iteration minus 2 times the control word plus 2, and the offset is 0. Let the fractional interval be equal to the oscillator register value obtained in the current iteration. Use the obtained fractional interval and offset as the fractional interval and offset of the current iteration, and return to step (1).

[0086] In summary, the present invention can complete parallel timing synchronization; the whole process processing is easy to implement; the baseband sampling rate is as low as 2 times the symbol rate; it has high flexibility; the processing speed and efficiency are high; the residual error after compensation is small; and it supports self-synchronization.

Claims

1. A parallel timing synchronization method for satellite-to-ground high-speed data transmission, characterized in that: The following steps are involved: (1) Interpolation: Input a signal including 2 × L components, obtain interpolation coefficients according to the fractional interval of the current iteration, combine the input signal with the last 4 components of the interpolation signal of the previous iteration to obtain a temporary signal, and interpolate the temporary signal in groups according to the interpolation coefficients to obtain the interpolation signal of the current iteration; (2) Interpolation signal marker: The interpolation signal marker sequence of the current iteration is obtained according to the offset of the current iteration and the interpolation signal marker sequence obtained in the previous iteration; (3) Data rearrangement: the interpolation signal components corresponding to the components of the interpolation signal flag sequence obtained in the current iteration whose value is 1 are placed into a first-in-first-out storage buffer queue; When the number of signals in the first-in-first-out storage buffer queue is greater than or equal to the parallel number of output symbols L0, the first L0 data in the first-in-first-out storage buffer queue are taken out as output signals; Otherwise, no operation is performed; (4) Clock error extraction: According to the interpolation signal marker sequence of the current iteration, the three adjacent components of the interpolation signal are grouped into one group, each group includes two peak points and one non-peak point, and the final L-2 sets of peak points and non-peak points are taken; the Gardner timing error detection formula is used to extract L-2 clock errors from the set, and the average value of the extracted L-2 clock errors is calculated as the error mean value of the current iteration; (5) Loop filtering: Based on the error mean value obtained in the current iteration, the error mean value obtained in the previous iteration, the control word obtained in the previous iteration, and the filter coefficient, a second-order active proportional integral filter is used to filter the output control word; (6) Numerical control oscillation: Based on the control word and the oscillator register value obtained in the previous iteration, the fractional interval and offset of the next iteration are obtained as the fractional interval and offset of the current iteration, and the process returns to step (1).

2. A parallel timing synchronization method for satellite-to-ground high-speed data transmission according to claim 1, characterized in that: The specific process of step (1) is as follows: (101) converting the fractional interval of the current iteration into a cubic or piecewise parabola-based Lagrangian coefficient, i.e., an interpolation coefficient, according to the interpolation selection; (102) The last 4 components of the interpolation signal obtained in the previous iteration and the input signal of 2×L components are combined to form a temporary signal with 2×L+4 components; (103) Every 4 adjacent components of the temporary signal are grouped into a group, for a total of 2×L+1 groups. Each group is interpolated once using the same interpolation coefficient to obtain an interpolated signal with 2×L+1 components.

3. The parallel timing synchronization method for satellite-to-ground high-speed data transmission according to claim 1, characterized in that: The specific process of step (2) is as follows: When the offset is 1, if the last component of the interpolation signal marker sequence obtained in the previous iteration is 0, then the first five components from the left of the interpolation signal marker sequence of the current iteration are 00101, and the following 2L-4 components are L-2 01 sequences; otherwise, the first five components from the left of the interpolation signal marker sequence of the current iteration are 00010, and the following 2L-4 components are L-2 10 sequences; When the offset is -1, if the last component of the interpolation signal marker sequence obtained in the previous iteration is 0, then the first five components from the left of the interpolation signal marker sequence of the current iteration are 10101, and the following 2L-4 components are L-2 01 sequences; otherwise, the first five components from the left of the interpolation signal marker sequence of the current iteration are 01010, and the following 2L-4 components are L-2 10 sequences; When the offset is 0, if the last component of the interpolation signal marker sequence obtained in the previous iteration is 0, then the first five components from the left of the interpolation signal marker sequence of the current iteration are 01010, and the following 2L-4 components are L-2 10 sequences; otherwise, the first five components from the left of the interpolation signal marker sequence of the current iteration are 00101, and the following 2L-4 components are L-2 01 sequences.

4. The parallel timing synchronization method for satellite-to-ground high-speed data transmission according to claim 1, characterized in that: The specific process of step (6) is as follows: (601) Calculate the difference between the oscillator register value obtained in the previous iteration and twice the control word; (602) If the difference is greater than -1, the oscillator register value of the current iteration is set equal to the oscillator register value obtained in the previous iteration minus 3 times the control word plus 2, and the offset is set to 1; If the difference is less than -2, the oscillator register value of the current iteration is set equal to the oscillator register value obtained in the previous iteration minus 2 times the control word plus 3, and the offset is set to -1; If the difference is greater than -1, the oscillator register value of the current iteration is set equal to the oscillator register value obtained in the previous iteration minus 2 times the control word plus 2, and the offset is set to 0; (603) Let the fractional interval be equal to the oscillator register value obtained in the current iteration, and use the obtained fractional interval and offset as the fractional interval and offset of the current iteration, and return to step (1).

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