High-precision circuit board and preparation method thereof

Abstract

The invention discloses a high-precision circuit board and a preparation method thereof. The preparation method comprises the following steps: acquiring a preset circuit diagram; setting a plurality of conductive layer groups according to a preset circuit diagram; wherein the conductive layers which need to form the same blind hole or buried hole form a conductive layer group, and the adjacent conductive layers which do not need to form the blind hole or buried hole form a conductive layer group; each conductive layer group comprises a core plate; placing the conductive layers in a stacked manner, placing bonding layers between the core plates in the same group or between the core plates and the conductive layers, and placing auxiliary layers between different conductive layer groups; laminating the conductive layer, the bonding layer and the auxiliary layer which are stacked, and stripping the auxiliary layer after lamination so as to enable the conductive layer group to form a sub-board; drilling a hole in a preset position of the daughter board to form a through hole; the daughter boards are placed in a stacked mode, and bonding layers are placed between the adjacent daughter boards; and laminating the sub-board and the bonding layer which are stacked. By adopting the technical scheme, the problems of alignment and warping caused by an asymmetric structure due to respective pressing of the sub-boards can be solved.

Description

Technical Field

[0001] The present invention relates to the technical field of printed circuit boards, and in particular to a high-precision circuit board and a preparation method thereof. Background Art

[0002] The ladder gold finger product has a wide range of applications. It can be used not only in conventional memory storage fields, but also in the current trend of AI server accelerator card products. It is a very important product in the current mainstream market. The top three server group companies in the world are all focusing on the development of such products in order to quickly occupy the AI ​​server accelerator card market.

[0003] The mainstream structure of the stepped gold finger printed circuit board used in AI server accelerator card products is 18 layers, consisting of 8 core boards + 2 layers of copper foil. Since the product design requires buried holes or blind holes, the conventional practice is to press together multiple sub-boards separately, then form through holes on the sub-boards, and then press together multiple sub-boards to form the final required 18 layers of conductive layers, and make the through holes of the sub-boards form buried holes or blind holes. There must be an asymmetric structure of the copper foil and the core board during the pressing process of the sub-board. Due to the asymmetry of the core board and the copper foil, the sub-board is heated and shrunk inconsistently in the press, which will inevitably cause serious misalignment and warping problems, resulting in the inability to meet the high alignment requirements, thereby limiting the development and growth of AI server accelerator card products. Summary of the invention

[0004] The present invention provides a high-precision circuit board and a preparation method thereof, so as to solve the technical problems of alignment and warping caused by asymmetric structures caused by pressing sub-boards separately.

[0005] According to one aspect of the present invention, there is provided a method for preparing a high-precision circuit board, the high-precision circuit board comprising at least one blind hole or buried hole;

[0006] The preparation method comprises:

[0007] Obtaining a preset circuit diagram of the high-precision circuit board;

[0008] According to the preset circuit diagram, a plurality of conductive layer groups are provided; wherein, the conductive layers adjacent to each other and the same blind hole or buried hole need to be formed constitute one conductive layer group, and the conductive layers adjacent to each other and the blind hole or buried hole do not need to be formed constitute one conductive layer group; each conductive layer group comprises a core board provided with two conductive layers;

[0009] The conductive layers are stacked, and a bonding layer is placed between the core plates of the same group or between the core plate and the conductive layer, and an auxiliary layer is placed between different and adjacent conductive layer groups;

[0010] Laminating the stacked conductive layer, the adhesive layer and the auxiliary layer, and peeling off the auxiliary layer after laminating, so that the conductive layer group forms a sub-board;

[0011] Drilling a hole at a preset position of at least one of the sub-boards to form a through hole;

[0012] stacking the sub-boards and placing the bonding layer between different and adjacent sub-boards;

[0013] The sub-board and the bonding layer are laminated and stacked, so that the through hole forms the blind hole or the buried hole.

[0014] Optionally, at least part of the conductive layer group includes a single conductive layer.

[0015] Optionally, the uppermost and lowermost conductive layer groups include an odd number of conductive layers;

[0016] According to the preset circuit diagram, a plurality of conductive layer groups are arranged, including:

[0017] According to the preset circuit diagram, a plurality of conductive layer groups are divided; wherein, the side close to the adjacent conductive layer group in the topmost and bottommost conductive layer groups is the single conductive layer, and / or, the side away from the adjacent conductive layer group in the topmost and bottommost conductive layer groups is the core board.

[0018] Optionally, the uppermost and lowermost conductive layer groups include an odd number of conductive layers;

[0019] According to the preset circuit diagram, a plurality of conductive layer groups are arranged, including:

[0020] According to the preset circuit diagram, a plurality of conductive layer groups are divided; wherein the side away from the adjacent conductive layer group in the topmost and bottommost conductive layer groups is the single conductive layer, and / or the side close to the adjacent conductive layer group in the topmost and bottommost conductive layer groups is the core board.

[0021] Optionally, the auxiliary layer includes the single conductive layer;

[0022] The uppermost and / or lowermost conductive layer group includes an odd number of conductive layers;

[0023] According to the preset circuit diagram, a plurality of conductive layer groups are arranged, including:

[0024] According to the preset circuit diagram, a plurality of conductive layer groups are divided; wherein one of the uppermost layer in the uppermost conductive layer group and the lowermost layer in the lowermost conductive layer group is the single conductive layer, and the other is the core board;

[0025] The conductive layers are stacked, a bonding layer is placed between the core plates in the same group or between the core plates and the conductive layers, and an auxiliary layer is placed between different and adjacent conductive layer groups, comprising:

[0026] The conductive layers are stacked, and a bonding layer is placed between the core plates in the same group or between the core plates and the conductive layers. The auxiliary layer is placed between different and adjacent conductive layer groups. The auxiliary layer is also placed above the top conductive layer group or below the bottom conductive layer group, so that the upper and lower edge conductive layers in all the conductive layers are single-layer conductive layers.

[0027] Optionally, the conductive layer includes a copper layer; and the auxiliary layer includes at least one layer of copper foil.

[0028] Optionally, the auxiliary layer includes two layers of copper foil;

[0029] Placing an auxiliary layer between different and adjacent conductive layer groups, comprising:

[0030] Two copper layers are placed between different and adjacent conductive layer groups, the shiny surface of the copper foil faces the adjacent conductive layer group, and the matte surface of the copper foil faces the inner side of the auxiliary layer.

[0031] Optionally, the auxiliary layer includes two layers of copper foil and the bonding layer located between the two layers of copper foil.

[0032] Optionally, the thickness of the copper foil is d, wherein 12um≤d≤70um.

[0033] According to another aspect of the present invention, there is provided a high-precision circuit board, which is manufactured by using any of the above-mentioned methods for manufacturing a high-precision circuit board.

[0034] The technical solution of the present invention can increase the thickness of the plate pressed at one time by pressing different conductive layer groups in the same process, and can also include part of the conductive layer that should be exposed to the outer layer during the pressing process in the middle position of the film layer structure, thereby increasing the uniformity of heat during the pressing process, making the expansion and contraction generated during the pressing process easier to control, and effectively reducing the layer deviation and warping generated by the pressing; in addition, pressing different conductive layer groups in the same process makes the consistency of the film layer expansion and contraction data of different conductive layer groups better, which is conducive to improving the alignment accuracy, simplifying the subsequent expansion and contraction adjustment process, and effectively solving the technical problems of alignment and warping caused by the asymmetric structure of each conductive layer group when they are pressed separately. The embodiments of the present invention can effectively solve the preparation problems of AI server accelerator cards, thereby promoting the rapid development of AI server accelerator card technology in the future.

[0035] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0037] Figure 1 It is a flow chart of a method for preparing a high-precision circuit board provided by an embodiment of the present invention;

[0038] Figure 2 It is a schematic diagram of a film layer structure of a preset circuit diagram of a high-precision circuit board provided by an embodiment of the invention;

[0039] Figure 3 It is a schematic diagram of a film layer structure in a stacked arrangement manner provided by an embodiment of the present invention;

[0040] Figure 4 is a schematic diagram of a film layer structure of a laminated sub-plate provided by an embodiment of the present invention;

[0041] Figure 5 It is a schematic diagram of a film layer structure in another stacking arrangement provided by an embodiment of the present invention;

[0042] Figure 6 It is a schematic diagram of a film layer structure in another stacking arrangement provided by an embodiment of the present invention;

[0043] Figure 7 It is a schematic diagram of a film layer structure in another stacking arrangement provided by an embodiment of the present invention;

[0044] Figure 8 It is a schematic diagram of a film layer structure in another stacking arrangement provided by an embodiment of the present invention;

[0045] Fig. 9 It is a schematic diagram of a film layer structure in another stacking arrangement provided by an embodiment of the present invention;

[0046] Fig.10 It is a schematic diagram of a film layer structure in another stacking arrangement provided by an embodiment of the present invention;

[0047] Fig.11 It is a schematic diagram of a membrane layer structure in another stacking arrangement provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0048] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0049] It should be noted that the terms "including" and "having" and any variations thereof in the specification and claims of the present invention and the above-mentioned drawings are intended to cover non-exclusive inclusions. For example, a process, method, system, product or apparatus comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or apparatus.

[0050] Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention.

[0051] Figure 1 is a flow chart of a method for preparing a high-precision circuit board provided by an embodiment of the present invention, with reference to Figure 1 , the preparation method comprises:

[0052] S1001. Obtain a preset circuit diagram of a high-precision circuit board.

[0053] Among them, the high-precision circuit board of the embodiment of the present invention can be applied to AI server acceleration card products, and can also be applied to computer system boards, mainboards and other products. Specifically, it can be a stepped gold finger printed circuit board, but it is not limited to this.

[0054] The preset circuit diagram includes the circuit patterns of each film layer in the high-precision circuit board, as well as the positions of blind holes and / or buried holes and their connection relationships. For example, taking the high-precision circuit board including 18 layers (L1-L18) of conductive layers 10 as an example, Figure 2 is a schematic diagram of a film structure of a preset circuit diagram of a high-precision circuit board provided by an embodiment of the invention, with reference to Figure 2 The preset circuit diagram shows the structure of each film layer, the position of the blind hole and / or the buried hole and their connection relationship, and also shows the bonding layer 102, which can bond and insulate the adjacent conductive layer 10. In addition, the preset circuit diagram can also show the circuit pattern of each film layer structure ( Figure 2 not shown).

[0055] S1002. According to a preset circuit diagram, a plurality of conductive layer groups are set; wherein, adjacent conductive layers that need to form the same blind hole or buried hole are one conductive layer group, and adjacent conductive layers that do not need to form blind holes or buried holes are one conductive layer group; each conductive layer group includes a core board provided with two conductive layers.

[0056] Exemplary, reference Figure 2 , the first conductive layer group 01 and the second conductive layer group 02 can be divided according to the film layer schematic diagram of the preset circuit diagram, and the conductive layer group (01, 02) can include a plurality of core boards 22, and the core board 22 includes a substrate layer 20 and a conductive layer 10 located on both sides of the substrate layer. In addition, the conductive layer group (01, 02) can also include a single conductive layer 11. In an optional embodiment, the conductive layer 10 can be a copper layer, and the single conductive layer 11 can be a copper foil.

[0057] In an optional embodiment, multiple conductive layer groups are provided according to a preset circuit diagram, including: dividing multiple conductive layer groups according to the preset circuit diagram, and forming a preset circuit on the conductive layer 10 located inside the conductive layer group. After forming the preset circuit, the circuit surface may be browned to increase the bonding force between the conductive layer 10 and the adhesive layer 102 during the subsequent lamination process.

[0058] Among them, the preset circuits of different conductive layers 10 may be different, and the conductive layers located on the surface of the conductive layer group (such as the first layer L1, the seventh layer L7, the eighth layer L8, and the eighteenth layer L18) may temporarily not form preset circuits to avoid damage to the preset circuits on the surface of the conductive layer group during the pressing process.

[0059] S1003, stacking the conductive layers, placing an adhesive layer between the core plates of the same group or between the core plate and the conductive layer, and placing an auxiliary layer between different and adjacent conductive layer groups.

[0060] For example, Figure 3 Schematic diagram of a film layer structure in a stacked arrangement manner provided by an embodiment of the present invention. Figure 3 As shown, an adhesive layer 102 is placed between each conductive layer structure (core board 22, single conductive layer 11) in the same conductive layer group, and an auxiliary layer 30 is placed between different conductive layer groups.

[0061] Among them, the bonding layer 102 can be a semi-cured sheet, also known as a PP sheet, which can be softened and melted in a high temperature environment, and solidified and bonded to adjacent film layers after cooling. The auxiliary layer 30 needs to be peelable and will not introduce pollution sources during the stacking and lamination process. The auxiliary layer 30 includes but is not limited to copper foil, aluminum sheet, steel plate, copper clad laminate, etc. The auxiliary layer 30 can be a metal material with a certain thickness, which can provide a certain hardness during the lamination process, which is conducive to reducing the misalignment and warping after lamination.

[0062] S1004, laminating the stacked conductive layer, adhesive layer and auxiliary layer, and peeling off the auxiliary layer after lamination, so that the conductive layer group forms a sub-board.

[0063] Specifically, a suitable preset temperature can be selected according to the material of the bonding layer 102, the stacked conductive layer, bonding layer and auxiliary layer are heated, and a certain pressure is applied to make the bonding layer 102 transform from a solid state to a molten state, and bond the adjacent film layer structures (core board 22, single-layer conductive layer 11). Among them, no bonding layer 102 is provided between different conductive layer groups, so different conductive layer groups are not bonded.

[0064] For example, Figure 4 is a schematic diagram of a film structure of a laminated sub-plate provided by an embodiment of the present invention, with reference to Figure 3 and Figure 4 After the first conductive layer group 01 is pressed together, a first sub-board 91 can be formed. After the second conductive layer group 02 is pressed together, a second sub-board 92 can be formed. Before pressing together, an auxiliary layer 30 is placed between the first conductive layer group 01 and the second conductive layer group 02. On the one hand, it can prevent the first sub-board 91 and the second sub-board 92 formed after pressing from being tightly attached and difficult to separate. On the other hand, it can prevent the pulling force during the separation process of the first sub-board 91 and the second sub-board 92 from damaging or bending the first sub-board 91 and / or the second sub-board 92, thereby preventing unnecessary losses.

[0065] In an optional embodiment, before laminating the stacked conductive layers, adhesive layers and auxiliary layers, the conductive layers 10 in each conductive layer group may be fixed together by riveting. For example, the conductive layers 10 of the L1-L7 layers may be fixed together, and the conductive layers 10 of the L8-L18 layers may be fixed together to reduce the displacement of the film layers during the lamination process.

[0066] S1005 , drilling a hole at a preset position of at least one sub-board to form a through hole.

[0067] For example, continue to refer to Figure 4 , a through hole can be formed in the daughter board by mechanical drilling, and then copper is plated in the through hole and the resin is plugged ( Figure 4 After plugging the hole, copper can be coated on the surface to prepare the pad ( Figure 4 After the holes are plugged, a preset circuit can be formed on the conductive layer 10 partially located on the surface (for example, the seventh layer L7 and the eighth layer L8). After the preset circuit is formed, the circuit surface can be browned to increase the bonding force between the conductive layer 10 and the adhesive layer 102 during the subsequent lamination process.

[0068] S1006, stacking the sub-boards and placing adhesive layers between different and adjacent sub-boards.

[0069] For example, Figure 5 FIG. 1 is a schematic diagram of a film layer structure in another stacking arrangement provided by an embodiment of the present invention. Figure 5 As shown, the second lamination requires placing an adhesive layer 102 between the sub-plates (91, 92) to bond the first sub-plate 91 and the second sub-plate 92 together after subsequent lamination.

[0070] S1007, pressing the stacked sub-boards and adhesive layers to form blind holes or buried holes through the through holes.

[0071] Exemplarily, after the first sub-board 91 and the second sub-board 92 are pressed and bonded together, a preset circuit may be formed on the conductive layer 10 located on the surface (eg, the first layer L1 and the eighteenth layer L18 ).

[0072] It should be noted that the figure only exemplarily shows that two conductive layer groups are required to form a high-precision circuit board. In other embodiments, the high-precision circuit board can also be formed by pressing three or more conductive layer groups together to form multiple sub-boards, and then pressing them again after through holes are formed in the sub-boards. Among them, when the sub-board in the middle position is provided with a through hole, a buried hole of the high-precision circuit board can be formed after pressing again (not shown in the figure).

[0073] It should also be noted that the figure only exemplarily shows that the high-precision circuit board includes 18 conductive layers. In other embodiments, the high-precision circuit board may also include less than 18 layers or more than 18 conductive layers, and the embodiments of the present invention are not limited to this.

[0074] In an optional embodiment, gold fingers can be formed on the edge of one or both sides of the surface of the daughter board before or after the daughter boards are pressed together, and the gold fingers can be properly aligned and connected with the connectors of other devices or circuit boards.

[0075] In the embodiment of the present invention, by laminating different conductive layers in the same process, the thickness of the plate pressed once can be increased, and part of the conductive layer (such as Figure 2-Figure 5 L7 and L8) are included in the middle position of the film layer structure, which increases the uniformity of heat during the pressing process, makes the expansion and contraction caused by the pressing process easier to control, and can effectively reduce the layer deviation and warping caused by the pressing; in addition, the different conductive layer groups are pressed in the same process, so that the expansion and contraction data of the film layers of different conductive layer groups are more consistent, which is beneficial to improving the alignment accuracy and simplifying the subsequent expansion and contraction adjustment process.

[0076] It should be noted that Figure 2-Figure 5For example, during the lamination process, the outermost layers of the first conductive layer group 01 and the second conductive layer group 02 still have an asymmetric structure with the single conductive layer 11 at the top and the core board 22 at the bottom. However, through the preparation method of the high-precision circuit board provided by the embodiment of the present invention, the first conductive layer group 01 and the second conductive layer group 02 are pressed together in the same process, which improves the heating uniformity of each film layer, and can effectively reduce the layer deviation and warping of the core board 22 at the bottom of the first conductive layer group 01, as well as the layer deviation and warping of the single conductive layer 11 at the top of the second conductive layer group 02; the first conductive layer group 01 and the second conductive layer group 02 are pressed together in the same process, which improves the expansion and contraction consistency of different conductive layer groups, and can also simplify or even omit the expansion and contraction coordination of the core board 22 at the bottom of the first conductive layer group 01 and the single conductive layer 11 at the top of the second conductive layer group 02, which can effectively solve the technical problems of alignment and warping caused by the asymmetric structure when each conductive layer group is pressed together separately. The embodiments of the present invention can effectively solve the difficulty in preparing AI server accelerator cards, thereby promoting the rapid development of AI server accelerator card technology in the future.

[0077] Optional, Figure 6 FIG. 1 is a schematic diagram of a film layer structure in another stacking arrangement provided by an embodiment of the present invention. Figure 6 As shown, each conductive layer group includes an even number of conductive layers 10, and each conductive layer group does not include a single conductive layer 11. In this way, each conductive layer group has a symmetrical structure, which is conducive to balancing the stress of each film layer in the first conductive layer group 01 and the second conductive layer group 02 during the high temperature and high pressure lamination process, and is conducive to further reducing the layer deviation and warpage after lamination.

[0078] However, the situation that each conductive layer group includes an even number of conductive layers 10 and each conductive layer group does not include a single conductive layer 11 is only applicable to special cases. In actual applications, at least some conductive layer groups include a single conductive layer 11, and the structural asymmetry of the conductive layer groups still needs to be considered.

[0079] Optional, Figure 7 FIG. 1 is a schematic diagram of a film layer structure in another stacking arrangement provided by an embodiment of the present invention. Figure 7 As shown, the topmost and bottommost conductive layer groups include an odd number of conductive layers 10; according to a preset circuit diagram, multiple conductive layer groups are set, including: according to a preset circuit diagram, multiple conductive layer groups are divided; wherein, in the topmost and bottommost conductive layer groups, the side close to the adjacent conductive layer group is a single conductive layer 11, and / or, in the topmost and bottommost conductive layer groups, the side away from the adjacent conductive layer group is a core board 22.

[0080] Exemplarily, when the conductive layer group includes an odd number of conductive layers 10, it is inevitably necessary to set a single conductive layer 11 in the conductive layer group. In a feasible embodiment, the single conductive layer 11 can be set at a position close to other conductive layer groups. For example, the single conductive layer 11 can be set at the bottom layer of the top first conductive layer group 01, and / or, at the top layer of the bottom second conductive layer group 02. In this way, when multiple conductive layer groups are pressed together in the same process, the single-layer conductive layer 11 that is prone to layer deviation and warping can be placed in the middle position, which is beneficial to improving the heating uniformity and expansion and contraction uniformity of the single-layer conductive layer 11 during the pressing process, thereby effectively reducing the layer deviation and warping of the single-layer conductive layer 11; in addition, when multiple conductive layer groups are pressed together in the same process, the top layer (first layer L1) and the bottom layer (eighteenth layer L18) are both core boards 22, so that the top layer (first layer L1) and the bottom layer (eighteenth layer L18) are symmetrical, which is beneficial to reducing the layer deviation and warping of the top layer (first layer L1) and / or the bottom layer (eighteenth layer L18).

[0081] In a feasible implementation manner, the single conductive layer 11 may also be disposed at a position away from other conductive layer groups. Figure 8 FIG. 1 is a schematic diagram of a film layer structure in another stacking arrangement provided by an embodiment of the present invention. Figure 8 As shown, the topmost and bottommost conductive layer groups include an odd number of conductive layers 10; multiple conductive layer groups are set according to a preset circuit diagram, including: multiple conductive layer groups are divided according to a preset circuit diagram; wherein, in the topmost and bottommost conductive layer groups, the side away from the adjacent conductive layer group is a single conductive layer 11, and / or, in the topmost and bottommost conductive layer groups, the side close to the adjacent conductive layer group is a core board 22.

[0082] For example, the single conductive layer 11 may be disposed at the topmost layer of the topmost first conductive layer group 01, and / or at the bottommost layer of the bottommost second conductive layer group 02. In this way, the topmost layer (first layer L1) and the bottommost layer (eighteenth layer L18) may be symmetrical, which is beneficial to reducing the layer deviation and warping of the topmost layer (first layer L1) and / or the bottommost layer (eighteenth layer L18).

[0083] However, for different practical needs, it may not be possible to make the top layer (the first layer L1) and the bottom layer (the eighteenth layer L18) symmetrical during lamination. Fig. 9 FIG. 1 is a schematic diagram of a film layer structure in another stacking arrangement provided by an embodiment of the present invention. Fig. 9As shown, the top and / or bottom conductive layer group includes an odd number of conductive layers 10; according to the preset circuit diagram, multiple conductive layer groups are set, including: according to the preset circuit diagram, multiple conductive layer groups are divided; wherein, one of the top layer in the top conductive layer group and the bottom layer in the bottom conductive layer group is a single conductive layer 11, and the other is a core board 22. The auxiliary layer 30 may include a single conductive layer 11. Before laminating multiple conductive layer groups at one time, in addition to placing the auxiliary layer 30 (i.e., the single conductive layer 11) between different and adjacent conductive layer groups, the auxiliary layer 30 (i.e., the single conductive layer 11) may also be placed above the top conductive layer group or below the bottom conductive layer group, so that the upper and lower edge conductive layers 10 in all conductive layers 10 are single conductive layers 11.

[0084] Exemplarily, according to special design requirements, in the combination of the first conductive layer group 01 and the second conductive layer group 02, the top layer is a single conductive layer 11, and the bottom layer is a core board 22. In this case, the single conductive layer 11 can be used as the auxiliary layer 30. When stacking the film layer structures, in addition to placing the auxiliary layer 30 (i.e., the single conductive layer 11) between the conductive layer groups, the auxiliary layer 30 (i.e., the single conductive layer 11) can also be placed under the bottom conductive layer 10 (i.e., the eighteenth layer L18) of the second conductive layer group 02. In this way, the bottom auxiliary layer 30 (i.e., the single conductive layer 11) can simulate the symmetrical structure of the top layer (the first layer L1) to reduce layer deviation and warping after lamination.

[0085] Optionally, the conductive layer includes a copper layer; and the auxiliary layer includes at least one layer of copper foil.

[0086] For example, one or more layers of copper foil can be placed between different conductive layer groups, and the thickness of a single layer of copper foil can be between 12um and 70um. Using copper foil as an auxiliary layer, on the one hand, the material properties of the copper foil make it easier to peel after lamination; on the other hand, the conductive layer on the surface of the conductive layer group and the copper foil of the auxiliary layer are made of the same material, so even if the peeling fails, impurities from other materials will not be introduced, which is conducive to improving product yield.

[0087] In an optional embodiment, the auxiliary layer includes two layers of copper foil; placing the auxiliary layer between different and adjacent conductive layer groups includes: placing two copper layers between different and adjacent conductive layer groups, with the glossy surface of the copper foil facing the adjacent conductive layer group and the rough surface of the copper foil facing the inner side of the auxiliary layer.

[0088] For example, Fig.10 FIG. 1 is a schematic diagram of a film layer structure in another stacking arrangement provided by an embodiment of the present invention. Fig.10As shown, the shiny surface of the copper foil in the lower layer of the auxiliary layer 30 can face the uppermost conductive layer 10 (eighth layer L8) of the second conductive layer group 02, and the shiny surface of the copper foil in the upper layer of the auxiliary layer 30 can face the lowermost conductive layer 10 (seventh layer L7) of the first conductive layer group 01. In this way, during the lamination process, the rough fur surfaces of the two copper foils in the auxiliary layer 30 can be attached to each other, and the shiny surface of the copper foil can contact the conductive layer 10 of the conductive layer group (01 or 02), which is conducive to subsequent peeling.

[0089] In addition, placing two layers of copper foil between adjacent conductive layer groups (01 and 02) is also beneficial to simulating a symmetrical structure of the conductive layer groups (01 and 02) to reduce layer deviation and warping during the lamination process.

[0090] For example, continue to refer to Fig.10 The top layer of the first conductive layer group 01 is a single conductive layer 11, such as copper foil, and the bottom layer of the first conductive layer group 01 is a core board 22, and the first conductive layer group 01 is an asymmetric structure; the bottom layer of the second conductive layer group 02 is a single conductive layer 11, such as copper foil, and the top layer of the second conductive layer group 02 is a core board 22, and the second conductive layer group 02 is also an asymmetric structure. By placing two layers of copper foil between the first conductive layer group 01 and the second conductive layer group 02, the copper foil in the upper layer of the auxiliary layer 30 can simulate the symmetrical structure of the uppermost copper foil in the first conductive layer group 01, and the copper foil in the lower layer of the auxiliary layer 30 can simulate the symmetrical structure of the lowermost copper foil in the second conductive layer group 02. During the lamination process, the copper foil in the upper layer of the first conductive layer group 01 and the auxiliary layer 30 form a symmetrical structure, and the copper foil in the lower layer of the second conductive layer group 02 and the auxiliary layer 30 form a symmetrical structure. During the high-temperature and high-pressure lamination process, it is beneficial to balance the stress of each film layer in the first conductive layer group 01 and the second conductive layer group 02, and it is beneficial to further reduce the layer deviation and warping after lamination.

[0091] In yet another optional embodiment, the auxiliary layer includes two layers of copper foil and an adhesive layer located between the two layers of copper foil.

[0092] For example, Fig.11 FIG. 1 is a schematic diagram of a film layer structure in another stacking arrangement provided by an embodiment of the present invention. Fig.11As shown, two layers of copper foil and an adhesive layer between the two layers of copper foil are placed between adjacent conductive layer groups, wherein the number of adhesive layers can be set according to actual needs. An adhesive layer 102 is set in the auxiliary layer 30, and the adhesive layer softens and melts at high temperatures. During the lamination process, the conductive layer 10 in the conductive layer group and the adhesive layer 102 can be buffered, which is conducive to the adhesive layer 102 filling the line gap of the conductive layer 10, improving the coating effect, and is particularly suitable for the case where the conductive layer 10 in the conductive layer group is thicker, avoiding the case where the conductive layer 10 in the conductive layer group is thicker and the adhesive layer 102 cannot be filled and can only contact the surface of the conductive layer 10, which can effectively solve the problem of easy delamination of the conductive layer 10 in the conductive layer group.

[0093] Based on the same inventive idea, the present invention also provides a high-precision circuit board. The high-precision circuit board provided by the embodiment of the present invention can be prepared by the method for preparing the high-precision circuit board provided by any embodiment of the present invention. Therefore, the high-precision circuit board provided by the embodiment of the present invention also has the beneficial effects of the method for preparing the high-precision circuit board provided by the embodiment of the present invention. For the contents not described in detail in this embodiment, refer to the above description of the method for preparing the high-precision circuit board, and will not be repeated here.

[0094] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0095] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for preparing a high-precision circuit board, characterized in that: The high-precision circuit board includes at least one blind hole or buried hole; The preparation method comprises: Obtaining a preset circuit diagram of the high-precision circuit board; According to the preset circuit diagram, a plurality of conductive layer groups are provided; wherein, the conductive layers adjacent to each other and the same blind hole or buried hole need to be formed constitute one conductive layer group, and the conductive layers adjacent to each other and the blind hole or buried hole do not need to be formed constitute one conductive layer group; each conductive layer group comprises a core board provided with two conductive layers; The conductive layers are stacked, and a bonding layer is placed between the core plates of the same group or between the core plate and the conductive layer, and an auxiliary layer is placed between different and adjacent conductive layer groups; Laminating the stacked conductive layer, the adhesive layer and the auxiliary layer, and peeling off the auxiliary layer after laminating, so that the conductive layer group forms a sub-board; Drilling a hole at a preset position of at least one of the sub-boards to form a through hole; stacking the sub-boards and placing the bonding layer between different and adjacent sub-boards; The sub-board and the bonding layer are laminated and stacked, so that the through hole forms the blind hole or the buried hole.

2. The method for preparing a high-precision circuit board according to claim 1, characterized in that: At least part of the conductive layer group includes a single conductive layer.

3. The method for preparing a high-precision circuit board according to claim 2, characterized in that: The uppermost and lowermost conductive layer groups include an odd number of conductive layers; According to the preset circuit diagram, a plurality of conductive layer groups are arranged, including: According to the preset circuit diagram, a plurality of conductive layer groups are divided; wherein, the side close to the adjacent conductive layer group in the topmost and bottommost conductive layer groups is the single conductive layer, and / or, the side away from the adjacent conductive layer group in the topmost and bottommost conductive layer groups is the core board.

4. The method for preparing a high-precision circuit board according to claim 2, characterized in that: The uppermost and lowermost conductive layer groups include an odd number of conductive layers; According to the preset circuit diagram, a plurality of conductive layer groups are arranged, including: According to the preset circuit diagram, a plurality of conductive layer groups are divided; wherein the side away from the adjacent conductive layer group in the topmost and bottommost conductive layer groups is the single conductive layer, and / or the side close to the adjacent conductive layer group in the topmost and bottommost conductive layer groups is the core board.

5. The method for preparing a high-precision circuit board according to claim 2, characterized in that: The auxiliary layer includes the single conductive layer; The uppermost and / or lowermost conductive layer group includes an odd number of conductive layers; According to the preset circuit diagram, a plurality of conductive layer groups are arranged, including: According to the preset circuit diagram, a plurality of conductive layer groups are divided; wherein one of the uppermost layer in the uppermost conductive layer group and the lowermost layer in the lowermost conductive layer group is the single conductive layer, and the other is the core board; The conductive layers are stacked, a bonding layer is placed between the core plates in the same group or between the core plates and the conductive layers, and an auxiliary layer is placed between different and adjacent conductive layer groups, comprising: The conductive layers are stacked, and a bonding layer is placed between the core plates in the same group or between the core plates and the conductive layers. The auxiliary layer is placed between different and adjacent conductive layer groups. The auxiliary layer is also placed above the top conductive layer group or below the bottom conductive layer group, so that the upper and lower edge conductive layers in all the conductive layers are single-layer conductive layers.

6. The method for preparing a high-precision circuit board according to claim 1, characterized in that: The conductive layer includes a copper layer; and the auxiliary layer includes at least one layer of copper foil.

7. The method for preparing a high-precision circuit board according to claim 6, characterized in that: The auxiliary layer includes two layers of copper foil; Placing an auxiliary layer between different and adjacent conductive layer groups, comprising: Two copper layers are placed between different and adjacent conductive layer groups, the shiny surface of the copper foil faces the adjacent conductive layer group, and the matte surface of the copper foil faces the inner side of the auxiliary layer.

8. The method for preparing a high-precision circuit board according to claim 6, characterized in that: The auxiliary layer includes two layers of copper foil and the bonding layer located between the two layers of copper foil.

9. The method for preparing a high-precision circuit board according to any one of claims 6 to 8, characterized in that: The thickness of the copper foil is d, wherein 12um≤d≤70um.

10. A high-precision circuit board, characterized in that: The high-precision circuit board is prepared by the method for preparing the high-precision circuit board as described in any one of claims 1 to 9.

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