Semiconductor structure and manufacturing method thereof, memory and electronic equipment

Abstract

The embodiment of the invention provides a semiconductor structure and a manufacturing method thereof, a memory and electronic equipment. The semiconductor structure includes a plurality of active pillars and a first polysilicon layer. The plurality of active column arrays are arranged on one side of the substrate, and each active column comprises a drain region, a channel region and a source region which are sequentially far away from the substrate; the first polycrystalline silicon layer is at least arranged on the periphery of the drain electrode region, the first polycrystalline silicon layer is obtained by solid phase epitaxy of an amorphous silicon layer covering the surface of the active column, and doped impurities in the drain electrode region come from the amorphous silicon layer. According to the embodiment of the invention, the doping of the drain region of the active column is realized in a manner of diffusing impurities in the amorphous silicon layer, so that the active column is protected from being amorphized, and meanwhile, the normal work of the semiconductor structure is ensured.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a manufacturing method thereof, a memory and an electronic device. Background Art

[0002] At present, semiconductor memory technology is developing in the direction of increasing integration and reducing component size. In order to reduce product costs as much as possible, people hope to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's needs for current products. Summary of the invention

[0003] In view of the shortcomings of the existing methods, the present application proposes a semiconductor structure and a manufacturing method thereof, a memory and an electronic device to solve the technical problem that the active pillars in the existing semiconductor structure are easily amorphized and cannot be restored.

[0004] In a first aspect, an embodiment of the present application provides a semiconductor structure, including:

[0005] A plurality of active pillars are arranged in an array on one side of the substrate, wherein the active pillars include a drain region, a channel region and a source region which are sequentially away from the substrate;

[0006] The first polysilicon layer is at least arranged at the periphery of the drain region. The first polysilicon layer is obtained by solid phase epitaxy of an amorphous silicon layer covering the surface of the active column. The doping impurities of the drain region originate from the amorphous silicon layer.

[0007] In a second aspect, an embodiment of the present application provides a memory, comprising: the semiconductor structure described in the first aspect.

[0008] In a third aspect, an embodiment of the present application provides an electronic device, comprising: the memory described in the second aspect.

[0009] In a fourth aspect, an embodiment of the present application provides a method for manufacturing a semiconductor structure, comprising:

[0010] Manufacturing initial active pillars arranged in an array and an amorphous silicon layer disposed on the surface of the active pillars on one side of the substrate;

[0011] The amorphous silicon layer is annealed so that the amorphous silicon layer covering the surface of the active pillar forms a first polysilicon layer, and impurities in the amorphous silicon layer diffuse into the initial active pillar to form an active pillar.

[0012] The beneficial technical effects brought about by the technical solution provided by the embodiment of the present application include:

[0013] By setting a first polysilicon layer at least on the periphery of the drain region, the first polysilicon layer is obtained by solid phase epitaxy of an amorphous silicon layer covering the surface of the active column, and the doping impurities in the drain region are derived from the amorphous silicon layer, instead of forming the drain region of the vertical junctionless transistor by high-energy and high-dose ion implantation in the related art, it is possible to avoid the difficult-to-repair damage to the active column caused by the high-dose ion implantation, thereby helping to protect the active column from being amorphized, and further helping to ensure the normal operation of the semiconductor structure.

[0014] Additional aspects and advantages of the present application will be partially given in the following description, which will become apparent from the following description, or will be understood through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0016] Figure 1 A schematic top view of a semiconductor structure provided in an embodiment of the present application;

[0017] Figure 2 for Figure 1 Schematic diagram of the cross section along the AA direction;

[0018] Figure 3 for Figure 1 Schematic diagram of the cross section along the BB direction;

[0019] Figure 4 for Figure 1 Schematic diagram of the cross section along CC direction;

[0020] Figure 5 for Figure 1 Schematic diagram of the cross section along the DD direction;

[0021] Figure 6 A schematic diagram of a process for manufacturing a semiconductor structure provided in an embodiment of the present application;

[0022] Figure 7 A schematic diagram of a process for manufacturing an array of initial active pillars and an amorphous silicon layer disposed on the surface of the active pillars on one side of a substrate in a method for manufacturing a semiconductor structure provided in an embodiment of the present application;

[0023] Figures 8 to 66 A schematic cross-sectional view of each step of a method for manufacturing a semiconductor structure provided in an embodiment of the present application.

[0024] Description of reference numerals:

[0025] 1- substrate;

[0026] 2-active column; 21-drain region; 22-channel region; 23-source region;

[0027] 3-first polysilicon layer;

[0028] 4-gate insulating layer;

[0029] 5-word line;

[0030] 6-bit line;

[0031] 7- a first isolation structure;

[0032] 81-first trench; 811-initial first trench; 82-first amorphous silicon layer; 821-initial first amorphous silicon layer; 83-isolation layer; 84-second trench; 85-initial active pillar; 86-second isolation structure; 87-second amorphous silicon layer; 88-second polysilicon layer;

[0033] 91 - first dielectric layer; 92 - second dielectric layer; 93 - third dielectric layer; 94 - fourth dielectric layer; 95 - fifth dielectric layer. DETAILED DESCRIPTION

[0034] The embodiments of the present application are described below in conjunction with the drawings in the present application. It should be understood that the implementation methods described below in conjunction with the drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions of the embodiments of the present application.

[0035] Those skilled in the art will appreciate that, unless expressly stated otherwise, the singular forms "a", "an", "said" and "the" used herein may also include plural forms. It should be further understood that the term "comprising" used in the specification of the present application refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the implementation of other features, information, data, steps, operations, elements, components and / or combinations thereof supported by the technical field. The term "and / or" used herein refers to at least one of the items defined by the term, for example, "A and / or B" may be implemented as "A", or as "B", or as "A and B".

[0036] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0037] The following is a detailed description of the technical solution of the present application and how the technical solution of the present application solves the above technical problems with specific embodiments. It should be noted that the following implementations can refer to, draw on or combine with each other, and the same terms, similar features and similar implementation steps in different implementations will not be described repeatedly.

[0038] The present application embodiment provides a semiconductor structure. The schematic diagram of the semiconductor structure is as follows: Figures 1 to 5 As shown, it includes: a plurality of active pillars 2 and a first polysilicon layer 3.

[0039] A plurality of active pillars 2 are arranged in an array on one side of the substrate 1 . The active pillars 2 include a drain region 21 , a channel region 22 and a source region 23 which are sequentially away from the substrate 1 .

[0040] The first polysilicon layer 3 is at least disposed on the periphery of the drain region 21 . The first polysilicon layer 3 is obtained by solid phase epitaxy of an amorphous silicon layer covering the surface of the active pillar 2 . Doping impurities in the drain region 21 originate from the amorphous silicon layer.

[0041] In the present embodiment, a first polysilicon layer 3 is provided at least on the periphery of the drain region 21. The first polysilicon layer 3 is obtained by solid phase epitaxy of an amorphous silicon layer covering the surface of the active pillar 2. The doping impurities of the drain region 21 are derived from the amorphous silicon layer, which replaces the high-energy and high-dose ion implantation method of the vertical junctionless transistor in the related art. This can avoid the difficult-to-repair damage to the active pillar 2 caused by the high-dose ion implantation, thereby helping to protect the active pillar 2 from being amorphized, and at the same time helping to ensure the normal operation of the semiconductor structure.

[0042] It is understandable that the first polysilicon layer 3 can be arranged at the periphery of the drain region 21; or the first polysilicon layer 3 can be arranged at the periphery of the drain region 21 and the source region 23, or the first polysilicon layer 3 is arranged at the periphery of the drain region 21, the source region 23 and the channel region 22.

[0043] Optionally, refer to Figure 2 and Figure 4 The first polysilicon layer 3 is disposed at the periphery of the drain region 21 and the source region 23 , and the doping concentrations of the drain region 21 and the source region 23 are both higher than the doping concentration of the channel region 22 .

[0044] In this embodiment, the first polysilicon layer 3 is arranged at the periphery of the drain region 21 and the source region 23, and the periphery of the channel region 22 is a single crystal silicon layer. The doping concentration of the drain region 21 and the source region 23 is higher than the doping concentration of the channel region 22, which can help reduce the off-state current and improve the switching ratio.

[0045] Moreover, since the gate insulating layer 4 needs to be manufactured at the periphery of the channel region 22, the thickness of the gate insulating layer 4 is limited. If the first polysilicon layer 3 at the periphery of the channel region 22 is not removed, the gate insulating layer 4 with a limited thickness will affect the thickness of the first polysilicon layer 3 deposited, thereby affecting the doping concentration of the first polysilicon layer 3. Therefore, removing the first polysilicon layer 3 at the periphery of the channel region 22 can avoid affecting the thickness of the gate insulating layer 4 at the periphery of the channel region 22, and can also avoid affecting the thickness and doping concentration of the first polysilicon layer 3 deposited, which is conducive to separately adjusting the thickness of the first polysilicon layer 3 and the thickness of the gate insulating layer 4, and is conducive to improving the process window and increasing the selectivity of process conditions.

[0046] Optionally, refer to Figure 2 and Figure 4 The semiconductor structure further includes a gate insulating layer 4 and a gate (not marked in the figure) disposed on the periphery of the channel region 22 .

[0047] In a plane parallel to the substrate 1 , the size of the gate insulating layer 4 is not smaller than the size of the first polysilicon layer 3 .

[0048] In this embodiment, the gate insulating layer 4 is obtained by oxidizing the first polysilicon layer 3 at the periphery of the channel region 22. In a plane parallel to the substrate 1, the size of the gate insulating layer 4 is not less than the size of the first polysilicon layer 3, that is, the thickness of the gate insulating layer 4 is not less than the thickness of the first polysilicon layer 3, which can ensure that the first polysilicon layer 3 at the periphery of the channel region 22 is completely consumed, thereby facilitating the avoidance of short circuit.

[0049] Optionally, refer to Figures 1 to 4 The semiconductor structure further includes a plurality of word lines 5, and each gate arranged in the same row along the first direction is connected to form a word line 5. The plurality of word lines 5 extend along the first direction and are arranged at intervals along the second direction. The first direction and the second direction have a designed angle and are both parallel to the substrate 1.

[0050] In this embodiment, the word line 5 can control the channel region 22 of the active pillars 2 located in the same row along the first direction.

[0051] Optionally, refer to Figure 1 , Figure 2 , Figure 4 and Figure 5 The semiconductor structure further includes a plurality of bit lines 6 and a plurality of first isolation structures 7. The plurality of bit lines 6 and the plurality of first isolation structures 7 are arranged at intervals along the first direction and extend along the second direction. The bit lines 6 are arranged on a side of the active pillar 2 close to the substrate 1.

[0052] refer to Figure 4 and Figure 5The bit lines 6 and the first isolation structures 7 are alternately arranged along the first direction, and the bottom surface of the first isolation structure 7 is closer to the bottom surface of the substrate 1 than the bottom surface of the bit lines 6 .

[0053] In this embodiment, the bit lines 6 and the first isolation structures 7 are alternately arranged along the first direction, and the first isolation structures 7 can isolate two adjacent bit lines 6 to prevent short circuits. The bottom surface of the first isolation structure 7 is closer to the bottom surface of the substrate 1 than the bottom surface of the bit lines 6, which can ensure that there is no signal connection between the two adjacent bit lines 6, which is conducive to ensuring normal signal transmission.

[0054] Based on the same inventive concept, an embodiment of the present application provides a memory, including the semiconductor structure provided by the above embodiment.

[0055] In this embodiment, since the memory adopts any one of the semiconductor structures provided in the aforementioned embodiments, its principles and technical effects can be referred to in the aforementioned embodiments and will not be described in detail here.

[0056] Based on the same inventive concept, an embodiment of the present application provides an electronic device, including the memory provided by the above embodiment.

[0057] In this embodiment, since the electronic device adopts any one of the memories provided in the aforementioned embodiments, its principles and technical effects can be referred to in the aforementioned embodiments and will not be described in detail here.

[0058] Optionally, the electronic device may include a smart phone, a computer, a tablet computer, artificial intelligence, a wearable device or a smart mobile terminal.

[0059] It should be noted that electronic devices are not limited to the above-mentioned ones. Those skilled in the art can set any one of the memories provided in the above-mentioned embodiments of the present application in different devices according to actual application requirements, so as to obtain the electronic device provided in the embodiments of the present application.

[0060] Based on the same inventive concept, the present application embodiment provides a method for manufacturing a semiconductor structure, and the flow chart of the manufacturing method is as follows: Figure 6 As shown, it includes steps S1 and S2:

[0061] S1: manufacturing initial active pillars 85 arranged in an array and an amorphous silicon layer disposed on the surface of the active pillars on one side of the substrate 1 .

[0062] S2 : performing annealing treatment on the amorphous silicon so that the amorphous silicon layer covering the surface of the initial active pillar 85 forms a first polysilicon layer 3 , and the impurities in the amorphous silicon layer diffuse into the initial active pillar 85 to form an active pillar 2 .

[0063] In the present embodiment, the active pillar 2 is doped by diffusing impurities in the amorphous silicon layer, instead of the high-energy and high-dose ion implantation method of the vertical junctionless transistor in the related art. This can avoid the difficult-to-repair damage to the active pillar 2 caused by the high-dose ion implantation, thereby helping to protect the active pillar 2 from being amorphized and ensuring the normal operation of the semiconductor structure.

[0064] Optionally, after step S2, it also includes: protecting the first polysilicon layer 3 on the periphery of the drain region 21 and the source region 23 of the active column 2, oxidizing the first polysilicon layer 3 on the periphery of the channel region 22 to obtain a gate insulating layer 4, and the doping concentration of the first polysilicon layer 3 is higher than the doping concentration of the channel region 22.

[0065] In this embodiment, when manufacturing the gate insulating layer 4, the first polysilicon layer 3 on the periphery of the channel region 22 can be oxidized and the first polysilicon layer 3 on the periphery of the channel region 22 can be removed, thereby reducing the doping concentration of the channel region 22 and ensuring that the channel region 22 is composed of single crystal silicon. The doping concentration of the first polysilicon layer 3 is higher than the doping concentration of the channel region 22, that is, the doping concentration of the channel region 22 is less than the doping concentrations of the drain region 21 and the source region 23, which can help reduce the off-state current and improve the switching ratio.

[0066] It should be noted that the method for manufacturing the gate insulating layer 4 is not limited to the above method. For example, the first polysilicon layer 3 on the periphery of the drain region 21 and the source region 23 of the active column 2 can be protected, and the first polysilicon layer 3 on the periphery of the channel region 22 can be removed; and then an insulating material is deposited on the periphery of the channel region 22 to obtain the gate insulating layer 4.

[0067] Optionally, in step S1, an array of initial active pillars 85 and an amorphous silicon layer disposed on the surface of the active pillars are manufactured on one side of the substrate 1, including steps S11 to S14. Figure 7 shown.

[0068] S11 : manufacturing first grooves 81 arranged at intervals along a first direction and extending along a second direction on one side of the substrate 1 ; the first direction and the second direction have a designed angle and are both parallel to the substrate 1 .

[0069] Optionally, in step S11, first grooves 81 spaced apart along the first direction and extending along the second direction are manufactured on one side of the substrate 1, including:

[0070] Initial first trenches 811 are formed on one side of the substrate 1 and are arranged at intervals along the first direction and extend along the second direction.

[0071] A first isolation structure 7 is manufactured in the initial first trench 811 to obtain a first trench 81 .

[0072] In this embodiment, Figure 8 It is a schematic top view after initial first grooves 811 arranged at intervals along the first direction and extending along the second direction are manufactured on one side of the substrate 1; Fig. 9 for Figure 8 The cross-section along the AA direction; Fig.10 for Figure 8 The cross-section along the BB direction; Fig.11 for Figure 8 The cross-section along CC direction; Fig.12 for Figure 8 Cross-section along DD direction.

[0073] Fig.13 To manufacture the first isolation structure 7 in the initial first trench 811, a cross-sectional view along the BB direction is obtained after the first trench 81 is obtained; Fig.14 To manufacture the first isolation structure 7 in the initial first trench 811, a cross-sectional view along the CC direction of the first trench 81 is obtained; Fig.15 To manufacture the first isolation structure 7 in the initial first trench 811, a cross-sectional view along the DD direction of the first trench 81 is obtained. Figures 12 to 15 , a first isolation structure 7 is filled in the initial first trench 811 , and the upper surface of the first isolation structure 7 is flush with the upper surface of the subsequently manufactured bit line 6 , which is beneficial to isolating the bit line 6 .

[0074] S12: conformally fabricating an initial first amorphous silicon layer 821 in the first trench 81 so that the initial first amorphous silicon layer 821 covers the entire surface of the substrate 1 ; removing the initial first amorphous silicon layer 821 at the bottom of the first trench 81 , and fabricating an isolation layer 83 that covers the remaining initial first amorphous silicon layer 821 and fills the first trench 81 .

[0075] In this embodiment, Fig.16 A schematic cross-sectional view along the AA direction obtained after the initial first amorphous silicon layer 821 is conformally manufactured in the first trench 81 so that the initial first amorphous silicon layer 821 covers the entire surface of the substrate 1; Fig.17 A schematic cross-sectional view along the BB direction obtained after the initial first amorphous silicon layer 821 is conformally manufactured in the first trench 81 so that the initial first amorphous silicon layer 821 covers the entire surface of the substrate 1; Fig.18 A schematic cross-sectional view along the CC direction obtained after the initial first amorphous silicon layer 821 is conformally manufactured in the first trench 81 so that the initial first amorphous silicon layer 821 covers the entire surface of the substrate 1; Fig.19 A schematic cross-sectional view along the DD direction obtained after the initial first amorphous silicon layer 821 is conformally manufactured in the first trench 81 so that the initial first amorphous silicon layer 821 covers the entire surface of the substrate 1. Figures 16 to 19, the initial first amorphous silicon layer 821 covers the surface of the first trench 81 but does not completely fill the first trench 81 .

[0076] Fig. 20 It is a schematic cross-sectional view along the BB direction obtained after removing the initial first amorphous silicon layer 821 at the bottom of the first trench 81; Fig.21 It is a schematic cross-sectional view along the CC direction obtained after removing the initial first amorphous silicon layer 821 at the bottom of the first trench 81; Fig. 22 FIG. 8 is a schematic cross-sectional view along the DD direction obtained after removing the initial first amorphous silicon layer 821 at the bottom of the first trench 81. Figure 20 to Figure 22 It can be seen that removing the initial first amorphous silicon layer 821 at the bottom of the first trench 81 while removing the initial first amorphous silicon layer 821 at the top of the first trench 81 can help avoid the situation where the initial first amorphous silicon layer 821 at the bottom of the first trench 81 that cannot be removed subsequently forms polycrystalline silicon and causes a short circuit.

[0077] Fig.23 A schematic cross-sectional view along the AA direction obtained after manufacturing the isolation layer 83 covering the remaining initial first amorphous silicon layer 821 and filling the first trench 81; Fig.24 A schematic cross-sectional view along the BB direction obtained after manufacturing the isolation layer 83 covering the remaining initial first amorphous silicon layer 821 and filling the first trench 81; Fig.25 A schematic cross-sectional view along the CC direction obtained after manufacturing the isolation layer 83 covering the remaining initial first amorphous silicon layer 821 and filling the first trench 81; Fig.26 This is a schematic cross-sectional view along the DD direction obtained after manufacturing the isolation layer 83 that covers the remaining initial first amorphous silicon layer 821 and fills the first trench 81. Figure 23 to Figure 26 The material of the isolation layer 83 of the present application may include at least one of dielectric materials having an isolation function, such as silicon dioxide and silicon nitride. The thickness of the isolation layer 83 along the direction perpendicular to the substrate is not less than 5 nanometers and not more than 10 nanometers.

[0078] It should be noted that the material of the initial first amorphous silicon layer 821 may include N-type phosphorus.

[0079] S13 : manufacturing second trenches 84 extending along the first direction and arranged at intervals along the second direction, obtaining initial active pillars 85 arranged in an array, a first amorphous silicon layer 82 formed by the initial first amorphous silicon layer 821 , and a second isolation structure 86 formed by the isolation layer 83 .

[0080] In this embodiment, Fig. 27A schematic cross-sectional view along the AA direction is obtained after manufacturing the second trenches 84 extending along the first direction and arranged at intervals along the second direction, obtaining the initial active pillars 85 arranged in an array, the first amorphous silicon layer 82 formed by the initial first amorphous silicon layer 821, and the second isolation structure 86 formed by the isolation layer 83; Fig.28 A schematic cross-sectional view along the BB direction obtained after manufacturing the second trenches 84 extending along the first direction and arranged at intervals along the second direction, obtaining the initial active pillars 85 arranged in an array, the first amorphous silicon layer 82 formed by the initial first amorphous silicon layer 821, and the second isolation structure 86 formed by the isolation layer 83; Fig.29 A schematic cross-sectional view along the CC direction obtained after manufacturing the second trenches 84 extending along the first direction and arranged at intervals along the second direction, obtaining the initial active pillars 85 arranged in an array, the first amorphous silicon layer 82 formed by the initial first amorphous silicon layer 821, and the second isolation structure 86 formed by the isolation layer 83; Fig.30 In order to manufacture the second grooves 84 extending along the first direction and arranged at intervals along the second direction, the initial active pillars 85 arranged in an array, the first amorphous silicon layer 82 formed by the initial first amorphous silicon layer 821 and the second isolation structure 86 formed by the isolation layer 83 are obtained, and a cross-sectional schematic diagram along the DD direction is obtained.

[0081] S14: manufacturing a second amorphous silicon layer 87 so that the second amorphous silicon layer 87 covers the surfaces of the second isolation structure 86 and the second trench 84. The amorphous silicon layer includes a first amorphous silicon layer 82 and a second amorphous silicon layer 87 covering the surfaces of the initial active pillars 85.

[0082] In this embodiment, Fig.31 A schematic cross-sectional view along the AA direction obtained after manufacturing the second amorphous silicon layer 87 so that the second amorphous silicon layer 87 covers the surface of the second isolation structure 86 and the second trench 84; Fig.32 A schematic cross-sectional view along the BB direction obtained after the second amorphous silicon layer 87 is manufactured so as to cover the surface of the second isolation structure 86 and the second trench 84; Fig.33 A schematic cross-sectional view along the CC direction obtained after the second amorphous silicon layer 87 is manufactured so as to cover the surface of the second isolation structure 86 and the second trench 84; Fig.34 A schematic cross-sectional view along the DD direction is obtained after the second amorphous silicon layer 87 is manufactured so as to cover the surface of the second isolation structure 86 and the second trench 84. It is understandable that the material of the second amorphous silicon layer 87 may also include N-type phosphorus.

[0083] Optionally, step S2 includes: annealing the entire substrate 1 so that the first amorphous silicon layer 82 and the second amorphous silicon layer 87 covering the periphery of the active pillar 2 together form a first polysilicon layer 3, and allowing impurities in the amorphous silicon layer to diffuse into the initial active pillar 85 to form the active pillar 2.

[0084] In this embodiment, Fig.35 A schematic cross-sectional view along the AA direction obtained after the entire substrate 1 is annealed so that the first amorphous silicon layer 82 and the second amorphous silicon layer 87 covering the periphery of the active pillar 2 form the first polysilicon layer 3 together, and the impurities in the amorphous silicon layer diffuse into the initial active pillar 85 to form the active pillar 2; Fig.36 A schematic cross-sectional view along the BB direction obtained after the entire substrate 1 is annealed so that the first amorphous silicon layer 82 and the second amorphous silicon layer 87 covering the periphery of the active pillar 2 form the first polysilicon layer 3 together, and the impurities in the amorphous silicon layer diffuse into the initial active pillar 85 to form the active pillar 2; Fig.37 A schematic cross-sectional view along the CC direction obtained after the entire substrate 1 is annealed so that the first amorphous silicon layer 82 and the second amorphous silicon layer 87 covering the periphery of the active pillar 2 form the first polysilicon layer 3 together, and the impurities in the amorphous silicon layer diffuse into the initial active pillar 85 to form the active pillar 2; Fig.38 The schematic cross-sectional view along the DD direction is obtained after the entire substrate 1 is annealed so that the first amorphous silicon layer 82 and the second amorphous silicon layer 87 covering the periphery of the active pillar 2 form the first polysilicon layer 3 together, and the impurities in the amorphous silicon layer diffuse into the initial active pillar 85 to form the active pillar 2. Figures 35 to 38 As shown, the first polysilicon layer 3 is obtained by solid phase epitaxy of the first amorphous silicon layer 82 and the second amorphous silicon layer 87 covering the periphery of the active pillar 2 at high temperature; at the same time, the impurities in the amorphous silicon layer can diffuse to the initial active pillar 85 to form the active pillar 2. This can replace the high-energy and high-dose ion implantation method of the drain of the vertical junctionless transistor in the related art, which can help protect the active pillar 2 from being amorphized and ensure the normal operation of the semiconductor structure. It can be understood that the first polysilicon layer 3 is obtained by solid phase epitaxy using the active pillar 2 (single crystal silicon) as a template, so the properties of the first polysilicon layer 3 are close to those of the active pillar 2.

[0085] Moreover, in the present application, the first polysilicon layer 3 is obtained by solid phase epitaxy of the amorphous silicon layer, which can have properties such as lower resistance and higher molar mobility.

[0086] It should be noted that the annealing temperature is less than 1000 degrees Celsius. Specifically, the annealing temperature is not less than 700 degrees Celsius and less than 1000 degrees Celsius. When the annealing temperature is within this range, the first amorphous silicon layer 82 and the second amorphous silicon layer 87 covering the periphery of the active pillar 2 can be prevented from changing from a solid phase epitaxial growth mode to a polycrystalline growth mode in vivo, thereby ensuring the performance of the first polycrystalline silicon layer 3.

[0087] Optionally, the entire substrate 1 is annealed so that the first amorphous silicon layer 82 and the second amorphous silicon layer 87 covering the surface of the active pillar 2 together form the first polysilicon layer 3, further comprising:

[0088] The entire substrate 1 is annealed, and the second amorphous silicon layer 87 covering the surface of the second isolation structure 86 is formed into a second polysilicon layer 88 .

[0089] In this embodiment, Figures 35 to 38 As shown, the second amorphous silicon layer 87 covering the surface of the second isolation structure 86 forms a second polysilicon layer 88, and the second polysilicon layer 88 is grown using the second isolation structure 86 (materials such as silicon dioxide) as a template. Since the second isolation structure 86 is non-single-crystal silicon, the second amorphous silicon layer 88 in contact with the second isolation structure 86 is in-vivo polycrystalline growth during annealing. Compared with the first polysilicon layer 3 in contact with the active pillar 2 of single-crystal silicon, the performance of the second polysilicon layer 88 is poor, such as large leakage, and the second polysilicon layer 88 needs to be removed later.

[0090] Optionally, the entire substrate 1 is annealed so that the first amorphous silicon layer 82 and the second amorphous silicon layer 87 covering the periphery of the active pillar 2 together form a first polycrystalline silicon layer 3, and the impurities in the amorphous silicon layer are diffused to the initial active pillar 85 to form the active pillar 2, and the first polycrystalline silicon layer 3 on the periphery of the drain region 21 and the source region 23 of the active pillar 2 is protected, and the first polycrystalline silicon layer 3 on the periphery of the channel region 22 is oxidized, before obtaining the gate insulating layer 4, it also includes: removing the second polycrystalline silicon layer 88.

[0091] In this embodiment, Fig.39 is a schematic cross-sectional view along the AA direction obtained after removing the second polysilicon layer 88; Fig.40 is a schematic cross-sectional view along the BB direction obtained after removing the second polysilicon layer 88; Fig.41 is a schematic cross-sectional view along the CC direction obtained after removing the second polysilicon layer 88; Fig.42 It is a schematic cross-sectional view along the DD direction obtained after the second polysilicon layer 88 is removed.

[0092] It should be noted that the second polysilicon layer 88 is removed by selective etching, and the first polysilicon layer 3 is retained.

[0093] Optionally, after removing the second polysilicon layer 88, protecting the first polysilicon layer 3 at the periphery of the drain region 21 and the source region 23 of the active pillar 2, and oxidizing the first polysilicon layer 3 at the periphery of the channel region 22, before obtaining the gate insulating layer 4, the manufacturing method further includes:

[0094] The bit lines 6 are manufactured on a side of each active pillar 2 close to the substrate 1 , so that the bit lines 6 are arranged at intervals along the first direction and extend along the second direction, and the bit lines 6 and the first isolation structures 7 are arranged alternately along the first direction.

[0095] In this embodiment, Fig.43 A schematic cross-sectional view along the AA direction obtained by manufacturing the bit lines 6 on the side of each active pillar 2 close to the substrate 1, so that the bit lines 6 are arranged at intervals along the first direction and extend along the second direction, and the bit lines 6 and the first isolation structures 7 are arranged alternately along the first direction; Fig.44 A schematic cross-sectional view along the BB direction obtained by manufacturing the bit lines 6 on the side of each active pillar 2 close to the substrate 1, so that the bit lines 6 are arranged at intervals along the first direction and extend along the second direction, and the bit lines 6 and the first isolation structures 7 are arranged alternately along the first direction; Fig.45 A schematic cross-sectional view along the CC direction obtained after manufacturing the bit lines 6 on the side of each active pillar 2 close to the substrate 1, so that the bit lines 6 are arranged at intervals along the first direction and extend along the second direction, and the bit lines 6 and the first isolation structures 7 are arranged alternately along the first direction; Fig.46 A schematic cross-sectional view along the DD direction is obtained after manufacturing the bit lines 6 on the side of each active pillar 2 close to the substrate 1, so that the bit lines 6 are arranged at intervals along the first direction and extend along the second direction, and the bit lines 6 and the first isolation structures 7 are arranged alternately along the first direction.

[0096] Optionally, before manufacturing the bit line 6 on the side of each active pillar 2 close to the substrate 1, the manufacturing method further includes:

[0097] An initial first dielectric layer is manufactured, and the initial first dielectric layer covers the entire surface of the substrate.

[0098] The initial first dielectric layer on the upper surface of the second isolation structure 86 and the bottom of the second trench 84 is removed to obtain a first dielectric layer 91 covering the second isolation structure 86 and the sidewalls of the second trench 84 .

[0099] In this embodiment, reference Figure 43 to Figure 46 The first dielectric layer 91 can protect the active pillar 2 from being etched when manufacturing the bit line 6. Specifically, the material of the first dielectric layer 91 can be silicon nitride.

[0100] Optionally, in step S12, the first polysilicon layer 3 at the periphery of the drain region 21 and the source region 23 of the active pillar 2 is protected, and the first polysilicon layer 3 at the periphery of the channel region 22 is oxidized to obtain a gate insulating layer 4, wherein the doping concentration of the first polysilicon layer 3 is higher than the doping concentration of the channel region 22, including:

[0101] The first dielectric layer 91 is removed, and a second dielectric layer 92 is manufactured to cover the sidewalls of the second isolation structure 86 and the surface of the second trench 84 ; and a third dielectric layer 93 is manufactured so that the third dielectric layer 93 fills the second trench 84 .

[0102] The second isolation structure 86 on the upper surface of the active pillar 2 is removed to expose the upper surface of the active pillar 2 .

[0103] The second dielectric layer 92 located at the periphery of the source region 23 is removed, and the material of the third dielectric layer 93 is filled at the periphery of the source region 23 to form a fourth dielectric layer 94 .

[0104] The second dielectric layer 92 located at the periphery of the channel region 22 is removed, and the first polysilicon layer 3 at the periphery of the channel region 22 is oxidized to obtain a gate insulating layer 4 .

[0105] In this embodiment, Fig.47 To remove the first dielectric layer 91, a second dielectric layer 92 is manufactured to cover the sidewalls of the second isolation structure 86 and the surface of the second trench 84; a third dielectric layer 93 is manufactured, so that the third dielectric layer 93 fills the second trench 84, and a cross-sectional schematic diagram along the AA direction is shown; Fig.48 To remove the first dielectric layer 91, a second dielectric layer 92 is manufactured to cover the sidewalls of the second isolation structure 86 and the surface of the second trench 84; a third dielectric layer 93 is manufactured so that the third dielectric layer 93 fills the second trench 84, a cross-sectional schematic diagram along the BB direction; Fig.49 To remove the first dielectric layer 91, a second dielectric layer 92 is manufactured to cover the sidewalls of the second isolation structure 86 and the surface of the second trench 84; a third dielectric layer 93 is manufactured, so that the third dielectric layer 93 fills the second trench 84, and a cross-sectional schematic diagram along the CC direction is shown; Fig.50 To remove the first dielectric layer 91, a second dielectric layer 92 is manufactured to cover the sidewalls of the second isolation structure 86 and the surface of the second trench 84; a third dielectric layer 93 is manufactured so that the third dielectric layer 93 fills the second trench 84, as shown in the cross-sectional view along the DD direction. Figures 47 to 50 It can be seen that the material of the second dielectric layer 92 is different from the material of the third dielectric layer 93, so as to facilitate the subsequent use of selective etching to manufacture the gate insulating layer 4 and the word line 5. Specifically, the material of the second dielectric layer 92 can be silicon dioxide, and the material of the third dielectric layer 93 can be silicon nitride; or, the material of the second dielectric layer 92 can be silicon nitride, and the third dielectric layer 93 can be silicon dioxide.

[0106] Fig.51 A schematic cross-sectional view along the AA direction obtained after removing the second isolation structure 86 on the upper surface of the active pillar 2 to expose the upper surface of the active pillar 2; Fig.52 A schematic cross-sectional view along the CC direction after removing the second isolation structure 86 on the upper surface of the active pillar 2 to expose the upper surface of the active pillar 2. Fig.51 and Fig.52 When the second isolation structure 86 on the upper surface of the active pillar 2 is removed, the second dielectric layer 92 and the third dielectric layer 93 on the same layer as the second isolation structure 86 on the upper surface of the active pillar 2 are also removed.

[0107] Fig.53 It is a schematic cross-sectional view along the AA direction obtained after removing the second dielectric layer 92 located at the periphery of the source region 23; Fig.54 is a schematic cross-sectional view along the BB direction obtained after removing the second dielectric layer 92 located at the periphery of the source region 23; Fig.55 FIG. 2 is a schematic cross-sectional view taken along the CC direction after removing the second dielectric layer 92 located at the periphery of the source region 23. Fig.54 When the second dielectric layer 92 at the periphery of the source region 23 is removed, the second isolation structure 86 disposed at the periphery of the source region 23 is also removed.

[0108] Fig.56 A schematic cross-sectional view along the AA direction obtained after the material of the third dielectric layer 93 is filled at the periphery of the source region 23 to form a fourth dielectric layer 94; Fig.57 A schematic cross-sectional view along the BB direction obtained after the material of the third dielectric layer 93 is filled at the periphery of the source region 23 to form a fourth dielectric layer 94; Fig.58 It is a schematic cross-sectional view along the CC direction obtained after the material of the third dielectric layer 93 is filled at the periphery of the source region 23 to form a fourth dielectric layer 94 .

[0109] Fig.59 It is a schematic cross-sectional view along the AA direction obtained after removing the second dielectric layer 92 located at the periphery of the channel region 22; Fig.60 It is a schematic cross-sectional view along the BB direction obtained after removing the second dielectric layer 92 located at the periphery of the channel region 22; Fig.61 It is a schematic cross-sectional view along the CC direction obtained after the second dielectric layer 92 located at the periphery of the channel region 22 is removed.

[0110] Fig.62 A schematic cross-sectional view along the AA direction obtained after the first polysilicon layer 3 at the periphery of the channel region 22 is oxidized to obtain a gate insulating layer 4; Fig.63 A schematic cross-sectional view along the CC direction is obtained after the first polysilicon layer 3 at the periphery of the channel region 22 is oxidized to obtain the gate insulating layer 4.

[0111] Optionally, after step 12, the manufacturing method further includes:

[0112] The word lines 5 are manufactured on the periphery of the gate insulating layer 4 , so that the word lines 5 extend along the first direction and are arranged at intervals along the second direction.

[0113] A fifth dielectric layer 95 is formed in the gap above the word line 5 .

[0114] In this embodiment, Fig.64 is a schematic cross-sectional view along the AA direction obtained after the word line 5 is manufactured on the periphery of the gate insulating layer 4; Fig.65 is a schematic cross-sectional view along the BB direction obtained after the word line 5 is manufactured on the periphery of the gate insulating layer 4; Fig.66 It is a schematic cross-sectional view along the CC direction obtained after the word line 5 is manufactured on the periphery of the gate insulating layer 4 .

[0115] Figures 2 to 5 Schematic diagrams of cross-sections in various directions obtained after the fifth dielectric layer 95 is manufactured in the gap above the word line 5 .

[0116] By applying the embodiments of the present application, at least the following beneficial effects can be achieved:

[0117] By setting a first polysilicon layer at least on the periphery of the drain region, the first polysilicon layer is obtained by solid phase epitaxy of an amorphous silicon layer covering the surface of the active column, and the doping impurities in the drain region are derived from the amorphous silicon layer, instead of the method of performing high-energy and high-dose ion implantation on the drain region of the vertical junctionless transistor in the related art, it is possible to avoid the difficult-to-repair damage to the active column caused by the high-dose ion implantation, thereby helping to protect the active column from being amorphized, and further helping to ensure the normal operation of the semiconductor structure.

[0118] Those skilled in the art will appreciate that the various operations, methods, steps, measures, and schemes in the processes discussed in this application may be alternated, altered, combined, or deleted. Further, other steps, measures, and schemes in the various operations, methods, and processes discussed in this application may also be alternated, altered, rearranged, decomposed, combined, or deleted. Further, the steps, measures, and schemes in the prior art that are similar to those disclosed in this application may also be alternated, altered, rearranged, decomposed, combined, or deleted.

[0119] In the description of the present application, the directions or positional relationships indicated by words such as "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the exemplary directions or positional relationships shown in the accompanying drawings. They are for the convenience of describing or simplifying the description of the embodiments of the present application, and do not indicate or imply that the referred device or component must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they should not be understood as limitations on the present application.

[0120] The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0121] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0122] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0123] It should be understood that, although the various steps in the flowchart of the accompanying drawings are displayed in sequence according to the indication of the arrows, the order of implementation of these steps is not limited to the order indicated by the arrows. Unless there is a clear description herein, in some implementation scenarios of the embodiments of the present application, the steps in each process can be performed in other orders according to demand. Moreover, some or all of the steps in each flow chart may include multiple sub-steps or multiple stages based on actual implementation scenarios. Some or all of these sub-steps or stages may be executed at the same time, or may be executed at different times in different scenarios at the execution time, and the execution order of these sub-steps or stages may be flexibly configured according to demand, and the embodiments of the present application do not limit this.

[0124] The above is only a partial implementation method of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the technical concept of the scheme of the present application, other similar implementation methods based on the technical ideas of the present application are also within the protection scope of the embodiments of the present application.

Claims

1. A semiconductor structure, characterized in that: include: A plurality of active pillars are arranged in an array on one side of the substrate, wherein the active pillars include a drain region, a channel region and a source region which are sequentially away from the substrate; The first polysilicon layer is at least arranged at the periphery of the drain region. The first polysilicon layer is obtained by solid phase epitaxy of an amorphous silicon layer covering the surface of the active column. The doping impurities of the drain region originate from the amorphous silicon layer.

2. The semiconductor structure according to claim 1, characterized in that: The first polysilicon layer is arranged at the periphery of the drain region and the source region, and the doping concentrations of the drain region and the source region are both higher than the doping concentration of the channel region.

3. The semiconductor structure according to claim 1, characterized in that: It also includes a gate insulating layer and a gate sequentially arranged at the periphery of the channel region; In a plane parallel to the substrate, a size of the gate insulating layer is not smaller than a size of the first polysilicon layer.

4. The semiconductor structure according to claim 3, characterized in that: Also includes: Multiple word lines; The gates arranged in the same row along the first direction are connected to form a word line. A plurality of word lines extend along the first direction and are arranged at intervals along the second direction. The first direction and the second direction have a designed angle and are both parallel to the substrate.

5. The semiconductor structure according to claim 1, characterized in that: Also includes: A plurality of bit lines and a plurality of first isolation structures, wherein the plurality of bit lines and the plurality of first isolation structures are arranged at intervals along a first direction and extend along a second direction; The bit line is arranged on a side of the active pillar close to the substrate; The bit lines and the first isolation structures are alternately arranged along a first direction, and a bottom surface of the first isolation structure is closer to a bottom surface of the substrate than a bottom surface of the bit lines.

6. A memory, characterized in that: The semiconductor structure comprises any one of claims 1 to 5.

7. An electronic device, characterized in that: Comprising the memory as claimed in claim 6.

8. A method for manufacturing a semiconductor structure, characterized in that: include: Manufacturing initial active pillars arranged in an array and an amorphous silicon layer disposed on the surface of the active pillars on one side of the substrate; The amorphous silicon layer is annealed so that the amorphous silicon layer covering the surface of the initial active pillar forms a first polysilicon layer, and impurities in the amorphous silicon layer diffuse into the initial active pillar to form an active pillar.

9. The manufacturing method according to claim 8, characterized in that: After annealing the amorphous silicon layer so that the amorphous silicon layer covering the surface of the active pillar forms a first polysilicon layer, and allowing impurities in the amorphous silicon layer to diffuse into the initial active pillar to form an active pillar, the method further includes: The first polysilicon layer around the drain region and the source region of the active column is protected, and the first polysilicon layer around the channel region is oxidized to obtain a gate insulating layer. The doping concentration of the drain region and the source region is higher than that of the channel region.

10. The manufacturing method according to claim 8, characterized in that: Manufacturing initial active pillars arranged in an array and an amorphous silicon layer disposed on the surface of the active pillars on one side of a substrate, comprising: Manufacturing first grooves arranged at intervals along a first direction and extending along a second direction on one side of the substrate; the first direction and the second direction have a designed angle and are both parallel to the substrate; Conformally manufacturing an initial first amorphous silicon layer in the first trench so that the initial first amorphous silicon layer covers the entire surface of the substrate; removing the initial first amorphous silicon layer at the bottom of the first trench, and manufacturing an isolation layer covering the remaining initial first amorphous silicon layer and filling the first trench; Manufacturing second trenches extending in the first direction and arranged at intervals in the second direction, obtaining initial active pillars arranged in an array, a first amorphous silicon layer formed by the initial first amorphous silicon layer, and a second isolation structure formed by the isolation layer; A second amorphous silicon layer is manufactured so that the second amorphous silicon layer covers the surface of the second isolation structure and the second trench; the amorphous silicon layer includes a first amorphous silicon layer and a second amorphous silicon layer covering the surface of the initial active pillar.

11. The manufacturing method according to claim 10, characterized in that: Annealing the amorphous silicon layer so that the amorphous silicon layer covering the surface of the active pillar forms a first polysilicon layer, and allowing impurities in the amorphous silicon layer to diffuse into the initial active pillar to form an active pillar, comprising: The entire substrate is annealed so that the first amorphous silicon layer and the second amorphous silicon layer covering the surface of the active pillar jointly form a first polysilicon layer.

12. The manufacturing method according to claim 11, characterized in that: Annealing the entire substrate so that the first amorphous silicon layer and the second amorphous silicon layer covering the surface of the active pillars together form a first polysilicon layer, further comprising: Performing annealing treatment on the entire substrate, and at the same time causing the second amorphous silicon layer covering the surface of the second isolation structure to form a second polysilicon layer; And, after annealing the amorphous silicon layer, protecting the first polysilicon layer around the drain region and the source region of the active pillar, oxidizing the first polysilicon layer around the channel region, and before obtaining the gate insulating layer, the method further includes: The second polysilicon layer is removed.

13. The manufacturing method according to claim 12, characterized in that: Manufacturing first grooves arranged at intervals along a first direction and extending along a second direction on one side of a substrate, comprising: Manufacturing initial first grooves arranged at intervals along a first direction and extending along a second direction on one side of the substrate; A first isolation structure is manufactured in the initial first trench to obtain a first trench.

14. The manufacturing method according to claim 13, characterized in that: After removing the second polysilicon layer, protecting the first polysilicon layer around the drain region and the source region, oxidizing the first polysilicon layer around the channel region, and before obtaining the gate insulating layer, the method further includes: A bit line is manufactured on a side of each active pillar close to the substrate, so that each bit line is arranged at intervals along a first direction and extends along a second direction, and the bit line and the first isolation structure are alternately arranged along the first direction.

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