Three-dimensional memory, manufacturing method thereof and electronic equipment

Abstract

The invention provides a three-dimensional memory, a manufacturing method thereof and electronic equipment. The three-dimensional memory comprises multiple layers of memory cells stacked along a third direction, each layer of memory cells comprises a first column of memory cells extending along a second direction and a second column of memory cells extending along the second direction, and the first column of memory cells and the second column of memory cells are adjacent and arranged along a first direction. The plurality of storage units of the first column of storage units share one bit line extending along the second direction, and the plurality of storage units of the second column of storage units share one bit line extending along the second direction; the storage unit comprises a transistor and a capacitor; the capacitor comprises a first electrode and a second electrode; a word line extending along a third direction; each transistor is provided with a channel region on at least one side of the word line connected with the transistor along the second direction, and the transistor is electrically connected with the first electrode. The manufacturing process of the device is simple.

Description

Technical Field

[0001] The present application relates to but is not limited to semiconductor technology, and in particular to a three-dimensional memory and a manufacturing method thereof, and an electronic device. Background Art

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and numbers of devices contained in a single chip are increasing accordingly, so that any slight difference in process production may affect device performance.

[0003] In order to reduce the cost of products as much as possible, people hope to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's needs for current products. Summary of the invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of protection of this application.

[0005] In one aspect, an exemplary embodiment of the present application provides a three-dimensional memory, comprising:

[0006] A plurality of memory cells stacked along a third direction, each layer of memory cells comprising a first column of memory cells extending along a second direction and a second column of memory cells extending along the second direction, the first column of memory cells and the second column of memory cells being adjacent and arranged along the first direction, a plurality of memory cells in the first column of memory cells sharing a bit line extending along the second direction, and a plurality of memory cells in the second column of memory cells sharing a bit line extending along the second direction;

[0007] The memory cell includes a transistor and a capacitor; the capacitor includes a first electrode and a second electrode;

[0008] The word line extends along the third direction;

[0009] Each of the transistors has a channel region only on at least one side of the word line connected thereto along the second direction;

[0010] The transistor is electrically connected to the first electrode, and the first direction intersects with the second direction and is perpendicular to the third direction.

[0011] In an exemplary embodiment, each of the transistors has a channel region only on two sides of the word line to which it is connected along the second direction.

[0012] In an exemplary embodiment, a bit line shared by the first column of memory cells and a bit line shared by the second column of memory cells are separated by an isolation portion, and the first column of memory cells and the second column of memory cells are symmetrical with respect to the isolation portion in the first direction.

[0013] In an exemplary embodiment, each of the transistors further includes a gate, which is a part of the corresponding word line, and a gate insulating layer is provided between the gate and the channel region; and each of the transistors of each memory cell stacked in the third direction shares a word line.

[0014] In an exemplary embodiment, in the third direction, the channel regions are disposed at intervals and the gate insulating layer is disposed continuously.

[0015] In an exemplary embodiment, each of the transistors further includes a first source / drain and a second source / drain located on both sides of the word line connected thereto in the first direction.

[0016] In an exemplary embodiment, the first source / drain, the second source / drain, the first electrode, and the bit line include the same material.

[0017] In an exemplary embodiment, the second electrode surrounds the first electrode.

[0018] In an exemplary embodiment, the capacitor includes a dielectric layer between the first electrode and the second electrode, and the dielectric layers of the capacitors of the respective storage cells are interconnected into an integrated structure.

[0019] In an exemplary embodiment, the second electrodes of the capacitors of each storage unit are connected to each other in an integrated structure.

[0020] In an exemplary embodiment, a conductive layer is provided between the plurality of second electrodes, a supporting portion is provided on a side of the capacitor away from the transistor, and the conductive layer is connected to the supporting portion.

[0021] In an exemplary embodiment, a plurality of second electrodes are electrically connected through the conductive layer, and the second electrodes and the conductive layer are made of different materials.

[0022] In another aspect, an exemplary embodiment of the present application provides a method for manufacturing a three-dimensional memory, comprising the following steps:

[0023] Alternatingly forming sacrificial layers and semiconductor layers along a third direction to form a stacked structure;

[0024] A plurality of first extension portions extending along the first direction and arranged at intervals along the second direction and a second extension portion extending along the second direction are formed in each of the semiconductor layers, each of the first extension portions is divided into a first sub-extension portion and a second sub-extension portion by the second extension portion in the first direction, and the first direction intersects the second direction and is perpendicular to the third direction;

[0025] An isolation region and bit line preset regions located on both sides of the isolation region are provided in the second extension portion;

[0026] In the first sub-extension portion, a second source / drain preset region, a word line preset region, a first source / drain preset region and a capacitor preset region are sequentially arranged along a first direction on a side of the bit line preset region away from the isolation region;

[0027] Forming a support portion on a side of the capacitor preset region away from the first source / drain preset region;

[0028] Removing the sacrificial layer in the preset area of ​​the capacitor to expose the semiconductor layers in the preset area of ​​the capacitor to form a first electrode of the capacitor;

[0029] forming a bit line in the bit line preset area;

[0030] In the word line preset area, a word line through hole penetrating the stacked structure is formed;

[0031] An insulating film and a conductive film are sequentially deposited around the inner peripheral wall of each word line through hole to form a gate insulating layer and a word line;

[0032] A channel region is formed in a region of the semiconductor layer located on at least one side of the word line along the second direction.

[0033] In an exemplary embodiment, the manufacturing method further comprises:

[0034] Depositing a dielectric film around the exposed first electrode and completely covering the first electrode to form a dielectric layer;

[0035] A conductive film is deposited around the dielectric layer and completely covers the dielectric layer to form a second electrode.

[0036] In an exemplary embodiment, forming a bit line includes:

[0037] Removing the stacked structure in the isolation region to form a groove penetrating the stacked structure;

[0038] The semiconductor layer in the predetermined bit line region is doped by means of the formed trench to form the bit line.

[0039] On the other hand, an exemplary embodiment of the present application provides an electronic device, comprising any of the memories described above, for example, the memory may be a DRAM memory.

[0040] In an exemplary embodiment, the electronic device includes a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power source.

[0041] The method of the present application adopts a method for manufacturing channels on both sides of the gate when manufacturing the transistor part, and only requires a vertical etcher to fill. This method greatly reduces the difficulty of the etching process and the subsequent filling process, and widens the process window.

[0042] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by implementing the present application. Other advantages of the present application can be realized and obtained by the schemes described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0044] Figure 1A A three-dimensional schematic diagram of a three-dimensional memory provided for an exemplary embodiment of the present application;

[0045] Figure 1B For along Figure 1A A schematic cross-sectional view taken along the C1 plane;

[0046] Figure 2A A three-dimensional schematic diagram of a three-dimensional memory provided for an exemplary embodiment of the present application;

[0047] Figure 2B For along Figure 2A A schematic cross-sectional view taken along the C2 plane;

[0048] Figure 3A A three-dimensional schematic diagram of a three-dimensional memory provided for an exemplary embodiment of the present application;

[0049] Figure 3B For along Figure 3A A schematic cross-sectional view taken along the C3 plane;

[0050] Figure 4A A three-dimensional schematic diagram of a three-dimensional memory provided for an exemplary embodiment of the present application;

[0051] Figure 4B For along Figure 4AA schematic cross-sectional view taken along the C4 plane;

[0052] Figure 5A A three-dimensional schematic diagram of a three-dimensional memory provided for an exemplary embodiment of the present application;

[0053] Figure 5B For along Figure 5A A schematic cross-sectional view taken at the C5 plane;

[0054] Fig. 6A A three-dimensional schematic diagram of a three-dimensional memory provided for an exemplary embodiment of the present application;

[0055] Figure 6B For along Fig. 6A A schematic cross-sectional view taken along the C6 plane;

[0056] Fig. 7A A three-dimensional schematic diagram of a three-dimensional memory provided for an exemplary embodiment of the present application;

[0057] Figure 7B For along Fig. 7A A schematic cross-sectional view taken at the C7 / C8 plane;

[0058] Fig. 8A A three-dimensional schematic diagram of a method for manufacturing a three-dimensional memory provided in an exemplary embodiment of the present application after forming a stacked structure including a sacrificial layer and a semiconductor layer;

[0059] Figure 8B for Fig. 8A A schematic vertical cross-sectional view of the structure shown taken along the cross-sectional line BB';

[0060] Fig.9A A three-dimensional schematic diagram of a method for manufacturing a three-dimensional memory after forming a stacked structure with a preset pattern provided in an exemplary embodiment of the present application;

[0061] Fig. 9B for Fig.9A A schematic horizontal cross-sectional view of the structure shown along the cross-sectional line AA';

[0062] Fig. 10A A three-dimensional schematic diagram of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in an exemplary embodiment of the present application;

[0063] Fig. 10B for Fig. 10A A schematic horizontal cross-sectional view of the structure shown along the cross-sectional line AA';

[0064] Fig.11AA three-dimensional schematic diagram of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in an exemplary embodiment of the present application;

[0065] Fig. 11B for Fig.11A A schematic horizontal cross-sectional view of the structure shown along the cross-sectional line AA';

[0066] Fig. 12A A three-dimensional schematic diagram of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in an exemplary embodiment of the present application;

[0067] Fig. 12B for Fig. 12A A schematic vertical cross-sectional view of the structure shown taken along the cross-sectional line BB';

[0068] Fig.13A A three-dimensional schematic diagram of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in an exemplary embodiment of the present application;

[0069] Fig. 13B A three-dimensional schematic diagram of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in an exemplary embodiment of the present application;

[0070] Fig.14A A three-dimensional schematic diagram of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in an exemplary embodiment of the present application;

[0071] Fig. 14B A three-dimensional schematic diagram of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in an exemplary embodiment of the present application;

[0072] Fig. 14C A three-dimensional schematic diagram of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in an exemplary embodiment of the present application;

[0073] Fig.15A A three-dimensional schematic diagram of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in an exemplary embodiment of the present application;

[0074] Fig. 15B A three-dimensional schematic diagram of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in an exemplary embodiment of the present application;

[0075] Fig. 15C A three-dimensional schematic diagram of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in an exemplary embodiment of the present application;

[0076] Fig.16A A three-dimensional schematic diagram of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in an exemplary embodiment of the present application;

[0077] Fig. 16B A three-dimensional schematic diagram of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in an exemplary embodiment of the present application; and

[0078] Fig. 16C A three-dimensional schematic diagram of an intermediate product obtained in an intermediate step of a method for manufacturing a three-dimensional memory provided in an exemplary embodiment of the present application.

[0079] Description of reference numerals: 1-laminated structure; 10-substrate; 20-sacrificial layer;

[0080] 30-semiconductor layer; 31-first extension portion; 32-second extension portion; 40-hard mask layer; 50-first source / drain; 60-second source / drain; 61-first electrode; 62-dielectric layer; 63-second electrode;

[0081] 64-conductive layer; 70-supporting portion; 80-bit line;

[0082] 90-word line; 91-gate insulating layer; 92-channel region;

[0083] 93 - gate; 100 - isolation region; 200 - bit line preset region; 300 - second source / drain preset region; 311 - first sub-extension portion; 312 - second sub-extension portion; 400 - word line preset region; 500 - first source / drain preset region; 600 - capacitor preset region; 700 - isolation portion. DETAILED DESCRIPTION

[0084] In order to make the purpose, technical solution and advantages of the present application more clear, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other arbitrarily without conflict.

[0085] The embodiments herein can be implemented in a plurality of different forms. A person skilled in the art can easily understand the fact that the implementation and content can be transformed into various forms without departing from the purpose and scope of the present application. Therefore, the present application should not be interpreted as being limited to the contents recorded in the following embodiments. In the absence of conflict, the embodiments in the present application and the features in the embodiments can be combined arbitrarily with each other.

[0086] The size and proportional relationship between the various film layers or components in the drawings of this application can be used as a reference in the actual process, which is an implementation method with better technical effects, but is not limited to this. For example: the width-to-length ratio of the semiconductor layer, the thickness and spacing of each film layer can be adjusted according to actual needs. The drawings described in this application are only structural schematic diagrams, and one method of this application is not limited to the shapes or values ​​shown in the drawings.

[0087] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation on this application. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification and can be appropriately replaced according to the situation.

[0088] In this specification, unless otherwise clearly specified and limited, the terms "disposed" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For those skilled in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0089] In the description of the present application, ordinal numbers such as "first" and "second" are provided to avoid confusion among constituent elements rather than to limit the quantity.

[0090] In this specification, "film" and "layer" may be interchanged. For example, "metal layer" may be replaced with "metal film" in some cases.

[0091] In recent years, with the rise of integrated circuits in 3D devices, capacitors and transistors are often stacked to improve integration. However, the inventors of this application have found that since 3D memory devices often use a gate-surround or channel-surround structure in the transistor part, the manufacturing process is complex and integration is difficult.

[0092] Therefore, an exemplary embodiment of the present application provides a three-dimensional memory, comprising a plurality of layers of memory cells stacked along a third direction, each layer of memory cells comprising a first column of memory cells extending along a second direction and a second column of memory cells extending along the second direction, the first column of memory cells and the second column of memory cells being adjacent and arranged along the first direction, a plurality of memory cells in the first column of memory cells sharing a bit line extending along the second direction, and a plurality of memory cells in the second column of memory cells sharing a bit line extending along the second direction; the memory cell comprising a transistor and a capacitor; the capacitor comprising a first electrode and a second electrode; a word line extending along the third direction; each of the transistors having a channel region only on at least one side of the word line to which it is connected along the second direction, the transistor being electrically connected to the first electrode, the first direction intersecting with the second direction and both being perpendicular to the third direction.

[0093] In an exemplary embodiment, each of the transistors has a channel region only on two sides of the word line to which it is connected along the second direction.

[0094] In an exemplary embodiment, a bit line shared by the first column of memory cells and a bit line shared by the second column of memory cells are separated by an isolation portion, and the first column of memory cells and the second column of memory cells are symmetrical with respect to the isolation portion in the first direction.

[0095] As used in this application, the term "first direction" X is defined as a direction perpendicular to the direction in which the bit lines extend; the term "second direction" Y is defined as a direction parallel to the direction in which the bit lines extend; the term "third direction" Z is defined as a direction perpendicular to the plane in which the substrate is located, that is, a direction parallel to the direction in which the word lines extend; the plane formed by the first direction X and the second direction Y is parallel to the substrate. The "first direction" X, the "second direction" Y, and the "third direction" Z can be as follows Figures 1A to 7B As shown in the following table.

[0096] As used in this application, the term "an integrated structure" may refer to the fact that there is no obvious boundary interface such as a fault or gap between A and B in the microstructure. Generally, a film layer patterned to form a connection is an integrated structure. For example, A and B are formed into a film layer using the same material and are simultaneously formed into a structure having a connection relationship through the same patterning process.

[0097] like Figures 1A to 7BAs shown, the three-dimensional memory may include multiple layers of memory cells stacked along a third direction, each layer of memory cells includes a first column of memory cells extending along a second direction Y and a second column of memory cells extending along the second direction Y, the first column of memory cells and the second column of memory cells are adjacent and arranged along the first direction X, a plurality of memory cells in the first column of memory cells share a bit line 80 extending along the second direction Y, and a plurality of memory cells in the second column of memory cells share a bit line 80 extending along the second direction Y. Each memory cell may include a transistor and a capacitor. The transistors vertically stacked in the third direction Z share a word line 90 extending along the third direction Z.

[0098] In an exemplary embodiment, Figure 1B The isolation part 700 and two columns of memory cells located on both sides of the isolation part 700 along the first direction X are shown. Each column of memory cells includes a plurality of transistors that share a bit line 80 extending along the second direction Y. The second source / drain 60 of each transistor is connected to the bit line 80, Figure 1B The dotted line II-II' schematically shows the approximate boundary between the bit line 80 and the second source / drain 60. Each transistor may further include a word line 90 and a first source / drain 50 and a second source / drain 60 located on both sides of the word line 90 along the first direction X. Each transistor may further include a capacitor, each capacitor may include a first electrode 61, a second electrode 63 surrounding the first electrode 61, and a dielectric layer 62 located between and separating the first electrode and the second electrode, the first electrode 61 being connected to the first source / drain 50. Figure 1B The dotted line II′ schematically shows the approximate boundary between the first electrode 61 and the first source / drain 50 .

[0099] In an exemplary embodiment, a silicide is formed on the surface of the bit line 80 , thereby further reducing the contact resistance of the bit line 80 .

[0100] Figure 1B It is also shown that the bit line 80 shared by the first column of memory cells and the bit line 80 shared by the second column of memory cells are separated by an isolation portion 700, and the first column of memory cells and the second column of memory cells are symmetrical with respect to the isolation portion in the first direction. The present application greatly improves the density of transistors per unit area and reduces manufacturing costs by making the overall structure of the device symmetrical.

[0101] Figure 1BIt is also shown that a conductive layer 64 is provided in the space surrounded by the second electrode 63 of the capacitor, and a support portion 70 is provided on the side of the capacitor away from the transistor, and the conductive layer 64 is connected to the support portion 70. The support portion 70 can be used to support the capacitor to prevent the capacitor from being disconnected from the transistor, and can also support the conductive layer 64 to prevent the conductive layer 64 from being separated from the second electrode 63.

[0102] Special References Figure 1B , Figure 1B It is clearly shown that the channel region 92 of each transistor is only located on at least one side of the corresponding word line 90 along the second direction Y. The present application forms a channel region only on at least one side of the second direction Y of the word line / gate, and each transistor does not have a channel region structure design on both sides of the word line 90 connected to it along the first direction X, so that only a vertical etcher is required for filling and deposition, which greatly reduces the difficulty of the etching process and the subsequent deposition and filling process, and widens the process window. In addition, channel regions can be formed on both sides of the word line / gate along the second direction, that is, double channels, thereby further increasing the saturation current of the transistor and enhancing the driving force of the device.

[0103] In an exemplary embodiment, the channel region 92 may include a single crystalline silicon material.

[0104] Figure 1B It is also shown that each transistor may further include a gate 93 , wherein the gate 93 is a part of the corresponding word line 90 , and a gate insulating layer 91 may be provided between the gate 93 and the channel region 92 .

[0105] Special References Figure 6B , Figure 6B It is clearly shown that in the third direction Z, the channel regions 92 are arranged at intervals and the gate insulating layer 91 is arranged continuously. In the present application, the channel regions are arranged at intervals in the extension direction of the word lines, so that parasitic MOS is not introduced and the stability of the device is improved.

[0106] As used in this application, the term "spacer setting" or "disconnection setting" can be a physical structural disconnection to achieve separation, such as with the help of an isolation layer formed by an insulating material, or a disconnection in electrical properties, for example, the conductivity of the semiconductor region between two channel regions is approximately insulating.

[0107] In an exemplary embodiment, Fig.13A As shown, the dielectric layers 62 of the capacitors of the storage cells may be interconnected to form an integrated structure.

[0108] In an exemplary embodiment, Fig. 13B As shown, the second electrodes 63 of the capacitors of the storage units may be connected to each other to form an integrated structure.

[0109] In an exemplary embodiment, the first source / drain 50 , the second source / drain 60 , the first electrode 61 , and the bit line 80 may all be formed of the same material.

[0110] In an exemplary embodiment, the first source / drain 50 and the second source / drain 60 may be formed by doping ions with the same semiconductor material, for example, a conductor structure formed by doping Si with ions.

[0111] In an exemplary embodiment, the first source / drain 50 and the second source / drain 60 of the same transistor may be located in the same conductive layer. It can be understood that the first source / drain 50 and the second source / drain 60 are located in the same metal layer and are formed by patterning a film layer.

[0112] Although first and second source / drain references are used herein to designate two separate and distinct source / drain regions, it is not intended that the source / drain regions referred to as the "first" and / or "second" source / drain regions have a unique meaning. It is intended that only one of the source / drain regions is connected to the bit line and the other may be connected to the first electrode / lower electrode of the capacitor.

[0113] In an exemplary embodiment, the first source / drain region 50 and the second source / drain region 60 are independent of each other. In an exemplary embodiment, one of the first source / drain region 50 and the second source / drain region 60 is the source of the transistor, and the other is the drain of the transistor.

[0114] The technical solution of the present application is further explained below through the manufacturing process of the three-dimensional memory of the exemplary embodiment of the present application. The "patterning process" mentioned in the exemplary embodiment includes deposition of film layers, coating of photoresist, mask exposure, development, etching, stripping of photoresist and other processes, which are mature manufacturing processes in the relevant technology. The "photolithography process" mentioned in the exemplary embodiment includes coating of film layers, mask exposure and development, which are mature manufacturing processes in the relevant technology. Deposition can adopt known processes such as sputtering, evaporation, chemical vapor deposition, coating can adopt known coating processes, and etching can adopt known methods, which are not specifically limited here. In the description of the exemplary embodiment, it should be understood that "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or a photolithography process during the entire manufacturing process, the "thin film" can also be called a "layer". If the "thin film" also requires a patterning process or a photolithography process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or the photolithography process contains at least one "pattern".

[0115] In an exemplary embodiment, a manufacturing process of a three-dimensional memory such as a three-dimensional DRAM may include:

[0116] S100: forming a laminated structure.

[0117] An exemplary step may include providing a substrate 10, and alternately depositing a sacrificial layer film and a semiconductor material film on the substrate 10 along a third direction Z to form a stacked structure 1 including a sacrificial layer 20 and a semiconductor layer 30, such as Fig. 8A and 8B As shown. Among them, Fig. 8A A three-dimensional schematic diagram of a method for manufacturing a three-dimensional memory provided in an exemplary embodiment of the present application after forming a stacked structure including a sacrificial layer and a semiconductor layer; Figure 8B for Fig. 8A The structure shown is a schematic vertical cross-sectional view taken along the cross-sectional line BB'.

[0118] In an exemplary embodiment, the sacrificial layer thin film and the semiconductor material thin film may be grown using an epitaxial growth method.

[0119] In an exemplary embodiment, the substrate 10 may be a semiconductor substrate; for example, it may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), at least one III V compound semiconductor material (e.g., a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), at least one II VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In an exemplary embodiment, the substrate 10 may be a single crystal silicon substrate.

[0120] In an exemplary embodiment, the sacrificial layer 20 may be made of SiGe, such as a SiGe single crystal material.

[0121] In an exemplary embodiment, the semiconductor layer 30 may be made of a semiconductor material such as silicon, including single crystal silicon.

[0122] In the present application, a single crystal stacked structure may be formed by epitaxially growing a plurality of SiGe single crystal layers and a plurality of single crystal silicon layers on a single crystal silicon substrate.

[0123] Figure 8B The stacked structure 1 shown in FIG. 1 may include three sacrificial layers 20 and three semiconductor layers 30. In other exemplary embodiments, the stacked structure may further include more or fewer sacrificial layers 20 and semiconductor layers 30 that are alternately arranged.

[0124] In addition, a hard mask layer 40 may be disposed on the top of the stacked structure 1 for use in subsequent patterning processes and will be removed after patterning.

[0125] In an exemplary embodiment, the hard mask layer 40 may be formed of an oxide such as silicon dioxide.

[0126] S200: Patterning the stacked structure.

[0127] An exemplary step may include first transferring a preset pattern to a photoresist layer by a photolithography process using a first mask having a preset pattern (also referred to as a first photomask, not shown); then etching (which may include anisotropic etching and isotropic etching) each sacrificial layer and semiconductor layer of the stacked structure based on the preset pattern, such as Fig.9A and 9B As shown. Among them, Fig.9A A three-dimensional schematic diagram of a method for manufacturing a three-dimensional memory after forming a stacked structure with a preset pattern provided in an exemplary embodiment of the present application; Fig. 9B for Fig.9A The structure shown is a horizontal cross-sectional schematic diagram taken along the section line AA'.

[0128] refer to Fig.9A and 9B The preset pattern may include 4 rows of first extension portions 31 extending along the first direction X and arranged at intervals along the second direction Y, and 1 column of second extension portions 32 extending along the second direction Y. The second extension portions 32 are perpendicular to the first extension portions 31. Both ends of the second extension portions 32 in the second direction Y extend beyond the first extension portions 31 along the second direction Y. The second extension portions 32 divide each row of first extension portions 31 into a first sub-extension portion 311 and a second sub-extension portion 312, and the two sub-extension portions 311 and 312 are symmetrical relative to the second extension portion 32 in the first direction X.

[0129] Continue to refer Fig.9A and 9B , the second extension portion 32 can be divided into an isolation region 100 and two bit line preset regions 200 on both sides of the isolation region 100 along the first direction X. In the region of the first sub-extension portion 311, on the side of the bit line preset region 200 away from the isolation region 100, the second source / drain preset region 300, the word line preset region 400, the first source / drain preset region 500 and the capacitor preset region 600 can be sequentially included along the first direction X, wherein the second source / drain preset region 300, the word line preset region 400 and the first source / drain preset region 500 can together constitute a transistor region.

[0130] Similarly, in the area of ​​the second sub-extension 312, on the side of the bit line preset area 200 away from the isolation area 100 along the direction away from the first direction X, a second source / drain preset area 300, a word line preset area 400, a first source / drain preset area 500 and a capacitor preset area 600 may be sequentially included.

[0131] Continue to refer Fig.9A and 9B A first trench T1 penetrating the stacked structure 1 and terminating at a side of the substrate 10 close to the sacrificial layer 20 is formed between two adjacent sub-extension portions 311 or 312 in the second direction Y. Fig.9A and 9B It is shown that the preset pattern includes 10 first trenches T1 in total, and the dimensions of each first trench T1 in the first direction X and the second direction Y are the same.

[0132] In an exemplary embodiment, Fig.9A and 9B The preset pattern shown is only an example, however, the preset pattern may also be other shapes, for example, the dimensions of each first trench T1 in the first direction X and the second direction Y are not the same; or more rows of first extension portions are included.

[0133] S300: forming a source and a drain.

[0134] Exemplary steps may include performing high-concentration doping in the first source / drain preset region 500 and the second source / drain preset region 300 by ion implantation, plasma implantation, diffusion annealing, etc., thereby forming a conductive region from the semiconductor region, that is, forming a first source / drain 50 and a second source / drain 60.

[0135] S400: forming a support portion.

[0136] Exemplary steps may include filling all first trenches T1 formed in the aforementioned steps with insulating material to form an isolation layer 21; photolithography and etching to remove the stacked structure on one side of the capacitor preset region 600 away from the first source / drain preset region 500 to form two support portion preset regions; depositing insulating material in the two support portion preset regions to form two support portions 70, such as Fig. 10A and 10B As shown. Among them, Fig. 10A A three-dimensional schematic diagram of an intermediate product obtained in an intermediate step (S400) of a method for manufacturing a three-dimensional memory provided in an exemplary embodiment of the present application; Fig. 10B for Fig. 10A The structure shown is a horizontal cross-sectional schematic diagram taken along the section line AA'.

[0137] In an exemplary embodiment, the insulating material used for the isolation layer 21 may be the same material as that used for the sacrificial layer 20, such as GeSi. However, in other exemplary embodiments, the material used for the isolation layer 21 may be other insulating materials.

[0138] In an exemplary embodiment, the insulating material used for the support portion 70 may be SiN, and the deposition method may be low temperature atomic layer deposition.

[0139] S500: forming a capacitor preset area.

[0140] An exemplary step may include removing the isolation layer 21 in the capacitor preset region 600 by photolithography and dry vertical etching, forming a plurality of second trenches T2 penetrating the stacked structure 1 in the capacitor preset region 600 and terminating at a side of the substrate 10 close to the sacrificial layer 20, exposing the capacitor preset region 600 at each semiconductor layer 30, such as Fig.11A and 11B As shown. Among them, Fig.11A A three-dimensional schematic diagram of an intermediate product obtained in an intermediate step (S500) of a method for manufacturing a three-dimensional memory provided in an exemplary embodiment of the present application; Fig. 11B for Fig.11A The structure shown is a horizontal cross-sectional schematic diagram taken along the cross-sectional line AA'.

[0141] S600: exposing the first electrode 61 of the capacitor to be formed.

[0142] An exemplary step may include removing the sacrificial layer 20 between the semiconductor layers 30 adjacent to each other in the third direction Z by lateral etching in the capacitor preset region 600 with the aid of the second trench T2, so that each semiconductor layer 30 in the capacitor preset region 600 is exposed and suspended, and the suspended semiconductor layer 30 does not collapse due to the support of the support portion 70; at the same time, the side of the isolation layer 21 in the transistor region opposite to the support portion 70 is exposed, such as Fig. 12A and 12B As shown. Among them, Fig. 12A A three-dimensional schematic diagram of an intermediate product obtained in an intermediate step (S600) of a method for manufacturing a three-dimensional memory provided in an exemplary embodiment of the present application; Fig. 12B for Fig. 12A The structure shown is a schematic vertical cross-sectional view taken along the cross-sectional line BB'.

[0143] S700: forming a capacitor.

[0144] Exemplary steps may include doping the exposed semiconductor layer 30 in the capacitor preset area 600 to form a conductive layer, that is, forming a first electrode 61 of the capacitor; depositing a dielectric film completely covering the first electrode 61 around the exposed first electrode 61 and also depositing a dielectric film completely covering the side of the isolation layer 21 in the transistor area opposite to the support portion 70 to form a dielectric layer 62; depositing a conductive film completely covering the dielectric layer 62 on the dielectric layer 62 to form a second electrode 63. The first electrode 61, the second electrode 63 covering the first electrode 61, and the dielectric layer 62 serving as an isolation therebetween constitute a capacitor, such as Fig.13A and 13B As shown. Among them, Fig.13A A three-dimensional schematic diagram of an intermediate product obtained in an intermediate step (S700) of a method for manufacturing a three-dimensional memory provided in an exemplary embodiment of the present application; Fig. 13B A three-dimensional schematic diagram of an intermediate product obtained in an intermediate step (S700) of a method for manufacturing a three-dimensional memory according to an exemplary embodiment of the present application.

[0145] In an exemplary embodiment, the dielectric film and the conductive film may be deposited by atomic layer deposition (ALD).

[0146] In an exemplary embodiment, the dielectric layer 62 may be a dielectric layer with a high dielectric constant, i.e., a dielectric layer with K≥3.9. The dielectric layer 62 may be made of one of the following materials: silicon oxide, aluminum oxide (Al2O3), and hafnium oxide. In an exemplary embodiment, Si or N elements may be doped in the dielectric film to improve the high temperature resistance of the dielectric.

[0147] In an exemplary embodiment, the conductive film may be made of a material including, but not limited to, at least one of the following: polysilicon, tungsten, and titanium nitride.

[0148] S800: Exemplary steps may include filling the space between the second electrodes of the capacitor with a conductive material (such as SiGe) in the capacitor preset area 600 by a furnace tube process and flattening it so that the space surrounded by the second electrodes 63 of the capacitor has a conductive layer 64; setting a hard mask layer on the capacitor preset area 600; using a dry etching method to laterally etch and vertically etch to remove the sacrificial layer 20 in other areas outside the capacitor preset area 600 to form a plurality of grooves, so that each semiconductor layer 30 in the non-capacitor preset area is exposed and suspended, and the suspended semiconductor layer 30 will not collapse due to the support of the capacitor preset area; using an atomic layer deposition method to deposit a layer of insulating material (such as SiO2) in the formed grooves and continue to use a spin coating method (Spin on Dielectric, SOD) to deposit insulating material to cover and fill the formed multiple grooves, that is, replacing the sacrificial layer material in the previous stacked structure formation step with an insulating material in the non-capacitor preset area to play an isolation and insulation role, such as Fig.14A , 14B and 14C. Fig.14A A three-dimensional schematic diagram of an intermediate product obtained in an intermediate step (S800) of a method for manufacturing a three-dimensional memory provided in an exemplary embodiment of the present application; Fig. 14B A three-dimensional schematic diagram of an intermediate product obtained in an intermediate step (S800) of a method for manufacturing a three-dimensional memory provided in an exemplary embodiment of the present application; and Fig. 14C A three-dimensional schematic diagram of an intermediate product obtained in an intermediate step (S800) of a method for manufacturing a three-dimensional memory according to an exemplary embodiment of the present application.

[0149] S900: forming a bit line and an isolation portion.

[0150] Exemplary steps may include removing the material in the isolation region 100 by dry etching under the protection of the hard mask layer, forming a third trench T3 penetrating the stacked structure and terminating at one side of the upper surface of the substrate 10 in the isolation region 100, wherein the third trench T3 may be used to separate two columns of memory cells; doping each semiconductor layer in the bit line preset region 200 by ion implantation with the aid of the third trench T3 to form a plurality of bit lines 80; filling the third trench T3 with an isolation insulating material to form an isolation portion 700, such as Fig.15A , 15B and 15C. Fig.15A A three-dimensional schematic diagram of an intermediate product obtained in an intermediate step (S900) of a method for manufacturing a three-dimensional memory provided in an exemplary embodiment of the present application; Fig. 15B A three-dimensional schematic diagram of an intermediate product obtained in an intermediate step (S900) of a method for manufacturing a three-dimensional memory provided in an exemplary embodiment of the present application; and Fig. 15CA three-dimensional schematic diagram of an intermediate product obtained in an intermediate step (S900) of a method for manufacturing a three-dimensional memory according to an exemplary embodiment of the present application.

[0151] In an exemplary embodiment, the isolation insulating material may be SiN.

[0152] In an exemplary embodiment, by means of the third trench T3 , a plasma doping process may be used to perform high-dose doping on the sidewall of each semiconductor layer in the bit line pre-set region 200 to reduce the bit line resistance.

[0153] In an exemplary embodiment, a layer of silicide may be formed on the surface of each bit line 80 by forming silicide, thereby further reducing the contact resistance of the bit line 80 .

[0154] The manufacturing method for forming the bit line of the present application greatly reduces the process difficulty of manufacturing the bit line.

[0155] S1000: forming a channel region.

[0156] Exemplary steps may include forming a word line through hole K penetrating the stacked structure in the word line preset area 400 by dry etching with the protection of a hard mask layer; sequentially depositing an insulating layer film and a conductive film around the inner peripheral wall of each word line through hole K to form a gate insulating layer 91 and a word line 90 (without the step of depositing a semiconductor material film); forming a channel region 92 in the semiconductor layer 30 at both sides of the word line 90 along the second direction Y, such as Fig.16A , 16B and 16C. Fig.16A A three-dimensional schematic diagram of an intermediate product obtained in an intermediate step (S1000) of a method for manufacturing a three-dimensional memory provided in an exemplary embodiment of the present application; Fig. 16B A three-dimensional schematic diagram of an intermediate product obtained in an intermediate step (S1000) of a method for manufacturing a three-dimensional memory provided in an exemplary embodiment of the present application; and Fig. 16C A three-dimensional schematic diagram of an intermediate product obtained in an intermediate step ( S1000 ) of a method for manufacturing a three-dimensional memory according to an exemplary embodiment of the present application.

[0157] In an exemplary embodiment, the orthographic projection of the word line through hole K on a plane parallel to the substrate 10 may be a rectangle, a square, a circle, etc.

[0158] In an exemplary embodiment, an orthographic projection of the word line through hole K on a plane parallel to the substrate 10 is located within an orthographic projection of the semiconductor layer 30 on a plane parallel to the substrate 10 .

[0159] In an exemplary embodiment, the gate insulating layer 91 may be a dielectric layer with a high dielectric constant, i.e., a dielectric layer with K≥3.9. The dielectric layer with a high dielectric constant may be used as a gate oxide. The gate insulating layer 91 may be any one or more of silicon oxide, aluminum oxide (Al2O3), and hafnium oxide.

[0160] In an exemplary embodiment, the word line 90 may be made of metal tungsten W or a composite metal of TiN / W, or may be made of ITO.

[0161] The exemplary embodiment of the present application also provides a method for manufacturing a three-dimensional memory, which may include the following steps:

[0162] S2000: alternately forming sacrificial layers and semiconductor layers along a third direction to form a stacked structure;

[0163] S2100: forming a plurality of first extension portions extending along the first direction and arranged at intervals along the second direction and a second extension portion extending along the second direction in each of the semiconductor layers, wherein each of the first extension portions is divided into a first sub-extension portion and a second sub-extension portion by the second extension portion in the first direction, and the first direction intersects the second direction and is perpendicular to the third direction;

[0164] S2200: Disposing an isolation region and bit line preset regions located on both sides of the isolation region in the second extension portion;

[0165] S2300: in the first sub-extension portion, sequentially disposing a second source / drain preset region, a word line preset region, a first source / drain preset region, and a capacitor preset region along a first direction on a side of the bit line preset region away from the isolation region;

[0166] S2400: forming a support portion in the capacitor preset region at a side away from the first source / drain preset region;

[0167] S2500: removing the sacrificial layer in the preset area of ​​the capacitor to expose the semiconductor layers in the preset area of ​​the capacitor, thereby forming a first electrode of the capacitor;

[0168] S2600: forming a bit line in the bit line preset area;

[0169] S2700: forming a word line through hole penetrating the stacked structure in the word line preset area;

[0170] S2800: sequentially depositing an insulating film and a conductive film around the inner peripheral wall of each word line through hole to form a gate insulating layer and a word line;

[0171] S2900: forming a channel region in a region of the semiconductor layer located on at least one side of the word line along the second direction.

[0172] In an exemplary embodiment, the manufacturing method further comprises:

[0173] Depositing a dielectric film around the exposed first electrode and completely covering the first electrode to form a dielectric layer;

[0174] A conductive film is deposited around the dielectric layer and completely covers the dielectric layer to form a second electrode.

[0175] In an exemplary embodiment, forming a bit line includes:

[0176] Removing the stacked structure in the isolation region to form a groove penetrating the stacked structure;

[0177] The semiconductor layer in the predetermined bit line region is doped by means of the formed trench to form the bit line.

[0178] The exemplary embodiments of the present application also provide an electronic device, comprising the three-dimensional memory provided by the exemplary embodiments of the present application, such as a three-dimensional DRAM.

[0179] In an exemplary embodiment, the electronic device may include a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power source.

[0180] Although the embodiments disclosed in this application are as above, the contents described are only embodiments adopted to facilitate understanding of this application and are not intended to limit this application. Any technician in the field to which this application belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in this application, but the scope of protection of this application shall still be based on the scope defined in the attached claims.

Claims

1. A three-dimensional memory, characterized in that: include: A plurality of memory cells stacked along a third direction, each layer of memory cells comprising a first column of memory cells extending along a second direction and a second column of memory cells extending along the second direction, the first column of memory cells and the second column of memory cells being adjacent and arranged along the first direction, a plurality of memory cells in the first column of memory cells sharing a bit line extending along the second direction, and a plurality of memory cells in the second column of memory cells sharing a bit line extending along the second direction; The memory cell includes a transistor and a capacitor; the capacitor includes a first electrode and a second electrode; The word line extends along the third direction; Each of the transistors has a channel region only on at least one side of the word line connected thereto along the second direction; The transistor is electrically connected to the first electrode, and the first direction intersects with the second direction and is perpendicular to the third direction.

2. The three-dimensional memory according to claim 1, characterized in that: Each of the transistors has a channel region only on two sides of the word line connected thereto along the second direction.

3. The three-dimensional memory according to claim 1, characterized in that: The bit line shared by the first column of memory cells and the bit line shared by the second column of memory cells are separated by an isolation portion, and the first column of memory cells and the second column of memory cells are symmetrical with respect to the isolation portion in a first direction.

4. The three-dimensional memory according to claim 1, characterized in that: Each of the transistors further includes a gate, which is a part of the corresponding word line, and a gate insulating layer is arranged between the gate and the channel region; and each of the transistors of each storage unit stacked in the third direction shares a word line.

5. The three-dimensional memory according to claim 4, characterized in that: In the third direction, the channel regions are arranged at intervals and the gate insulating layer is arranged continuously.

6. The three-dimensional memory according to claim 4, characterized in that: Each of the transistors further includes a first source / drain and a second source / drain located on both sides of the word line connected thereto in the first direction.

7. The three-dimensional memory according to claim 6, characterized in that: The first source / drain, the second source / drain, the first electrode, and the bit line include a same material.

8. The three-dimensional memory according to claim 1, characterized in that: The second electrode surrounds the first electrode.

9. The three-dimensional memory according to claim 8, characterized in that: The capacitor includes a dielectric layer located between the first electrode and the second electrode, and the dielectric layers of the capacitors of the storage units are interconnected to form an integrated structure.

10. The three-dimensional memory according to claim 9, characterized in that: The second electrodes of the capacitors of the storage units are connected to each other to form an integrated structure.

11. The three-dimensional memory according to claim 1, characterized in that: A conductive layer is provided between the plurality of second electrodes, a support portion is provided on a side of the capacitor away from the transistor, and the conductive layer is connected to the support portion.

12. The three-dimensional memory according to claim 11, characterized in that: The plurality of second electrodes are electrically connected via the conductive layer, and the second electrodes and the conductive layer are made of different materials.

13. A method for manufacturing a three-dimensional memory, characterized in that: The steps include: Alternatingly forming sacrificial layers and semiconductor layers along a third direction to form a stacked structure; A plurality of first extension portions extending along the first direction and arranged at intervals along the second direction and a second extension portion extending along the second direction are formed in each of the semiconductor layers, each of the first extension portions is divided into a first sub-extension portion and a second sub-extension portion by the second extension portion in the first direction, and the first direction intersects the second direction and is perpendicular to the third direction; An isolation region and bit line preset regions located on both sides of the isolation region are provided in the second extension portion; In the first sub-extension portion, a second source / drain preset region, a word line preset region, a first source / drain preset region and a capacitor preset region are sequentially arranged along a first direction on a side of the bit line preset region away from the isolation region; Forming a support portion on a side of the capacitor preset region away from the first source / drain preset region; Removing the sacrificial layer in the preset area of ​​the capacitor to expose the semiconductor layers in the preset area of ​​the capacitor to form a first electrode of the capacitor; forming a bit line in the bit line preset area; In the word line preset area, a word line through hole penetrating the stacked structure is formed; An insulating film and a conductive film are sequentially deposited around the inner peripheral wall of each word line through hole to form a gate insulating layer and a word line; A channel region is formed in a region of the semiconductor layer located on at least one side of the word line along the second direction.

14. The manufacturing method according to claim 13, characterized in that: The manufacturing method further comprises: Depositing a dielectric film around the exposed first electrode and completely covering the first electrode to form a dielectric layer; A conductive film is deposited around the dielectric layer and completely covers the dielectric layer to form a second electrode.

15. The manufacturing method according to claim 13, characterized in that: Forming the bit line includes: Removing the stacked structure in the isolation region to form a groove penetrating the stacked structure; The semiconductor layer in the predetermined bit line region is doped by means of the formed trench to form the bit line.

16. An electronic device, characterized in that: Comprising a three-dimensional memory according to any one of claims 1-12.

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