Erasing method of flash memory unit

Abstract

The invention provides an erasing method of a flash memory unit. The flash memory cell includes a memory transistor and a gate transistor connected in series. The erasing method comprises the steps that erasing voltages are applied to electrodes of the flash memory unit and gate electrodes of transistors, the erasing voltages applied to the gate electrodes of the erased memory transistors are lower than second power supply voltages, and therefore the channel hot electron induced hot hole injection physical effect occurs. Therefore, hot holes in the channel are attracted into the storage medium layer to realize erasing. Compared with the existing band-to-band tunneling hot hole (BBHH) erasing method, the erasing method of the flash memory unit disclosed by the invention has wider hole distribution and higher injection efficiency, so that the erasing method disclosed by the invention has higher erasing speed, larger erasing window, smaller hot carrier damage, lower leakage current and higher durability and reliability.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a method for erasing a flash memory cell. Background Art

[0002] Flash memory, also known as flash memory, is a non-volatile memory, which means that the stored data will not be lost even when the power is disconnected. It is particularly suitable for fields such as mobile communications and computer storage components. In addition, some flash memories also have high-density storage capabilities, which are suitable for applications such as large-capacity mobile storage media.

[0003] Traditional flash memory uses a floating gate cell structure. The floating gate non-volatile memory originated from the MIMIS (Metal-Insulator-Metal-Insulator-Semiconductor) structure proposed by D. Kahng and S. Sze in 1967. This structure adds a metal floating gate and an ultra-thin tunneling oxide layer to the traditional MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), thereby using the metal floating gate to store charge. Based on this, Masuoka et al. first proposed the concept of flash memory in 1984, that is, to achieve high-speed erasing capability by erasing by block (sector) and writing (programming) by bit, and eliminate the selection tube required in EEPROM (Erasable Programmable Read-only memory), thereby having a smaller storage cell size. After the emergence of flash memory, it has rapidly developed with its high write speed, high integration and superior performance. In 1988, Intel proposed the ETOX structure flash memory cell (ETOX: Electron Tunneling Oxide device), which has become the development foundation of most floating gate flash memory cell structures to date.

[0004] However, floating gate flash memory has the following disadvantages: the process is relatively complex; the existence of the floating gate structure in the flash memory cell increases the vertical height of the gate structure, which is not conducive to proportionally reducing the process size and unit area; at the same time, due to the conductivity of the floating gate, the stored charge can move freely in the floating gate, which is not conducive to improving the reliability of the memory. In order to solve the problems of complex process and poor reliability of floating gate flash memory, researchers proposed a charge trapping memory (CTM: Charge-Trapping-Memory) that uses silicon nitride medium to store charge, also known as SONOS (Silicon-Oxide-Nitride-Oxide-Silicon: Silicon-Oxide-Nitride-Oxide-Silicon) flash memory. Based on this, B.Eitan et al. proposed a two-bit storage cell structure NROM (Nitride-Read-Only-Memory: Silicon Nitride Read-Only Memory) in 2000. This cell structure uses the non-conductive properties of the insulating silicon nitride storage medium to realize two storage bits at the source and drain ends of a storage transistor respectively. However, this cell structure has the disadvantages that the two storage bits interfere with each other and the device size cannot be reduced. On the other hand, existing SONOS flash memory cells generally use the channel hot electron injection (CHE) physical effect for write operations, and use the band-band tunneling hot hole injection (BBHH) physical effect or the FN tunneling physical effect for erase operations. Due to the different physical mechanisms used in erase and write, the trapped electron charge injected in the write operation and the trapped hole charge injected in the erase operation are inconsistently distributed, which easily produces a trapped charge mismatch effect (TCME), resulting in degradation of the durability and retention reliability of the flash memory cell.

[0005] However, existing floating gate ETOX flash memories and SONOS NROM flash memories have problems such as inability to reduce process size, large cell area, high write power consumption and large array area overhead, and cannot achieve high-density integration above Gb capacity.

[0006] With the rapid development of applications such as mobile smart terminals, wearable devices, and smart sensor networks, higher requirements are placed on the power consumption, storage capacity, and cost of flash memory. Therefore, a flash memory technology with the advantages of low power consumption, small unit area, shrinkable process size, high array integration density, and large capacity is needed. Summary of the invention

[0007] The above information disclosed in this Background section is only for understanding the background of the inventive concept and therefore it may contain information that does not constitute prior art.

[0008] In order to solve the above problems existing in the prior art, the present disclosure proposes a method for erasing a flash memory unit.

[0009] According to one aspect of the present disclosure, a method for erasing a flash memory cell is provided, the flash memory cell comprising: a substrate and a well region arranged in the substrate; a storage transistor arranged on the well region and configured to store data; and a gating transistor arranged on one side of the storage transistor in a horizontal direction on the well region and configured to perform a gating operation on the storage transistor, wherein the gating transistor and the storage transistor are connected in series, wherein a source region of the storage transistor is connected to a first electrode of the flash memory cell, and a drain region of the gating transistor is connected to a second electrode of the flash memory cell, the erasing method comprising: applying a second power supply voltage to the well region, applying a first erasing voltage to the first electrode, applying a second erasing voltage to the second electrode, A third erase voltage is applied to the gate electrode of the storage transistor, and a fourth erase voltage is applied to the gate electrode of the selection transistor, and an erase operation is performed on the storage transistor, wherein the first erase voltage is higher than a preset voltage, the second erase voltage is equal to or higher than the second power supply voltage, the third erase voltage is equal to or lower than the second power supply voltage, and the fourth erase voltage is equal to or lower than the first power supply voltage, wherein the first power supply voltage is higher than the second power supply voltage, wherein the preset voltage is pre-set based on a carrier barrier height at an interface between a substrate and a gate dielectric stack of the storage transistor, and wherein the first erase voltage and the fourth erase voltage are higher than the second erase voltage, so that both the storage transistor and the selection transistor are turned on.

[0010] According to another aspect of the present disclosure, a method for erasing a flash memory cell is provided, the flash memory cell comprising: a substrate and a well region arranged in the substrate; a first storage transistor arranged on the well region and configured to store first data; a second storage transistor arranged on the well region and configured to store second data; and a selection transistor arranged between the first storage transistor and the second storage transistor in a horizontal direction on the well region, configured to isolate the first storage transistor and the second storage transistor and perform a selection operation on the first storage transistor and the second storage transistor, wherein the first storage transistor, the selection transistor and the second storage transistor are connected in series in sequence, wherein the source region of the first storage transistor is connected to the first electrode of the flash memory cell, and the drain region of the second storage transistor is connected to the second electrode of the flash memory cell, the erasing method comprising: applying a second power supply voltage to the well region, applying a first erasing voltage to the first electrode or the second electrode, and applying a second erasing voltage to the first A second electrode or a first electrode, a third erasing voltage is applied to the gate electrode of the first storage transistor or the second storage transistor, a fourth erasing voltage is applied to the gate electrode of the selection transistor, and a fifth erasing voltage is applied to the gate electrode of the second storage transistor or the first storage transistor, and an erasing operation is performed on the first storage transistor or the second storage transistor, wherein the first erasing voltage is higher than a preset voltage, the second erasing voltage is equal to or higher than the second power supply voltage, the third erasing voltage is equal to or lower than the second power supply voltage, and the fourth erasing voltage is equal to or lower than the first power supply voltage, wherein the first power supply voltage is higher than the second power supply voltage, wherein the preset voltage is pre-set according to the carrier barrier height at the interface between the substrate and the gate dielectric stack of the first storage transistor and the second storage transistor, and wherein the first erasing voltage, the fourth erasing voltage and the fifth erasing voltage are higher than the second erasing voltage, so that the first storage transistor, the second storage transistor and the selection transistor are all turned on.

[0011] According to the erasing method disclosed in the present invention, the erasing voltage applied to the gate electrode of the erased storage transistor is lower than the second power supply voltage, so that a channel hot electron induced hot hole injection physical effect occurs to attract the hot holes in the channel into the storage medium layer to achieve erasure, so that compared with the existing band-to-band tunneling hot hole (BBHH) erasing method, the erasing method disclosed in the present invention has a higher erasing speed (tens of microseconds), a larger erasing window, smaller hot carrier damage, lower leakage current and higher endurance reliability.

[0012] However, the effects of the present disclosure are not limited to the above-mentioned effects, and various extensions may be made without departing from the spirit and scope of the present disclosure. It should be understood that both the foregoing general description and the following detailed description are exemplary and explanatory, and are intended to provide further explanation of the present disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the disclosure and together with the description serve to explain the inventive concept.

[0014] Figure 1 A cross-sectional view of a flash memory cell according to an embodiment of the present disclosure is shown.

[0015] Figure 2 An equivalent circuit diagram of a flash memory cell according to an embodiment of the present disclosure is shown.

[0016] Figure 3 A schematic diagram showing an erasing operation performed on a first storage transistor by an erasing method according to an embodiment of the present disclosure is shown.

[0017] Figure 4 A schematic diagram showing an erasing operation performed on a second storage transistor by an erasing method according to an embodiment of the present disclosure is shown.

[0018] Figure 5 A cross-sectional view of a flash memory cell according to another embodiment of the present disclosure is shown.

[0019] Figure 6 An equivalent circuit diagram of a flash memory cell according to another embodiment of the present disclosure is shown.

[0020] Figure 7 A schematic diagram showing an erasing operation performed on a storage transistor by an erasing method according to another embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0021] In the following description, for the purpose of illustration, many specific details are set forth in order to provide a thorough understanding of each exemplary embodiment or implementation of the present disclosure. As used herein, "implementation" and "implementation" are interchangeable terms, which are non-limiting examples of devices or methods using one or more inventive concepts disclosed herein. However, it is apparent that each exemplary embodiment can be practiced without these specific details or with one or more equivalent arrangements. In addition, each exemplary embodiment may be different, but does not have to be exclusive. For example, without departing from the inventive concept, the specific shape, configuration and characteristics of the exemplary embodiment may be used or implemented in other exemplary embodiments.

[0022] Unless otherwise specified, the exemplary embodiments described should be understood as providing exemplary features of varying details of some ways in which the inventive concept can be implemented in practice. Therefore, unless otherwise specified, the features, components, modules, layers, films, substrates, regions and / or aspects of each embodiment (hereinafter individually or collectively referred to as "elements") can be combined, separated, interchanged and / or rearranged without departing from the inventive concept.

[0023] The use of cross hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Thus, the presence or absence of cross hatching or shading cannot convey or indicate any preference or requirement for a particular material, material properties, size, ratio, commonality between the elements shown, and / or any other characteristics, attributes, shapes, etc. of the elements, unless otherwise stated. In addition, in the drawings, the size and relative size of the elements may be exaggerated for clarity and / or descriptive purposes. When the exemplary embodiments can be implemented in different ways, a specific processing sequence can be performed differently from the described sequence. For example, two processes described in succession can be performed substantially simultaneously or in an order opposite to the described sequence. Similarly, the same reference numerals represent the same elements.

[0024] When an element such as a layer is referred to as being "on", "connected to" or "coupled to" another element or layer, it may be directly on, directly connected to or coupled to, another element or layer, or there may be an intervening element or layer. However, when an element or layer is referred to as being "directly" "on", "directly connected to" or "directly coupled to" another element or layer, there may be no intervening element or layer. For this reason, the term "connection" may refer to a physical, electrical and / or fluid connection with or without an intervening element. In addition, the D1 axis, the D2 axis, and the D3 axis are not limited to the three axes of a rectangular coordinate system, such as the x, y, and z axes, and may be interpreted in a broader sense. For example, the D1 axis, the D2 axis, and the D3 axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purpose of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as, for example, XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0025] Although the terms "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0026] Spatially relative terms, such as "below," "beneath," "below," "above," "upper," and "on the side" (e.g., as in "sidewall"), etc., may be used herein for descriptive purposes to describe the relationship between one element as shown in the figures and other elements. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture other than the orientation shown in the drawings. For example, if the device in the drawings is flipped, an element described as being "below" or "beneath" other elements or features will be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both above and below orientations. Additionally, the device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and thus the spatially relative descriptors used herein are interpreted accordingly.

[0027] The terms used herein are for the purpose of describing specific embodiments, but are not intended to be restrictive. As used herein, the singular forms "one", "an" and "the" are intended to also include plural forms, unless the context clearly indicates otherwise. In addition, when used in this specification, the terms "include" and / or "comprise" indicate that there are stated features, integers, steps, operations, elements, parts and / or their groups, but do not exclude the presence or increase of one or more other features, integers, steps, operations, elements, parts and / or their groups. It should also be noted that, as used herein, the terms "substantially", "about" and other similar terms are used as approximate terms rather than degree terms, and are therefore utilized to account for the inherent deviations in the values ​​recognized by those of ordinary skill in the art, calculated and / or provided.

[0028] Embodiments are described herein with reference to cross-sectional views and / or exploded views, which are schematic diagrams of idealized embodiments and / or intermediate structures. In this way, variations in the illustrated shapes, for example due to manufacturing techniques and / or tolerances, are to be expected. Therefore, the embodiments disclosed herein need not necessarily be interpreted as being limited to the specific illustrated shapes of the regions, but rather include shape deviations caused by, for example, manufacturing. In this way, the regions shown in the drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and therefore this is not necessarily intended to be limiting.

[0029] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. Terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0030] Figure 1 A cross-sectional view of a flash memory cell MC 100 according to an embodiment of the present disclosure is shown.

[0031] like Figure 1 As shown, a flash memory cell MC 100 according to an embodiment of the present disclosure may include a substrate 101 including a deep well region DNW 103 of a second doping type and a well region PW 102 of a first doping type disposed on the deep well region DNW 103 .

[0032] Despite Figure 1 As an example, the first doping type is defined as P type and the second doping type is defined as N type, but those skilled in the art should recognize that the present disclosure is not limited to this, and the first doping type may also be N type, in which case the second doping type may be P type.

[0033] According to an embodiment of the present disclosure, the substrate 101 may be, for example, a silicon (Si) substrate.

[0034] In addition, the flash memory cell MC100 includes a first storage transistor MS110, a gate transistor MG120, and a second storage transistor MD130 connected in series in sequence. The first storage transistor MS110 may be disposed on the well region PW102 and store first data DATA1. The second storage transistor MD130 may be disposed on the well region PW102 and store second data DATA2. The gate transistor MG120 is disposed between the first storage transistor MS110 and the second storage transistor MD130 along the horizontal direction DR1 on the well region PW102, and is used to isolate the first storage transistor MS110 and the second storage transistor MD130 and perform a gate operation on the first storage transistor MS110 and the second storage transistor MD130.

[0035] According to an embodiment of the present disclosure, the flash memory cell MC100 includes two storage transistors MS110 and MD130, so the flash memory cell MC100 can implement a two-bit storage function, that is, store the first data DATA1 and the second data DATA2 simultaneously.

[0036] In addition, if Figure 1As shown, the source region of the first storage transistor MS110 is connected to the first electrode S of the flash memory cell MC100, which can also be referred to as the source S of the flash memory cell MC100, and the drain region of the second storage transistor MD130 is connected to the second electrode D of the flash memory cell MC100, which can also be referred to as the drain D of the flash memory cell MC100.

[0037] Those skilled in the art should recognize that the source and drain of a flash memory cell are defined herein for ease of description; however, the definition of the source and drain of a flash memory cell is relative, and the terms "source" and "drain" may be used interchangeably under different operating conditions.

[0038] In addition, if Figure 1 As shown, the first storage transistor MS110 has a gate structure including a channel region 111, a gate dielectric stack 112, a gate electrode 116, and a hard mask stopper 117 sequentially arranged along a vertical direction DR2. The gate dielectric stack 112 has a first oxide layer 113, a storage dielectric layer 114, and a second oxide layer 115 sequentially stacked along the vertical direction. In addition, the second storage transistor MD130 has a gate structure including a channel region 131, a gate dielectric stack 132, a gate electrode 136, and a hard mask stopper 137 sequentially arranged along the vertical direction DR2. The gate dielectric stack 132 has a first oxide layer 133, a storage dielectric layer 134, and a second oxide layer 135 sequentially stacked along the vertical direction.

[0039] According to an embodiment of the present disclosure, the flash memory cell MC 100 includes two storage transistors MS 110 and MD 130 , and thus can implement a two-bit storage function.

[0040] According to the embodiments of the present disclosure, Figure 1 As shown, the flash memory cell MC100 for two-bit storage may be composed of three closely arranged transistors, namely, a gate transistor MG120 located in the middle of the flash memory cell MC100, a first storage transistor MS110 located at a first end of the flash memory cell MC100, and a second storage transistor MD130 located at a second end of the flash memory cell MC100.

[0041] like Figure 1 As shown, the flash memory cell MC 100 may be formed on a well region PW 102 in a semiconductor substrate 101. In addition, in order to isolate the well region PW 102 from the substrate 101 so as to apply a voltage to the well region PW 102 under certain working conditions, such as Figure 1 As shown in FIG. 1 , the well region PW 102 may be formed in the deep well region DNW 103 .

[0042] like Figure 1As shown, a source region 140 formed by N-type doping is provided at the first end of the flash memory cell MC 100, and a drain region 150 formed by N-type doping is also provided at the second end of the flash memory cell MC 100. The source region 140 is connected to a metal source electrode 142 located at an upper layer, i.e., a first electrode S, through a contact hole 141, and the drain region 150 is connected to a metal drain electrode 152 located at an upper layer, i.e., a second electrode D, through a contact hole 151.

[0043] According to an embodiment of the present disclosure, the first electrode S and the second electrode D may include metal or highly doped polysilicon. When the first electrode S and the second electrode D are formed of metal, they may include at least one of the following materials: aluminum, titanium, titanium nitride, copper, tungsten, cobalt, and manganese.

[0044] As mentioned above, if Figure 1 As shown, the gate structure of the first storage transistor MS110 may include, from bottom to top, a channel region 111, a gate dielectric stack 112, a gate electrode 116, and a hard mask barrier 117 for sidewall self-alignment. According to an embodiment of the present disclosure, the gate electrode 116 may include, for example, polysilicon, a metal gate, a metal silicide material, or a combination of the above materials. According to an embodiment of the present disclosure, the hard mask barrier 117 may include, for example, silicon oxide, silicon nitride, silicon glass material, or a combination of the above materials.

[0045] In addition, if Figure 1 As shown, the gate dielectric stack 112 has a first oxide layer (tunneling oxide layer) 113, a storage dielectric layer (charge storage layer) 114, and a second oxide layer (blocking oxide layer) 115 stacked in sequence from bottom to top along the vertical direction DR2. According to an embodiment of the present disclosure, the first oxide layer 113 and the second oxide layer 115 may include, for example, silicon oxide or aluminum oxide. According to an embodiment of the present disclosure, the thickness of the first oxide layer (tunneling oxide layer) 113 may be 1 to 6 nm.

[0046] According to an embodiment of the present disclosure, the storage medium layer 114 may include one or more layers of storage medium. In addition, according to an embodiment of the present disclosure, the storage medium forming the storage medium layer 114 may include: a monovalent or polyvalent oxide, such as hafnium oxide, tantalum oxide, titanium oxide, zirconium oxide, hafnium aluminum oxide; a monovalent or polyvalent nitride, such as silicon nitride; a monovalent or polyvalent oxynitride, such as silicon oxynitride; polycrystalline silicon or nanocrystalline material; or a combination of the above materials.

[0047] According to an embodiment of the present disclosure, when the storage medium layer 114 is formed of, for example, a silicon nitride material, the first oxide layer 113, the storage medium layer 114, and the second oxide layer 115 may form a gate dielectric stack 112 as an ONO (oxide-nitride-oxide) composite storage medium. In this case, the first storage transistor MS110 may be a SONOS (silicon-oxide-nitride-oxide-silicon) type storage transistor.

[0048] In addition, according to an embodiment of the present disclosure, the first storage transistor MS110 may be other trapped charge capture type storage transistors having a similar operating mechanism to the SONOS type storage transistor. This type of storage transistor uses a high-K material rich in charge traps such as silicon oxynitride, hafnium oxide, tantalum oxide, titanium oxide, zirconium oxide, hafnium aluminum oxide, etc. to replace the silicon nitride material in the SONOS memory as the storage medium layer 114.

[0049] In addition, according to an embodiment of the present disclosure, the first storage transistor MS110 may also be a floating gate storage transistor. This type of storage transistor uses polysilicon material to replace the silicon nitride material in the SONOS memory to form a floating gate for storing charges as the storage medium layer 114 .

[0050] In addition, according to an embodiment of the present disclosure, the first storage transistor MS110 may also be a nano-crystal memory transistor. This type of storage transistor uses a nano-crystal material with quantum dots to replace the silicon nitride material in the SONOS memory as the storage medium layer 114 .

[0051] According to an embodiment of the present disclosure, the length of the gate electrode 116 of the first storage transistor MS110 can be defined by the length of the hard mask stopper 117 disposed on the gate electrode 116 through a self-alignment process. Those skilled in the art should note that the "length" mentioned herein means the size of the stated object in the first direction DR1.

[0052] According to an embodiment of the present disclosure, except for being disposed on the opposite side of the selection transistor MG120, the second storage transistor MD130 has the same structure as the first storage transistor MS110 and can be manufactured by the same process as the first storage transistor MS110, so for the sake of brevity, a detailed description of the structure of the second storage transistor MD130 will be omitted here.

[0053] The gate structure of the gate transistor MG 120 may include a channel region 121, a gate dielectric layer 122, and a gate electrode 123 from bottom to top. According to an embodiment of the present disclosure, the gate electrode 123 of the gate transistor MG 120 is connected to the word line, and the length of the gate electrode 123 is defined by the process size of the photolithography process. According to an embodiment of the present disclosure, the gate dielectric layer 122 may include materials such as silicon oxide, silicon oxynitride, and hafnium oxide. In addition, according to an embodiment of the present disclosure, the gate electrode 123 may include, for example, polysilicon, a metal gate, a metal silicide material, or a combination of the above materials.

[0054] According to an embodiment of the present disclosure, the channel regions 111, 131 and 121 of the first storage transistor MS110, the second storage transistor MD130 and the gate transistor MG120 may all have a first doping type, and the doping concentration of the channel regions 111 and 131 of the first storage transistor MS110 and the second storage transistor MD130 may be lower than the doping concentration of the channel region 121 of the gate transistor MG120.

[0055] Furthermore, according to an embodiment of the present disclosure, the channel regions 111 and 131 of the first and second storage transistors MS110 and MD130 may have a second doping type or be undoped intrinsic channel regions, and the channel region 121 of the gate transistor MG120 may have a first doping type different from the second doping type.

[0056] For example, Figure 1 As shown, when the first doping type is P-type and the second doping type is N-type, the doping concentrations of the P-type channels 111 and 131 of the first storage transistor MS110 and the second storage transistor MD130 are lower than the doping concentration of the P-type channel 121 of the gate transistor MG120. In addition, according to an embodiment of the present disclosure, the channel regions 111 and 131 may also be undoped intrinsic channels or N-type doped channel regions.

[0057] According to an embodiment of the present disclosure, the flash memory cell MC100 may further include: a first isolation portion 124, which is arranged between the first storage transistor MS110 and the selection transistor MG120 along the horizontal direction DR1, and is used to isolate the gate electrode 116 of the first storage transistor MS110 and the gate electrode 123 of the selection transistor MG120; and a second isolation portion 125, which is arranged between the selection transistor MG120 and the second storage transistor MD130 along the horizontal direction DR1, and is used to isolate the gate electrode 123 of the selection transistor MG120 and the gate electrode 136 of the second storage transistor MD130.

[0058] Specifically, Figure 1As shown, a first isolation portion 124 and a second isolation portion 125 in the form of sidewalls are provided on both sides of the gate electrode 123 of the gate transistor MG 120, which are respectively used to electrically isolate the gate electrode 116 of the first storage transistor MS110 and the gate electrode 136 of the second storage transistor MD 130 with a specific isolation gap length. According to an embodiment of the present disclosure, the first isolation portion 124 and the second isolation portion 125 may include the same material as the gate dielectric layer 122.

[0059] The flash memory cell according to the embodiment of the present disclosure can implement two storage transistors in one flash memory cell, so the equivalent area of ​​each storage bit can be greatly reduced, thereby achieving lower cost and higher integration density.

[0060] In addition, the storage transistor in the flash memory cell according to the embodiment of the present disclosure can adopt a simple SONOS type device structure, which has the advantages of simple process, low gate electrode operation voltage, and good data retention reliability.

[0061] In addition, in the flash memory cell according to the embodiment of the present disclosure, the mutual influence of the two storage bits is isolated by the selection transistor, and the distribution width and lateral diffusion of the stored charge are suppressed, so that a higher storage charge density can be obtained in the silicon nitride storage layer, avoiding the problems of wide charge distribution, large mutual interference, and inability to reduce gate length that exist in the existing NROM storage cell that also uses two-bit storage, thereby significantly improving the storage window and data reliability.

[0062] In particular, the equivalent channel length of the flash memory cell according to the embodiment of the present disclosure is the sum of the lengths of the gate electrodes of the first storage transistor, the selection transistor, and the second storage transistor. As described above, the gate electrode length of the selection transistor is defined by the process feature size of the photolithography process, and is generally approximately equal to or slightly greater than the critical feature size (Critical Feature Size) of the photolithography process, which is generally represented as F (or CF). In addition, the gate electrode lengths of the first storage transistor and the second storage transistor are respectively defined by the lengths of the self-aligned sidewall hard mask blocking portion, so that their sizes can be smaller than F. Therefore, according to the embodiment of the present disclosure, a smaller channel length of the flash memory cell can be obtained under the same process feature size, thereby achieving the purpose of reducing the area and manufacturing cost of the flash memory cell.

[0063] In addition, in a flash memory cell array composed of flash memory cells according to the embodiments of the present disclosure, for flash memory cells that are not selected for operation, the gate electrodes of the selection transistor and the first and second storage transistors are grounded, so that the entire series channel of the flash memory cell is completely turned off, and the equivalent channel length is enlarged, so that the source-drain punch-through of the flash memory cell under high operating voltage can be avoided at a smaller process feature size, thereby overcoming the problem that the gate electrode length of the existing flash memory cell cannot be reduced as the process feature size is reduced. Therefore, the flash memory cell according to the embodiments of the present disclosure has better process miniaturization capability, and can obtain a smaller unit area and manufacturing cost by reducing the process feature size.

[0064] In addition, in the flash memory cell according to the embodiment of the present disclosure, by reducing the doping concentration of the P-type channel region of the first storage transistor and the second storage transistor or designing them as N-type doped channel regions, the threshold voltage of the storage transistor and the gate electrode operating voltage during the erase and read operations can be reduced, thereby improving the reliability of the storage transistor. At the same time, by increasing the doping concentration of the P-type channel region of the selection transistor, the punch-through voltage of the flash memory cell can be increased, and the leakage current between the source and the drain of the non-selected flash memory cell can be reduced.

[0065] Figure 2 An equivalent circuit diagram of a flash memory cell MC100 according to an embodiment of the present disclosure is shown. Figure 3 FIG. 1 is a schematic diagram showing an erasing operation performed on the first storage transistor MS 110 by an erasing method according to an embodiment of the present disclosure. Figure 4 FIG. 1 is a schematic diagram showing an erasing operation performed on the second memory transistor MD 130 according to an erasing method according to an embodiment of the present disclosure.

[0066] Specifically, Figure 2 As shown in FIG. 1 , the flash memory cell MC100 includes a first storage transistor MS110, a gate transistor MG120, and a second storage transistor MD130 connected in series in sequence. The gate transistor MG120 can isolate the first storage transistor MS110 and the second storage transistor MD130 and perform a gate operation on the first storage transistor MS110 and the second storage transistor MD130. Figure 2 As shown in , by controlling the voltages applied to the source region (i.e., the first electrode S) of the first storage transistor MS110, the gate electrode 116 of the first storage transistor MS110, the gate electrode 123 of the selection transistor MG120, the gate electrode 136 of the second storage transistor MD130, and the drain region (i.e., the second electrode D) of the second storage transistor MD130, the erase operation of the first storage transistor MS110 or the second storage transistor MD130 can be respectively implemented.

[0067] According to an embodiment of the present disclosure, when an erase operation is performed on the flash memory cell MC 100 , the well region PW 102 of the flash memory cell MC 100 may be grounded.

[0068] Specifically, according to the embodiments of the present disclosure, Figure 3 As shown, when performing an erase operation on the first storage transistor MS110 of the flash memory cell MC100, the erase method according to the present disclosure includes applying the second power supply voltage VSS to the well region PW102, applying the first erase voltage VE1 to the first electrode S, applying the second erase voltage VE2 to the second electrode D, applying the third erase voltage VE3 to the gate electrode 116 of the first storage transistor MS110, applying the fourth erase voltage VE4 to the gate electrode 123 of the gate transistor MG120, and applying the fifth erase voltage VE5 to the gate electrode 136 of the second storage transistor MD130. For example, the second power supply voltage VSS may be a ground voltage GND, such as 0V.

[0069] According to an embodiment of the present disclosure, the first erase voltage VE1 may be higher than a preset voltage VP, wherein the preset voltage VP is preset according to a carrier barrier height at an interface between the substrate and the gate dielectric stack 112 of the first storage transistor MS110. Figure 1 In the flash memory cell MC 100 shown, the preset voltage can enable carriers to cross the carrier barrier at the interface between the P-type channel region 111 and the lower first oxide layer (tunneling oxide) 113 in the gate dielectric stack 112. For example, in the case where the P-type channel region 111 includes silicon and the first oxide layer 113 includes silicon dioxide, the carriers are holes and the hole barrier height is 4.8 electron volts (eV). In this case, the first erase voltage VE1 is generally greater than 4 volts (V). For example, the first erase voltage VE1 can be in the range of 3V to 6V, for example, the first erase voltage VE1 can be 4.6V. According to an embodiment of the present disclosure, the first erase voltage VE1 can be provided by an external constant voltage source.

[0070] According to an embodiment of the present disclosure, the second erase voltage VE2 may be equal to or higher than the second power supply voltage VSS, wherein the second power supply voltage VSS may be the ground voltage GND. For example, according to an embodiment of the present disclosure, the second erase voltage VE2 may be 0.2V.

[0071] According to an embodiment of the present disclosure, the third erase voltage VE3 may be equal to or lower than the second power supply voltage VSS. According to an embodiment of the present disclosure, the third erase voltage VE3 may be in the range of -8V to 0V. For example, according to an embodiment of the present disclosure, the third erase voltage VE3 may be -4.8V.

[0072] According to an embodiment of the present disclosure, the negative third erase voltage VE3 applied to the gate electrode 116 of the first storage transistor MS110 may cause the ionized hot holes ( Figure 3 The hollow circles in the figure represent holes) are attracted by the negative third erase voltage VE3 and injected into the storage dielectric layer 114, such as silicon nitride, in the gate dielectric stack 112 of the first storage transistor MS110 (such as Figure 3 The hot holes neutralize the electrons stored during the write (programming) operation of the flash memory cell MC100 ( Figure 3 The solid circles in the figure represent electrons), so that the threshold voltage of the first storage transistor MS110 decreases, thereby achieving erasure of the first storage transistor MS110.

[0073] According to an embodiment of the present disclosure, the fourth erase voltage VE4 may be equal to or lower than the first power voltage VDD, wherein the first power voltage VDD is higher than the second power voltage VSS, and may be in the range of 0.8 V to 5 V. For example, according to an embodiment of the present disclosure, the fourth erase voltage VE4 may be 1V.

[0074] According to an embodiment of the present disclosure, the first erase voltage VE1, the fourth erase voltage VE4 and the fifth erase voltage VE5 are higher than the second erase voltage VE2, so that the first storage transistor MS110, the second storage transistor MD130 and the gate transistor MG120 are all turned on, that is, the flash memory cell MC100 is turned on as a whole.

[0075] According to an embodiment of the present disclosure, the fifth erase voltage VE5 may be in the range of 3 V to 8 V. For example, according to an embodiment of the present disclosure, the fifth erase voltage VE5 may be 5V.

[0076] Similarly, according to the embodiments of the present disclosure, Figure 4 As shown, when an erase operation is performed on the second storage transistor MD130 of the flash memory cell MC100, the erase method according to the present disclosure includes applying a second power supply voltage VSS to the well region PW102, applying a first erase voltage VE1 to the second electrode D, applying a second erase voltage VE2 to the first electrode S, applying a fifth erase voltage VE5 to the gate electrode 116 of the first storage transistor MS110, applying a fourth erase voltage VE4 to the gate electrode 123 of the selection transistor MG120, and applying a third erase voltage VE3 to the gate electrode 136 of the second storage transistor MD130.

[0077] It can be seen that due to the symmetrical structure of the flash memory cell MC100, the erase voltages VE1 to VW5 applied during the erasing of the first storage transistor MS110 and the second storage transistor MD130 also have a symmetrical relationship. Therefore, for the sake of brevity, the erase voltage applied during the erasing of the second storage transistor MD130 is not repeatedly described here.

[0078] Specifically, taking the first storage transistor MS110 as an example, when the erasing operation is performed on the first storage transistor MS110, the gate electrode 123 of the selection transistor MG120 is applied with a fourth erasing voltage VE4 slightly higher than its threshold voltage, so it is in a weakly turned-on state, thereby suppressing the conduction current (generally in the microampere level) of the flash memory cell MC100, which can greatly reduce the voltage difference of the series channel (121 and 131) of the selection transistor MG120 and the second storage transistor MD130. Therefore, the voltage difference VE1-VE2 between the first electrode S and the second electrode D of the flash memory cell MC110 is mostly applied to the channel region 111 of the first storage transistor MS110, so that the channel hot electron induced hot hole injection physical effect occurs.

[0079] In particular, the erasing method according to the embodiment of the present disclosure is based on the physical effect of channel hot electron induced hot hole injection (Channel Hot Electron Induced Hot Hole Injection) first discovered by the inventor. Specifically, taking the erasing of the first storage transistor MS110 as an example, when the erasing operation is performed on the first storage transistor MS110, the gate transistor MG 120 and the second storage transistor MD 130 are turned on, and at the same time, the first erasing voltage VE1 applied to the first electrode 142 completely depletes the channel region 111 of the first storage transistor MS110 to form a depletion region, and the flash memory cell MC 100 is turned on as a whole, and an electron current is generated in the channel region and hot electrons are formed under the acceleration of the lateral electric field, and then electron-hole pairs are generated in the depletion region through impact ionization, and the hot holes are injected into the storage medium layer 114 of the first storage transistor MS110 under the attraction of the negative third erasing voltage VE3 applied to the gate electrode 116 of the first storage transistor MS110, thereby achieving the erasure of the first storage transistor MS110.

[0080] According to the embodiment of the present disclosure, when the erasing operation is performed on the first storage transistor MS110, since the fourth erasing voltage VE4 applied to the gate electrode 123 of the gate transistor MG120 and the erasing voltage VE5 applied to the gate electrode 136 of the second storage transistor MD130 are both higher than the second power supply voltage VSS, that is, the positive voltage, the second storage transistor MD130 and the gate transistor MG120 are turned on. In addition, according to the embodiment of the present disclosure, when the erasing operation is performed on the first storage transistor MS110, although the third erasing voltage VE3 applied to the gate electrode 116 of the first storage transistor MS110 is equal to or lower than the second power supply voltage VSS, as described above, due to the first erasing voltage VE1, the channel region 111 of the first storage transistor MS110 is completely depleted to form a depletion region, so that the first storage transistor MS110 is still turned on. Therefore, when the erasing method according to the embodiment of the present disclosure is performed, the flash memory cell MC100 is turned on as a whole.

[0081] Although in the above example, the first doping type is defined as P-type, and the second doping type is defined as N-type, so that the first storage transistor MS110, the gate transistor MG 120, and the second storage transistor MD 130 are all N-type transistors. However, those skilled in the art should recognize that the present disclosure is not limited to this, and the first doping type may also be N-type, and correspondingly the second doping type may be P-type, in which case the first storage transistor MS110, the gate transistor MG 120, and the second storage transistor MD 130 are all P-type transistors. In this case, the erasing method according to the embodiment of the present disclosure is based on the physical effect of channel hot hole induced hot electron injection (Channel Hot Hole Induced Hot Electron Injection), and its basic principle is consistent with the physical effect of channel hot electron induced hot hole injection described above, so it will not be described in more detail.

[0082] In addition, since the gate electrode length of the first storage transistor MS110 is much shorter than the equivalent channel length of the flash memory cell MC100, the lateral electric field of the conduction channel of the first storage transistor MS110 and the channel hot hole injection efficiency can be significantly increased.

[0083] Those skilled in the art will appreciate that although the above Figure 1 The flash memory cell MC 100 shown in the figure describes the erasing method of the flash memory cell of the present disclosure, but the erasing method of the flash memory cell of the present disclosure is not limited to Figure 1The flash memory cell MC 100 is shown. According to the teachings of the present disclosure, those skilled in the art may conceive to apply the flash memory cell erasing method of the present disclosure to other types of flash memory cells, such as a flash memory cell including only one storage transistor, and all these variations should be included in the scope of the present disclosure.

[0084] Figure 5 A cross-sectional view of a flash memory cell MC 200 according to another embodiment of the present disclosure is shown. Figure 6 An equivalent circuit diagram of a flash memory cell MC 200 according to another embodiment of the present disclosure is shown.

[0085] like Figure 5 and Figure 6 As shown, the flash memory unit MC 200 is similar to the above reference Figure 1 and Figure 2 The only difference between the described flash memory cell MC100 is that the flash memory cell MC200 includes only one storage transistor, which may correspond to the first storage transistor MS110 in the flash memory cell MC100, so that Figure 5 and Figure 6 In the flash memory cell MC 200 shown in FIG. Figure 1 and Figure 2 The same components of the illustrated flash memory unit MC 100 are denoted by the same reference numerals, and the corresponding detailed description will be omitted.

[0086] like Figure 5 As shown, a flash memory cell MC 200 according to another embodiment of the present disclosure may include a substrate 101 including a second doping type deep well region DNW 103 and a first doping type well region PW102 disposed on the deep well region DNW 103. According to an embodiment of the present disclosure, the substrate 101 may be, for example, a silicon (Si) substrate.

[0087] like Figure 5 and Figure 6 As shown, according to another embodiment of the present disclosure, the flash memory cell MC 200 includes a storage transistor MS110 and a gate transistor MG120 connected in series. The storage transistor MS110 may be disposed on the well region PW102 and store data DATA1. The gate transistor MG120 is disposed on the well region PW102 along the horizontal direction DR1 on one side of the storage transistor MS110 for performing a gate operation on the storage transistor MS110.

[0088] like Figure 5As shown, according to another embodiment of the present disclosure, the source region of the storage transistor MS110 is connected to the first electrode S of the flash memory cell MC 200, which can also be referred to as the source S of the flash memory cell MC 200, and the drain region of the selection transistor MG120 is connected to the second electrode D of the flash memory cell MC 200, which can also be referred to as the drain D of the flash memory cell MC 200.

[0089] like Figure 5 As shown, according to another embodiment of the present disclosure, the storage transistor MS110 has a gate structure including a channel region 111, a gate dielectric stack 112, a gate electrode 116 and a hard mask barrier 117 sequentially arranged along the vertical direction DR2. The gate dielectric stack 112 has a first oxide layer 113, a storage dielectric layer 114 and a second oxide layer 115 sequentially stacked along the vertical direction. According to an embodiment of the present disclosure, when the storage dielectric layer 114 is formed of, for example, a silicon nitride material, the first oxide layer 113, the storage dielectric layer 114 and the second oxide layer 115 can form a gate dielectric stack 112 as an ONO composite storage medium. In this case, the storage transistor MS110 can be a SONOS type storage transistor.

[0090] like Figure 5 As shown, according to another embodiment of the present disclosure, the gate structure of the gate transistor MG 120 may include a channel region 121 , a gate dielectric layer 122 , and a gate electrode 123 in sequence from bottom to top.

[0091] like Figure 5 As shown, according to another embodiment of the present disclosure, a source region 140 formed by N-type doping is provided at the first end of the flash memory cell MC 200, and a drain region 150 formed by N-type doping is also provided at the second end of the flash memory cell MC 200. The source region 140 is connected to a metal source electrode 142 located at an upper layer, that is, a first electrode S, through a contact hole 141, and the drain region 150 is connected to a metal drain electrode 152 located at an upper layer, that is, a second electrode D, through a contact hole 151.

[0092] like Figure 5 As shown, according to another embodiment of the present disclosure, the flash memory cell MC200 may further include an isolation portion 124 disposed between the storage transistor MS110 and the gate transistor MG120 along the horizontal direction DR1 for isolating the gate electrode 116 of the storage transistor MS110 and the gate electrode 123 of the gate transistor MG120.

[0093] Figure 7 FIG. 1 is a schematic diagram showing an erasing operation performed on the storage transistor MS110 by an erasing method according to another embodiment of the present disclosure.

[0094] Specifically, Figure 6As shown in FIG. 1 , the flash memory cell MC 200 includes a storage transistor MS110 and a gate transistor MG120 connected in series. The gate transistor MG120 can perform a gate operation on the storage transistor MS110. Figure 6 As shown in , by controlling the voltages applied to the source region (i.e., the first electrode S) of the storage transistor MS110, the gate electrode 116 of the storage transistor MS110, the gate electrode 123 of the selection transistor MG120, and the drain region (i.e., the second electrode D) of the selection transistor MG120, the erasing operation of the storage transistor MS110 can be achieved.

[0095] According to another embodiment of the present disclosure, when an erase operation is performed on the flash memory cell MC 200 , the well region PW 102 of the flash memory cell MC 200 may be grounded.

[0096] Specifically, according to another embodiment of the present disclosure, Figure 7 As shown, when performing an erase operation on the storage transistor MS110 of the flash memory cell MC200, the erase method according to the present disclosure includes applying the second power supply voltage VSS to the well region PW102, applying the first erase voltage VE1 to the first electrode S, applying the second erase voltage VE2 to the second electrode D, applying the third erase voltage VE3 to the gate electrode 116 of the storage transistor MS110, and applying the fourth erase voltage VE4 to the gate electrode 123 of the gate transistor MG120. For example, the second power supply voltage VSS may be a ground voltage GND, such as 0V.

[0097] According to another embodiment of the present disclosure, the first erase voltage VE1 may be higher than a preset voltage VP, wherein the preset voltage VP is preset according to the carrier barrier height at the interface between the substrate and the gate dielectric stack 112 of the storage transistor MS110. Figure 5 In the flash memory cell MC 200 shown, the preset voltage can enable holes to cross the hole barrier at the interface between the P-type channel region 111 and the lower first oxide layer (tunneling oxide) 113 in the gate dielectric stack 112. For example, in the case where the P-type channel region 111 includes silicon and the first oxide layer 113 includes silicon dioxide, the barrier height is 4.8 electron volts (eV). In this case, the first erase voltage VE1 is generally greater than 4 volts (V). For example, the first erase voltage VE1 can be in the range of 3V to 6V, for example, the first erase voltage VE1 can be 4.6V. According to an embodiment of the present disclosure, the first erase voltage VE1 can be provided by an external constant voltage source.

[0098] According to another embodiment of the present disclosure, the second erase voltage VE2 may be equal to or higher than the second power supply voltage VSS, wherein the second power supply voltage VSS may be the ground voltage GND. For example, according to an embodiment of the present disclosure, the second erase voltage VE2 may be 0.2V.

[0099] According to another embodiment of the present disclosure, the third erase voltage VE3 may be equal to or lower than the second power supply voltage VSS. According to an embodiment of the present disclosure, the third erase voltage VE3 may be in the range of -8V to 0V. For example, according to an embodiment of the present disclosure, the third erase voltage VE3 may be -4.8V.

[0100] According to another embodiment of the present disclosure, the negative third erase voltage VE3 applied to the gate electrode 116 of the storage transistor MS110 may cause the ionized hot holes ( Figure 7 The hollow circles in the figure represent holes) are attracted by the negative third erase voltage VE3 and injected into the storage dielectric layer 114, such as silicon nitride, in the gate dielectric stack 112 of the storage transistor MS110 (such as Figure 3 The hot holes neutralize the electrons stored during the write (program) operation of the flash memory cell MC 200 ( Figure 7 The solid circles in the figure represent electrons), so that the threshold voltage of the storage transistor MS110 decreases, thereby achieving erasure of the storage transistor MS110.

[0101] According to an embodiment of the present disclosure, the fourth erase voltage VE4 may be equal to or lower than the first power voltage VDD, wherein the first power voltage VDD is higher than the second power voltage VSS, and may be in the range of 0.8 V to 5 V. For example, according to an embodiment of the present disclosure, the fourth erase voltage VE4 may be 1V.

[0102] According to an embodiment of the present disclosure, the first erase voltage VE1 and the fourth erase voltage VE4 are higher than the second erase voltage VE2, so that the storage transistor MS110 and the gate transistor MG120 are both turned on, that is, the flash memory cell MC200 is turned on as a whole.

[0103] The erasing method according to another embodiment of the present disclosure is also based on the physical effect of channel hot electron induced hot hole injection (Channel Hot Electron Induced Hot Hole Injection) first discovered by the inventors, so for the sake of brevity, no further detailed description is given here.

[0104] The erasing method according to the embodiment of the present disclosure is based on the physical effect of channel hot electron induced hot hole injection first discovered by the inventors. Compared with the existing band-to-band tunneling hot hole (BBHH) erasing method, it has a wider hole distribution and higher injection efficiency, so that the erasing method according to the embodiment of the present disclosure has a higher erasing speed (tens of microseconds), a larger erasing window, smaller hot carrier damage, lower leakage current and higher endurance reliability.

[0105] Although the present disclosure has been described with reference to the embodiments thereof, it will be appreciated by those skilled in the art that various modifications and changes may be made to the present disclosure without departing from the spirit and scope of the present disclosure as disclosed in the appended claims.

Claims

1. A method for erasing a flash memory unit, the flash memory unit comprising: a substrate and a well region disposed in the substrate; a storage transistor disposed on the well region and configured to store data; as well as a gating transistor, arranged on the well region along a horizontal direction on one side of the storage transistor, and configured to perform a gating operation on the storage transistor, wherein the gate transistor and the storage transistor are connected in series, The source region of the storage transistor is connected to the first electrode of the flash memory unit, and the drain region of the selection transistor is connected to the second electrode of the flash memory unit. The erasing method comprises: performing an erase operation on the memory transistor by applying a second power supply voltage to the well region, applying a first erase voltage to the first electrode, applying a second erase voltage to the second electrode, applying a third erase voltage to the gate electrode of the memory transistor, and applying a fourth erase voltage to the gate electrode of the selection transistor, wherein the first erase voltage is higher than a preset voltage, the second erase voltage is equal to or higher than the second power supply voltage, the third erase voltage is equal to or lower than the second power supply voltage, and the fourth erase voltage is equal to or lower than the first power supply voltage, wherein the first power supply voltage is higher than the second power supply voltage, The preset voltage is preset according to the carrier barrier height at the interface between the substrate and the gate dielectric stack of the storage transistor, and The first erasing voltage and the fourth erasing voltage are higher than the second erasing voltage, so that the storage transistor and the gate transistor are both turned on.

2. A method for erasing a flash memory unit, the flash memory unit comprising: a substrate and a well region disposed in the substrate; a first storage transistor disposed on the well region and configured to store first data; a second storage transistor disposed on the well region and configured to store second data; as well as a gating transistor, disposed between the first storage transistor and the second storage transistor in a horizontal direction on the well region, configured to isolate the first storage transistor and the second storage transistor and perform a gating operation on the first storage transistor and the second storage transistor, The first storage transistor, the selection transistor and the second storage transistor are connected in series in sequence. The source region of the first storage transistor is connected to the first electrode of the flash memory unit, and the drain region of the second storage transistor is connected to the second electrode of the flash memory unit. The erasing method includes: performing an erase operation on the first storage transistor or the second storage transistor by applying a second power supply voltage to the well region, applying a first erase voltage to the first electrode or the second electrode, applying a second erase voltage to the second electrode or the first electrode, applying a third erase voltage to a gate electrode of the first storage transistor or the second storage transistor, applying a fourth erase voltage to a gate electrode of the selection transistor, and applying a fifth erase voltage to a gate electrode of the second storage transistor or the first storage transistor, wherein the first erase voltage is higher than a preset voltage, the second erase voltage is equal to or higher than the second power supply voltage, the third erase voltage is equal to or lower than the second power supply voltage, and the fourth erase voltage is equal to or lower than the first power supply voltage, wherein the first power supply voltage is higher than the second power supply voltage, The preset voltage is preset according to the carrier barrier height at the interface between the substrate and the gate dielectric stack of the first storage transistor and the second storage transistor, and The first erasure voltage, the fourth erasure voltage, and the fifth erasure voltage are higher than the second erasure voltage, so that the first storage transistor, the second storage transistor, and the selection transistor are all turned on.

3. The erasing method according to claim 1 or 2, wherein: The erasing method is based on the physical effect of hot hole injection induced by channel hot electrons.

4. The erasing method according to claim 1 or 2, wherein: The storage transistor is a charge trapping storage transistor, and its gate dielectric stack comprises a tunneling oxide layer, a charge storage layer and a blocking oxide layer.

5. The erasing method according to claim 4, wherein: The thickness of the tunnel oxide layer is 1 to 6 nm.

6. The erasing method according to claim 4, wherein: The charge storage layer includes one or more oxides, one or more nitrides, one or more oxynitrides, polysilicon or nanocrystalline materials, or a combination of the above materials.

7. The erasing method according to claim 4, wherein: The charge storage layer includes a high-K material rich in charge traps.

8. The erasing method according to claim 4, wherein: The tunneling oxide layer and the blocking oxide layer include silicon oxide or aluminum oxide.

9. The erasing method according to claim 1, wherein: The first power supply voltage is in the range of 0.8V to 5V, The second power supply voltage is a ground voltage, The first erase voltage is in the range of 3V to 6V, and The third erase voltage is in the range of -8V to 0V.

10. The erasing method according to claim 2, wherein: The first power supply voltage is in the range of 0.8V to 5V, The second power supply voltage is a ground voltage, The first erase voltage is in the range of 3V to 6V, The third erase voltage is in the range of -8V to 0V, and The fifth erase voltage is in the range of 3V to 8V.

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