High electron mobility transistor and preparation method thereof
By setting a passivation layer between the barrier layer of the HEMT and forming a through hole, the problems of cap element penetration and etching damage are solved, and the performance and quality of HEMT are improved.
Patent Information
- Application Number
- CN202411220994.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-02
- Publication Date
- 2025-02-28
AI Technical Summary
During the formation of a high electron mobility transistor (HEMT), elements in the cap layer are prone to penetrate into the barrier layer and channel layer, affecting the HEMT performance, and easily damage the barrier layer when etching the cap layer, resulting in poor HEMT quality.
By providing a passivation layer between the barrier layer and the cap layer, and forming a through hole exposed on the passivation layer, the cap layer is connected to the barrier layer through the through hole, thereby reducing the risk of elemental penetration and etching damage.
The probability of cap element penetration into the barrier layer and channel layer is effectively reduced, the performance of HEMT is improved, and the etching damage is reduced by protecting the barrier layer, thereby improving the quality of HEMT.
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Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a high electron mobility transistor and a method for preparing the same. Background Art
[0002] High Electron Mobility Transistor (HEMT) is a heterojunction field effect transistor that is widely used in various electrical appliances.
[0003] In the related art, HEMT includes a substrate, a channel layer, a barrier layer, a cap layer and a passivation layer, wherein the substrate, the channel layer, the barrier layer and the cap layer are stacked in sequence, and the passivation layer is located on the surface of the cap layer away from the barrier layer and the surface of the barrier layer away from the channel layer.
[0004] However, since the channel layer, barrier layer and cap layer are stacked in sequence, the elements in the cap layer are easily infiltrated into the barrier layer and the channel layer during the formation of the cap layer, thus affecting the performance of the HEMT. In addition, during the process of etching the cap layer, the barrier layer is easily etched and damaged, resulting in poor quality of the HEMT. Summary of the invention
[0005] The embodiments of the present disclosure provide a high electron mobility transistor and a method for manufacturing the same, which can ensure good performance of the HEMT and improve the quality of the HEMT. The technical solution is as follows:
[0006] On the one hand, a high electron mobility transistor is provided, comprising a substrate, a channel layer, a barrier layer, a passivation layer and a cap layer, wherein the substrate, the channel layer, the barrier layer and the passivation layer are stacked in sequence, and the passivation layer has a through hole exposing the barrier layer; the cap layer is located on a surface of the passivation layer away from the barrier layer, and is connected to the barrier layer through the through hole.
[0007] Optionally, an orthographic projection of an opening of the through hole close to the barrier layer on the barrier layer is located inside an orthographic projection of an opening of the through hole far from the barrier layer on the barrier layer.
[0008] Optionally, the passivation layer has a thickness of 100 nm to 200 nm.
[0009] Optionally, the cap layer has a thickness of 150 nm to 250 nm.
[0010] Optionally, the high electron mobility transistor further includes a gate electrode layer, and the gate electrode layer is located on a surface of the cap layer away from the barrier layer.
[0011] Optionally, the high electron mobility transistor also includes a source electrode layer and a drain electrode layer, the source electrode layer and the drain electrode layer are located on a surface of the passivation layer away from the barrier layer, the source electrode layer penetrates the passivation layer and the barrier layer and is connected to the channel layer, and the drain electrode layer penetrates the passivation layer and the barrier layer and is connected to the channel layer.
[0012] On the other hand, a method for preparing a high electron mobility transistor is provided, comprising: forming a channel layer and a barrier layer in sequence on a substrate; forming a passivation layer on the barrier layer, the passivation layer having a through hole exposing the barrier layer; forming a cap layer on the passivation layer, the cap layer being connected to the barrier layer through the through hole.
[0013] Optionally, forming a passivation layer on the barrier layer comprises: forming a passivation material layer on the barrier layer; and wet-etching the passivation material layer to form the through hole exposing the barrier layer, thereby obtaining the passivation layer.
[0014] Optionally, the growth pressure of the passivation material layer is 25 Torr to 100 Torr.
[0015] Optionally, forming a cap layer on the passivation layer includes: sequentially forming a GaN material layer and a gate electrode material layer on the passivation layer; and etching the GaN material layer and the gate electrode material layer to obtain the cap layer and the gate electrode layer.
[0016] The technical solution provided by the embodiments of the present disclosure brings the following beneficial effects:
[0017] In the disclosed embodiment, the passivation layer is disposed between the barrier layer and the cap layer, the passivation layer has a through hole exposing the barrier layer, the cap layer is located on the surface of the passivation layer away from the barrier layer, and is connected to the barrier layer through the through hole. In the process of forming the cap layer, the passivation layer can reduce the probability of the elements in the cap layer penetrating into the barrier layer and the channel layer and affecting the performance of the HEMT, thereby ensuring that the performance of the HEMT is good. In addition, the passivation layer can also protect the barrier layer, reduce the probability of etching damage to the barrier layer in the process of etching to form the cap layer, thereby improving the quality of the HEMT. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0019] Figure 1 is a structural schematic diagram of a HEMT provided by an embodiment of the present disclosure;
[0020] Figure 2 is a top view of a HEMT provided by an embodiment of the present disclosure;
[0021] Figure 3 is a flow chart of a method for preparing a HEMT provided in an embodiment of the present disclosure;
[0022] Figure 4 is a flow chart of another method for preparing HEMT provided in an embodiment of the present disclosure;
[0023] Figure 5 It is a structural schematic diagram of a HEMT preparation process provided by an embodiment of the present disclosure.
[0024] Reference numerals:
[0025] 10: channel layer; 20: barrier layer; 30: passivation layer; 31: through hole; 40: cap layer; 41: GaN material layer; 50: gate electrode layer; 51: gate electrode material layer; 60: substrate; 70: source electrode layer; 80: drain electrode layer; 90: first groove; 91: second groove. DETAILED DESCRIPTION
[0026] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.
[0027] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second", "third" and similar words used in the patent application specification and claims of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantitative limitation, but indicate the existence of at least one. Words such as "include" and similar words mean that the elements or objects appearing before "include" include the elements or objects listed after "include" and their equivalents, and do not exclude other elements or objects. Words such as "connect" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", etc. are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.
[0028] Figure 1 Schematic diagram of the structure of a HEMT provided by an embodiment of the present disclosure. Figure 1As shown, the HEMT includes a substrate 60, a channel layer 10, a barrier layer 20, a passivation layer 30 and a cap layer 40. The substrate 60, the channel layer 10, the barrier layer 20 and the passivation layer 30 are stacked in sequence, and the passivation layer 30 has a through hole 31 exposing the barrier layer 20. The cap layer 40 is located on a surface of the passivation layer 30 away from the barrier layer 20, and is connected to the barrier layer 20 through the through hole 31.
[0029] In the embodiment of the present disclosure, the passivation layer 30 is disposed between the barrier layer 20 and the cap layer 40, and the passivation layer 30 has a through hole 31 exposing the barrier layer 20. The cap layer 40 is located on the surface of the passivation layer 30 away from the barrier layer 20, and is connected to the barrier layer 20 through the through hole 31. In the process of forming the cap layer 40, the passivation layer 30 can reduce the probability of the elements in the cap layer 40 penetrating into the barrier layer 20 and the channel layer 10 and affecting the performance of the HEMT, thereby ensuring that the performance of the HEMT is good. In addition, the passivation layer 30 can also protect the barrier layer 20, reduce the probability of etching damage to the barrier layer 20 in the process of etching to form the cap layer 40, thereby improving the quality of the HEMT.
[0030] In the embodiment of the present disclosure, the HEMT may be an enhanced HEMT. The working principle of the HEMT is: by utilizing the piezoelectric effect and polarization effect of the channel layer 10 and the barrier layer 20, a high-mobility two-dimensional electron gas can be generated at the interface of the channel layer 10 and the barrier layer 20, and the concentration of the two-dimensional electron gas can be controlled by controlling the voltage of the gate electrode set on the cap layer 40 to achieve the conduction or shutdown of the HEMT. When the voltage of the gate electrode is less than or equal to the threshold voltage, the enhanced HEMT is in the off state, and when the voltage of the gate electrode is greater than the threshold voltage, the enhanced HEMT is in the on state.
[0031] Optionally, the substrate 60 is a GaN substrate, a sapphire substrate, a Si substrate or a SiC substrate.
[0032] In the disclosed embodiment, the substrate 60 is a sapphire substrate, which has high mechanical strength and is easy to handle and clean.
[0033] In a possible implementation, the HEMT further includes a nucleation layer and a buffer layer, which are located between the substrate 60 and the channel layer 10 and are stacked in sequence in a direction away from the substrate 60. The nucleation layer can alleviate the lattice mismatch of the HEMT and reduce the dislocation density of the HEMT, and the buffer layer can reduce the thermal mismatch stress between the substrate 60 and the semiconductor material, thereby ensuring good quality of the HEMT.
[0034] Optionally, the nucleation layer is an AlN nucleation layer.
[0035] Exemplarily, the nucleation layer includes a low-temperature AlN nucleation layer and a high-temperature AlN nucleation layer stacked in a direction away from the substrate 60 .
[0036] Exemplarily, the thickness of the nucleation layer is 10 nm to 300 nm.
[0037] Optionally, the buffer layer is a GaN buffer layer.
[0038] Exemplarily, the thickness of the buffer layer is 100 nm to 5000 nm.
[0039] In other embodiments, the buffer layer may include an AlGaN buffer layer and a GaN buffer layer sequentially stacked in a direction away from the substrate 60 , which is not limited in the present disclosure.
[0040] Optionally, the channel layer 10 includes a GaN channel layer.
[0041] Exemplarily, the thickness of the channel layer 10 is 500 nm to 1500 nm. For example, the thickness of the channel layer 10 may be 500 nm, 1000 nm, or 1500 nm.
[0042] Optionally, the barrier layer 20 includes an AlGaN barrier layer.
[0043] Exemplarily, the thickness of the barrier layer 20 is 200 nm to 400 nm. For example, the thickness of the barrier layer 20 may be 200 nm, 300 nm, or 400 nm.
[0044] Optionally, the passivation layer 30 includes at least one of a SiN layer and a SiO2 layer. Both the SiN layer and the SiO2 layer have good passivation effects, so that the passivation layer 30 can better protect the barrier layer 20, can effectively reduce the probability of the elements in the cap layer 40 penetrating into the barrier layer 20 and the channel layer 10 and affecting the performance of the HEMT, and can also effectively reduce the probability of etching damage to the barrier layer 20 during the process of etching to form the cap layer 40, which is beneficial to reducing parasitic capacitance, improving the current collapse effect of the HEMT, and improving the reliability and performance of the HEMT.
[0045] In addition, both the SiN layer and the SiO2 layer are easy to etch by wet etching. In this way, when forming the passivation layer 30, the through hole 31 can be formed by wet etching. The wet etching process will not cause etching damage to the barrier layer 20 under the passivation layer 30, thereby further improving the quality of the HEMT.
[0046] By way of example, the passivation layer 30 may be a SiN layer.
[0047] Optionally, the thickness of the passivation layer 30 is 100 nm to 200 nm. If the thickness of the passivation layer 30 is too small, the passivation layer 30 cannot play a good passivation effect to protect the HEMT, and cannot play a good effect of reducing the probability of etching damage to the barrier layer 20; if the thickness of the passivation layer 30 is too large, it may cause material waste and increase production costs. When the thickness of the passivation layer 30 is within this range, the passivation layer 30 can effectively reduce the elements in the cap layer 40 from penetrating into the barrier layer 20 and the channel layer 10 and affecting the performance of the HEMT, and reduce the probability of etching damage to the barrier layer 20, thereby improving the performance and reliability of the HEMT without increasing additional production costs.
[0048] For example, the thickness of the passivation layer 30 may be 150 nm to 200 nm. For example, the thickness of the passivation layer 30 may be 150 nm, 175 nm, or 200 nm.
[0049] In the related art, the thickness of the passivation layer is relatively small. In the embodiment of the present disclosure, affected by the accuracy of the etching process, during the process of etching to form the cap layer 40, the passivation layer 30 may be etched to a certain depth to protect the barrier layer 20. Therefore, the thickness of the passivation layer 30 is within the above larger thickness range, which can play an effective protective role without increasing additional production costs, thereby reducing the probability of etching damage to the barrier layer 20.
[0050] Optionally, the opening areas of the through holes 31 are different.
[0051] Exemplarily, the orthographic projection of the opening of the through hole 31 close to the barrier layer 20 on the barrier layer 20 is located inside the orthographic projection of the opening of the through hole 31 away from the barrier layer 20 on the barrier layer 20. In this way, the cap layer 40 can better cover the through hole 31, form a reliable connection with the barrier layer 20 through the through hole 31, reduce the probability of the cap layer 40 falling off, and improve the reliability of the HEMT. In addition, the opening area of the through hole 31 close to the barrier layer 20 is small, which can further reduce the probability of the elements in the cap layer 40 penetrating into the barrier layer 20 and the channel layer 10 and affecting the performance of the HEMT.
[0052] Optionally, the cap layer 40 is a P-type GaN layer. In this way, the cap layer 40 can realize the zero bias shutdown function of the enhanced HEMT, and the cap layer 40 can increase the concentration of the two-dimensional electron gas, improve the dynamic characteristics of the HEMT, and also improve the anti-breakdown performance of the HEMT and improve the reliability of the HEMT.
[0053] For example, the cap layer 40 is a Mg-doped GaN layer. When the cap layer 40 is a Mg-doped GaN layer, the passivation layer 30 can reduce the probability that Mg and Ga in the cap layer 40 penetrate into the barrier layer 20 and the channel layer 10 and affect the performance of the HEMT.
[0054] Optionally, the thickness of the cap layer 40 is 150 nm to 250 nm. When the thickness of the cap layer 40 is within this range, the cap layer 40 can effectively improve the dynamic characteristics of the HEMT, improve the breakdown resistance of the HEMT, and thus improve the performance and reliability of the HEMT.
[0055] By way of example, the thickness of the cap layer 40 may be 150 nm, 200 nm, or 250 nm.
[0056] Figure 2 FIG. 1 is a top view of a HEMT provided by an embodiment of the present disclosure. Figure 1 and Figure 2 As shown, the orthographic projection of the through hole 31 on the barrier layer 20 is located inside the orthographic projection of the cap layer 40 on the barrier layer 20 .
[0057] Exemplarily, the cap layer 40 is in the shape of a prism with a T-shaped cross section.
[0058] Optionally, the HEMT further includes a gate electrode layer 50, which is located on a surface of the cap layer 40 away from the barrier layer 20. The gate electrode layer 50 can be connected to an external power source, which is beneficial for controlling the voltage of the gate electrode layer 50 to realize the on or off function of the HEMT.
[0059] Optionally, the gate electrode layer 50 includes at least one of a TiN layer, a Ni layer, an Au layer, a Pt layer, a W layer, and a Pd layer.
[0060] Exemplarily, the gate electrode layer 50 may be a TiN layer.
[0061] Exemplarily, the thickness of the gate electrode layer 50 is 150 nm to 250 nm. For example, the thickness of the gate electrode layer 50 may be 150 nm, 200 nm, or 250 nm.
[0062] like Figure 1 and Figure 2 As shown, the orthographic projection of the gate electrode layer 50 on the barrier layer 20 is located inside the orthographic projection of the cap layer 40 on the barrier layer 20 .
[0063] Exemplarily, the gate electrode layer 50 is in the shape of a quadrangular prism, and the shape of the cross section in the length direction of the quadrangular prism is a trapezoid.
[0064] Optionally, the HEMT further includes a source electrode layer 70 and a drain electrode layer 80, the source electrode layer 70 and the drain electrode layer 80 are located on the surface of the passivation layer 30 away from the barrier layer 20, the source electrode layer 70 penetrates the passivation layer 30 and the barrier layer 20 and is connected to the channel layer 10, and the drain electrode layer 80 penetrates the passivation layer 30 and the barrier layer 20 and is connected to the channel layer 10. The source electrode layer 70 and the drain electrode layer 80 can be connected to an external power source, and cooperate with the gate electrode layer 50 to realize various functions of the HEMT, such as current amplification function and switching function.
[0065] Exemplarily, the orthographic projections of the source electrode layer 70 and the drain electrode layer 80 on the barrier layer 20 are respectively located on both sides of the orthographic projection of the cap layer 40 on the barrier layer 20 . Figure 2 In the figure, the orthographic projection of the source electrode layer 70 in the top view is located on the left side of the orthographic projection of the cap layer 40 in the top view, and the orthographic projection of the drain electrode layer 80 in the top view is located on the right side of the orthographic projection of the cap layer 40 in the top view.
[0066] like Figure 1 As shown, the channel layer 10, the barrier layer 20 and the passivation layer 30 have a first groove 90 and a second groove 91. The first groove 90 penetrates the passivation layer 30 and the barrier layer 20 and extends to below the interface between the channel layer 10 and the barrier layer 20. The second groove 91 penetrates the passivation layer 30 and the barrier layer 20 and extends to below the interface between the channel layer 10 and the barrier layer 20.
[0067] Exemplarily, the source electrode layer 70 is connected to the channel layer 10 through the first groove 90 , and the drain electrode layer 80 is connected to the channel layer 10 through the second groove 91 .
[0068] Since a two-dimensional electron gas is formed at the interface between the channel layer 10 and the barrier layer 20, and the two-dimensional electron gas is located in the channel layer 10, the first groove 90 and the second groove 91 extend below the interface between the channel layer 10 and the barrier layer 20, so that the source electrode layer 70 and the drain electrode layer 80 can directly contact the two-dimensional electron gas, thereby improving the ohmic contact effect of the source electrode layer 70 and the drain electrode layer 80.
[0069] Optionally, the source electrode layer 70 and the drain electrode layer 80 each include at least one of a TiN layer, a Ni layer, an Au layer, a Pt layer, a W layer, and a Pd layer.
[0070] Exemplarily, the source electrode layer 70 and the drain electrode layer 80 are prism-shaped with a T-shaped cross section.
[0071] Exemplarily, the length directions of the gate electrode layer 50 , the source electrode layer 70 , and the drain electrode layer 80 are parallel to each other.
[0072] It should be noted that Figure 1 and Figure 2 The film layer structure of the HEMT shown and the materials of the above film layers are only used as an example. In other embodiments, the HEMT may also include more or fewer film layer structures, and the materials of each film layer may be selected according to actual needs, etc., and the disclosure does not impose any limitation on this.
[0073] Figure 3 is a flow chart of a method for preparing a HEMT provided by an embodiment of the present disclosure. Figure 3 As shown, the preparation method comprises:
[0074] In step S101 , a channel layer and a barrier layer are sequentially formed on a substrate.
[0075] In step S102 , a passivation layer is formed on the barrier layer.
[0076] The passivation layer has a through hole exposing the barrier layer.
[0077] In step S103 , a cap layer is formed on the passivation layer.
[0078] The cap layer is connected to the barrier layer through a through hole.
[0079] In the disclosed embodiment, the passivation layer is disposed between the barrier layer and the cap layer, the passivation layer has a through hole exposing the barrier layer, the cap layer is located on the surface of the passivation layer away from the barrier layer, and is connected to the barrier layer through the through hole. In the process of forming the cap layer, the passivation layer can reduce the probability of the elements in the cap layer penetrating into the barrier layer and the channel layer and affecting the performance of the HEMT, thereby ensuring that the performance of the HEMT is good. In addition, the passivation layer can also protect the barrier layer, reduce the probability of etching damage to the barrier layer in the process of etching to form the cap layer, thereby improving the quality of the HEMT.
[0080] Figure 4 FIG. 1 is a flow chart of another method for preparing a HEMT provided in an embodiment of the present disclosure. Figure 4 As shown, the preparation method comprises:
[0081] In step S201 , a channel layer is formed on a substrate.
[0082] Optionally, before performing step S201, the preparation method further includes: placing the substrate in a metal-organic chemical vapor deposition (MOCVD) reaction chamber to clean the substrate surface. Exemplarily, the oxide on the substrate surface can be decomposed using hydrogen under high temperature conditions.
[0083] Illustratively, the substrate may be a sapphire substrate.
[0084] Exemplarily, the channel layer may be a GaN channel layer.
[0085] Optionally, in step S201, the temperature of the reaction chamber can be controlled to be 900° C. to 1100° C., the growth pressure can be 25 Torr to 100 Torr, NH 3 and TMGa can be introduced, and the growth time can be 25 min to 35 min to form a GaN channel layer on the substrate to obtain a channel layer.
[0086] Exemplarily, the temperature of the reaction chamber can be controlled to be 1000° C., the growth pressure can be 50 Torr, NH 3 and TMGa can be introduced, the growth time can be 30 min, and a GaN channel layer with a thickness of 1000 nm can be formed on the substrate to obtain a channel layer.
[0087] Optionally, before forming the channel layer, the preparation method may further include: sequentially forming a nucleation layer and a buffer layer on the substrate.
[0088] Exemplarily, the nucleation layer may be an AlN nucleation layer.
[0089] Exemplarily, the buffer layer may be a GaN buffer layer.
[0090] In step S202 , a barrier layer is formed on the channel layer.
[0091] Exemplarily, the barrier layer may be an AlGaN barrier layer.
[0092] Optionally, in step S202, the temperature of the reaction chamber can be controlled to be 900° C. to 1000° C., the growth pressure can be 25 Torr to 100 Torr, TMAl, NH 3 and TMGa can be introduced, the growth time can be 25 min to 35 min, and an AlGaN barrier layer can be formed on the channel layer to obtain a barrier layer.
[0093] Exemplarily, the temperature of the reaction chamber can be controlled to 950° C., the growth pressure to 50 Torr, TMAl, NH 3 and TMGa to be introduced, the growth time to be 30 min, and an AlGaN barrier layer with a thickness of 300 nm is formed on the channel layer to obtain a barrier layer.
[0094] Through the above steps S201 to S202 , a channel layer and a barrier layer can be formed in sequence on the substrate.
[0095] In step S203 , a passivation layer is formed on the barrier layer.
[0096] Optionally, step S203 may include the following steps:
[0097] In the first step, a passivation material layer is formed on the barrier layer.
[0098] Exemplarily, the passivation material layer may be a SiN layer.
[0099] Optionally, a low pressure chemical vapor deposition (LPCVD) technique may be used to form a SiN layer on the barrier layer to obtain a passivation material layer.
[0100] Optionally, the growth temperature of the passivation material layer is 700° C. to 900° C. For example, the growth temperature of the passivation material layer may be 700° C., 800° C., or 900° C., etc.
[0101] Optionally, the growth pressure of the passivation material layer is 25 Torr to 100 Torr. In this way, by growing the passivation material layer by LPCVD in a relatively low pressure range, the film quality of the passivation material layer can be improved, so that the passivation layer has a better passivation effect, thereby reducing the probability of the elements in the cap layer penetrating into the barrier layer and the channel layer in the subsequent process steps and affecting the performance of the HEMT, and reducing the probability of etching damage to the barrier layer during the process of etching to form the cap layer, thereby improving the performance and reliability of the HEMT.
[0102] For example, the growth pressure of the passivation material layer may be 25 Torr, 50 Torr, or 100 Torr, etc.
[0103] Optionally, the growth time of the passivation material layer is 25 min to 35 min. Exemplarily, the growth time of the passivation material layer can be 25 min, 30 min or 35 min, etc.
[0104] Exemplarily, the product obtained in step S202 can be transferred to a LPCVD reaction chamber, the temperature of the reaction chamber is controlled to be 800°C, the growth pressure is 50 Torr, NH3 and dichlorosilane are introduced, the growth time is 30 minutes, and a SiN layer with a thickness of 150 nm is formed on the barrier layer to obtain a passivation material layer.
[0105] In the second step, the passivation material layer is wet-etched to form a through hole exposing the barrier layer, thereby obtaining a passivation layer.
[0106] Dry etching easily causes etching damage to the barrier layer. Compared with dry etching, the etching solution used in the wet etching process will not produce an etching effect on the barrier layer, thereby preventing etching damage to the barrier layer and helping to improve the quality of HEMT.
[0107] In step S204 , a GaN material layer and a gate electrode material layer are sequentially formed on the passivation layer.
[0108] Exemplarily, the GaN material layer may be a P-type GaN layer. For example, the GaN material layer may be a Mg-doped GaN layer.
[0109] Figure 5 Schematic diagram of a HEMT manufacturing process provided by an embodiment of the present disclosure. Figure 5As shown, the product obtained in step S203 can be transferred to a MOCVD reaction chamber, the temperature of the reaction chamber is controlled to be 900°C to 1000°C, the growth pressure is 25 Torr to 100 Torr, NH3, TMGa and Cp2Mg are introduced, the growth time is 15 min to 25 min, and a Mg-doped GaN layer is formed on the passivation layer 30 to obtain a GaN material layer 41.
[0110] For example, the temperature of the reaction chamber can be controlled to be 950° C., the growth pressure can be 50 Torr, NH3, TMGa and Cp2Mg can be introduced, the growth time can be 20 min, and a Mg-doped GaN layer with a thickness of 200 nm can be formed on the passivation layer 30 to obtain the GaN material layer 41. Since the passivation layer 30 is provided between the GaN material layer 41 and the barrier layer 20, the contact area between the GaN material layer 41 and the barrier layer 20 is reduced, so the passivation layer 30 can reduce the probability that Mg and Ga in the GaN material layer 41 penetrate into the barrier layer 20 and the channel layer 10 and affect the performance of the HEMT.
[0111] Exemplarily, the gate electrode material layer 51 may be a TiN layer.
[0112] Exemplarily, an electron beam evaporation technique may be used to form a TiN layer with a thickness of 200 nm on the GaN material layer 41 to obtain the gate electrode material layer 51 .
[0113] In step S205 , the GaN material layer and the gate electrode material layer are etched to obtain a cap layer and a gate electrode layer.
[0114] For example, a photoresist structure can be obtained on the gate electrode material layer 51 by photoresist coating, exposure, development and other processes, and the GaN material layer 41 and the gate electrode material layer 51 are etched by dry etching using the photoresist structure as a mask, and the photoresist layer is removed to obtain the following: Figure 1 The cap layer 40 and the gate electrode layer 50 are shown. The cap layer 40 is connected to the barrier layer 20 through the through hole 31, and the gate electrode layer 50 is located on the surface of the cap layer 40 away from the barrier layer 20. In this way, the cap layer 40 and the gate electrode layer 50 can be formed by a single photolithography process, which is conducive to simplifying the process steps and improving production efficiency. The passivation layer 30 can protect the barrier layer 20 and reduce the probability of etching damage to the barrier layer 20 during the process of forming the cap layer 40 by dry etching, thereby improving the quality of the HEMT.
[0115] Exemplarily, the orthographic projection of the through hole 31 on the barrier layer 20 is located inside the orthographic projection of the cap layer 40 on the barrier layer 20 .
[0116] Exemplarily, the orthographic projection of the gate electrode layer 50 on the barrier layer 20 is located inside the orthographic projection of the cap layer 40 on the barrier layer 20 .
[0117] Through the above steps S204 to S205 , a cap layer and a gate electrode layer can be formed on the passivation layer.
[0118] Optionally, after completing steps S201 to S205, the method may further include:
[0119] In step S206 , a first groove and a second groove are formed in the channel layer, the barrier layer and the passivation layer.
[0120] Illustratively, a photoresist structure can be obtained on the passivation layer by processes such as photoresist coating, exposure, and development, and the passivation layer, barrier layer, and channel layer can be etched by dry etching using the photoresist structure as a mask to form a first groove and a second groove, wherein the first groove penetrates the passivation layer and the barrier layer and extends to below the interface between the channel layer and the barrier layer, and the second groove penetrates the passivation layer and the barrier layer and extends to below the interface between the channel layer and the barrier layer.
[0121] In step S207 , a source electrode layer and a drain electrode layer are formed on the passivation layer.
[0122] Exemplarily, a photoresist structure can be obtained on the passivation layer through processes such as photoresist coating, exposure, and development, and a source electrode layer and a drain electrode layer are formed by an electron beam evaporation process and a stripping process using the photoresist structure as a mask. The source electrode layer is connected to the channel layer through a first groove, and the drain electrode layer is connected to the channel layer through a second groove.
[0123] Exemplarily, the orthographic projections of the source electrode layer and the drain electrode layer on the barrier layer are respectively located on both sides of the orthographic projection of the cap layer on the barrier layer.
[0124] The above description does not limit the present disclosure in any form. Although the present disclosure has been disclosed as above through the embodiments, it is not used to limit the present disclosure. Any technician familiar with the profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical contents disclosed above without departing from the scope of the technical solution of the present disclosure. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present disclosure without departing from the content of the technical solution of the present disclosure still falls within the scope of the technical solution of the present disclosure.
Claims
1. A high electron mobility transistor, characterized in that: The invention comprises a substrate (60), a channel layer (10), a barrier layer (20), a passivation layer (30) and a cap layer (40), The substrate (60), the channel layer (10), the barrier layer (20) and the passivation layer (30) are stacked in sequence, and the passivation layer (30) has a through hole (31) exposing the barrier layer (20); The cap layer (40) is located on a surface of the passivation layer (30) away from the barrier layer (20), and is connected to the barrier layer (20) through the through hole (31).
2. The high electron mobility transistor according to claim 1, characterized in that: The orthographic projection of the opening of the through hole (31) close to the barrier layer (20) on the barrier layer (20) is located inside the orthographic projection of the opening of the through hole (31) far from the barrier layer (20) on the barrier layer (20).
3. The high electron mobility transistor according to claim 1 or 2, characterized in that: The thickness of the passivation layer (30) is 100 nm to 200 nm.
4. The high electron mobility transistor according to claim 1 or 2, characterized in that: The cap layer (40) has a thickness of 150 nm to 250 nm.
5. The high electron mobility transistor according to claim 1 or 2, characterized in that: The high electron mobility transistor further comprises a gate electrode layer (50), wherein the gate electrode layer (50) is located on a surface of the cap layer (40) away from the barrier layer (20).
6. The high electron mobility transistor according to claim 1 or 2, characterized in that: The high electron mobility transistor further comprises a source electrode layer (70) and a drain electrode layer (80); the source electrode layer (70) and the drain electrode layer (80) are located on a surface of the passivation layer (30) away from the barrier layer (20); the source electrode layer (70) penetrates the passivation layer (30) and the barrier layer (20) to be connected to the channel layer (10); and the drain electrode layer (80) penetrates the passivation layer (30) and the barrier layer (20) to be connected to the channel layer (10).
7. A method for preparing a high electron mobility transistor, characterized in that: include: A channel layer (10) and a barrier layer (20) are sequentially formed on a substrate (60); forming a passivation layer (30) on the barrier layer (20), wherein the passivation layer (30) has a through hole (31) exposing the barrier layer (20); A cap layer (40) is formed on the passivation layer (30), and the cap layer (40) is connected to the barrier layer (20) through the through hole (31).
8. The preparation method according to claim 7, characterized in that: The step of forming a passivation layer (30) on the barrier layer (20) comprises: forming a passivation material layer on the barrier layer (20); The passivation material layer is wet-etched to form the through hole (31) exposing the barrier layer (20), thereby obtaining the passivation layer (30).
9. The preparation method according to claim 8, characterized in that: The growth pressure of the passivation material layer is 25 Torr to 100 Torr.
10. The preparation method according to any one of claims 7 to 9, characterized in that: The forming of a cap layer (40) on the passivation layer (30) comprises: forming a GaN material layer (41) and a gate electrode material layer (51) in sequence on the passivation layer (30); The GaN material layer (41) and the gate electrode material layer (51) are etched to obtain the cap layer (40) and the gate electrode layer (50).