Trench MOSFET device with protection gate structure and manufacturing method thereof

Abstract

A silicon carbide MOSFET device includes an N-channel MOSFET and a JFET connected to the N-channel MOSFET with their drain-source current paths in series. The gate of the JFET is connected to the gate of the N-channel MOSFET device through a voltage divider, and the voltage divider is formed on the same chip as the silicon carbide substrate and the first to fourth silicon carbide layers. The protection gate structure may protect the channel oxide from a high drain voltage during the off state. The voltage divider is configured to limit a gate voltage of the JFET such that a silicon carbide PN diode formed within the silicon carbide MOSFET device is turned off when the N-channel MOSFET is turned on or off.

Description

Technical Field

[0001] The present invention relates to semiconductor devices, in particular to silicon carbide MOSFET. Background Art

[0002] Silicon carbide (SiC) is a wide bandgap semiconductor with properties superior to silicon and is considered the next generation of power device materials. The critical electric field of silicon carbide is ten times higher than that of silicon, so the drift region is thinner, enabling high voltage applications. In addition, the thermal conductivity of silicon carbide is three times that of silicon, which allows devices to operate at high temperatures and high current densities without catastrophic failure.

[0003] However, conventional silicon carbide has a disadvantage, namely the high interface state density of the SiC / SiO2 layer, which leads to low channel mobility and high on-resistance. Although silicon carbide trench MOSFETs have higher channel mobility and smaller cell sizes than planar MOSFETs, they are subject to high voltage shocks when the MOSFET is reversed because the gate oxide at the bottom of the trench is exposed to the electric field. For 1200V trench MOSFETs, this electric field can be as high as 7MV / cm, far exceeding the safety level of 3MV / cm, resulting in premature breakdown or long-term reliability issues.

[0004] In the art, there have been some attempts to reduce the electric field and protect the bottom oxide area of ​​the trench, such as configuring a thick bottom oxide to reduce the electric field at the bottom of the trench, creating a P-shielding area at the bottom of the trench and connecting it to a self-biasing circuit, configuring a side P-shielding area, and creating an additional buried well for protection. However, all of these conventional techniques have certain drawbacks. For example, using only a thick bottom oxide will result in very low efficiency of the silicon carbide MOSFET, while the exposed sidewall gate oxide is still susceptible to the strong oxide field. Using a self-biasing circuit means that additional diodes and capacitors are required, which greatly reduces the response time of the device. Using a side P-shielding area may help reduce the resistance of the junction field effect transistor (JFET), but it will sacrifice part of the unit area of ​​the transistor channel. Finally, using an additional buried well for protection will occupy additional unit area, and the buried well will form a parasitic JFET, which will generate a large resistance during conduction, thereby increasing the on-resistance of the trench MOSFET. Summary of the invention

[0005] In view of the above background, an object of the present invention is to address the above disadvantages and propose another silicon carbide MOSFET device to provide better protection for the gate oxide of these devices.

[0006] Those skilled in the art will derive other objects of the present invention from the following description. Therefore, the above object statements are not exhaustive, but are only used to illustrate some of the numerous objects of the present invention.

[0007] In a first aspect, the present invention provides a silicon carbide MOSFET device, comprising an N-channel MOSFET and a JFET connected to the N-channel MOSFET. The drain-source current paths of the N-channel MOSFET and the JFET are connected in series with each other. The gate of the JFET is connected to the gate of the N-channel MOSFET device through a voltage divider.

[0008] In some embodiments, the drain of the JFET is configured as the drain of the silicon carbide MOSFET device. The source of the N-channel MOSFET is configured as the source of the silicon carbide MOSFET device. The source of the JFET is connected to the drain of the N-channel MOSFET.

[0009] In some embodiments, the voltage divider includes a resistor network.

[0010] Additionally or alternatively, the voltage divider is configured to limit the gate voltage of the JFET such that a SiC PN diode formed within the silicon carbide MOSFET device is turned off when the N-channel MOSFET is turned on or off.

[0011] In some embodiments, a gate resistor is connected between a gate of the silicon carbide MOSFET device and a gate of the N-channel MOSFET. The gate resistor is configured to control a switching speed of the N-channel MOSFET.

[0012] In another aspect of the present invention, a silicon carbide MOSFET device is provided, comprising a silicon carbide substrate of a first doping type, a first silicon carbide layer of a first dopant type located on top of the silicon carbide substrate, a plurality of grooves partially formed in the first silicon carbide layer, a second silicon carbide layer of a second doping type embedded in the first silicon carbide layer, a third silicon carbide layer of a second dopant type located above at least a portion of the second silicon carbide layer; and a fourth silicon carbide layer located above at least a portion of the third silicon carbide layer. The exterior of each of the plurality of grooves is covered with a gate oxide. The second silicon carbide layer includes a plurality of second portions. The gate oxide of each of the plurality of grooves includes a bottom surface and a side surface, and a corresponding one of the plurality of second portions is located directly below the bottom surface of the gate oxide of each of the plurality of grooves. The silicon carbide MOSFET device further includes a plurality of resistors formed on the same chip as the silicon carbide substrate and the first to fourth silicon carbide layers.

[0013] In some embodiments, the first dopant type is N, and the second dopant type is P. The second silicon carbide layer and the third silicon carbide layer are P-layers. The fourth silicon carbide layer includes P+ and N+ regions.

[0014] In some embodiments, a corresponding one of the plurality of second portions does not cover a side surface of a gate oxide of each of the plurality of trenches.

[0015] In some embodiments, the plurality of resistors are offset from the plurality of trenches in a horizontal direction.

[0016] In some embodiments, a plurality of resistors are located over the fourth silicon carbide layer.

[0017] According to a variation of the preferred embodiment, the plurality of resistors includes a first resistor and a second resistor. The first resistor and the second resistor are both connected to the plurality of second portions.

[0018] In some embodiments, the first resistor and the second resistor form a voltage divider.

[0019] In some embodiments, the second resistor is electrically connected to a source of the silicon carbide MOSFET device.

[0020] According to another variation of the preferred embodiment, the plurality of resistors includes a third resistor. The third resistor connects the polysilicon in each of the plurality of trenches to the gate of the silicon carbide MOSFET device.

[0021] In some embodiments, the gate electrode is horizontally offset from the source of the silicon carbide MOSFET device.

[0022] According to another variation of the preferred embodiment, the silicon carbide MOSFET device further comprises a field oxide layer located on top of the fourth silicon carbide layer. The field oxide layer comprises a plurality of oxide portions, each oxide portion being formed above and corresponding to one of the plurality of trenches.

[0023] In some embodiments, the silicon carbide MOSFET device further includes a dielectric layer substantially located on top of the field oxide layer. The dielectric layer includes a plurality of dielectric insulating portions. Each of the dielectric insulating portions is formed above and corresponds to one of the oxide portions.

[0024] In another aspect of the present invention, a method for producing a silicon carbide MOSFET device is provided, comprising the following steps: providing a first silicon carbide layer of a first doping type on a silicon carbide substrate; forming a plurality of grooves, the plurality of grooves partially embedded in the first silicon carbide layer, each of the plurality of grooves being covered with a gate oxide; embedding a second silicon carbide layer of a second dopant type in the first silicon carbide layer, the second silicon carbide layer comprising a plurality of second portions; providing a third silicon carbide layer of a second dopant type over at least a portion of the second silicon carbide layer; providing a fourth silicon carbide layer over at least a portion of the third silicon carbide layer; and forming a plurality of resistors monolithically with the silicon carbide substrate and the first to fourth silicon carbide layers. The gate oxide of each of the plurality of grooves comprises a bottom surface and a side surface. A corresponding one of the plurality of second portions is located directly below the bottom surface of the gate oxide of each of the plurality of grooves.

[0025] In some embodiments, the first dopant type is N, and the second dopant type is P. The second silicon carbide layer and the third silicon carbide layer are P-layers. The fourth silicon carbide layer includes a P+ region and an N+ region.

[0026] In some embodiments, the step of embedding the second silicon carbide layer further includes: forming a plurality of first grooves in the first silicon carbide layer; performing epitaxy of a second dopant type on the first silicon carbide layer including the plurality of first grooves to form a second silicon carbide layer; and patterning and etching the second silicon carbide layer at predetermined positions to form a plurality of second portions.

[0027] In some embodiments, the step of monolithically forming multiple resistors also includes: providing a polysilicon layer on the fourth silicon carbide layer; implanting the polysilicon layer with a first dopant type to reduce the resistivity of the resistor; and patterning and etching the polysilicon layer to form a first resistor and a second resistor.

[0028] In some embodiments, the first resistor and the second resistor form a voltage divider.

[0029] According to a variation of the preferred embodiment, the second resistor is electrically connected to the source of the silicon carbide MOSFET device.

[0030] Therefore, embodiments of the present invention provide different silicon carbide MOSFET structures, the robustness of which MOSFET devices are improved without affecting the relatively small area of ​​the MOSFET unit used. For example, in certain embodiments of the present invention, the P-shield region is located at the bottom of the trench gate, which does not sacrifice the width of half the transistor trench and does not require additional buried well area. For example, the protection gate structure can utilize the JFET region to ensure that any SiC PN diode formed by the P-shield region and the N-drift region is always in the off state, thereby protecting the trench oxide from the high drain voltage during the off state. The JFET region widens the current path of the JFET region during conduction, so that a lower on-resistance can be obtained compared to the traditional P-shield structure. In some embodiments, the silicon carbide MOSFET device can be manufactured on a monolithic silicon carbide chip without the need for external components. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other features of the present invention will be apparent from the following description of preferred embodiments, which are described by way of example only with reference to the accompanying drawings:

[0032] Figure 1 An equivalent circuit diagram of a silicon carbide MOSFET device according to a first embodiment of the present invention is shown.

[0033] Figure 2 show Figure 1 A simplified circuit layout of the circuit diagram.

[0034] Figure 3 FIG. 4 shows a simplified cross-sectional structure diagram of a silicon carbide MOSFET device according to a second embodiment of the present invention, which can be Figure 1-2 The circuit layout is shown in .

[0035] Figure 4a Shows when Figure 2 A specific example of the gate voltage applied to the JFET and N-MOSFET in the device when the device is turned on.

[0036] Figure 4b Shows when Figure 2 The device is turned off when applied to Figure 2 Another specific example of the gate voltages of the JFET and N-MOSFET in a device.

[0037] Figure 5a Shows Figure 4a The variation of VMG, VPG and Vds over time when the SiC MOSFET device in the example is turned on.

[0038] Figure 5b Show in Figure 4bFigure 3 shows the variation of VMG, VPG and Ids over time when the SiC MOSFET device is turned off.

[0039] Figure 6 A device layout of a silicon carbide MOSFET device according to a third embodiment of the present invention is shown.

[0040] Figure 7 Shows Figure 6 Equivalent circuit diagram of SiC MOSFET device.

[0041] Figure 8 For SiC MOSFET devices along Figure 6 Cross-section along line AA.

[0042] Figure 9a The starting materials of a method for manufacturing a silicon carbide MOSFET device according to another embodiment of the present invention are shown.

[0043] Figure 9b shows the change from the SiC surface to Figure 9a The steps of patterning and etching a first trench in the N-drift layer of the starting material.

[0044] Fig.9c Shown in Figure 9b The steps shown are followed by a step of forming a P shielding region by an epitaxial process.

[0045] Figure 9d Shown in Fig.9c The steps shown are followed by a step of removing excess P-shield portions using chemical mechanical planarization (CMP).

[0046] Fig.9e Shown in Figure 9d The steps shown are followed by the steps of patterning and implanting the P-substrate region.

[0047] Figure 9f for Fig.9e The steps shown are followed by P+ and N+ region patterning and implantation steps.

[0048] Figure 9g Shown in Figure 9f The steps shown are followed by the steps of patterning and etching a second trench.

[0049] Figure 9h Shown in Figure 9g The steps shown are followed by a step of depositing an underlying gate oxide by a high density plasma chemical vapor deposition (HDP-CVD) process.

[0050] Figure 9i Shows Figure 9h The steps shown are followed by a step of removing redundant portions of the bottom gate oxide by oxide etching.

[0051] Figure 9j Shown in Figure 9i The steps shown are followed by a step of forming a sidewall gate oxide by an oxidation process.

[0052] Figure 9k Shown in Figure 9j The steps shown are followed by a step of forming trench gate polysilicon by a CVD process.

[0053] Figure 9l Shown in Figure 9k The steps shown are followed by a step of removing excess gate polysilicon and gate oxide using CMP.

[0054] Figure 9m Shown in Figure 9l The steps shown are followed by steps of depositing a field oxide by CVD, followed by patterning and etching to form the contact areas.

[0055] Figure 9n Shown in Figure 9m The steps shown are followed by the steps of depositing and annealing a barrier metal to form an ohmic contact.

[0056] Figure 9o Shown in Figure 9n After the steps shown, pad polysilicon is deposited by CVD and the polysilicon resistivity is trimmed by blank ion implantation.

[0057] Figure 9p Shown in Figure 9o The steps shown are followed by patterning and implantation steps to form highly doped gate resistor and gate bus polysilicon.

[0058] Figure 9q Shown Figure 9p The steps shown are followed by patterning and etching steps to separate the individual polysilicon resistors and the gate bus polysilicon.

[0059] Figure 9r Shown in Figure 9q The steps shown are followed by steps of depositing an ILD (inter-layer dielectric) layer, patterning it and etching it to form electrode contacts.

[0060] Figure 9s Shown in Figure 9r The steps shown are followed by steps of depositing, patterning and etching the front metal to form source and gate electrodes.

[0061] Figure 9t Shown in Figure 9s The steps shown are followed by a step of depositing and annealing a backside metal to form a drain electrode.

[0062] Fig.10 It is a summary Figure 9a-9t Flow chart of the manufacturing method steps.

[0063] Fig.11a The starting materials for a method of manufacturing a silicon carbide MOSFET device according to a further embodiment of the present invention are shown.

[0064] Fig.11b The first trench of the silicon carbide surface is patterned and etched into Fig.11a Step 1 of the N drift layer of the initial material.

[0065] Fig.11c Shown in Fig.11b The steps shown are followed by a step of forming a P-shield region by an epitaxial process.

[0066] Fig.11d Shown in Fig.11c The steps shown are followed by a step of removing the excess P-shield using CMP.

[0067] Fig.11e Shown in Fig.11d The steps shown are followed by the steps of patterning and implanting the P-base regions.

[0068] Fig.11f for Fig.11e The steps shown are followed by P+ and N+ region patterning and implantation steps.

[0069] Figure 11g Show Fig.11f The steps shown are followed by the steps of patterning and etching a second trench.

[0070] Fig.11h Shown in Figure 11g The steps shown are followed by a step of depositing a bottom gate oxide by a HDP-CVD process.

[0071] Fig.11i Shown in Fig.11h The steps shown are followed by a step of removing redundant portions of the bottom gate oxide by oxide etching.

[0072] Fig.11j Shown in Fig.11i The steps shown are followed by a step of forming a sidewall gate oxide by an oxidation process.

[0073] Figure 11k Shown in Fig.11j The steps shown are followed by a step of forming trench gate polysilicon by a CVD process.

[0074] Figure 11l Shown in Figure 11kThe steps shown are followed by a step of removing excess gate polysilicon and gate oxide using CMP.

[0075] Figure 11m Shown in Figure 11l The steps shown are followed by a step of depositing a field oxide by CVD, which is then patterned and etched to form the contact areas.

[0076] Figure 11n Shown in Figure 11m The steps shown are followed by the steps of depositing and annealing a barrier metal to form an ohmic contact.

[0077] Fig.11o Shown in Figure 11n The steps shown are followed by a step of depositing a pad layer of polysilicon by CVD and trimming the polysilicon resistivity by blank ion implantation.

[0078] Figure 11p Shown in Fig.11o The steps shown are followed by patterning and implantation steps to form highly doped gate resistor and gate bus polysilicon.

[0079] Figure 11q Shown in Figure 11p The steps shown are followed by patterning and etching steps to separate the individual polysilicon resistors and the gate bus polysilicon.

[0080] Figure 11r Shown in Figure 11q The steps shown are followed by steps of depositing an ILD layer, patterning it and etching it to form contact areas.

[0081] Figure 11s Shown in Figure 11r The steps shown are followed by steps of depositing, patterning and etching the front metal to form the source and gate electrodes.

[0082] Figure 11t Shown in Figure 11s The steps shown are followed by a step of depositing and annealing a backside metal to form a drain electrode.

[0083] Fig.12 It is a summary Figures 11a-11t Flow chart of the manufacturing method steps.

[0084] Fig.13a The starting materials for a method of manufacturing a SiC MOSFET device according to a further embodiment of the present invention are shown.

[0085] Fig.13b The first trench of the SiC surface is patterned and etched into Fig.13a Step 1 of the N drift layer of the initial material.

[0086] Fig.13c Shown in Fig.13b The steps shown are followed by a step of forming a P-shield region by an epitaxial process.

[0087] Fig.13d Shown in Fig.13c The steps shown are followed by a step of removing the excess P-shield using CMP.

[0088] Fig.13e Shown in Fig.13d The steps shown are followed by steps for patterning and implanting the P+ regions.

[0089] Fig.13f Shown Fig.13e The steps shown are followed by the steps of patterning and implanting the N+ regions.

[0090] Figure 13g Shows Fig.13f The steps shown are followed by the steps of patterning and etching a second trench.

[0091] Fig.13h Shown in Figure 13g The steps shown are followed by a step of depositing an underlying gate oxide by a plasma enhanced chemical vapor deposition (PE-CVD) process.

[0092] Fig.13i Shows Fig.13h The steps shown are followed by a step of removing redundant portions of the bottom gate oxide by oxide etching.

[0093] Fig.13j Shown in Fig.13i The steps shown are followed by a step of forming a sidewall gate oxide by an oxidation process.

[0094] Figure 13k Shown in Fig.13j The steps shown are followed by a step of forming trench gate polysilicon by a CVD process.

[0095] Figure 13l Shown in Figure 13k The steps shown are followed by a step of removing excess gate polysilicon and gate oxide using CMP.

[0096] Figure 13m Shown Figure 13l The steps shown are followed by a step of depositing a field oxide by CVD, which is then patterned and etched to form the contact areas.

[0097] Fig.13n Shown in Figure 13m The steps shown are followed by the steps of depositing and annealing a barrier metal to form an ohmic contact.

[0098] Fig.13o Shown in Fig.13n The steps shown are followed by a step of depositing a pad layer of polysilicon by CVD and trimming the polysilicon resistivity by blank ion implantation.

[0099] Figure 13p Shown in Fig.13o The steps shown are followed by patterning and implantation steps to form highly doped gate resistor and gate bus polysilicon.

[0100] Figure 13q Shown in Figure 13p The steps shown are followed by patterning and etching steps to separate the individual polysilicon resistors and the gate bus polysilicon.

[0101] Figure 13r Shown in Figure 13q The steps shown are followed by steps of depositing an ILD layer, patterning it and etching it to form contact areas.

[0102] Figure 13s Shown in Figure 13r The steps shown are followed by steps for depositing, patterning and etching front side metal to form source and gate electrodes.

[0103] Figure 13t Shown in Figure 13s The steps shown are followed by a step of depositing and annealing a backside metal to form a drain electrode.

[0104] Fig.14 It is a summary Figure 13a-11t Flow chart of the manufacturing method steps.

[0105] In the drawings, like numerals refer to like parts throughout the several embodiments described herein. DETAILED DESCRIPTION

[0106] As used in this specification and the appended claims, "coupled" or "connected" means electrically coupled or connected directly or indirectly, via one or more electrical means, unless otherwise stated.

[0107] The terms "horizontal", "vertical", "upward", "downward", "above", "below" and the like as used herein are intended to describe the normal orientation of use of the invention and are not intended to limit the invention to any particular orientation.

[0108] When describing the silicon carbide structure of any MOSFET device, the terms "region" and "portion" can be used interchangeably, because a region of a MOSFET device that is made of a specific material different from its surrounding portions can also be said to be a portion made of a specific material.

[0109] Now refer to Figure 1The first embodiment of the present invention is a silicon carbide (SiC) MOSFET device, and its equivalent circuit is as follows: Figure 1 Please note that the actual cell layout of the SiC MOSFET device (e.g., silicon carbide layer) is not shown in the figure, and those skilled in the art should understand that Figure 1 The circuit shown can correspond to many different SiC MOSFET structures (examples of which will be described later) within the spirit of the present invention. The SiC MOSFET device includes a JFET J1 and an N-channel MOSFET Q1 connected in series. In other words, the drain-source current path of the JFET J1 is connected in series with the drain-source current path of the N-channel MOSFET Q1. Figure 1 As shown, the source of JFET J1 is connected to the drain of N-channel MOSFET Q1, the drain of JFET J1 is connected to the drain of the entire SiC MOSFET device (indicated by the pin where Vdd is located), and the source of N-channel MOSFET Q1 is connected to the source of the entire SiC MOSFET device (indicated by the pin where Vss is located). On the other hand, the gate of JFET J1 and the gate of N-channel MOSFET Q1 are both connected to the gate of the entire SiC MOSFET device (indicated by the pin where Vg is located). However, a voltage divider in the form of a resistor network is connected between the gate of JFET J1 and the gate of the entire SiC MOSFET device, and a gate resistor Rg is connected between the gate of N-channel MOSFET Q1 and the gate of the entire SiC MOSFET device. The resistor network includes two resistors R1 and R2 connected in series, and the gate of JFET J1 is connected between resistor R1 and resistor R2. The other end of resistor R2 is connected to the source of N-channel MOSFET Q1 (and therefore the source of the entire SiC MOSFET device). Resistor R1 and resistor Rg are both connected to the gate of the entire SiC MOSFET device.

[0110] Figure 2 yes Figure 1 A simplified schematic of the circuit in Figure 2, omitting the voltage divider. Figure 2 The gate voltages of JFET J1 and N-channel MOSFET Q1 are represented by V PG and V MG Indicates. Figure 1 From the circuit diagram, we can see that V MG Equal to the voltage applied to the gate of the entire SiCMOSFET device ( Figure 1 is Vg), and V PG The voltage divider ratio determines the desired V PGIn a preferred embodiment, the ratio of R1 to R2 is 5:1, for example, the resistances of R1 and R2 are 25 MΩ and 5 MΩ, respectively.

[0111] In this embodiment, the gate of the N-channel MOSFET Q1 is called the main gate, and the gate of the JFET J1 is called the protection gate, because the N-channel MOSFET Q1 is the main element to realize the function of the SiC MOSFET device, and the JFET J1 is used as a protection device for the gate oxide of the N-channel MOSFET Q1. In addition, in a preferred embodiment, the source of the N-channel MOSFET Q1 is connected to the ground (so Vss = 0V).

[0112] Figure 1 The operation of the circuit shown will now be described with reference to an exemplary SiC MOSFET device, a simplified cross-sectional diagram of which is shown in FIG. Figure 3 Please note that Figure 1 The device structure in the example is not intended to be limiting, but it should be recognized that there are many other possible SiC MOSFET devices with different structures that can be applied Figure 1 and / or Figure 2 For ease of discussion, the ratio of R1 to R2 is 5:1 as an example. Assuming the maximum gate voltage Vg of the SiC MOSFET device is 15V, due to the above 5:1 ratio, V MG The range of variation is 0-15V, and V PG The range of variation is 0-2.5V. The resistance values ​​of R1 and R2 mentioned above are 25MΩ and 5MΩ respectively, and these two resistance values ​​are also used in this example. The resistance values ​​of R1 and R2 are large enough to limit the gate current of the entire SiC MOSFET device. Since the maximum gate voltage Vg is 15V, the maximum gate current of the above resistance value is limited to 500nA when driven by a 15V gate voltage.

[0113] In this example, the gate voltage of JFET J1 is V PG is configured to be lower than the conduction voltage of the SiC PN diode formed by the P-shield region 24 and the N-drift region 22 in the SiC MOSFET device (see Figure 3), and is generally between 2.7V and 3V. When the N-channel MOSFET Q1 is in the off state, the electromotive force of the N-drift region 22 will be between the source region (represented by the P+ region 30 and the N+ region 28) and the drain region (defined by the silicon substrate 20), for example 50V. The P-shield region 24 connected to the gate of the JFET J1 is now 0V. This keeps the SiC PN diode in the off state, otherwise, if the SiC PN diode is turned on, leakage current will occur. On the other hand, when the N-channel MOSFET Q1 is in the on state, the drain-to-source voltage Vds drops, which causes the electromotive force of the N-drift region 22 to drop to almost 0V. The voltage of the P-shield region 24 connected to the gate of the JFET J1 is now 2.5V. This keeps the SiC PN diode in the off state. Therefore, whether the N-channel MOSFET Q1 is turned on or off, the SiC PN diode is always in the off state. It can be seen that by limiting the gate voltage of JFET J1 (limited to no more than 2.5V in this example), the potential difference between the P-shield region 24 and the N-drift region 22 is kept below the turn-on voltage of the SiC PN diode. Compared with the prior art, the above SiC MOSFET device not only protects the on state of the N-channel MOSFET Q1, but also protects the off state.

[0114] on the other hand, Figure 1 The gate resistor Rg in is used to control the switching speed of the N-channel MOSFET Q1 to minimize the instantaneous gate voltage pulse during switching. Even if the instantaneous pulse causes the SiC PN diode to inject holes, these holes will be quickly collected by the P-base region 26 of the N-channel MOSFET Q1, or recombine with electrons in the N-drift region 22. The value of the resistor Rg can be very small, even close to zero, or it can be very large, depending on the choice of the actual circuit design.

[0115] Please note, Figure 3 The various resistors R1, R2, and Rg are not shown in the simplified structure in FIG. Figure 3 The stacked structure of various silicon carbide layers is shown, and the N-drift region 22 is stacked on top of the silicon substrate 20. There are multiple trenches 36 in the device, each of which is filled with gate polysilicon 34. There is a gate oxide 32 outside the trench 36, and the gate oxide 32 has a bottom surface and a side surface. The P-shield region 24 is located directly below the bottom surface of each trench 36. The P-shield region 24 is also the gate of the JFET J1, and the gate voltage V PGApplied to JFET J1. A portion of each trench 36 is embedded in the N-drift region 22, and the P-shielding region 24 is embedded in the N-drift region 22. There is a P-base region 26 between the top of the N-drift region 22 and the trench 36, and there is a P+ region 30 on the top of the P-base region 26, which is located between the two N+ portions 28. The silicon substrate 20 defines the drain region of the SiC MOSFET device (which is also the drain region of the JFET J1). The P+ region 30 and the N+ portion 28 define the source region of the SiC MOSFET device (which is also the source region of the N-channel MOSTFET Q1). As shown in FIG. Figure 2 As shown, the source region is grounded in a preferred embodiment. The top portion of the gate polysilicon 34 in the trench 36 defines the gate region of the N-channel MOSTFET Q1.

[0116] Next, refer to Figure 4a-5b , using the example setup of the above resistor values ​​and gate voltages to describe Figure 3 The circuit behavior of the exemplary SiC MOSFET device in FIG. 1 is shown in FIG. 1 . When the SiC MOSFET device is turned on, as shown in FIG. Figure 5a As shown, the gate voltage Vg rises from 0V to 15V. The main gate voltage V MG Will follow the Vg signal from 0V to 15V, while the protection gate voltage V PG Then it rises from 0V to 2.5V under the drive of the voltage divider (because the ratio of R1 to R2 of the voltage divider is 5:1). Figure 5a As shown, when V MG Exceeding the threshold voltage V th When the N-channel MOSFET Q1 is turned on, the drain current Ids begins to increase. However, due to the two adjacent P-shield regions 24 (such as Figure 3 As shown in Figure 2, the depletion of JFET J1 causes Ids to be limited to Figure 5a However, as time goes by, when V PG With V MG As Ids continues to rise, the depletion of JFET J1 begins to shrink, causing the conduction path of the N-channel MOSFET between the two adjacent P-shield regions 24 to widen. As a result, Ids begins to rise again, exceeding Figure 5a When V MG Reach 15V and V PG When it reaches 2.5V (such as Figure 4a As shown), the channel of JFET J1 is at its maximum width, so Ids is saturated at level b.

[0117] On the other hand, when the SiC MOSFET device is about to be turned off, the gate voltage Vg drops from 15V to 0V. MGwill follow the Vg signal from 15V to 0V, and V PG The voltage divider drives the voltage from 2.5V to 0V (considering that the ratio of R1 to R2 of the voltage divider is 5:1), such as Figure 5b As shown. When V PG As V decreases, the depletion of JFET J1 caused by the two adjacent P-shield regions 24 will increase, thereby reducing the conduction path of N-channel MOSFET Q1. Therefore, Ids starts to decrease. When V PG When it drops to a certain level, the depletion becomes stable and the Ids of the N-channel MOSFET Q1 drops to level c. MG Lower than V th When V MG and V PG When both are 0V (such as Figure 4b As shown in FIG. 1 , the N-channel MOSFET Q1 is turned off, and the JFET J1 channel is squeezed, that is, the channel thickness is zero, and the carriers no longer move from the source to the drain, and the current remains constant. Therefore, the depletion of the two adjacent P-shield regions 24 protects the gate oxide 32 of the trench 36 from the high electric field of the drain voltage.

[0118] It should be noted that, although the gate voltage is reduced to zero in the above example, in a variation of this embodiment, the gate voltage can be further reduced to a negative value if required by the actual application. MG can drop to -5V to turn off the N-channel MOSFET Q1. The negative gate voltage V PG The JFET J1 may be further clamped and the protection of the gate oxide 32 of the trench 36 may be increased.

[0119] Now watch Figure 6-8 , a SiC MOSFET device according to another embodiment of the present invention will be described below. Figure 6 shows a top view of the device, Figure 7 The circuit schematic of the device is shown in Figure 1. Figure 7 The circuit shown is Figure 1-2 The circuit shown is consistent, which proves Figure 1-2 The circuit in FIG. 1 can be used as a design guide to design many different SiC MOSFET devices. A person skilled in the art will appreciate that Figure 6 Shown is the active component layout (ie, a fully functional MOSFET can be formed by expanding the active component to the desired size and then surrounding it with edge termination).

[0120] To explain Figure 6 The layout in Figure 6The two key components of the SiC MOSFET device are shown in Figure 1, namely the transistor component and the resistor component. The transistor component contains JFET J1 and N-channel MOSFET Q1 ( Figure 6 The resistor components include resistors R1, R2 and Rg (not shown). Figure 6 142), which are located in the resistor region 140 adjacent to the gate pad 142. The source pad 144 is located to one side of the resistor region 140, and it can be seen that the resistor region 140 is located between the source pad 144 and the gate pad 142. As will be described in detail later, the SiC MOSFET device in this embodiment uses a doped polysilicon layer (also used as a gate connection) to make resistors. It should be expected that these resistors are located on the field oxide above the SiC surface.

[0121] Figure 8 The SiC MOSFET device is shown along the vertical plane through Figure 6 The cross-sectional view of the AA line in the middle. The SiC MOSFET device is arranged with source, gate and drain, which form the silicon pillar (such as Figure 8 As shown). Among them, the silicon carbide substrate 120 is configured as the underlying structure and epitaxy of the SiC MOSFET device. As will be appreciated by those skilled in the art, the silicon carbide substrate 120 is made of a SiC wafer, and in the present embodiment, the silicon carbide substrate 120 adopts N+ type as the first doping type. For example, the silicon carbide substrate 120 may be a 4H-SiC, 3C-SiC or 6H-SiC semiconductor layer doped with N+, and in some embodiments, the thickness is about 350um and the resistivity is 0.02Ω·cm to 0.03Ω·cm. It is well known to those skilled in the art that the silicon carbide substrate 120 will eventually be thinned to reduce resistance. A metal layer 146 is also formed on the bottom surface of the silicon carbide substrate 120 as a drain contact of the silicon carbide MOSFET device. On the top of the silicon carbide substrate 120, there is a first N-type silicon carbide layer 122, and the first silicon carbide layer 122 serves as an N-drift layer. The doping level of the first silicon carbide layer 122 is lower than that of the silicon carbide substrate 120, which are represented by N- and N+ respectively. The first silicon carbide layer 122 is formed by an epitaxial process, and has a thickness of, for example, 4 μm to 35 μm, and a doping concentration of 1e15 cm -3 to 3e16cm -3 In one embodiment, a 1200V SiC trench MOSFET is constructed using 12um epitaxy with a doping concentration of 1e16cm -3 .

[0122] A plurality of trenches 136 are formed by etching the first silicon carbide layer 122, for example, the trench depth is in the range of 0.8 μm to 1.6 μm, and the trench width is in the range of 0.6 μm to 1.2 μm. In one example, the bottom of the trench 136 is 0.4 μm shallower than the P-shield region 124a. Each trench 136 is filled with polysilicon material 134. The trench 136 is only partially embedded in the first silicon carbide layer 122 near the bottom end, the upper part of the trench 136 passes through the third silicon carbide layer 126 and the fourth silicon carbide layer, and the top surface of the trench 136 is flush with the top surface of the fourth silicon carbide layer. The periphery of each trench 136 is covered with the gate oxide of the N-channel MOSFET Q1, which consists of a bottom gate oxide 132a and a sidewall gate oxide 132b. The thickness of the bottom gate oxide 132a is equal to or greater than the sidewall gate oxide 132b, depending on the method of forming the gate oxide. Common methods for forming gate oxides include thermal oxidation, HDP-CVD, PE-CVD, and low pressure chemical vapor deposition (LP-CVD). The thickness of the bottom gate oxide 132a is between 1000A and 4000A. The function of the sidewall gate oxide 132b is to adjust the conductance of the channel of the N-channel MOSFET Q1. The sidewall gate oxide 132b is formed by thermal oxidation and undergoes appropriate post-oxidation annealing to improve electrical and interface properties. Preferably, the thickness of the sidewall gate oxide 132b is between 500A and 2000A.

[0123] A P-shield portion 124a is disposed directly below each bottom gate oxide 132a, so that Figure 8 The multiple P-shield portions 124a shown in the figure correspond to the multiple trenches 136 respectively. These P-shield portions 124a are composed of multiple P-shield junctions on the transistor unit cell and the P-shield bus (not shown). These P-shield junctions form the gate of the JFET J1 and play a role in protecting the bottom gate oxide 132a and the sidewall gate oxide 132b of the N-channel MOSFET Q1. In addition to the P-shield region 124a, there is another P-shield region 124b, which is horizontally offset from the P-shield region 124a. The P-shield region 124b is connected to each P-shield region 124a through a P-shield bus (not shown in the figure) and is connected to the SiC MOSFET device (not shown in the figure, but connected to the SiC MOSFET device). Figure 6 The resistor region and gate pad are substantially aligned as shown in FIG. 1 . The P-shielding portions 124 a and 124 b together form a second silicon carbide layer of the SiC MOSFET device. The second silicon carbide layer has a second dopant type P compared to the first dopant type N of the first silicon carbide layer 122 and the silicon carbide substrate 120. In one example, aluminum is used as a dopant to form the P-shielding regions 124 a and 124 b, with a doping concentration ranging from 1e17 cm -3to 5e18cm -3 .

[0124] The third silicon carbide layer 126 is located on top of the P-shield portion 124b, although there is a discontinuity within the third silicon carbide layer 126. Figure 8 As shown, the third silicon carbide layer 126 in the transistor region has a plurality of P-base regions 126c, which are separated from each other by trenches 136. In each transistor unit cell, these P-base regions 126c extend laterally (i.e., horizontally) away from the P-shielding region 124a to form the base region of the N-channel MOSFET Q1. The third silicon carbide layer 126 between the resistor region and the transistor region is discontinuous. It terminates at 126a on one side of the transistor region and 126d on one side of the resistor region. In the resistor region, the third silicon carbide layer 126 includes a P-base region 126d, which overlaps the P-shielding region 124b to increase the doping of the node. The third silicon carbide layer 126 has a second dopant type P, for example, the third silicon carbide layer 126 can be formed using an aluminum or boron dopant ion implantation method, and its junction depth is in the range of 0.3μm to 0.6μm below the SiC surface, and the doping concentration is 5e17cm -3 to 5e18cm -3 Range, usually 2e18cm -3 .

[0125] The fourth silicon carbide layer is substantially located above the third silicon carbide layer 126, and the fourth silicon carbide layer includes two materials of different conductivity types. The first is a P+ region 130 of the second conductivity type (P-type). In each transistor cell, these P+ regions 130 act as body contacts for the N-channel MOSFET Q1. In the resistor region, the P+ region 130 overlaps the P-shield region 124b to increase the doping of the node below the resistor region to form an ohmic contact. These P+ regions also run along the P-shield busbar (not shown) to connect multiple P-shield junctions 124a of each transistor cell to resistors R1 and R2 (to be described later). In one example, the P+ region 130 can be formed using aluminum or boron dopant ion implantation, with a junction depth ranging from 0.2μm to 0.4μm and a doping concentration ranging from 5e19cm -3 to 2e20cm -3 In addition to the P+ region 130, the fourth silicon carbide layer also includes N+ regions 128 of the first conductivity type (N type). In each transistor cell, these N+ regions 128 serve as source contacts of the N-channel MOSFET Q1. In one example, the N+ regions 128 can be formed using nitrogen or phosphorus dopant ion implantation, with a junction depth between 0.2 μm and 0.4 μm and a doping concentration of 1e20 cm -3 to 1.5e20cm -3 between.

[0126] In the present embodiment, the top surface of the fourth silicon carbide layer is defined as a silicon carbide surface (SiC surface). A field oxide 148 is provided on the top of the fourth silicon carbide layer as a dielectric layer for isolating the various components in the transistor region and the resistor region, for example, isolating the polysilicon material 134 in the groove 136 from the P+ region 130 and the N+ region 128. By patterning and etching the field oxide 148 in a specific area, a plurality of oxide portions 148b can be formed above the plurality of grooves 136, each corresponding to one of the plurality of grooves 136. Between the oxide portions 148b, a contact region for connecting the components below the silicon carbide surface and the components above the field oxide 148 is formed. For example, between two transistor unit cells (each unit cell is defined by a groove 136), a contact region (shown by arrow 148a) can be formed for connecting the source electrode 150 with the barrier metal 152. In one example, field oxide 148 is deposited by LP-CVD or PE-CVD with a thickness between 6000 Å and 15000 Å.

[0127] The barrier metal 152 is also formed on the fourth silicon carbide layer, and is located at the discontinuity of the field oxide 148. Figure 8 As shown, there is a barrier metal 152 in contact with the source electrode 150 between each two adjacent transistor unit cells, the source electrode 150 extends downward through the contact region, and the barrier metal 152 is also in direct contact with the corresponding P+ region 130 and N+ region 128. The barrier metal 152 forms an ohmic contact in the contact region. In one example, the barrier metal is made of nickel or titanium material and is deposited by a sputtering process.

[0128] like Figure 8 The SiC MOSFET device shown includes three resistors R1, R2 and Rg, which are made of undoped pad polysilicon ( Figure 8 The undoped polysilicon is formed by a first conductive type (N-type) dopant such as phosphorus or arsenic (not shown), trimmed to obtain the correct resistivity, and implanted with a first conductivity type (N-type) dopant such as phosphorus or arsenic. Resistors R1 and R2 are formed using a lower dopant dose, while resistor Rg and gate polysilicon 156 are formed using the same process but with a much higher dose. The thickness of the undoped polysilicon is between 4000A and 8000A. Figure 8As can be seen in FIG, both ends of the resistor have a generally "T" shaped cross section because they extend downward through the field oxide 148 and contact the P+ region 130 in the resistor region, where the P+ region 130 serves as an ohmic contact for the gate of JFET J1. The aforementioned P-shield bus connects the multiple P-shield regions 124a of each transistor unit cell together and is integrated into the P+ region 130 below the resistor region. On the other hand, the resistor Rg does not contact the P+ region 130 below the resistor region, but it connects the polysilicon material 134 in the trench 136 in the transistor unit cell to the gate electrode 158. It can be seen that Figure 1 The circuit connections shown reflect the Figure 8 in the unit layout.

[0129] On top of different parts of the field oxide 148, as well as on top of the resistors R1, R2, Rg and the gate polysilicon 156, an interlayer dielectric (ILD) layer is provided, which includes a plurality of ILD portions 154. The ILD portion 154 acts as an insulating medium to insulate each element in the transistor region and the resistor region. Like the field oxide 148, the ILD layer is not continuous, but it opens certain windows as contact areas to form electrode contacts, thereby forming separate ILD portions 154. For the ILD portions 154 located at the top of the trench 136, they not only cover the top surface of the corresponding oxide portions 148b of the field oxide 148, but also cover the sides of these oxide portions 148b. Please note that the ILD portion 154 does not cover the entire top surface of the resistors R1, R2, Rg and the gate polysilicon 156. It leaves windows at both ends of the resistor and the gate pad 142 for connection through metallization. In one example, the ILD layer is made of phosphosilicate glass (PSG) and is deposited using a LP-CVD or PE-CVD process. In one example, the thickness of the ILD material ranges from 8000 Å to 15000 Å.

[0130] As the topmost element, there is a layer of deposited and patterned power metal above the various electrode contacts. The power metal in the transistor area is the source electrode 150 ( Figure 7 Vss is present in the source electrode 150). The source electrode 150 connects each P+ region 130 and N+ region 128 in the N-channel MOSFET Q1 through the barrier metal 152, and the source electrode 150 is also connected to the resistor R2. The power metal in the resistor region is the gate electrode 158 ( Figure 7The power metal is located at the gate electrode 158, which connects the polysilicon material 134 in the trench 136 in the transistor unit cell to the gate electrode 158 through the gate polysilicon 156 and the gate resistor Vg. In one example, the power metal is aluminum, which is formed by a sputtering process. For example, the thickness of this aluminum is between 3μm and 5μm.

[0131] A back metal layer is deposited on the other side of the SiC surface to form a drain electrode 146 ( Figure 7 The back metal is usually deposited after the silicon carbide substrate 120 is thinned to the required thickness. It should be noted that Figure 8 As will be appreciated by those skilled in the art, some surface passivation materials, such as silicon oxide, silicon nitride and polyimide, are necessary in the packaging of silicon carbide MOSFET devices.

[0132] Figure 9a-9t Shows how to produce Figure 8 An exemplary method for a SiC MOSFET device in FIG. Fig.10 The flowchart shown summarizes Figure 9a-9t Please note that the exemplary method described in this example is not limiting because Figure 8 The SiC MOSFET devices in may be produced using other methods and / or a different sequence of steps. Fig.10 The method begins at step 160, in which, if Figure 9a As shown, an unprocessed silicon carbide epitaxial wafer cleaned using an RCA cleaning procedure is prepared. The wafer has an N+ type silicon carbide substrate 120 and an N-type first silicon carbide layer 122. It should be noted that before the wafer is cut into individual MOSFET device chips, the entire wafer will be processed into multiple MOSFET devices. As mentioned above, the first silicon carbide layer 122 is an epitaxial N-type drift layer with a lower doping level than the silicon carbide substrate 120.

[0133] Then, if Figure 9b As shown, in step 161, a first mask (eg, a dielectric mask, such as SiO2) is used to pattern a plurality of first trenches 121 and etch from the SiC surface into the first silicon carbide layer 122. Figure 9a-9b As shown, before this step, the SiC surface is the top surface of the first silicon carbide layer 122. The groove width of the first groove 121 is preferably between 0.3 μm and 0.8 μm, and the groove depth is preferably between 1.2 μm and 2.0 μm. Fig.9cAs shown, the first trench 121 in step 162 is filled with a second silicon carbide layer of a second conductivity type (P type) by epitaxy to form P-shielding regions 124a, 124b. Each P-shielding region 124a corresponds to a transistor unit in the transistor region, and the P-shielding region 124b corresponds to the resistor region. At this stage, the P-shielding region 124a completely fills the corresponding trench, which is consistent with Figure 8 The final device shown is different from the situation where the P-shield region 124a only exists under the corresponding trench after the final device is fabricated. As previously described, the P-shield region 124a is composed of multiple P-shield junctions and a P-shield bus (not shown) on each transistor cell. These P-shield junctions form the gate of JFET J1 and serve to protect the trench gate oxide of N-channel MOSFET Q1. The P-shield bus connects the multiple P-shield junctions of each transistor cell together and integrates to the node under the resistor region.

[0134] In step 163, CMP is performed to remove the excess P-shield and planarize the SiC surface. Thus, a desired thickness is left above the first silicon carbide layer 122 (see FIG. Figure 9d Next, in step 164, as Fig.9e As shown, a third silicon carbide layer 126 of a second conductivity type (P type) is formed by patterning and ion implantation using a second mask. The third silicon carbide layer 126 includes P-base regions 126c, 126d. Please note that during the formation of the third silicon carbide layer 126, the node depth of the P-base implantation is well controlled to implant through the P-shielding region, so that the portion of the P-shielding region 124c near the surface remains unchanged. After the third silicon carbide layer 126 is formed, the method proceeds to step 165, in which the third mask is patterned to form the P+ region 130 by ion implantation, and proceeds to step 166, in which the fourth mask is patterned to form the N+ region 128 by ion implantation. Figure 9f 1 shows the fabricated P+ region 130 and N+ region 128. Please note that during the formation of the P+ region 130 and the N+ region 128, the P-type portion at the top of the P-shielding region 124c is counter-doped by P+ implantation or N+ implantation. There is only one area at the top of the P-shielding region 124c that is not counter-doped, and this area disconnects the transistor region from the resistor region.

[0135] After the various silicon carbide layers are fabricated as described above, the method proceeds to step 167, where a fifth mask is used to pattern and etch a trench 136 into the first silicon carbide layer 122, and the trench 136 is aligned with each adjacent P-shield region 124a and extends laterally from each adjacent P-shield region 124a. The extension length depends on the control capability of alignment and critical dimension. In other words, Figure 9g As shown, the width of each trench 136 is greater than its corresponding P-shield region 124 a.

[0136] Next, in step 168, if Figure 9h The bottom gate oxide 132a is deposited using a HDP-CVD process as shown, and then a wet etch is performed in step 169 to remove the oxide on the surface and sidewalls of the trench 136, as shown in FIG. Figure 9i Thus, in one example, the thickness of the bottom gate oxide 132a is between 1000A and 4000A. On the other hand, in step 170, the sidewall gate oxide 132b is formed by a thermal oxidation process, such as Figure 9j As shown, a post-oxidation annealing is performed in step 171 to enhance electrical and interface properties.

[0137] In step 172, polysilicon material 134 is embedded in each trench 136. Figure 9k As shown, the initially embedded polysilicon material 134 is a layer covering the bottom gate oxide 132a, the sidewall gate oxide 132b and the entire surface of the silicon carbide. The polysilicon material 134 is deposited by LP-CVD and in-situ doped. To ensure good coverage and a planarized surface, the thickness of the polysilicon material 134 above the silicon carbide surface is preferably at least 5000 Å. Then, CMP is performed in step 173 to remove excess gate polysilicon or gate oxide from the silicon carbide surface, thereby forming Figure 9l After this, the polysilicon material 134 becomes discontinuous and is only located in each trench 136.

[0138] In step 174, field oxide 148 is deposited by a CVD process, and then patterned and etched using a sixth mask in step 175 to form contact regions for connecting upper and lower components on the silicon carbide surface. As described above, these contact regions are located between adjacent oxide portions 148b. The etched field oxide 148 is as shown in FIG. Figure 9m In step 176, as shown. Figure 9n As shown, a barrier metal 152 is deposited (including the contact region described above) and annealed to form an ohmic contact. Each barrier metal 152 is located between two adjacent oxide portions in the horizontal direction.

[0139] In step 177, if Figure 9o As shown, the pad polysilicon 123 is deposited on top of the field oxide 148 and the barrier metal 152 by CVD, and then the resistivity of the pad polysilicon 123 is trimmed by blanket ion implantation with a lower dopant dose in step 178. As described above, Figure 9q As shown, the pad polysilicon 123 eventually forms resistors R1, R2, Rg and gate polysilicon 156. In step 179, the appropriate portion of the pad polysilicon 123 is patterned using a seventh mask, and then ion implantation is performed using a higher dose of dopant to form resistors Rg and gate polysilicon 156, as shown in FIG. Figure 9p Then, in step 180, an eighth mask is used for patterning and etching to separate the resistors R1, R2, Rg and the gate polysilicon 156 from each other, as shown. Figure 9q shown.

[0140] Next, an ILD layer is deposited on top of the field oxide 148 and the barrier metal 152 in step 181 , and then patterned and etched using a ninth mask in step 182 to form a plurality of ILD portions 154 between which contact regions for electrode contacts may be formed. Figure 9r 18 shows the individual ILD portions 154 separated by contact regions. In step 183, a front metal is deposited using a sputtering process to form a source electrode 150 and a gate electrode 158. Figure 9s As shown, in step 184, the front metal is patterned and etched using a tenth mask to separate the source electrode 150 and the gate electrode 158 from each other. Finally, in step 185, a back metal is deposited on the back side of the silicon carbide substrate 120 of the silicon carbide MOSFET device and annealed to form a drain 146. At this point, the manufacture of the MOSFET device is completed.

[0141] Figure 11a-12 Another method for manufacturing a SiC MOSFET device according to another embodiment of the present invention is shown. Most of the steps in this method are the same as those described above with reference to Figure 9a-10 The steps described are similar, so for the sake of brevity, these steps will not be described in detail. Figure 11a-12 The methods and Figure 9a-10 Specifically, in step 262, when the first epitaxial process of the second conductivity type is performed to form the P-shielding region 224, as shown in FIG. Fig.11cAs shown in FIG. 2 , the portion of the P-shield region 224 (see 224c) above the first silicon carbide layer 222 is redundant and is only for planarization purposes. Therefore, in step 263, all the redundant P-shield portions above the silicon carbide surface are removed by CMP, and the top surface of the P-shield region 224 is flush with the top surface of the trench 221. Figure 9d In the embodiment where a certain thickness of the P-shielding region is left above the first silicon carbide layer 122, Fig.11d In the case of SiC, there is no extra P-shield region above the SiC surface. Fig.11e FIG. 2 shows that a second mask and ion implantation are used to perform patterning in step 264 to form a P-base region of the third silicon carbide layer 226, but Fig.11e and Fig.9e The difference is that the P-base region 226c is continuous in the transistor region across the transistor unit cell, while Fig.9e Nevertheless, in step 267, when etching trench 236, P-base region 226c is still separated into a plurality of parts, such as Figure 11g As shown, with Figure 9g Likewise, there is a discontinuity in the third silicon carbide layer 226 between the P-substrate region 226c on the transistor region side and the P-substrate region 226d on the resistor region side.

[0142] Figure 13a-14 Another method for manufacturing a SiC MOSFET device according to another embodiment of the present invention is shown. Most of the steps in this method are the same as those described above with reference to Figure 9a-10 The steps described are similar and will not be described in detail for the sake of brevity. Figure 13a-14 The methods and Figure 9a-10 In particular, Fig.13a The starting materials shown are Figure 9a The initial materials shown are different because the silicon carbide epitaxial wafer includes not only an N+ type silicon carbide substrate 320, an N-type first silicon carbide layer 322 thereon, but also a P-base layer 326 on the first silicon carbide layer 322. This can be achieved by the dual epitaxial material in step 361. Since the P-base layer 326 is provided in the initial material, there is no need to perform patterning and ion implantation to generate the P-base region in the subsequent steps. In the next step of forming the first trench 321, i.e., step 362, as shown in FIG. Fig.13b As shown, the P-base layer 326 is also etched together with the first silicon carbide layer 322 to form a plurality of P-base regions 326c. Fig.13c As shown, in step 363 of performing the first epitaxial process to form the P-shielding layer 324, the existing P-base region 326c will not be affected. Fig.13d As shown, in step 364, all the excess P-shield layer portions above the SiC surface are removed by CMP, and the top surface of the P-shield layer region 324 is flush with the top surface of the trench 321. Figure 9d In the embodiment different from Figure 9d In the embodiment, a P-shielding region with a certain thickness is left above the first silicon carbide layer 122 .

[0143] At this point, the exemplary embodiments of the present invention have been fully described. Although specific embodiments have been mentioned in the description, it will be apparent to those skilled in the art that the present invention can be implemented by variations of these specific details. Therefore, the present invention should not be construed as being limited to the embodiments described herein.

[0144] Although the present invention has been illustrated and described in detail in the accompanying drawings and the aforementioned specific embodiments, it should be regarded as exemplary rather than restrictive. It goes without saying that the present invention only shows and describes exemplary embodiments and does not limit the scope of the present invention in any way. It is understood that any feature described herein can be used in any embodiment. The exemplary embodiments of the present invention are not mutually exclusive, nor are they exclusive of other embodiments not described herein. Therefore, the present invention also provides an embodiment comprising a combination of one or more of the above-mentioned illustrative embodiments. Without departing from the spirit and scope of the present invention, the present invention described herein may be modified and varied, and therefore, only the limitations specified in the appended claims should be applied.

[0145] exist Figure 4a-5b In the described embodiments, specific gate voltages, such as 0-15V and 0-2.5V, and specific resistance values ​​are mentioned. It should be understood by those skilled in the art that the present invention is not limited to any specific gate voltage, resistance value, or voltage divider ratio. Instead, the layout of the circuit and the structure of the SiC MOSFET device are the unique features of the embodiments of the present invention.

[0146] Similarly, in the exemplary embodiments, different materials for making electrodes, masks or dopants are described. In addition, different thicknesses and doping concentrations are discussed. It should be understood by those skilled in the art that all these specific parameters and selections should not be considered as limitations of the present invention. On the contrary, the technician can adopt different materials and / or different parameters according to different practical applications without departing from the spirit of the present invention. For example, when making electrodes, a variety of conductive materials can be selected, such as titanium (Ti), nickel (Ni), titanium nitride (TiN), titanium aluminum (TiAl), platinum (Pt), aluminum (Al), etc.

Claims

1. A silicon carbide MOSFET device, comprising: N-channel MOSFET; a JFET connected to the N-channel MOSFET such that drain-source current paths of the N-channel MOSFET and the JFET are connected in series with each other; Wherein, the gate of the JFET is connected to the gate of the N-channel MOSFET device through a voltage divider.

2. The silicon carbide MOSFET device according to claim 1, wherein the drain of the JFET is configured as the drain of the silicon carbide MOSFET device; the source of the N-channel MOSFET is configured as the source of the silicon carbide MOSFET device; and the source of the JFET is connected to the drain of the N-channel MOSFET. 3 . The silicon carbide MOSFET device of claim 1 , wherein the voltage divider comprises a resistor network.

4. The silicon carbide MOSFET device according to claim 1, wherein the voltage divider is configured to limit the gate voltage of the JFET so that when the N-channel MOSFET is turned on or off, the SiC PN diode formed in the silicon carbide MOSFET device is turned off.

5. The silicon carbide MOSFET device according to claim 1, wherein a gate resistor is connected between a gate of the silicon carbide MOSFET device and the gate of the N-channel MOSFET; the gate resistor is configured to control a switching speed of the N-channel MOSFET.

6. A silicon carbide MOSFET device, comprising: a silicon carbide substrate of a first doping type; a first silicon carbide layer of a first dopant type located on top of the silicon carbide substrate; a plurality of grooves partially formed in the first silicon carbide layer; The exterior of each of the plurality of trenches is covered with a gate oxide; a second silicon carbide layer of a second doping type embedded in the first silicon carbide layer; the second silicon carbide layer comprising a plurality of second portions; a third silicon carbide layer of a second dopant type overlying at least a portion of the second silicon carbide layer; as well as a fourth silicon carbide layer overlying at least a portion of the third silicon carbide layer; The gate oxide of each of the plurality of trenches includes a bottom surface and a side surface; a corresponding one of the plurality of second portions is located directly below the bottom surface of the gate oxide of each of the plurality of trenches; The silicon carbide MOSFET device further includes a plurality of resistors, which are formed on the same chip as the silicon carbide substrate and the first to fourth silicon carbide layers.

7. The silicon carbide MOSFET device according to claim 6, wherein the first dopant type is N, the second dopant type is P; the second silicon carbide layer and the third silicon carbide layer are P-layers; and the fourth silicon carbide layer includes P+ and N+ regions. 8 . The silicon carbide MOSFET device of claim 6 , wherein a corresponding one of the plurality of second portions does not cover the side surface of the gate oxide of each of the plurality of trenches. 9 . The silicon carbide MOSFET device according to claim 6 , wherein the plurality of resistors are offset from the plurality of trenches in a horizontal direction. 10 . The silicon carbide MOSFET device of claim 9 , wherein the plurality of resistors are located above the fourth silicon carbide layer. 11 . The silicon carbide MOSFET device according to claim 6 , wherein the plurality of resistors include a first resistor and a second resistor; the first resistor and the second resistor are both connected to the plurality of second portions. 12 . The silicon carbide MOSFET device of claim 11 , wherein the first resistor and the second resistor form a voltage divider. 13 . The silicon carbide MOSFET device of claim 11 , wherein the second resistor is electrically connected to a source of the silicon carbide MOSFET device.

14. The silicon carbide MOSFET device of claim 6, wherein the plurality of resistors comprises a third resistor; the third resistor connects the polysilicon in each of the plurality of trenches to the gate of the silicon carbide MOSFET device. 15 . The silicon carbide MOSFET device of claim 14 , wherein the gate electrode is horizontally offset from a source of the silicon carbide MOSFET device.

16. The silicon carbide MOSFET device according to claim 6, further comprising a field oxide layer located on top of the fourth silicon carbide layer; the field oxide layer comprises a plurality of oxide portions, each of the oxide portions being formed above and corresponding to one of the plurality of trenches.

17. The silicon carbide MOSFET device of claim 16, further comprising a dielectric layer substantially located on top of the field oxide layer; the dielectric layer comprising a plurality of dielectric insulating portions, each of the dielectric insulating portions being formed above and corresponding to one of the oxide portions.

18. A method for producing a silicon carbide MOSFET device, comprising the following steps: providing a first silicon carbide layer of a first doping type on a silicon carbide substrate; forming a plurality of trenches partially embedded in the first silicon carbide layer; each of the plurality of trenches being covered with a gate oxide; embedding a second silicon carbide layer of a second dopant type in the first silicon carbide layer; the second silicon carbide layer comprising a plurality of second portions; providing a third silicon carbide layer of a second dopant type over at least a portion of the second silicon carbide layer; as well as providing a fourth silicon carbide layer over at least a portion of the third silicon carbide layer; as well as A plurality of resistors formed on the same chip as the silicon carbide substrate and the first to fourth silicon carbide layers; The gate oxide of each of the plurality of trenches includes a bottom surface and a side surface; and a corresponding one of the plurality of second portions is located directly below the bottom surface of the gate oxide of each of the plurality of trenches.

19. The method according to claim 18, wherein the first dopant type is N, the second dopant type is P; the second silicon carbide layer and the third silicon carbide layer are P-layers; and the fourth silicon carbide layer includes a P+ region and an N+ region.

20. The method of claim 18, wherein the step of embedding the second silicon carbide layer further comprises: forming a plurality of first trenches in the first silicon carbide layer; Performing epitaxy of a second dopant type on the first silicon carbide layer including the plurality of first trenches to form a second silicon carbide layer; as well as The second silicon carbide layer is patterned and etched at predetermined locations to form the plurality of second portions.

21. The method of claim 18, wherein the step of monolithically forming a plurality of resistors further comprises: providing a polysilicon layer on the fourth silicon carbide layer; implanting the polysilicon layer with a first dopant type to achieve a suitable resistivity in the polysilicon layer; The polysilicon layer is patterned and etched to form a first resistor and a second resistor.

22. The method of claim 21, wherein the first resistor and the second resistor form a voltage divider.

23. The method of claim 21, wherein the second resistor is electrically connected to a source of the silicon carbide MOSFET device.

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