Groove type MOSFET device integrated with junction control diode and electronic equipment

Abstract

The invention provides a trench type MOSFET device integrated with a junction control diode and electronic equipment, and relates to the technical field of semiconductor devices. The P-type epitaxial layer, the first P-type masking layer and the second P-type masking layer are grounded, a better electric field shielding effect can be obtained during reverse voltage withstanding, and voltage jump caused by floating of the P-type epitaxial layer, the first P-type masking layer and the second P-type masking layer can be avoided in the switching process, so that degradation of the switching characteristic of the device is avoided. Moreover, a junction-controlled fly-wheel diode region is led out between the two trench MOSFET regions, and the conduction voltage drop of the integrated junction-controlled fly-wheel diode is lower than that of a body diode of the device, so that the conduction of the body diode is shielded; moreover, the junction-controlled fly-wheel diode is a unipolar device, does not have a minority carrier storage effect, is short in reverse recovery time, can reduce the switching loss of the device, and improves the performance of the trench type MOSFET device.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and more specifically, to a trench MOSFET device and electronic equipment with an integrated junction-controlled diode. Background Art

[0002] In recent years, wide-bandgap semiconductor materials such as silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), diamond (C), and aluminum nitride (AlN) have advantages over silicon (Si) in physical properties such as bandgap width, breakdown field strength, and electron saturation drift velocity. The power devices prepared from them, such as diodes, transistors, and power modules, have better electrical properties and can overcome the defects of silicon-based materials that cannot meet application requirements such as high power, high voltage, high frequency, and high temperature. They are also one of the breakthrough paths that can surpass Moore's Law. Therefore, they are widely used in new energy fields such as photovoltaics, energy storage, charging piles, electric vehicles, and other fields.

[0003] However, in the actual design, manufacture and application of power devices, there are still several problems in the actual process manufacturing and application of trench MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) made of wide bandgap semiconductor materials: the high electric field in the drift region of the material leads to a high electric field on the gate dielectric layer, which is aggravated at the groove corner, causing the gate dielectric layer to break down quickly under high drain voltage, and poor tolerance to electrostatic effects in harsh environments and high-voltage spikes in the circuit; the parasitic body diode has a minority carrier storage effect, and the reverse recovery time is long, which increases the switching loss. Therefore, how to reduce the switching loss while reducing the electric field at the groove corner of the gate trench of the wide bandgap semiconductor trench MOSFET device has become a problem that needs to be solved. Summary of the invention

[0004] In view of this, the present application provides a trench MOSFET device and electronic device with an integrated junction-controlled diode, which effectively solves the technical problems existing in the prior art and improves the performance of the trench MOSFET device.

[0005] To achieve the above objectives, the technical solutions provided by this application are as follows:

[0006] A trench MOSFET device with an integrated junction-controlled diode, the trench MOSFET device comprising: two trench MOSFET regions arranged along a first direction, and a junction-controlled freewheeling diode region between the two trench MOSFET regions;

[0007] The drain, the N-type substrate, the first N-type epitaxial layer, the P-type epitaxial layer and the second N-type epitaxial layer are sequentially stacked along the third direction:

[0008] Wherein, at the trench MOSFET region, the P-type epitaxial layer includes at least one N-type current channel arranged along the second direction; a P-type well region located on the second N-type epitaxial layer; a source contact region located on the P-type well region, the source contact region including a source N+ region and a source P+ region; a trench gate electrode penetrating the source contact region and the P-type well region and extending deep into the second N-type epitaxial layer; a second P-type shielding layer located at the bottom of the trench gate electrode; a first P-type grounding column connecting the second P-type shielding layer and the P-type epitaxial layer; and an interlayer dielectric layer covering the top of the trench gate electrode; the first direction and the second direction intersect at a reference plane, and the third direction intersects with the reference plane;

[0009] The junction-controlled freewheeling diode region includes a first P-type shielding layer located in the second N-type epitaxial layer and connected to the P-type epitaxial layer, and the first P-type shielding layer is connected to the P-type well region;

[0010] And, a source located at a side of the source contact region away from the N-type substrate.

[0011] Optionally, in the trench MOSFET region, the source N+ region and the source P+ region are arranged along the first direction, and the source P+ region is located on a side close to the first P-type masking layer, and the trench gate electrode penetrates the source N+ region and the P-type well region and penetrates into the second N-type epitaxial layer.

[0012] Optionally, at the junction-controlled freewheeling diode region, the first P-type shielding layer is extended along the second direction;

[0013] The first P-type masking layer and the P-type well region have a gap filled with the second N-type epitaxial layer in the first direction, and the trench MOSFET device also includes at least one second P-type grounding column located between the first P-type masking layer and the P-type well region, and the second P-type grounding column is in contact and connected with the first P-type masking layer and the P-type well region.

[0014] Optionally, in the first direction, the second P-type grounding columns on both sides of the first P-type shielding layer are symmetrically or asymmetrically arranged with the first P-type shielding layer as an axis.

[0015] Optionally, the source P+ region also extends to the junction-controlled freewheeling diode region, an overlapping area is provided between the source P+ region and the first P-type shielding layer in the third direction, and a gap filled with the second N-type epitaxial layer is provided between the source P+ region and the first P-type shielding layer in the third direction.

[0016] Optionally, in a direction from the source to the drain, a width of the first P-type shielding layer in the first direction tends to decrease.

[0017] Optionally, at the trench MOSFET region, the source N+ region includes a plurality of sub-source N+ regions extending along the first direction, and the source P+ region includes a plurality of sub-source P+ regions extending along the first direction, and the sub-source N+ regions and the sub-source P+ regions are alternately arranged in the second direction;

[0018] The sub-source N+ region and the sub-source P+ region of the two trench MOSFET regions are extended to the junction-controlled freewheeling diode region and are connected correspondingly.

[0019] Optionally, at the junction-controlled freewheeling diode region, the first P-type shielding layer includes a plurality of sub-P-type shielding layers spaced apart along the second direction;

[0020] The sub-P-type shielding layer is in contact with and connected to the P-type well region.

[0021] Optionally, in the third direction, the sub-P-type shielding layer and the sub-source P+ region have an overlapping area.

[0022] Based on the same inventive concept, the present application also provides an electronic device, which includes the above-mentioned trench MOSFET device with integrated junction-controlled diode.

[0023] Compared with the prior art, the technical solution provided by this application has at least the following advantages:

[0024] The present application provides a trench MOSFET device and an electronic device with an integrated junction-controlled diode, wherein the trench MOSFET device comprises: two trench MOSFET regions arranged along a first direction, and a junction-controlled freewheeling diode region is included between the two trench MOSFET regions; a drain, an N-type substrate, a first N-type epitaxial layer, a P-type epitaxial layer, and a second N-type epitaxial layer are sequentially stacked along a third direction: wherein, at the trench MOSFET region, the P-type epitaxial layer comprises at least one N-type current channel arranged along a second direction; a P-type well region located on the second N-type epitaxial layer; a source contact region located on the P-type well region, the source contact region comprising a source N+ region and a source P+ region ; a trench gate electrode that penetrates the source contact area and the P-type well area and penetrates into the second N-type epitaxial layer; a second P-type shielding layer located at the bottom of the trench gate electrode; a first P-type grounding column connecting the second P-type shielding layer and the P-type epitaxial layer; and an interlayer dielectric layer covering the top of the trench gate electrode; the first direction and the second direction intersect at a reference plane, and the third direction intersects with the reference plane; at the junction-controlled freewheeling diode area, includes a first P-type shielding layer located in the second N-type epitaxial layer and connected to the P-type epitaxial layer, the first P-type shielding layer is connected to the P-type well area; and a source located at the side of the source contact area away from the N-type substrate.

[0025] It can be seen from the above content that the technical solution provided by the present application shields the electric field at the trench gate electrode through the P-type epitaxial layer, the first P-type shielding layer and the second P-type shielding layer, and the design that the first P-type grounding column and the first P-type shielding layer are connected to the P-type well region makes the P-type epitaxial layer, the first P-type shielding layer and the second P-type shielding layer grounded, and can obtain a better electric field shielding effect during reverse withstand voltage, and can avoid the P-type epitaxial layer, the first P-type shielding layer and the second P-type shielding layer from floating and causing voltage jumps during the switching process, thereby avoiding the degradation of the switching characteristics of the device. In addition, a junction-controlled freewheeling diode region is introduced between the two trench MOSFET regions, and the conduction voltage drop of the integrated junction-controlled freewheeling diode will be lower than the body diode of the device, thereby shielding the conduction of the body diode; and the junction-controlled freewheeling diode is a unipolar device, there is no minority carrier storage effect, and the reverse recovery time is short, which can reduce the switching loss of the device, thereby improving the performance of the trench MOSFET device. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0027] Figure 1 A schematic diagram of the structure of a trench MOSFET device with an integrated junction-controlled diode provided in an embodiment of the present application;

[0028] Figure 2 A flow chart of a method for preparing a trench MOSFET device with an integrated junction-controlled diode provided in an embodiment of the present application;

[0029] Figures 3a to 3f for Figure 2 The structural schematic diagram corresponding to each step in the figure;

[0030] Figure 4 A schematic structural diagram of another trench MOSFET device with an integrated junction-controlled diode provided in an embodiment of the present application;

[0031] Figure 5 A schematic structural diagram of another trench MOSFET device with an integrated junction-controlled diode provided in an embodiment of the present application;

[0032] Figure 6 for Figure 5 A cross-sectional view at the mid-section A;

[0033] Figure 7 for Figure 5 Another cross-sectional view at the mid-section A. DETAILED DESCRIPTION

[0034] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0035] As described in the background technology, in the actual design, manufacture and application of power devices, there are still several problems in the actual process manufacture and application of trench MOSFET made of wide bandgap semiconductor materials: the high electric field in the drift region of the material leads to a high electric field on the gate dielectric layer, which is aggravated at the groove corner, causing the gate dielectric layer to break down quickly under high drain voltage, and poor tolerance to electrostatic effects in harsh environments and high-voltage spikes in the circuit; the parasitic body diode has a minority carrier storage effect, and the reverse recovery time is long, which increases the switching loss. Therefore, how to reduce the switching loss while reducing the electric field at the groove corner of the gate trench of the wide bandgap semiconductor trench MOSFET device has become a problem that needs to be solved.

[0036] Based on this, the embodiments of the present application provide a trench MOSFET device and electronic device with an integrated junction-controlled diode, which effectively solves the technical problems existing in the prior art and improves the performance of the trench MOSFET device.

[0037] To achieve the above purpose, the technical solution provided in the embodiment of the present application is as follows, specifically combined with Figures 1 to 7 The technical solution provided in the embodiment of the present application is described in detail. It should be noted that the trench MOSFET device with integrated junction-controlled diode provided in the present application has many regions and structural layers, so the attached Figures 1 to 7 Each region and / or structural layer shown in the figure is indicated by different colors; Figures 1 to 7 The different colors shown are only used to distinguish the positional relationship of various regions and / or structural layers of the device.

[0038] refer to Figure 1As shown, it is a schematic diagram of the structure of a trench MOSFET device with an integrated junction-controlled diode provided in an embodiment of the present application, wherein the trench MOSFET device includes: two trench MOSFET regions S1 arranged along a first direction, and a junction-controlled freewheeling diode region S2 is included between the two trench MOSFET regions S1. The trench MOSFET device is in a stacked structure in a third direction, wherein the trench MOSFET device includes: a drain 10, an N-type substrate 21, a first N-type epitaxial layer 22, a P-type epitaxial layer 31, and a second N-type epitaxial layer 23 stacked in sequence along the third direction: wherein, at the trench MOSFET region S1, the P-type epitaxial layer 31 includes at least one N-type current channel 24 arranged along the second direction; a P-type well region 32 located on the second N-type epitaxial layer 23; a source contact region located on the P-type well region 32, the source contact region including a source N+ region 25 and source P+ region 33; a trench gate electrode that penetrates the source contact region and the P-type well region 32 and penetrates into the second N-type epitaxial layer 23, the trench gate electrode can extend along the second direction, and the trench gate electrode can include a gate dielectric layer 41 covering the inner wall of the gate trench and a gate 42 located in a groove formed in the gate dielectric layer 41; a second P-type masking layer 34 located at the bottom of the trench gate electrode; a first P-type grounding column 35 connecting the second P-type masking layer 34 and the P-type epitaxial layer 31; and an interlayer dielectric layer 43 covering the top of the trench gate electrode. The junction-controlled freewheeling diode region S2 includes a first P-type shielding layer 36 located in the second N-type epitaxial layer 23 and connected to the P-type epitaxial layer 31, the first P-type shielding layer 36 is connected to the P-type well region 32; and a source 50 located on the side of the source contact region away from the N-type substrate 21, the source 50 covers the source contact region, the interlayer dielectric layer 43 and the exposed surface of the second N-type epitaxial layer 23. The first direction and the second direction intersect at the reference plane, and the third direction intersects with the reference plane; optionally, the first direction and the second direction are perpendicular to each other, and the third direction is perpendicular to the reference plane.

[0039] It can be understood that the first P-type grounding column 35 provided in the embodiment of the present application connects the P-type epitaxial layer 31 and the second P-type shielding layer 34, the first P-type shielding layer 36 is arranged in the second N-type epitaxial layer 23 and connected to the P-type epitaxial layer 31, the first P-type shielding layer 36 is also connected to the P-type well region 32, the source P+ region 33 is arranged on the P-type well region 32 and connected, and the source P+ region 33 is connected to the source 50, thereby forming a second P-type shielding layer 36. The connecting paths are from the shielding layer 34 to the first P-type grounding column 35, from the first P-type grounding column 35 to the P-type epitaxial layer 31, from the P-type epitaxial layer 31 to the first P-type shielding layer 36, from the first P-type shielding layer 36 to the P-type well region 32, from the P-type well region 32 to the source P+ region 33, and from the source P+ region to the source 50. Since the source 50 is grounded by default when the trench MOSFET device is working, the grounding of all P-type regions in the trench MOSFET device is achieved.

[0040] It can be seen from the above content that the technical solution provided in the embodiment of the present application jointly shields the electric field at the trench gate electrode through the P-type epitaxial layer 31, the first P-type shielding layer 36 and the second P-type shielding layer 34, and through the design of the first P-type grounding column 35 and the first P-type shielding layer 36 connected to the P-type well area 32, the P-type epitaxial layer 31, the first P-type shielding layer 36 and the second P-type shielding layer 34 are grounded, and a better electric field shielding effect can be obtained during reverse withstand voltage, and during the switching process, the P-type epitaxial layer 31, the first P-type shielding layer 36 and the second P-type shielding layer 34 can be prevented from causing voltage jumps due to floating, thereby avoiding degradation of the switching characteristics of the device. In addition, a junction-controlled freewheeling diode region S2 is introduced between the two trench MOSFET regions S1. The on-state voltage drop of the integrated junction-controlled freewheeling diode will be lower than the body diode of the device, thereby shielding the conduction of the body diode. In addition, the junction-controlled freewheeling diode is a unipolar device, has no minority carrier storage effect, and has a short reverse recovery time, which can reduce the switching loss of the device, thereby improving the performance of the trench MOSFET device.

[0041] continue Figure 1As shown, at the trench MOSFET region S1, the source N+ region 25 and the source P+ region 33 are arranged along the first direction, and the source P+ region 33 is located on the side close to the first P-type masking layer 36 (that is, the side of the source P+ region 33 close to the junction-controlled freewheeling diode region S2), and the trench gate electrode penetrates the source N+ region 25 and the P-type well region 32, and penetrates into the second N-type epitaxial layer 23. Among them, the gate trench penetrates the source N+ region 25 and the P-type well region 32, and penetrates into the second N-type epitaxial layer 23, and a gate dielectric layer 41 is formed on the inner wall of the gate trench, and a gate 42 is arranged in the groove formed by the gate dielectric layer 41. In order to prevent the trench gate electrode from being short-circuited with the source 50, an interlayer dielectric layer 43 is provided to cover the top surface of the gate 42. Among them, the source P+ region 33 also extends to the junction-controlled freewheeling diode region S2, and there is an overlapping area between the source P+ region 33 and the first P-type masking layer 36 in the third direction, and there is a gap filled with the second N-type epitaxial layer 23 between the source P+ region 33 and the first P-type masking layer 36 in the third direction, and the second N-type epitaxial layer extends to fill the gap between the source P+ regions 33 of the two trench MOSFET regions S1, so that a PN junction-controlled freewheeling diode is formed between the two source P+ regions 33.

[0042] Still Figure 1 As shown, at the junction-controlled freewheeling diode area S2, the first P-type masking layer 36 is extended along the second direction; the first P-type masking layer 36 and the P-type well area 32 have a gap filled by the second N-type epitaxial layer 23 in the first direction, and the trench MOSFET device also includes at least one second P-type grounding column 37 located between the first P-type masking layer 36 and the P-type well area 32, and the second P-type grounding column 37 is in contact and connected with the first P-type masking layer 36 and the P-type well area 32, that is, the connection between the first P-type masking layer 36 and the P-type well area 32 is achieved through the second P-type grounding column 37. The trench MOSFET device provided in the embodiment of the present application introduces three JFET (Junction Field-Effect Transistor) regions between the two source P+ regions 33, between the first P-type masking layer 36 and the P-type well region 32, and between the first P-type masking layer 36 and the source P+ region 33. During reverse withstand voltage, the presence of multiple JFET regions can better suppress the leakage of the junction-controlled freewheeling diode, further improving the performance of the trench MOSFET device.

[0043] In one embodiment of the present application, the first P-type shielding layer 36, the second P-type shielding layer 34, the first P-type grounding column 35, the second P-type grounding column 37, the P-type well region 32, the source N+ region 25, the source P+ region 33, and the N-type current channel 24 provided in the embodiment of the present application can be formed by ion implantation. Figure 1 As shown in Figure 3, Figure 2 A flowchart of a method for preparing a trench MOSFET device with an integrated junction-controlled diode provided in an embodiment of the present application, Figures 3a to 3f for Figure 2 The structural schematic diagram corresponding to each step in the present invention is shown in FIG. 1 . The method for preparing a trench MOSFET device includes:

[0044] S1, sequentially growing a first N-type epitaxial layer 22, a P-type epitaxial layer 31 and a second N-type epitaxial layer 23 on an N-type substrate 21, as shown in Figure 3a The N-type substrate 21 may be made of wide bandgap semiconductor materials, such as silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), diamond (C), aluminum nitride (AlN), etc., so that the trench MOSFET device is formed into a wide bandgap trench MOSFET device.

[0045] S2, forming a first P-type shielding layer 36, a second P-type grounding column 37, a P-type well region 32, a source N+ region 25 and a source P+ region 33, as shown in FIG. Figure 3b shown. Figure 3b The left side figure is a cross-sectional view of the second P-type grounding column 37. Figure 3b The right side figure is a cross-sectional view without the second P-type grounding column 37. The second N-type epitaxial layer 23 is processed by ion implantation to form a first P-type masking layer 36, a second P-type grounding column 37, a P-type well region 32, a source N+ region 25 and a source P+ region 33 in the second N-type epitaxial layer 23, wherein the first P-type masking layer 36 is in contact with the P-type epitaxial layer 31, the second P-type grounding column 37 is in contact with the P-type well region 32, and the first P-type masking layer 36 is in contact with the second P-type grounding column 37. Optionally, the first P-type shielding layer 36 and the first P-type grounding column 37 can be formed simultaneously by ion implantation; or, the first P-type shielding layer 36 and the first P-type grounding column 37 can be formed in two steps by ion implantation, and the ion input depths of the first P-type shielding layer 36 and the first P-type grounding column 37 are the same or different when they are formed, wherein the heights of the first P-type shielding layer 36 and the first P-type grounding column 37 in the third direction can be the same or different.

[0046] In the first direction, the second P-type grounding columns 37 on both sides of the first P-type shielding layer 36 provided in the embodiment of the present application are symmetrically or asymmetrically arranged with the first P-type shielding layer 36 as an axis.

[0047] S3, etching to form a gate trench 44, such as Figure 3c shown. Figure 3c The left side figure is a cross-sectional view of the second P-type grounding column 37. Figure 3c The right side figure is a cross-sectional view without the second P-type grounding column 37. The gate trench 44 penetrates the source contact area, the P-type well area 32 and penetrates into the second N-type epitaxial layer 23. The gate trench 44 can be formed by dry etching process, and this application does not make any specific restrictions on this.

[0048] S4, forming a first P-type masking layer 34, such as Figure 3d shown. Figure 3d The left side figure is a cross-sectional view of the second P-type grounding column 37. Figure 3d The right side figure is a cross-sectional view without the second P-type grounding column 37 , and the first P-type masking layer 34 is formed at the bottom of the gate trench 44 by ion implantation.

[0049] S5, forming an N-type current channel 24 and a first P-type grounding column 35, such as Figure 3e shown. Figure 3e The left side figure is a cross-sectional view of the second P-type grounding column 37, and Figure 3e The left figure shows the N-type current channel 24; Figure 3e The right side figure is a cross-sectional view without the second P-type grounding column 37, and Figure 3e The right side figure uses the first P-type grounding column 35 as an illustration, and uses ion implantation to form an N-type current channel 24 in the P-type epitaxial layer 31, and the N-type current channel 24 connects the first N-type epitaxial layer 22 and the second N-type epitaxial layer 23; and uses ion implantation to form the first P-type grounding column 35 to connect the second masking layer 34 and the P-type epitaxial layer 31.

[0050] S6, forming a gate dielectric layer 41, a gate 42, an interlayer dielectric layer 43, a source 50 and a drain 10, as shown in Figure 3f shown. Figure 3f The left side figure is a cross-sectional view of the second P-type grounding column 37, and Figure 3f The left figure shows the N-type current channel 24; Figure 3f The right side figure is a cross-sectional view without the second P-type grounding column 37, and Figure 3f The right side figure shows the first P-type grounding column 35 as an example. A gate dielectric layer 41 is grown on the inner wall of the gate trench 44, and then the gate 32 is filled in the groove formed by the gate dielectric layer 41 to form a trench gate electrode. Finally, an interlayer dielectric layer 43 is deposited and etched on the source contact area to cover the trench gate electrode. In addition, a source metal is deposited to form a source 50, and the source 50 covers the interlayer dielectric layer 43, the source contact area, and the exposed surface of the second N-type epitaxial layer 23; and a drain metal is deposited to form a drain 10, and the drain 10 is located on the side of the N-type substrate 21 away from the source 50.

[0051] exist Figure 1 Based on the trench MOSFET device shown, the first P-type masking layer 36 provided in the embodiment of the present application can also be optimized to increase the current channel. Figure 4 FIG. 1 is a schematic diagram of the structure of another trench MOSFET device with integrated junction-controlled diode provided in an embodiment of the present application, wherein Figure 1 On the basis of the trench MOSFET device shown, in the direction from the source 50 to the drain 10, the width of the first P-type shielding layer 36 in the first direction tends to decrease, and the first P-type shielding layer 36 is prepared into a shape that is wide at the top and narrow at the bottom, so that the current channel below it is wider, further improving the performance of the trench MOSFET device. Optionally, the sidewall of at least one side of the first P-type shielding layer 36 in the first direction is in a plurality of steps.

[0052] In some embodiments, the shapes of the trench MOSFET region S1 and the junction-controlled freewheeling diode region S2 provided in the embodiments of the present application can also be deformed to distinguish them from Figure 1 The specific structure of the trench MOSFET device shown in FIG. Figure 5 and Figure 6 As shown, Figure 5 A schematic diagram of the structure of another trench MOSFET device with an integrated junction-controlled diode provided in an embodiment of the present application, Figure 6 for Figure 5Sectional view at section A. Wherein, the trench MOSFET device includes: two trench MOSFET regions S1 arranged along the first direction, and a junction-controlled freewheeling diode region S2 is included between the two trench MOSFET regions S1. The trench MOSFET device is in a stacked structure in the third direction, wherein the trench MOSFET device includes: a drain 10, an N-type substrate 21, a first N-type epitaxial layer 22, a P-type epitaxial layer 31 and a second N-type epitaxial layer 23 stacked in sequence along the third direction: wherein, at the trench MOSFET region S1, the P-type epitaxial layer 31 includes at least one N-type current channel 24 arranged along the second direction; a P-type well region 32 located on the second N-type epitaxial layer 23; a source contact region located on the P-type well region 32, the source contact region including a source N+ region 25 and source P+ region 33; a trench gate electrode that penetrates the source contact region and the P-type well region 32 and penetrates into the second N-type epitaxial layer 23, the trench gate electrode can extend along the second direction, and the trench gate electrode can include a gate dielectric layer 41 covering the inner wall of the gate trench and a gate 42 located in a groove formed in the gate dielectric layer 41; a second P-type masking layer 34 located at the bottom of the trench gate electrode; a first P-type grounding column 35 connecting the second P-type masking layer 34 and the P-type epitaxial layer 31; and an interlayer dielectric layer 43 covering the top of the trench gate electrode. At the junction-controlled freewheeling diode region S2, it includes a first P-type shielding layer 36 located in the second N-type epitaxial layer 23 and connected to the P-type epitaxial layer 31, the first P-type shielding layer 36 is connected to the P-type well region 32; and a source 50 located on the side of the source contact region away from the N-type substrate 21, the source 50 covers the source contact region, the interlayer dielectric layer 43 and the exposed surface of the second N-type epitaxial layer 23.

[0053] Continue as Figure 5As shown, at the trench MOSFET area S1, the source N+ area 25 includes a plurality of sub-source N+ areas 251 extending along the first direction, and the source P+ area 33 includes a plurality of sub-source P+ areas 331 extending along the first direction, and the sub-source N+ areas 251 and the sub-source P+ areas 331 are alternately arranged in the second direction; the sub-source N+ areas 251 and the sub-source P+ areas 331 of the two trench MOSFET areas S1 extend to the junction-controlled freewheeling diode area S1 and are correspondingly connected. And, at the junction-controlled freewheeling diode area S1, the first P-type shielding layer 36 includes a plurality of sub-P-type shielding layers 361 spaced apart along the second direction; the sub-P-type shielding layer 361 is in contact with the P-type well area 32, wherein the gap between two adjacent sub-P-type shielding layers 361 is filled by the second N-type epitaxial layer 23, and the gap between the sub-P-type shielding layer 361 and the source contact area is also filled by the second N-type epitaxial layer 23, so that a PN junction-controlled freewheeling diode is formed between the two sub-source P+ areas 331, and the conduction voltage drop of the junction-controlled freewheeling diode will be lower than the body diode of the device, thereby shielding the conduction of the body diode; and the junction-controlled freewheeling diode is a unipolar device, there is no minority carrier storage effect, and the reverse recovery time is short, which can reduce the switching loss of the device, thereby improving the performance of the trench MOSFET device.

[0054] Moreover, in the third direction, the sub-P-type masking layer 361 and the sub-source P+ region 331 have an overlapping area, so that two JFET regions are introduced between two adjacent sub-P-type masking layers 361 and between the sub-P-type masking layer 361 and the sub-source P+ region 331. During reverse withstand voltage, the existence of multiple JFET regions can better suppress the leakage of the junction-controlled freewheeling diode, further improving the performance of the trench MOSFET device.

[0055] It can be understood that the first P-type grounding column 35 provided in the embodiment of the present application connects the P-type epitaxial layer 31 and the second P-type shielding layer 34, the first P-type shielding layer 36 is arranged in the second N-type epitaxial layer 23 and is connected to the P-type epitaxial layer 31, the sub-P-type shielding layer 361 is also in contact with the P-type well region 32, the source P+ region 33 is arranged on the P-type well region 32 and is connected, and the source P+ region 33 is connected to the source 50, thereby forming a second P-type shielding layer The connection paths from the first P-type grounding column 34 to the first P-type grounding column 35, the first P-type grounding column 35 to the P-type epitaxial layer 31, the P-type epitaxial layer 31 to the sub-P-type shielding layer 361, the sub-P-type shielding layer 361 to the P-type well region 32, and the P-type well region 32 to the sub-source P+ region 331, and the sub-source P+ region 331 to the source 50. Since the source 50 is grounded by default when the trench MOSFET device is working, the grounding of all P-type regions in the trench MOSFET device is achieved. Furthermore, a better electric field shielding effect can be obtained during reverse withstand voltage, and during the switching process, the P-type epitaxial layer 31, the first P-type shielding layer 36 and the second P-type shielding layer 34 can be prevented from generating voltage jumps due to floating, thereby avoiding the degradation of the switching characteristics of the device.

[0056] like Figure 6 As shown, the sub-P-type shielding layer 361 and the sub-source P+ region 331 provided in the embodiment of the present application can be arranged to overlap relatively in the third direction, that is, the sub-P-type shielding layer 361 and the sub-source P+ region 331 can have the same width in the second direction, and the sub-P-type shielding layer 361 and the sub-source P+ region 331 overlap in the third direction. Or, as Figure 7 As shown, the sub-P-type shielding layer 361 and the sub-source P+ region 331 provided in the embodiment of the present application can be staggered and overlapped in the third direction, that is, the widths of the sub-P-type shielding layer 361 and the sub-source P+ region 331 in the second direction can be the same, and the sub-P-type shielding layer 361 and the sub-source P+ region 331 partially overlap in the third direction. In some embodiments, the widths of the sub-P-type shielding layer 361 and the sub-source P+ region 331 in the second direction can also be different, and it is only necessary to ensure that the sub-P-type shielding layer 361 and the sub-source P+ region 331 at least partially overlap in the third direction, and the present application does not make any specific restrictions on this.

[0057] Based on the same inventive concept, an embodiment of the present application further provides an electronic device, which includes a trench MOSFET device with an integrated junction-controlled diode provided by any of the above embodiments.

[0058] The embodiment of the present application provides a trench MOSFET device and an electronic device with an integrated junction-controlled diode, wherein the trench MOSFET device comprises: two trench MOSFET regions arranged along a first direction, and a junction-controlled freewheeling diode region is included between the two trench MOSFET regions; a drain, an N-type substrate, a first N-type epitaxial layer, a P-type epitaxial layer, and a second N-type epitaxial layer stacked in sequence along a third direction: wherein, at the trench MOSFET region, the P-type epitaxial layer comprises at least one N-type current channel arranged along a second direction; a P-type well region located on the second N-type epitaxial layer; a source contact region located on the P-type well region, the source contact region comprising a source N+ region and a source P+ region; a trench gate electrode that penetrates the source contact region and the P-type well region and penetrates into the second N-type epitaxial layer; a second P-type shielding layer located at the bottom of the trench gate electrode; a first P-type grounding column connecting the second P-type shielding layer and the P-type epitaxial layer; and an interlayer dielectric layer covering the top of the trench gate electrode; the first direction and the second direction intersect at a reference plane, and the third direction intersects with the reference plane; at the junction-controlled freewheeling diode region, includes a first P-type shielding layer located in the second N-type epitaxial layer and connected to the P-type epitaxial layer, the first P-type shielding layer is connected to the P-type well region; and a source located on the side of the source contact region away from the N-type substrate.

[0059] It can be seen from the above content that the technical solution provided by the embodiment of the present application shields the electric field at the trench gate electrode through the P-type epitaxial layer, the first P-type shielding layer and the second P-type shielding layer, and the design of the first P-type grounding column and the first P-type shielding layer being connected to the P-type well region makes the P-type epitaxial layer, the first P-type shielding layer and the second P-type shielding layer grounded, so that a better electric field shielding effect can be obtained during reverse withstand voltage, and the P-type epitaxial layer, the first P-type shielding layer and the second P-type shielding layer can be prevented from floating and causing voltage jumps during the switching process, thereby avoiding the degradation of the switching characteristics of the device. In addition, a junction-controlled freewheeling diode region is introduced between the two trench MOSFET regions. The junction-controlled freewheeling diode is a unipolar device, does not have a minority carrier storage effect, and has a short reverse recovery time, which can reduce the switching loss of the device, thereby improving the performance of the trench MOSFET device.

[0060] In the description of the embodiments of the present application, it needs to be understood that the orientation or position relationship indicated by terms such as "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.

[0061] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the embodiments of the present application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0062] In the embodiments of the present application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral one; it can be a mechanical connection, an electrical connection, or communication with each other; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0063] In the embodiments of the present application, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0064] In the embodiments of the present application, if the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" appear, it means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples without contradiction.

[0065] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A trench MOSFET device with an integrated junction-controlled diode, characterized in that: The trench MOSFET device comprises: two trench MOSFET regions arranged along a first direction, and a junction-controlled freewheeling diode region is included between the two trench MOSFET regions; The drain, the N-type substrate, the first N-type epitaxial layer, the P-type epitaxial layer and the second N-type epitaxial layer are sequentially stacked along the third direction: Wherein, at the trench MOSFET region, the P-type epitaxial layer includes at least one N-type current channel arranged along the second direction; a P-type well region located on the second N-type epitaxial layer; a source contact region located on the P-type well region, the source contact region including a source N+ region and a source P+ region; a trench gate electrode penetrating the source contact region and the P-type well region and extending deep into the second N-type epitaxial layer; a second P-type shielding layer located at the bottom of the trench gate electrode; a first P-type grounding column connecting the second P-type shielding layer and the P-type epitaxial layer; and an interlayer dielectric layer covering the top of the trench gate electrode; the first direction and the second direction intersect at a reference plane, and the third direction intersects with the reference plane; The junction-controlled freewheeling diode region includes a first P-type shielding layer located in the second N-type epitaxial layer and connected to the P-type epitaxial layer, and the first P-type shielding layer is connected to the P-type well region; And, a source located at a side of the source contact region away from the N-type substrate.

2. The trench MOSFET device with integrated junction controlled diode according to claim 1, characterized in that: In the trench MOSFET region, the source N+ region and the source P+ region are arranged along the first direction, and the source P+ region is located on a side close to the first P-type masking layer, and the trench gate electrode penetrates the source N+ region and the P-type well region and penetrates into the second N-type epitaxial layer.

3. The wide trench MOSFET device with integrated junction controlled diode according to claim 2, characterized in that: At the junction-controlled freewheeling diode region, the first P-type shielding layer is extended along the second direction; The first P-type masking layer and the P-type well region have a gap filled with the second N-type epitaxial layer in the first direction, and the trench MOSFET device also includes at least one second P-type grounding column located between the first P-type masking layer and the P-type well region, and the second P-type grounding column is in contact and connected with the first P-type masking layer and the P-type well region.

4. The wide trench MOSFET device with integrated junction controlled diode according to claim 3, characterized in that: In the first direction, the second P-type grounding columns on both sides of the first P-type shielding layer are symmetrically or asymmetrically arranged with the first P-type shielding layer as an axis.

5. The wide trench MOSFET device with integrated junction controlled diode according to claim 3, characterized in that: The source P+ region also extends to the junction-controlled freewheeling diode region, and an overlapping area is provided between the source P+ region and the first P-type shielding layer in the third direction, and a gap filled with the second N-type epitaxial layer is provided between the source P+ region and the first P-type shielding layer in the third direction.

6. The trench MOSFET device with integrated junction controlled diode according to claim 3, characterized in that: In the direction from the source to the drain, the width of the first P-type shielding layer in the first direction tends to decrease.

7. The trench MOSFET device with integrated junction controlled diode according to claim 1, characterized in that: At the trench MOSFET region, the source N+ region includes a plurality of sub-source N+ regions extending along the first direction, and the source P+ region includes a plurality of sub-source P+ regions extending along the first direction, and the sub-source N+ regions and the sub-source P+ regions are alternately arranged in the second direction; The sub-source N+ region and the sub-source P+ region of the two trench MOSFET regions are extended to the junction-controlled freewheeling diode region and are connected correspondingly.

8. The trench MOSFET device with integrated junction controlled diode according to claim 7, characterized in that: At the junction-controlled freewheeling diode region, the first P-type shielding layer includes a plurality of sub-P-type shielding layers spaced apart along the second direction; The sub-P-type shielding layer is in contact with and connected to the P-type well region.

9. The trench MOSFET device with integrated junction controlled diode according to claim 7, characterized in that: In the third direction, the sub-P-type shielding layer and the sub-source P+ region have an overlapping area.

10. An electronic device, characterized in that: The electronic device comprises a trench MOSFET device with an integrated junction-controlled diode as claimed in any one of claims 1 to 9.

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