Integrated assemblies including hydrogen diffused within two or more different semiconductor materials and methods of forming integrated assemblies

Abstract

The present disclosure relates to integrated assemblies including hydrogen diffused within two or more different semiconductor materials and methods of forming integrated assemblies. Some embodiments include an integrated assembly having a first semiconductor material between two regions of a second semiconductor material. The second semiconductor material is a different composition than the first semiconductor material. Hydrogen diffuses within the first and second semiconductor materials. The conductivity of the second semiconductor material increases in response to the hydrogen diffused therein to thereby create a structure having the second semiconductor material as a source / drain region and having the first semiconductor material as a channel region between the source / drain regions. A transistor gate is adjacent the channel region and is configured to induce an electric field within the channel region. Some embodiments include methods of forming an integrated assembly.

Description

[0001] Information about divisional applications

[0002] This application is a divisional application of the Chinese invention patent application with application number 202080019268.3, application date February 11, 2020, and invention name “Integrated assembly including hydrogen diffused in two or more different semiconductor materials and method for forming an integrated assembly”.

[0003] Related patent data

[0004] This patent claims priority to and the benefit of U.S. patent application serial number 16 / 298,947, filed on March 11, 2019, the disclosure of which is incorporated herein by reference. Technical Field

[0005] An integrated assembly comprising hydrogen diffused within two or more different semiconductor materials and a method of forming the integrated assembly. Background Art

[0006] Semiconductor materials can be incorporated into integrated assemblies. For example, semiconductor materials can be used to form the channel region and source / drain regions of a transistor. The transistor can be used as an access device in a memory array or other applications.

[0007] It would be desirable to develop improved arrangements of semiconductor materials suitable for utilization in integrated assemblies, and to develop integrated components utilizing improved arrangements of semiconductor materials. Summary of the invention

[0008] At least in some aspects, the present disclosure relates to a method of forming an integrated assembly, which includes: forming a structure including a first semiconductor region between a pair of second semiconductor regions; the first semiconductor region includes a different composition relative to the second semiconductor region; forming a transistor gate adjacent to the first semiconductor region; diffusing hydrogen within the first and second semiconductor regions; the conductivity of the second semiconductor region increases in response to the hydrogen diffused therein to convert the second semiconductor region into a source / drain region; the first semiconductor region having the hydrogen diffused therein is a channel region between the source / drain regions; and the source / drain regions, the channel region and the transistor gate are together comprised by a transistor; the transistor gate is configured to induce an electric field in the channel region in an on-state of the transistor, and thereby couple the source / drain regions to each other through the channel region in the on-state; the transistor has an off-state; in the off-state of the transistor, the channel region has a lower conductivity than the source / drain region. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figures 1 to 4is a schematic cross-sectional side view of a region of an example integrated assembly at an example process stage of an example method for fabricating an example memory cell. Figure 4A is along Figure 4 Schematic cross-sectional view of line AA.

[0010] Figure 5 is a schematic cross-sectional side view of a region of an example integrated assembly including a portion of an example memory array.

[0011] Figure 6 is a schematic diagram of a region of an example memory array.

[0012] Figure 7 and 8 is a schematic side view of a region of an example integrated assembly at an example process stage of an example method for treating multiple components with hydrogen.

[0013] Fig. 9 and 10 is a schematic cross-sectional side view of a region of an example integrated assembly illustrating an example memory cell.

[0014] Fig.11 is a schematic cross-sectional side view of a region of an example assembly including stacked layers.

[0015] Fig.12 is a schematic cross-sectional side view of a region of an example integrated assembly including an example transistor. DETAILED DESCRIPTION

[0016] Some embodiments include an assembly having a different semiconductor material composition in a channel region location of a transistor device than in a source / drain region location of the transistor device. The conductivity of the source / drain region location is substantially increased (e.g., increased by at least 10 times) due to hydrogen diffusion therein, while the conductivity of the channel region location is increased little, if at all, due to hydrogen diffusion therein. Some embodiments include a method of forming an integrated assembly. Reference Figures 1 to 12 Example embodiments are discussed.

[0017] refer to Figure 1 , showing a region of an integrated assembly (construction) 10 at an example process stage of an example method of forming an example structure (e.g., an example transistor, and in some embodiments, an example memory cell). Assembly 10 includes a first semiconductor material 12, a second semiconductor material 14, and a third semiconductor material 16. In some embodiments, the first semiconductor material can be considered to have a first side 11 and an opposing second side 13; and the second semiconductor material 14 can be considered to be directly against the first side 11, while the third semiconductor material 16 is directly against the second side 13.

[0018] The second and third semiconductor materials 14 and 16 are compositionally different from the semiconductor material 12; and may be the same composition as one another or compositionally different relative to one another.

[0019] In some embodiments, materials 12, 14, and 16 may be considered to form a stack 18 of semiconductor materials. Semiconductor materials 14 and 16 may be identical in composition to one another, and both may be referred to as "second semiconductor materials." Thus, stack 18 may be considered to include first semiconductor material 12 as a first region 19; and this first region may be considered to be between two regions 20 of second semiconductor material (where materials 14 and 16 are both referred to as "second semiconductor materials").

[0020] Semiconductor materials 12, 14, and 16 may comprise any suitable composition; and in some embodiments may comprise, consist essentially of, or consist of at least one metal (e.g., one or more of aluminum, gallium, indium, thallium, tin, cadmium, zinc, etc.) in combination with one or more of oxygen, sulfur, selenium, and tellurium.

[0021] In some embodiments, semiconductor materials 12, 14, and 16 may each include at least one element from Group 13 of the periodic table (e.g., gallium) in combination with at least one element from Group 16 of the periodic table (e.g., oxygen). For example, semiconductor materials 12, 14, and 16 may each include at least one element selected from the group consisting of gallium, indium, and mixtures thereof in combination with at least one element selected from the group consisting of oxygen, sulfur, selenium, tellurium, and mixtures thereof.

[0022] In some embodiments, the first semiconductor material 12 may include, consist essentially of, or consist of GaO (where the chemical formula indicates the major components rather than a specific stoichiometric ratio); and both the second and third semiconductor materials 14 and 16 may include, consist essentially of, or consist of InGaZnO (where the chemical formula indicates the major components rather than a specific stoichiometric ratio). Thus, the first, second, and third semiconductor materials 12, 14, and 16 may include semiconductor oxides. The stoichiometric content of the semiconductor oxide may be expressed as a percentage of metal atoms. Specifically, the content of each of the metals of the semiconductor oxide may be expressed in terms of its concentration relative to the total concentration of all metals of the semiconductor oxide; and the concentration of oxygen is ignored.

[0023] In some example embodiments, the semiconductor oxide of materials 14 and 16 may include InGaZnO having a metal atomic percentage of indium in a range from about 16 to about 26, a metal atomic percentage of gallium in a range from about 45 to about 55, and a metal atomic percentage of zinc in a range from about 24 to about 34. In some example embodiments, the metal atomic percentage of indium may be in a range from about 18 to about 24, the metal atomic percentage of gallium may be in a range from about 47 to about 53, and the metal atomic percentage of zinc may be in a range from about 26 to about 32.

[0024] In some example embodiments, the semiconductor oxide of material 12 may include GaO. Thus, the metal atomic percentage of gallium will be approximately 100%.

[0025] In embodiments where the semiconductor oxide of material 12 comprises GaO and where the semiconductor oxides of materials 14 and 16 comprise InGaZnO, the metal atomic percentage of gallium in the first semiconductor material 12 will be greater than the metal atomic percentage of gallium in the second and third semiconductor materials 14 and 16 .

[0026] In the embodiment shown, stack 18 is supported by conductive material 22. This conductive material may be configured as digit line 24. Conductive material 22 may include any suitable conductive composition; such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.). In the embodiment shown, semiconductor material 14 is directly against the upper surface of conductive material 22 (i.e., may be considered to be directly against the upper surface of digit line 24 in some embodiments).

[0027] Stack 18 and conductive material 22 are supported by base 26. Base 26 may include semiconductor material; and may, for example, include, consist essentially of, or consist of single crystal silicon. Base 26 may be referred to as a semiconductor substrate. The term "semiconductor substrate" means any construction including semiconductor material, including, but not limited to, bulk semiconductor material, such as a semiconductor wafer (alone or in an assembly including other materials), and a layer of semiconductive material (alone or in an assembly including other materials). The term "substrate" refers to any supporting structure, including, but not limited to, the semiconductor substrate described above. In some applications, base 26 may correspond to a semiconductor substrate containing one or more materials associated with integrated circuit manufacturing. Such materials may include, for example, one or more of refractory metal materials, barrier materials, diffusion materials, insulator materials, and the like.

[0028] In the illustrated embodiment, a gap is provided between substrate 26 and conductive material 22 to indicate that other materials, components, etc. may be provided between substrate 26 and conductive material 22 .

[0029] refer to Figure 2 , semiconductor materials 12, 14, and 16 are patterned to form vertically extending pillars 28. In some embodiments, base 26 can be considered to extend in the direction of the x-axis, and pillars 28 can be considered to extend in the direction of the z-axis; wherein the x-axis and the z-axis are shown adjacent Figure 2 of construction 10, and are orthogonal to each other.

[0030] Materials 12, 14, and 16 may be patterned by any suitable method. For example, a patterned mask (not shown) may be provided to define the locations of pillars 28, one or more suitable etches may be used to transfer the pattern into materials 12, 14, and 16, and the mask may then be removed to leave Figure 2 The structure described.

[0031] In the embodiment shown, pillars 28 include a portion of bottom semiconductor material 14. In other embodiments, pillars may include only semiconductor materials 12 and 16. In such other embodiments, pillars 28 may be considered to extend upward from the upper surface of bottom semiconductor material 14.

[0032] refer to Figure 3 , transistor gate 30 is formed adjacent to first semiconductor region 19 (i.e., adjacent to first semiconductor material 12). In the illustrated embodiment, the transistor gate vertically overlaps a portion of first semiconductor material 12 and does not vertically overlap with either of semiconductor materials 14 and 16. In other embodiments, the gate may vertically overlap with a region of one or both of semiconductor materials 14 and 16, as described below with reference to Fig. 9 and 10 Discussion.

[0033] Still reference Figure 3 , transistor gate 30 includes conductive material 32. Any suitable conductive component may be included, such as, for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing components (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductively doped semiconductor materials (e.g., conductively doped silicon, conductively doped germanium, etc.).

[0034] Transistor gate 30 is coupled to word line WL1; and in the embodiment shown is part of the word line. Figure 3 A cross-sectional view of a wordline extending into and out of the page.

[0035] Insulating material 34 extends along the sidewalls of pillar 28 and surrounds transistor gate 30. Insulating material 34 may include any suitable composition; and in some embodiments may include one or more of silicon dioxide and various high-k materials (where the term high-k means that the dielectric constant is greater than the dielectric constant of silicon dioxide). The region of insulating material 34 between gate 30 and pillar 28 corresponds to gate dielectric material 36 (also referred to as gate insulating material). Such a region may include the same composition as the remainder of insulating material 34, or may include a different composition relative to the remainder of insulating material 34. In some embodiments, gate dielectric material 36 may include, consist essentially of, or consist of silicon oxide.

[0036] The top semiconductor material 16 is electrically coupled to a storage element 38. The storage element may be any suitable device having at least two detectable states; and in some embodiments may be, for example, a capacitor, a resistive memory device, a conductive bridge device, a phase change memory (PCM) device, a programmable metallization cell (PMC), etc.

[0037] In the illustrated embodiment, storage element 38 is a capacitor. Capacitor 38 has a node coupled to a reference voltage 40. This reference voltage may be ground, Vcc / 2, or any other suitable reference voltage.

[0038] refer to Figure 4 , hydrogen (specifically, diatomic hydrogen (H2)) diffuses into assembly 10. Hydrogen diffuses into first and second semiconductor regions 19 and 20; and specifically diffuses into semiconductor materials 12, 14, and 16. The conductivity of materials 14 and 16 increases in response to the hydrogen diffused therein to convert second semiconductor region 20 into source / drain regions 42 and 44. The conductivity of first semiconductor material 12 changes little, if at all, in response to the diffusion of hydrogen therein. Thus, first semiconductor region 19 having hydrogen diffused therein becomes channel region 46 extending between source / drain regions 42 and 44.

[0039] In some embodiments, in response to hydrogen diffusion within materials 12, 14, and 16, second and third semiconductor materials 14 and 16 may be considered to have substantially increased conductivity compared to first semiconductor material 12. For example, in Figure 3 At the processing stage of , the first, second and third semiconductor materials 12, 14 and 16 may have approximately the same conductivity as each other; and reference Figure 4 The described hydrogen diffusion can increase the conductivity within semiconductor materials 14 and 16 to form second regions 20 (ie, Figure 4 The source / drain regions 42 and 44 of the first region 19 (ie, Figure 4The conductivity of the channel region 46 is at least about 10 times greater than that of the first region 19, at least about 100 times greater than that of the first region 19, and at least about 1000 times greater than that of the first region 19.

[0040] In some embodiments, the conductivity of semiconductor material 12 does not change after hydrogen is diffused therein. In some embodiments, the conductivity may change, but the increase is much less than the increase in the conductivity of materials 14 and 16 in response to hydrogen incorporation. For example, in some embodiments, the conductivity of first semiconductor region 19 (i.e., semiconductor material 12) may change by an amount ranging from about zero to about three times relative to the initial conductivity of region 19 before hydrogen is incorporated therein; and the conductivity of second semiconductor region 20 (i.e., semiconductor materials 14 and 16) may change by an amount of at least about five times relative to the conductivity of region 20 before hydrogen is incorporated therein. In some embodiments, the conductivity of region 20 may increase by at least about one order of magnitude, at least about two orders of magnitude, at least about three orders of magnitude, etc.

[0041] The hydrogen diffusion may utilize any suitable processing conditions. In some example embodiments, the hydrogen diffusion may correspond to a hydrogen anneal utilizing a temperature of at least about 100° C. and a pressure of at least about 1 atmosphere for a duration of at least about one minute. The hydrogen may be provided in an environment including at least about 1% H2 by volume in an inert carrier gas (e.g., Ar, N2, etc.).

[0042] exist Figures 1 to 4 In the illustrated embodiment of FIG. 1 , hydrogen diffusion occurs after formation of transistor gate 30 and storage element 38. In other embodiments, hydrogen diffusion may be performed at other process stages. For example, hydrogen diffusion may occur at Figure 1 and 2 However, it may be advantageous to perform hydrogen diffusion later in the manufacturing process because hydrogen diffusion may be used to process other components besides semiconductor materials 12, 14, and 16. For example, hydrogen diffusion may be used to passivate silicon / silicon dioxide interfaces, as described below with reference to Figure 7 and 8 Describe in more detail.

[0043] Figure 4The configuration includes a transistor 48, which includes a transistor gate 30 in conjunction with a channel region 46 and source / drain regions 42 / 44. The transistor gate 30 is adjacent to the channel region 46 and is configured to induce an electric field in the channel region in response to providing a voltage along the word line WL1. When an electric field is induced in the channel region 46, the transistor 48 will have an on-state, and the source / drain regions 42 and 44 will be coupled to each other through the channel region in this on-state. The transistor will also have an off-state, in which an electric field is not induced in the channel region 46 to a suitable level to couple the source / drain regions 42 and 44 to each other. In the off-state of the transistor 48, the channel region 46 has a lower conductivity than the source / drain regions 42 and 44. In some embodiments, the conductivity of source / drain regions 42 and 44 may be at least about 10 times greater than the conductivity of channel region 46 in the off state, at least about 100 times greater than the conductivity of the channel region in the off state, at least about 1000 times greater than the conductivity of the channel region in the off state, and so on.

[0044] Figure 4A Display along Figure 4 AA, and shows word line WL1 extending in the y-axis direction, wherein this direction is orthogonal to the x-axis direction of digit line DL1 ( Figure 4 1 ). Moreover, pillar 28 is shown as one of several substantially identical pillars within construction 10 (where the term “substantially identical” means identical within reasonable tolerances of manufacturing and measurement). Pillars 28 are separated from one another by insulating material 52. Insulating material 52 may include any suitable composition; and in some embodiments, may include, consist essentially of, or consist of one or both of silicon dioxide and silicon nitride.

[0045] In the illustrated embodiment, word line WL1 extends along both sides of each of pillars 28. In other embodiments, the word line may extend along only one of the sides of the pillars. In other embodiments, at least some of insulating material 52 may be omitted so that the transistor gate wraps around pillars 28.

[0046] exist Figure 4 In the illustrated embodiment of , source / drain region 42 is electrically coupled with digit line 24 (and is specifically shown directly against digit line 24 ), and source / drain region 44 is electrically coupled with storage element 38 .

[0047] Transistor 48 and storage element 38 together form memory cell 50. In some embodiments, transistor 48 may be considered an access transistor utilized within memory cell 50. Memory cell 50 may be a representative memory cell within memory array 54, and may be one of a large number of substantially identical memory cells.

[0048] Figure 5A portion of an integrated assembly 10a is shown including a region of an example memory array 54. The memory array 54 includes a number of memory cells 50. Each memory cell includes an access transistor 48 coupled to a memory cell 38. The memory cells 38 are schematically illustrated with blocks to indicate that such elements may include any suitable components. The components may be Figure 4 , or may be other suitable devices having two or more detectable states. Each of memory cells 50 includes a gate 30, where the gate is coupled to word lines WL1, WL2, and WL3.

[0049] Figure 6 A portion of a memory array 54 is schematically illustrated, and such a memory array is shown including digit lines DL1, DL2, and DL3, and word lines WL1, WL2, and WL3. Each of the memory cells 50 within the memory array is uniquely addressed by a combination of one of the word lines and one of the digit lines. The memory array may include any suitable number of memory cells 50; and in some embodiments may include hundreds, millions, tens of millions, etc. of memory cells.

[0050] As mentioned above, in some embodiments, hydrogen diffusion (ie, hydrogen annealing) may be used to increase the conductivity ( Figure 3 and 4 ), and can also be used to process other materials of the integrated assembly. For example, Figure 7 and 8 A region of construction (integrated assembly) 10b is shown and an example embodiment is illustrated in which a hydrogen anneal is used to process a silicon / silicon dioxide interface within a CMOS (complementary metal oxide semiconductor) circuitry 56 disposed proximate to a memory array 54. In the illustrated embodiment, CMOS circuitry 56 is disposed beneath array 54, and digit lines (e.g., DL1) and word lines (e.g., WL1) extend from array 54 to circuitry associated with CMOS circuitry 56. In some embodiments, the word lines may extend to word line driver circuitry associated with CMOS circuitry 56, and the digit lines may extend to sense amplifier circuitry associated with CMOS circuitry 56.

[0051] Figure 7 Region 58 of array 54 is shown in an expanded view to indicate that this region includes pillars 28 including semiconductor materials 12, 14, and 16. Region 60 of CMOS 56 is also shown in an expanded view to indicate that this region includes silicon 62 with adjacent silicon dioxide 64. The illustrated region also includes conductive material 66. In some embodiments, materials 62, 64, and 66 may be part of a planar field effect transistor (FET). Silicon 62 is bonded to silicon dioxide 64 along interface 65. This interface may problematically include dangling bonds.

[0052] refer to Figure 8 , you can refer to the above Figure 4 A hydrogen anneal is described to form source / drain regions 42 and 44 within memory array 54. The same hydrogen anneal may also advantageously passivate interface 65 to reduce or even eliminate problematic dangling bonds.

[0053] Figure 4 An example transistor 48 is shown having a conductive gate 30 that vertically overlaps a channel region 46 instead of source / drain regions 42 and 44. In other embodiments, gate 30 is configured to vertically overlap at least one of source / drain regions 42 and 44. For example, Fig. 9 An assembly 10c is shown having a transistor 48a with a transistor gate 30 that vertically overlaps a portion of the lower source / drain region 42. As another example, Fig.10 Assembly 10d is shown having a transistor 48b with a transistor gate 30 that vertically overlaps portions of both the lower source / drain region 42 and the upper source / drain region 44 .

[0054] In some embodiments, Figures 4 to 6 The memory array 54 may be within a memory layer (ie, a memory level) that is within a vertically stacked arrangement of layers (or levels). For example, Fig.11 A portion of an integrated assembly 10e is shown that includes a vertically stacked arrangement of layers 68, 70, 72, and 74 (also labeled layers 1-4). The vertically stacked arrangement may be extended upward to include additional layers. Layers 1-4 may be considered examples of tiers stacked on top of each other. The tiers may be within different semiconductor dies (wafers), or at least two of the tiers may be within the same semiconductor die. The bottom layer (layer 1) may include control circuitry and / or sensing circuitry (e.g., may include word line drivers, sense amplifiers, etc.; and may include Figure 7 and 8 The upper layers (layers 2-4) may include memory arrays, such as, for example, memory array 54. The memory arrays within the various layers may be identical to one another (e.g., may all be DRAM arrays), or may be different relative to one another (e.g., some may be DRAM arrays while others are NAND arrays). In addition, one or more of the upper layers may include control circuitry or other logic circuitry.

[0055] Figure 4 The embodiment of shows transistor 48 having a vertically extending channel region. In other embodiments, similar transistors may be configured to have a horizontally extending channel region. For example, Fig.12A portion of an integrated assembly 10f is shown having a transistor 48c having a horizontally extending channel region 46c (ie, the channel region 46c extends in the direction of the x-axis). The transistor 48c is supported by the substrate 26 and is similar to Figure 4 The transistor 48 is different only in that the channel region 46c of the transistor 48c extends horizontally (ie, along the x-axis), while Figure 4 The channel region 46 of the transistor 48 extends vertically (ie, along the z-axis). In some embodiments, Fig.12 The semiconductor material 12 of the transistor 48c can be considered to have a first side 11 and a second side 13 that are disposed horizontally relative to each other. Figure 4 The same first and second sides 11 and 13 of the transistor 46 are disposed in a vertical relationship relative to each other.

[0056] The assemblies and structures discussed above may be utilized within integrated circuits (where the term "integrated circuit" means an electronic circuit supported by a semiconductor substrate); and may be incorporated into electronic systems. Such electronic systems may be used, for example, in memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multi-layer, multi-chip modules. The electronic system may be any of a wide range of systems such as, for example, cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0057] Unless otherwise stated, the various materials, substances, compositions, etc. described herein may be formed by any suitable method now known or yet to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0058] The terms "dielectric" and "insulating" may be used to describe materials with insulating electrical properties. The terms are considered synonymous in the present invention. The use of the term "dielectric" in some examples and the term "insulating" (or "electrically insulating") in other examples may provide language variations within the present invention to simplify the premise basis within the appended claims and is not intended to indicate any significant chemical or electrical differences.

[0059] The specific orientations of the various embodiments in the drawings are for illustration purposes only, and in some applications, the embodiments may be rotated relative to the orientation shown. The description provided herein and the appended claims are directed to any structure having the described relationships between the various features, regardless of whether the structure is in a specific orientation of the drawings or rotated relative to this orientation.

[0060] To simplify the drawings, the cross-sectional views of the drawings show only features within the plane of the cross-section and do not show material behind the plane of the cross-section unless otherwise indicated.

[0061] When a structure is referred to as being on, such as "on," "adjacent," or "against" another structure, it may be directly on the other structure or intervening structures may also be present. In contrast, when a structure is referred to as being "directly on," "directly adjacent," or "directly against" another structure, there are no intervening structures present. The terms "directly below," "directly over," and the like do not indicate direct physical contact (unless expressly stated otherwise), but rather indicate upright alignment.

[0062] A structure (e.g., layer, material, etc.) may be referred to as "vertically extending" to indicate a structure that extends generally upward from an underlying base (e.g., substrate). A vertically extending structure may or may not extend substantially orthogonally relative to an upper surface of the base.

[0063] Some embodiments include an integrated assembly including a first semiconductor material having a first side and an opposing second side. A second semiconductor material is directly adjacent to the first side of the first semiconductor material and has a different composition than the first semiconductor material. A third semiconductor material is directly adjacent to the second side of the first semiconductor material and has a different composition than the first semiconductor material. Hydrogen diffuses within the first, second, and third semiconductor materials. In response to the hydrogen diffused therein, the second and third semiconductor materials have substantially increased conductivity compared to the first semiconductor material.

[0064] Some embodiments include an integrated assembly having a first semiconductor material between two regions of a second semiconductor material. The second semiconductor material is a different composition than the first semiconductor material. Hydrogen diffuses within the first and second semiconductor materials. The conductivity of the second semiconductor material increases in response to the hydrogen diffused therein to thereby create a structure having the second semiconductor material as source / drain regions and having the first semiconductor material as a channel region between the source / drain regions. A transistor gate is adjacent to the channel region and is configured to induce an electric field within the channel region.

[0065] Some embodiments include a method of forming an integrated assembly. A structure is formed that includes a first semiconductor region between a pair of second semiconductor regions. The first semiconductor region includes a different composition relative to the second semiconductor region. A transistor gate is formed adjacent to the first semiconductor region. Hydrogen is diffused within the first and second semiconductor regions. The conductivity of the second semiconductor region increases in response to the hydrogen diffused therein to convert the second semiconductor region into a source / drain region. The first semiconductor region with the hydrogen diffused therein is a channel region between the source / drain regions. The source / drain region, the channel region, and the transistor gate are together comprised by a transistor. The transistor gate is configured to induce an electric field in the channel region in an on-state of the transistor, and thereby couple the source / drain regions to each other through the channel region in the on-state. The transistor has an off-state. The channel region has a lower conductivity than the source / drain region in the off-state of the transistor.

[0066] In accordance with the statute, the subject matter disclosed herein has been described in language more or less specific as to structural and methodological features. It should be understood, however, that the claims are not limited to the specific features shown and described, as the components disclosed herein include example embodiments. Therefore, the claims should be given full scope in accordance with their literal terms and appropriately interpreted in accordance with the doctrine of equivalents.

Claims

1. A method of forming an integrated assembly, comprising: forming a structure including a first semiconductor region between a pair of second semiconductor regions; the first semiconductor region including a different composition relative to the second semiconductor region; forming a transistor gate adjacent to the first semiconductor region; hydrogen is diffused in the first and second semiconductor regions; the conductivity of the second semiconductor region increases in response to the hydrogen diffused therein to convert the second semiconductor region into a source / drain region; the first semiconductor region having the hydrogen diffused therein is a channel region between the source / drain regions; and The source / drain regions, the channel region and the transistor gate together are comprised by a transistor; the transistor gate is configured to induce an electric field in the channel region in an on-state of the transistor and thereby couple the source / drain regions to each other through the channel region in the on-state; The transistor has an off state; the channel region has a lower conductivity than the source / drain region in the off state of the transistor. 2 . The method of claim 1 , wherein the second semiconductor regions of the pair are of the same composition as each other. The method of claim 1 , wherein the second semiconductor regions of the pair are of different compositions relative to each other. 4 . The method of claim 1 , wherein the conductivity of the source / drain regions is at least about 10 times greater than the conductivity of the channel region in the off state of the transistor. 5 . The method of claim 1 , wherein the conductivity of the source / drain regions is at least about 100 times greater than the conductivity of the channel region in the off state of the transistor.

6. The method of claim 1, wherein the conductivity of the source / drain regions is at least about 1000 times greater than the conductivity of the channel region in the off state of the transistor. The method of claim 1 , wherein said transistor gate is formed prior to said diffusion of said hydrogen.

8. The method of claim 1, wherein the first and second semiconductor regions comprise first and second semiconductor materials, respectively; and wherein the first and second semiconductor materials comprise at least one metal in combination with one or more of oxygen, sulfur, selenium, and tellurium.

9. The method of claim 8, wherein the at least one metal is one or more of aluminum, gallium, indium, thallium, tin, cadmium, and zinc.

10. The method of claim 8, wherein the first semiconductor material comprises GaO, and wherein the second semiconductor material comprises InGaZnO; wherein the chemical formula indicates major components rather than a specific stoichiometric ratio.

11. The method according to claim 1, comprising: coupling one of the source / drain regions to a storage element; coupling another of the source / drain regions to a digit line; coupling the transistor gate to a word line; and The transistor and the storage element are comprised of a memory cell.

12. The method of claim 11 wherein the memory cell is one of many substantially identical memory cells formed within a memory array; wherein the word line is one of many word lines formed within the memory array; wherein the digit line is one of many digit lines formed within the memory array; and wherein each of the memory cells is uniquely addressed by one of the digit lines in combination with one of the word lines.

13. The method of claim 12 wherein the memory array is formed proximate circuitry having an interface between silicon and silicon dioxide; and wherein the diffusion of the hydrogen also diffuses the hydrogen into the circuitry to passivate the interface.

14. The method of claim 12 wherein the memory array is formed over CMOS circuitry, wherein the CMOS circuitry includes an interface between silicon and silicon dioxide; and wherein the diffusion of the hydrogen also diffuses the hydrogen into the CMOS circuitry to passivate the interface.

15. The method of claim 12, wherein the memory array is formed within a layer; and wherein the layer is within a vertically stacked arrangement of layers and above at least one other of the layers within the vertically stacked arrangement.

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