Circuit board and semiconductor package including same

Abstract

A circuit board according to an embodiment includes: an insulating layer; a protective member disposed on the insulating layer; and a plurality of pillars disposed on the insulating layer along a periphery of the protective member, in which the protective member includes an upper surface, a lower surface, and a side surface disposed between the upper surface and the lower surface, in which the lower surface of the protective member faces the upper surface of the insulating layer, in which the side surfaces of the plurality of pillars face the side surface of the protective member, and wherein a side surface of the protective member includes protruding portions between the plurality of posts.

Description

Technical Field

[0001] Embodiments relate to a circuit board and a semiconductor package including the circuit board. Background Art

[0002] A semiconductor package has a structure in which a semiconductor chip is attached to a circuit board. A semiconductor package can be provided by integrating a plurality of packages to which different devices are attached into one package. Since a plurality of components are implemented in one package, such a semiconductor package has an advantage of being able to transmit high-speed signals through a short path. Therefore, semiconductor packages are widely used in mobile devices and the like.

[0003] In addition, when an electronic device such as a semiconductor chip is attached to a circuit board, semiconductor packaging is performed by applying wiring. A semiconductor package having a wiring structure has a problem of increased volume. Therefore, semiconductor packaging is being implemented recently by flip chip packaging. Flip chip packaging is a method of bonding and packaging a semiconductor chip and a circuit board by melting solder bumps to a connection pattern of a semiconductor chip or a circuit board without using an additional connection material such as wiring when an electronic component such as a semiconductor chip is attached to a circuit board.

[0004] Recently, due to the demand for high-speed, large-capacity data processing and miniaturization of electronic products, the bump pitch of electronic devices has become smaller and smaller. Following this trend, the reliability of the bump connection between the circuit board and the semiconductor chip in the flip chip package is decreasing. In order to prevent such a decrease in reliability, Korean Patent Publication No. 10-2013-0027870 proposes a structure including a column with improved reliability. Summary of the invention

[0005] Technical issues

[0006] Embodiments provide a circuit board having a novel structure and a semiconductor package including the same.

[0007] Furthermore, embodiments provide a circuit board capable of reducing an interval or a pitch between a plurality of pillars and a semiconductor package including the same.

[0008] Furthermore, the embodiment provides a circuit board capable of improving circuit integration and a semiconductor package including the same.

[0009] Furthermore, embodiments provide a circuit board having improved physical and / or electrical connection reliability between a pillar and a pad and a semiconductor package including the same.

[0010] The technical problems to be solved by the proposed implementation are not limited to the above-mentioned technical problems, and other technical problems not mentioned can be clearly understood by technicians in the field to which the proposed implementation belongs from the following description.

[0011] Technical Solution

[0012] According to an embodiment, a circuit board includes: a protective member, which is arranged on the insulating layer; and a plurality of pillars, which are arranged on the insulating layer along the periphery of the protective member, wherein the protective member includes an upper surface, a lower surface and a side surface arranged between the upper surface and the lower surface, wherein the lower surface of the protective member faces the upper surface of the insulating layer, wherein the side surfaces of the plurality of pillars face the side surface of the protective member, and wherein the side surface of the protective member includes a protruding portion protruding between the plurality of pillars.

[0013] In addition, the side surface of the protective member includes a first side surface extending in a first direction, a second side surface extending in the first direction and spaced apart from the first side surface, a third side surface extending in a second direction perpendicular to the first direction, and a fourth side surface extending in the second direction and spaced apart from the third side surface, and the protruding surface of the protective member is arranged on the first side surface and the third side surface.

[0014] In addition, the third side surface includes a first surface, a second surface and a third surface, the first surface has a first separation distance from the multiple columns along the first direction, the second surface has a second separation distance smaller than the first separation distance, and the third surface has a third separation distance greater than the first separation distance.

[0015] Furthermore, a separation distance between the fourth side surface and the plurality of pillars along the first direction is uniform.

[0016] Furthermore, the second side surface of the protection member includes a recessed surface recessed toward the first side surface of the protection member.

[0017] Furthermore, the protection member includes a plurality of through holes, and a width of the plurality of through holes is smaller than a width of the pillar.

[0018] Furthermore, the circuit board further includes an outer protective member disposed on the insulating layer and having a through hole, and the pillar and the protective member are disposed in the through hole of the outer protective member.

[0019] In addition, the circuit board further includes a surface treatment layer disposed on the pillar.

[0020] In addition, the circuit board also includes a plurality of pads, which are arranged between the insulating layer and the protective member, the width of the plurality of through holes of the protective member is smaller than the width of the plurality of pads, and the width of the column is smaller than the width of the pads.

[0021] In addition, the circuit board also includes a surface treatment layer, which is arranged on each of the multiple through holes of the protective member, and the surface treatment layer arranged on each of the multiple through holes of the protective member and the surface treatment layer arranged on the column are provided with the same material.

[0022] Furthermore, the protection member and the outer protection member constitute an upper protection layer provided on an upper surface of the insulating layer.

[0023] Furthermore, the outer protection member is provided along an edge of an upper surface of the substrate.

[0024] Furthermore, the protection member is disposed inside the outer protection member with a partition area interposed therebetween in a horizontal direction.

[0025] Furthermore, a separation region between an inner side surface of the outer protection member and an outer side surface of the protection member includes a first separation region having a first width in a horizontal direction and a second separation region having a second width different from the first width.

[0026] Furthermore, the separation area is provided as a closed loop along the outer side surface of the protection member.

[0027] Furthermore, the outer side surface of the protection member includes a protruding surface protruding toward the inner side surface of the outer protection member.

[0028] Furthermore, the protruding surface of the protection member is disposed in the second partition region, and the first width is greater than the second width.

[0029] Furthermore, the outer side surface of the protection member includes a recessed surface recessed toward the inner side of the protection member.

[0030] Furthermore, the recessed surface of the protection member is provided in the first partition region, and the first width is greater than the second width.

[0031] Furthermore, the protruding surface of the protection member includes a first protruding surface protruding toward the inner side surface of the outer protection member with a first protruding width, and a second protruding surface protruding toward the outer side surface of the outer protection member with a second protruding width greater than the first protruding width.

[0032] In addition, the inner surface of the outer protective member includes a first inner surface, a second inner surface facing the first inner surface, and a third inner surface and a fourth inner surface arranged between the first inner surface and the second inner surface and facing each other, and the outer surface of the protective member includes a first outer surface adjacent to the first inner surface, a second outer surface adjacent to the second outer surface, a third outer surface adjacent to the third inner surface, and a fourth outer surface adjacent to the fourth inner surface, and a separation area between the first inner surface of the outer protective member and the first outer surface of the protective member includes the first separation area and the second separation area.

[0033] In addition, a spacing between a plurality of pads disposed between the insulating layer and the pillar is smaller than a width of each of the plurality of pads.

[0034] Beneficial Effects

[0035] A circuit board according to an embodiment includes an insulating layer and a protective layer disposed on the insulating layer. At this time, the protective layer can be referred to as a protective member disposed in a portion of an area on the upper surface of the insulating layer. At this time, the circuit board includes a plurality of columns disposed along the periphery of the protective member on the insulating layer. In addition, the protective member includes an upper surface, a lower surface, and a side surface disposed between the upper surface and the lower surface, the lower surface of the protective member faces the upper surface of the insulating layer, the side surfaces of the plurality of columns face the side surfaces of the protective member, and the side surface of the protective member includes a protruding portion protruding between the plurality of columns.

[0036] For example, the outer side surface of the protective member may have a step in the horizontal direction along the periphery. Specifically, the protective member may include a protruding surface or a recessed surface protruding toward the column. In addition, the protruding surface and the recessed surface may be designed based on the position of the column. For example, the protruding surface may protrude toward the area between multiple pads. In this way, the embodiment can increase the design freedom of arranging the pads. Therefore, the embodiment can increase the integration of the pads and the column.

[0037] In addition, the outer surface of the protective member of the embodiment can be located a certain distance inside the insulating layer more than the outer surface of the insulating layer. In this way, the embodiment can improve the warpage characteristics of the circuit board by using the protruding surface of the outer surface of the protective member. That is, the protective member can be the uppermost insulating layer arranged in the circuit board. In addition, the process of forming the protective member includes exposure, development and curing processes. In addition, in the exposure, development and curing processes of the protective member, stress is applied to the circuit board, so the side end of the circuit board may be bent in the upward direction or the downward direction. At this time, the embodiment can allow the outer surface of the protective member to be arranged more inward than the outer surface of the insulating layer, so that the stress caused by expansion and / or contraction due to thermal cycling can be minimized. Therefore, the embodiment can improve the warpage characteristics of the circuit board and the semiconductor package including the circuit board, and further improve product reliability. In addition, the embodiment can minimize the stress acting on the interface between each component of the circuit board including the interface between the insulating layer and the protective member, the interface between the pad and the protective member, etc., and can stably protect the circuit board and the semiconductor package from problems such as cracks caused by stress.

[0038] In addition, the circuit board further includes an outer protective member disposed on the outer side of the protective member. In this case, the outer protective member is disposed along the edge of the upper surface of the insulating layer, and the protective member is disposed on the inner side of the outer protective member and has a separation area therebetween. In this case, the separation area between the inner side surface of the outer protective member and the outer side surface of the protective member includes a first separation area having a first width in the horizontal direction and a second separation area having a second width different from the first width.

[0039] In this way, the embodiment includes a first separation area and a second separation area, in which different widths are provided along the inner surface of the outer protective member and the periphery of the outer surface of the protective member in the first separation area and the second separation area, thereby allowing each separation area to have different circuit integration. For example, the first width may be greater than the second width. Therefore, a pad with a relatively high degree of integration is provided in the protective member adjacent to the first separation area having the first width, and a pad with a relatively low degree of integration is provided in the protective member adjacent to the second separation area having the second width. In this way, the embodiment can provide a protective member and an outer protective member including a first separation area and a second separation area through the arrangement design of the pads, thereby improving the electrical reliability and / or mechanical reliability of the semiconductor package. In addition, the embodiment can reduce the signal transmission distance by controlling the circuit integration, and can improve the signal transmission characteristics by minimizing the signal transmission loss accordingly.

[0040] In addition, a plurality of first pads are arranged in a separation area between the protection member and the outer protection member. At this time, the first pads do not contact the protection layer (protection member and outer protection member). For example, a plurality of first pads do not contact each of the protection member and the outer protection member. In this way, the embodiment can solve the problem of size limitation of SRO (Solder Resister Open, solder resist opening) that can be formed in the protection layer in the separation area. Therefore, the embodiment can reduce the width of the first pad arranged in the separation area. In addition, the embodiment can improve the circuit integration of the first pad in the separation area.

[0041] In addition, the embodiment has a structure in which a protective layer is not provided between a plurality of first pads in the separation area. Therefore, the spacing between adjacent first pads can be reduced. In addition, the embodiment can allow the spacing between adjacent first pads to be less than the width of the first pad. In this way, the embodiment can increase the density of the first pads in the separation area. Therefore, the embodiment can reduce the area of ​​the circuit board and the semiconductor package including the circuit board.

[0042] In addition, a column is provided on the first pad. At this time, a seed layer of the column is not provided between the column and the pad. Specifically, the column of the embodiment is in direct contact with the first pad. More specifically, the column is electroplated using a seed layer for electroplating the first pad. Therefore, the embodiment has a structure in which a chemical copper plating layer is not provided between the first pad and the column. Therefore, since the first pad and the column are electroplated by the same seed layer, the embodiment can improve the physical connection and electrical connection between the first pad and the column. This is because the contact performance between electrolytic copper is better than the contact characteristics between chemical plating and electrolytic plating. In addition, the embodiment can solve the signal transmission loss caused by the chemical copper plating layer, thereby improving the signal transmission characteristics.

[0043] In addition, the embodiment can solve the problem of undercutting the lower end of the column due to etching the chemical copper plating layer. In this way, the embodiment can allow the upper surface and the lower surface of the column to have approximately the same width. Therefore, the embodiment can solve the dendrite problem caused by electromigration due to the width difference between the upper surface and the lower surface of the column, thereby further improving the electrical and / or physical properties of the column.

[0044] In addition, the embodiment can omit the process of forming the chemical copper plating layer for forming the pillar and etching the chemical copper plating layer. In this way, the embodiment can simplify the manufacturing process of the circuit board. Therefore, the embodiment can improve the process yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 is a cross-sectional view showing a circuit board according to a comparative example.

[0046] Figure 2 is a cross-sectional view showing a circuit board according to the first embodiment.

[0047] Figure 3 It has been removed Figure 2 A plan view of a circuit board of the first protective layer and pillars.

[0048] Figure 4 yes Figure 2 A plan view of the first protective layer.

[0049] Figure 5 yes Figure 2 A plan view of a circuit board.

[0050] Figure 6 It is shown Figure 2 A cross-sectional view of a detailed layer structure of a first through-electrode, a first circuit layer, and a pillar.

[0051] Figure 7 is a cross-sectional view showing a circuit board according to a second embodiment.

[0052] Figure 8 It is shown Figure 7 A magnified view of a portion of the area.

[0053] Fig. 9 2 is a diagram showing a semiconductor package according to a first embodiment.

[0054] Fig.10 is a cross-sectional view showing a circuit board according to a third embodiment.

[0055] Fig.11 is a cross-sectional view showing a semiconductor package according to a second embodiment.

[0056] Fig.12 is a cross-sectional view showing a circuit board according to a fourth embodiment.

[0057] Fig.13 yes Fig.12 Top plan view of the circuit board.

[0058] Fig.14 yes Fig.12 An enlarged view of a local area of ​​a circuit board.

[0059] Figures 15 to 28 It is described in order of process Figure 2 FIG. 2 is a diagram of a method for manufacturing a circuit board according to a first embodiment shown in FIG. DETAILED DESCRIPTION

[0060] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the spirit and scope of the present invention are not limited to a part of the described embodiments, and can be implemented in various other forms, and within the spirit and scope of the present invention, one or more elements in the embodiments can be selectively combined and re-presented.

[0061] In addition, unless otherwise explicitly defined and described, the terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as having the same meaning as commonly understood by ordinary technicians in the field to which the present invention belongs, and terms such as terms defined in commonly used dictionaries may be interpreted as having meanings consistent with their meanings in the relevant technical context.

[0062] In addition, the terms used in the embodiments of the present invention are used to describe the embodiments and are not intended to limit the present invention. In the present application, unless otherwise specified in a phrase, a singular form may also include a plural form, and when described as "at least one (or more) of A (and), B and C", the singular form may include at least one of all combinations that can be combined with A, B and C.

[0063] In addition, when describing elements of the embodiments of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are only used to distinguish one element from other elements, and these terms are not limited to the nature, order, or sequence of the elements.

[0064] In addition, when an element is described as being “connected,” “coupled” or “contacting” another element, it may include not only when the element is directly “connected,” “coupled” or “contacting” another element, but also when the element is “connected,” “coupled” or “contacting” with another element through other elements therebetween.

[0065] In addition, when described as being formed or disposed “on (above)” or “under (below)” each element, “on (above)” or “under (below)” may include not only when the two elements are directly connected to each other but also when one or more other elements are formed or disposed between the two elements.

[0066] In addition, when expressed as “upper” or “lower”, it may include not only an upper direction but also a lower direction based on one element.

[0067] - Comparative Example -

[0068] Figure 1 is a cross-sectional view showing a circuit board according to a comparative example.

[0069] Reference Figure 1, the circuit board includes an insulating layer 10.

[0070] In addition, a first circuit pattern 20 is provided on the upper surface of the insulating layer 10, and a second circuit pattern 30 is provided on the lower surface of the insulating film 10. The first circuit pattern 20 includes a pad. In addition, the circuit board of the comparative example includes a through electrode passing through the insulating layer 10. The protective layer 50 is provided on the upper surface of the insulating layer 10, and has an opening vertically overlapping with the upper surface of the pad of the first circuit pattern 20.

[0071] In addition, a pillar 70 is provided on the pad of the first circuit pattern 20. The pillar 70 has a certain height or thickness and protrudes on the pad of the first circuit pattern 20. Therefore, the height or thickness of the pillar 70 is at least 80 μm. As a result, it is difficult to form the pillar 70 by electroless plating.

[0072] Therefore, a seed layer 60 for electroplating the pillar 70 is provided between the bump 70 and the pad of the first circuit pattern 20. The seed layer 60 is a chemical copper plating layer. The seed layer 60 is provided on the upper surface of the pad of the first circuit pattern 20 and the inner wall of the protective layer 50, respectively.

[0073] That is, the comparative example has a structure in which the seed layer 60 is provided between the pillar 70 and the pad of the first circuit pattern 20. Therefore, the comparative example has a problem in that a process of forming the seed layer 60 must be additionally performed, and the manufacturing process becomes complicated or the manufacturing time increases accordingly.

[0074] In addition, the circuit board of the comparative example experiences a whitening phenomenon of the protective layer 50 due to the solution used in the decontamination process of the seed layer 60 formed by electroless plating. In addition, the circuit board of the comparative example has a structure in which the seed layer 60 is provided between the pad and the column 70, so the bump layer has a porous microstructure. At this time, the porous structure has a low metal density, and therefore, there is a problem of cracks occurring in the porous seed layer 60 due to external impact or other physical forces. In addition, there is a problem that the column 70 is damaged due to the occurrence of cracks, so the reliability or durability of the product is greatly reduced. In addition, in the comparative example, there is a problem that the seed layer 60 is additionally provided between the pad and the column 70, so the loss increases during signal transmission, thereby reducing the signal transmission characteristics.

[0075] - Electronic Devices -

[0076] Before describing the embodiments, an electronic device including a semiconductor package of the embodiments will be briefly described. The electronic device includes a mainboard (not shown). The mainboard can be physically and / or electrically connected to various components. For example, the mainboard can be electrically connected to the semiconductor package of the embodiments. Various devices can be mounted on the semiconductor package. The semiconductor package can include various devices or chips. The device or chip can include memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory, application processor chips such as central processing units (e.g., CPUs), graphics processors (e.g., GPUs), antenna chips, digital signal processors, encryption processors, microprocessors, and microcontrollers, and logic chips such as analog-to-digital converters and ASICs (application-specific ICs).

[0077] Furthermore, a device or chip may include passive devices and active devices.

[0078] An active device refers to a component that actively utilizes the nonlinear part of the signal characteristics. In addition, a passive device refers to a component that does not utilize the nonlinear signal characteristics even if there are both linear and nonlinear signal characteristics. For example, active devices may include transistors, IC semiconductor devices, and passive devices may include capacitors, resistors, inductors, etc. Passive devices can increase the signal processing speed of a semiconductor chip as an active device, or perform a filtering function. In addition, the chip may be a wireless communication chip that can be used for Wi-Fi or 5G communication.

[0079] In addition, the product group of the semiconductor package to which the implementation scheme is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package) and SIP (System In Package), but is not limited thereto.

[0080] In this case, the electronic device may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automobile, etc. However, the embodiment is not limited thereto, and may be any other electronic device that processes data in addition to these.

[0081] - Circuit Boards and Semiconductor Packaging -

[0082] Hereinafter, a circuit board and a semiconductor package according to embodiments will be described.

[0083] Figure 2 is a cross-sectional view showing a circuit board according to a first embodiment. Figure 2 The overall structure of the circuit board of the first embodiment is described.

[0084] Reference Figure 2 , the circuit board 100 can attach at least one chip. In addition, the circuit board 100 of the embodiment can be attached to the main board of the electronic device. The main board can refer to the motherboard of the electronic device. The circuit board 100 can be connected to at least one chip and the motherboard to form a first package.

[0085] In addition, the first package including the circuit board 100 of the embodiment can be combined with the second package. The second package can be a memory package. In one embodiment, the circuit board 100 can be combined with the memory substrate of the second package. In another embodiment, the circuit board can be combined with an interposer that is combined with the memory substrate.

[0086] The circuit board 100 includes an insulating layer 110. The insulating layer 110 may include a plurality of layers. In one embodiment, the insulating layer 110 may have a three-layer structure, but is not limited thereto. At this time, the insulating layer 110 may be referred to as a supporting substrate supporting the circuit board 100, and thus may be referred to as a "substrate".

[0087] In one embodiment, the circuit board 100 may be a core substrate. For example, the circuit board 100 may include a core layer. For example, the insulating layer 110 of the circuit board 100 of the embodiment may include a third insulating layer 113 corresponding to the core layer including the reinforcing fiber.

[0088] The circuit board 100 may have a structure in which at least one insulating layer is stacked on each of the upper and lower parts with the third insulating layer 113 interposed therebetween. In one embodiment, the insulating layer stacked on the upper side of the third insulating layer 113 and the insulating layer stacked on the lower side thereof may have a symmetrical structure. In another embodiment, the insulating layer stacked on the upper side of the third insulating layer 113 and the insulating layer stacked on the lower side thereof may have an asymmetrical structure.

[0089] Hereinafter, the circuit board 100 of the embodiment is described as a core substrate, and thus, the third insulating layer 113 is a core layer. However, the embodiment is not limited thereto. For example, the circuit board 100 of another embodiment may be a coreless substrate that does not include a core layer.

[0090] In addition, the circuit board of the embodiment is characterized in that the opening of the protective layer, and the outermost circuit layer and the column arranged in the opening of the protective layer. In addition, the protective layer, the circuit layer and the column described below can be applied to the coreless substrate. In addition, at least one of the outermost circuit layers of the embodiment can have an ETS (Embedded Trace Substrate) structure embedded in the surface of the insulating layer 110.

[0091] The insulating layer (or substrate) 110 of the circuit board 100 of the embodiment may include a first insulating layer 111 , a second insulating layer 112 , and a third insulating layer 113 .

[0092] The third insulating layer 113 may refer to an inner insulating layer disposed inside the plurality of insulating layers. The third insulating layer 113 may be disposed between the first insulating layer 111 and the second insulating layer 112. The third insulating layer 113 may include prepreg. The third insulating layer 113 may include reinforcing fibers.

[0093] The first insulating layer 111 may be disposed on the third insulating layer 113. For example, the first insulating layer 111 may be disposed on the upper surface of the third insulating layer 113. The first insulating layer 111 may refer to the first outermost insulating layer among the insulating layers 110 of the circuit board 100. For example, the first insulating layer 111 may refer to the insulating layer disposed on the uppermost side among the insulating layers 110 of the circuit board 100. The first insulating layer 111 may provide a mounting area in which at least one chip is mounted, or provide a first bonding area in which a first external substrate is bonded. The first external substrate may be a mainboard of an electronic device.

[0094] The second insulating layer 112 may be disposed below the third insulating layer 113. The second insulating layer 112 may refer to the second outermost insulating layer among the insulating layers 110 of the circuit board 100. For example, the second insulating layer 112 may refer to the insulating layer disposed at the lowermost side among the insulating layers 110 of the circuit board 100. The second insulating layer 112 may provide a mounting area in which at least one chip is mounted, or provide a second bonding area in which a second external substrate is bonded. The second external substrate may be a memory substrate or an interposer.

[0095] The first insulating layer 111 and the second insulating layer 112 may be rigid or flexible. For example, the first insulating layer 111 and the second insulating layer 112 may include glass or plastic. In detail, the first insulating layer 111 and the second insulating layer 112 may include chemically strengthened / semi-strengthened glass such as soda lime glass or aluminosilicate glass. Alternatively, the first insulating layer 111 and the second insulating layer 112 may include reinforced plastic or flexible plastic, such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), or polycarbonate (PC). Alternatively, the first insulating layer 111 and the second insulating layer 112 may include sapphire.

[0096] In addition, the first insulating layer 111 and the second insulating layer 112 may include an optically isotropic film. For example, the first insulating layer 111 and the second insulating layer 112 may include COC (Cyclic Olefin Copolymer), COP (Cyclic Olefin Polymer), optically isotropic polycarbonate (PC) or optically isotropic polymethyl methacrylate (PMMA).

[0097] In addition, the first insulating layer 111 and the second insulating layer 112 may be formed of a material including an inorganic filler and an insulating resin. For example, the first insulating layer 111 and the second insulating layer 112 may include a structure in which an inorganic filler such as silicon dioxide or aluminum oxide is dispersed in a thermosetting resin such as an epoxy resin or a thermoplastic resin such as polyimide. For example, the first insulating layer 111 and the second insulating layer 112 may include ABF (Ajinomoto Build-up Film), FR-4, BT (Bismaleimide Triazine), PID (Photo Imagable Dielectric resin), BT, etc.

[0098] Each of the first insulating layer 111 and the second insulating layer 112 may have a thickness in the range of 10 μm to 60 μm. Preferably, each of the first insulating layer 111 and the second insulating layer 112 may have a thickness in the range of 12 μm to 50 μm. More preferably, each of the first insulating layer 111 and the second insulating layer 112 may have a thickness in the range of 15 μm to 40 μm.

[0099] If the thickness of the first insulating layer 111 or the second insulating layer 112 is less than 10 μm, the circuit layer included in the circuit board 100 may not be stably protected. In addition, if the thickness of the first insulating layer 111 or the second insulating layer 112 exceeds 60 μm, the thickness of the circuit board 100 may increase, and thus the thickness of the semiconductor package may increase. In addition, if the thickness of the first insulating layer 111 or the second insulating layer 112 exceeds 60 μm, the thickness of the circuit layer and the thickness of the through-electrode may increase accordingly. In addition, if the thickness of the circuit layer and the thickness of the through-electrode increase, it will be difficult to achieve miniaturization, which will reduce the circuit integration. In addition, the signal transmission distance may increase, which will increase the signal transmission loss.

[0100] In addition, the first insulating layer 111 may be divided into a plurality of regions in a direction.

[0101] The first insulating layer 111 may include a first region R1 adjacent to a periphery 111a of the first insulating layer 111. The periphery 111a of the first insulating layer 111 may refer to a periphery of an upper surface of the first insulating layer 111. The periphery 111a of the first insulating layer 111 may refer to an edge of an upper surface of the first insulating layer 111 adjacent to a side surface of the first insulating layer 112. The first insulating layer 111 may include a second region R2 other than the first region R1. The periphery 111a of the first insulating layer 111 may refer to an outermost portion of an upper surface of the first insulating layer 111 that is closest to a side surface of the first insulating layer 112. At this time, the first region R1 may be a region corresponding to a first opening of the protective layer to be described later, and may correspond to a separation region between an outer protective member and a protective member in another embodiment.

[0102] The second region R2 may refer to a region farther from the periphery 111 a of the first insulating layer 111 than the first region R1 .

[0103] At this time, the first region R1 of the first insulating layer 111 may be formed along the peripheral direction of the first insulating layer 111. In addition, the second region R2 of the first insulating layer 111 may refer to an inner region of the first region R1 formed along the peripheral direction. For example, the first region R1 of the first insulating layer 111 may refer to an outer region of the upper surface of the first insulating layer 111, and the second region R2 may refer to an inner region of the upper surface of the first insulating layer 111 excluding the first region R1.

[0104] In addition, the first and second regions R1 and R2 are described as the first and second regions R1 and R2 of the first insulating layer 111 , but are not limited thereto. For example, the first and second regions R1 and R2 may refer to the first and second regions R1 and R2 of the circuit board 100 .

[0105] The circuit board 100 of the embodiment includes a circuit layer provided on a surface of an insulating layer 110 .

[0106] For example, the circuit board 100 may include a first circuit layer 120 disposed on an upper surface of the first insulating layer 111. For example, the circuit board 100 may include a second circuit layer 130 disposed on a lower surface of the second insulating layer 112. In addition, the circuit board 100 may include a third circuit layer 140 disposed between the lower surface of the first insulating layer 111 and the upper surface of the third insulating layer 113. For example, the circuit board 100 may include a fourth circuit layer 150 disposed between the upper surface of the second insulating layer 112 and the lower surface of the third insulating layer 113.

[0107] The first circuit layer 120, the second circuit layer 130, the third circuit layer 140 and the fourth circuit layer 150 can be manufactured using conventional printed circuit board manufacturing processes, such as additive process, subtractive process, modified semi-additive process (MSAP) and semi-additive process (SAP), and their detailed description is omitted here.

[0108] The first circuit layer 120 may refer to a circuit layer disposed on a first outermost layer of the circuit board 100. In addition, the second circuit layer 130 may refer to a circuit layer disposed on a second outermost layer of the circuit board 100.

[0109] The first circuit layer 120 may include a plurality of pads disposed on the first insulating layer 111 .

[0110] The first circuit layer 120 may include a first pad 121 disposed in the first region R1 of the first insulating layer 111. In addition, the first circuit layer 120 may include a second pad 122 disposed in the second region R2 of the first insulating layer 111. The second pad 122 may be spaced farther from the periphery 111a of the first insulating layer 111 than the first pad 121.

[0111] The first pad 121 may perform a first function, and the second pad 122 may perform a second function different from the first function.

[0112] The first function of the first pad 121 may refer to a function for bonding the first external substrate to the circuit board 100. In addition, the second function of the second pad 122 may refer to a function for mounting a chip on the circuit board 100.

[0113] In addition, the first circuit layer 120 may further include traces. The traces of the first circuit layer 120 may be disposed in the first region R1 and the second region R2 of the first insulating layer 111. The traces of the first circuit layer 120 may be connected between the plurality of first pads, between the plurality of second pads, or between the first pad 121 and the second pad 122.

[0114] The planar area of ​​the first pad 121 may be different from the planar area of ​​the second pad 122. For example, the diameter of the first pad 121 in the first horizontal direction may be different from the diameter of the second pad 122 in the first horizontal direction. For example, the width of the first pad 121 may be different from the width of the second pad 122.

[0115] That is, the first pad 121 is a pad for bonding with the first external substrate, and the second pad 122 is a pad for mounting the chip. In addition, due to 5G, the Internet of Things (IOT), the improvement of image quality and the increase of communication speed, the number of terminals of the chip is increasing, or the width or spacing of the terminals of the chip is getting smaller. In contrast, the pads provided on the first external substrate may have a width or spacing larger than the terminals of the chip. Therefore, the plane area, diameter or width of the first pad 121 in the first horizontal direction may be larger than the plane area, diameter or width of the second pad 122 in the first horizontal direction.

[0116] The first pad 121 may be disposed in the first region R1 while not contacting the protective layer of the circuit board 100. For example, the side surface and the upper surface of the first pad 121 may not contact the protective layer. This will be described in more detail below.

[0117] In contrast, the second pad 122 may be disposed in the second region R2 while contacting the protective layer of the circuit board 100. For example, at least a portion of a side surface and an upper surface of the second pad 122 may contact the protective layer.

[0118] In addition, the second circuit layer 130 may further include a plurality of pads. The pads of the second circuit layer 130 of the circuit board 100 of the first embodiment may include only pads for mounting chips, but is not limited thereto.

[0119] In addition, the first circuit layer 120, the second circuit layer 130, the third circuit layer 140 and the fourth circuit layer 150 may be formed of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu) and zinc (Zn). In addition, the first circuit layer 120, the second circuit layer 130, the third circuit layer 140 and the fourth circuit layer 150 may be formed of a paste or solder paste including at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu) and zinc (Zn) having excellent bonding strength. Preferably, the first circuit layer 120, the second circuit layer 130, the third circuit layer 140 and the fourth circuit layer 150 may be formed of relatively inexpensive copper (Cu).

[0120] In addition, the thickness of the first circuit layer 120 and the second circuit layer 130 may be in the range of 5 μm to 30 μm. For example, the thickness of the first circuit layer 120 and the second circuit layer 130 may be in the range of 6 μm to 25 μm. The thickness of the first circuit layer 120 and the second circuit layer 130 may be in the range of 7 μm to 20 μm. If the thickness of the first circuit layer 120 and the second circuit layer 130 is less than 5 μm, the resistance may increase and the signal transmission loss may increase. If the thickness of the first circuit layer 120 and the second circuit layer 130 exceeds 30 μm, it is difficult to achieve miniaturization, and the circuit integration will be reduced accordingly.

[0121] The circuit board 100 of the embodiment may include a post 190 .

[0122] The pillar 190 may be disposed on the first circuit layer 120. Preferably, the pillar 190 may be disposed on the first pad 121 of the first circuit layer 120.

[0123] The pillar 190 may have a diameter or width smaller than that of the first pad 121. Thus, a portion of the first pad 121 may vertically overlap the pillar 190, and the remaining portion of the first pad 121 may not vertically overlap the pillar 190.

[0124] The pillar 190 may not be in contact with the first protective layer 170 described below. For example, the pillar 190 may be disposed in the first opening 171 of the first protective layer 170. Accordingly, the first pad 121 of the first circuit layer 120 may also be disposed in the first opening 171 of the first protective layer 170. At this time, in another embodiment described below, the first protective layer 170 in the first embodiment may have a structure including only a "protective member". Therefore, the first opening 170 of the first protective layer 170 may correspond to a separation area between the "external protective member" and the protective member described below.

[0125] Pillar 190 may be disposed at a certain height on first pad 121. The height may refer to a vertical distance from an upper surface of pillar 190 to a lower surface of pillar 190. Pillar 190 may have a height greater than 100 μm, greater than 120 μm, greater than 140 μm, greater than 160 μm, or greater than 200 μm.

[0126] For example, the height of the pillar 190 may satisfy the range of 100 μm to 220 μm. Preferably, the height of the pillar 190 may satisfy the range of 110 μm to 215 μm. More preferably, the height of the pillar 190 may satisfy the range of 115 μm to 210 μm.

[0127] If the height of the post 190 is less than 100 μm, the first external substrate may not be stably bonded to the post 190. If the height of the post 190 is less than 100 μm, the distance between the first external substrate and the circuit board 100 is reduced, and therefore, the signal transmission characteristics may be degraded due to signal interference therebetween. In addition, if the height of the post 190 exceeds 220 μm, the rigidity of the post 190 may be reduced. In addition, if the rigidity of the post 190 is reduced, physical reliability issues such as collapse may occur during bonding with the first external substrate. If the height of the post 190 exceeds 220 μm, the thickness of the circuit board 100 and the thickness of the semiconductor package may increase.

[0128] The circuit board 100 of the embodiment may include a through electrode, and the through electrode may penetrate the insulating layer 110 .

[0129] For example, the circuit board 100 may include a first through electrode 161 penetrating the first insulating layer 111. Also, the circuit board 100 may include a second through electrode 162 penetrating the second insulating layer 112. Also, the circuit board 100 may include a third through electrode 163 penetrating the third insulating layer 113.

[0130] The first through electrode 161, the second through electrode 162, and the third through electrode 163 may be disposed in through holes penetrating at least one insulating layer. For example, the first through electrode 161, the second through electrode 162, and the third through electrode 163 may be formed by filling the through holes with a conductive material.

[0131] The through hole can be formed by any one of mechanical, laser and chemical processing methods. The through hole can be formed by mechanical processing methods such as milling, drilling and routing. In addition, the through hole can use UV or CO2 laser method. In addition, the first through hole can use a chemical processing method, and the chemical processing method uses chemical reagents including aminosilane, ketone, etc.

[0132] In addition, a plurality of first through electrodes 161 may be formed in the first insulating layer 111 at intervals in the horizontal direction.

[0133] At this time, the first through electrode 161 may overlap the first circuit layer 120 in a vertical direction.

[0134] The first through electrode 161 may vertically overlap at least one of the first pad 121 and the second pad 122. For example, the first through electrode 161 may include a first electrode portion vertically overlapping the first pad 121 and a second electrode portion vertically overlapping the second pad 122. In addition, the first electrode portion and the second electrode portion of the first through electrode 161 may have different widths. At this time, each of the first electrode portion and the second electrode portion of the first through electrode 161 may have a slope whose width decreases from the upper surface to the lower surface. In addition, the upper surface of the first electrode portion of the first through electrode 161 may have a greater width than the lower surface of the second electrode portion of the first through electrode 161. That is, the first electrode portion of the first through electrode 161 is connected to the first pad 121, and the first pad 121 has a relatively greater width than the width of the second pad 122 connected to the second electrode portion of the first through electrode 161. Therefore, the first electrode portion of the first through electrode 161 may have a greater width than the second electrode portion.

[0135] In this way, the embodiment allows a plurality of electrode portions that are arranged in the same layer and horizontally spaced from each other to have different widths, thereby improving the circuit integration. Specifically, the second electrode portion of the first through electrode 161 is connected to the second pad 122 connected to the chip. In addition, the second electrode portion has a relatively small width, thereby reducing the width and spacing of the second pad 122. The embodiment can improve the circuit integration in the second region R2 where the second pad 122 is provided. In addition, the first electrode portion of the embodiment has a relatively large width. Therefore, the embodiment can improve the heat transfer characteristics generated in the circuit board 100 by the first electrode portion. In this way, the embodiment can improve the heat dissipation characteristics of the circuit board 100 and the semiconductor package including the circuit board 100.

[0136] In addition, circuit board 100 of the embodiment includes a protective layer.

[0137] Specifically, a first protective layer 170 is provided on the upper surface of the first insulating layer 111. The first protective layer 170 includes an opening. The opening may be defined as a "through hole" penetrating the upper and lower surfaces of the first protective layer 170. In addition, the opening 171 may also be defined as an "unset area" or an "opening area" where the first protective layer 170 is not provided on the upper surface of the first insulating layer 111 and / or the upper surface of the first circuit layer 120. In addition, the opening of the first protective layer 170 may be defined as a separation area. At this time, the first protective layer 170 of the first embodiment has a structure including only a protective member of the protective layer of another embodiment, and therefore, the separation area may refer to a separation area between the outer side of the insulating layer and the outer side of the first protective layer 170. For example, the first protective layer 170 of the first embodiment may be referred to as a "protection member".

[0138] Furthermore, in a region vertically overlapping with the opening of the first protection layer 170 , an upper surface of the first insulating layer 111 and / or an upper surface of the first circuit layer 120 may be exposed to the upper side of the circuit board 100 .

[0139] The first protective layer 170 may include a first opening 171 and a second opening 172 .

[0140] The first opening 171 of the first protective layer 170 may be disposed in the first region R1. In addition, the second opening 172 of the first protective layer 170 may be disposed in the second region R2 of the first protective layer 170. The number of the first openings 171 and the number of the second openings 172 may be different. The number of the first openings 171 may be one. For example, the first protective layer 170 may include a first opening 171 vertically overlapping with the plurality of first pads 121. In addition, the first opening 171 may also vertically overlap with the column 190 disposed on the first pad 121. In addition, the number of the second openings 172 may be multiple. For example, the first protective layer 170 may include a plurality of second openings 172 vertically overlapping with each of the plurality of second pads 122.

[0141] At this time, the first opening 171 of the first protective layer 170 may vertically overlap with the first region R1 as a whole. That is, the first opening 171 of the first protective layer 170 may completely open the upper surface of the first insulating layer 111 and the upper surface and side surface of the first circuit layer 120 in the first region R1. Therefore, the first opening 171 may generally refer to an undisposed area in which the first protective layer 170 is not disposed on the first insulating layer 111 and the first circuit layer 120. In addition, the first opening 171 may not be connected to the plurality of second openings 172.

[0142] The second opening 172 of the first protective layer 170 may partially vertically overlap the second region R2. That is, the second opening 172 of the first protective layer 170 may partially vertically overlap the upper surfaces of the first insulating layer 111 and the first circuit layer 120 in the second region R2.

[0143] For example, the first region R1 may include a first sub-region vertically overlapping with a plurality of first pads. In addition, the first protective layer 170 does not vertically overlap with the first sub-region. For example, the first opening 171 of the first protective layer 170 vertically overlaps with the first sub-region. In addition, the first region R1 may include a second sub-region corresponding to a region between a plurality of adjacent first pads. In addition, the first protective layer 170 does not vertically overlap with the second sub-region. In other words, the first opening 171 of the first protective layer 170 vertically overlaps with the second sub-region.

[0144] Therefore, the first opening 171 of the first protective layer 170 of the embodiment may vertically overlap the first region R1 in its entirety, and the second opening 172 may vertically overlap partially with the second region R2 .

[0145] In addition, the circuit board 100 may further include a second protection layer 180 disposed on the lower surface of the second insulating layer 112 .

[0146] The second protective layer 180 may include at least one opening. For example, the second protective layer 180 may include an opening vertically overlapping at least a portion of the second circuit layer 130. The opening of the second protective layer 180 may vertically overlap with a pad connected to the chip in the second circuit layer 130 in whole or in part.

[0147] The first protective layer 170 and the second protective layer 180 may include an insulating material. The first protective layer 170 and the second protective layer 180 may include various materials that can be applied and then cured by heating to protect the surfaces of the insulating layer and the circuit layer.

[0148] The first protective layer 170 and the second protective layer 180 may be solder resist layers including organic polymer materials. For example, the first protective layer 170 and the second protective layer 180 may include epoxy acrylate resins. In detail, the first protective layer 170 and the second protective layer 180 may include resins, curing agents, photoinitiators, pigments, solvents, fillers, additives, acrylic monomers, etc. However, the embodiment is not limited thereto, and the first protective layer 170 and the second protective layer 180 may be any one of a photo solder resist layer, a cover layer, and a polymer material.

[0149] The thickness of the first protective layer 170 and the second protective layer 180 may be 1 μm to 20 μm. The thickness of the first protective layer 170 and the second protective layer 180 may be 1 μm to 15 μm. For example, the thickness of the first protective layer 170 and the second protective layer 180 may be 5 μm to 20 μm. If the thickness of the first protective layer 170 and the second protective layer 180 exceeds 20 μm, the overall thickness of the circuit board and the semiconductor package may increase.

[0150] In the following, the following will be described in detail Figure 2 A partial configuration of the circuit board 100 is shown.

[0151] Figure 3 It has been removed Figure 2 A plan view of the circuit board of the first protective layer and pillars, Figure 4 yes Figure 2 A plan view of the second protective layer. Figure 5 yes Figure 2 A plan view of a circuit board. Figure 6 It is shown Figure 2 A cross-sectional view of a detailed layer structure of a first through-electrode, a first circuit layer, and a pillar.

[0152] Reference Figure 3 , the first insulating layer 111 may include a first region R1 and a second region R2. The first region R1 of the first insulating layer 111 may be a region adjacent to a periphery 111a of the first insulating layer 111. For example, the first region R1 of the first insulating layer 111 may be an outer region of an upper surface of the first insulating layer 111.

[0153] The first region R1 may be adjacent to the periphery 111a of the first insulating layer 111 and may be disposed in the peripheral direction of the first insulating layer 111. For example, the first region R1 may be adjacent to the periphery 111a of the first insulating layer 111 and may have a closed loop shape corresponding to the periphery 111a. However, the embodiment is not limited thereto. The first region R1 may have an open loop shape including only some regions of the peripheral region in the peripheral direction.

[0154] A plurality of first pads 121 may be disposed in the first region R1 of the first insulating layer 111. The plurality of first pads 121 may be disposed in the first region R1 of the first insulating layer 111 along a peripheral direction of the first insulating layer 111.

[0155] In addition, a plurality of second pads 122 may be disposed in the second region R2 of the first insulating layer 111. The plurality of second pads 122 may be selectively disposed in the second region R2 of the first insulating layer 111 while being spaced apart from the first pads 121 in a horizontal direction.

[0156] In addition, although Figure 3 Although not shown in the figure, the traces of the first circuit layer 120 may be disposed in the second region R2 of the first insulating layer 111. The traces of the first circuit layer 120 may be electrically connected between the plurality of second pads disposed in the second region R2.

[0157] In addition, the traces of the first circuit layer 120 may not be disposed in the first region R1 of the first insulating layer 111. Specifically, only a plurality of first pads 121 may be disposed in the first region R1 of the first insulating layer 111. In addition, the first pads 121 may be electrically connected to other circuit layers of the circuit board 100 through the first through-electrodes 161. However, the embodiment is not limited thereto. For example, the traces of the first circuit layer 120 may also be disposed in the first region R1.

[0158] The first pad 121 may have a first width W1. In addition, the second pad 122 may have a second width W2. At this time, the first width W1 may be different from the second width W2.

[0159] Specifically, the first width W1 may correspond to a pad provided in a first external substrate (preferably, a main board of an electronic device) combined with the circuit board 100. In addition, the second width W2 may correspond to a width of a terminal provided in a chip.

[0160] At this time, the pads provided in the first external substrate have a width relatively greater than that of the terminals of the chip. Therefore, the first width W1 of the first pad 121 may be greater than the second width W2 of the second pad 122.

[0161] The first width W1 of the first pad 121 may be 25 μm to 85 μm. Preferably, the first width W1 of the first pad 121 may be 30 μm to 80 μm. More preferably, the first width W1 of the first pad 121 may be 32 μm to 75 μm.

[0162] If the first width W1 of the first pad 121 is less than 25 μm, the bonding performance with the first external substrate may be reduced. If the first width W1 of the first pad 121 is less than 25 μm, the width W3 of the column 190 provided on the first pad 121 may be reduced accordingly. In addition, if the width W3 of the column 190 is reduced, the height H1 of the column 190 that can be formed may be reduced accordingly. In addition, if the first width W1 of the first pad 121 is less than 25 μm, the heat dissipation characteristics of the circuit board 100 may be deteriorated.

[0163] If the first width W1 of the first pad 121 exceeds 85 μm, the number of first pads 21 that can be disposed in the first region R1 may decrease. For example, if the first width W1 of the first pad 121 exceeds 85 μm, the circuit integration in the first region R1 may decrease. Therefore, the area of ​​the circuit board 100 may increase in order to place all the first pads connected to the first external substrate in the first region R1.

[0164] In addition, the first pad 121 may have a circular planar shape. In addition, when the planar shape of the first pad 121 is a circle, the first width W1 may represent a diameter of the first pad 120 .

[0165] In another embodiment, the planar shape of the first pad 121 may be a square or a rectangle. In addition, when the planar shape of the first pad 121 is a square or a rectangle, the first width W1 of the first pad 121 may represent the smaller width of the width of the first pad 121 in the width direction and the width in the length direction.

[0166] In another embodiment, the planar shape of the first pad 121 may be an ellipse. In addition, when the planar shape of the first pad 121 is an ellipse, the first width W1 of the first pad 122 may represent a diameter in a minor axis direction of the ellipse.

[0167] In addition, the plurality of first pads in the first region R1 may be spaced apart by a first interval D1. The first interval D1 may represent a minimum interval between two adjacently disposed first pads among the plurality of first pads disposed in the first region R1.

[0168] In one implementation, the first interval D1 may have a range corresponding to the first width W1 of one first pad 121 .

[0169] In another embodiment, the first distance D1 may be smaller than the first width W1 of one first pad 121 .

[0170] For example, the first spacing D1 between the plurality of first pads may satisfy a range of 20% to 90% of the first width W1 of the first pad 121. Preferably, the first spacing D1 between the plurality of first pads may satisfy a range of 23% to 88% of the first width W1 of the first pad 121. More preferably, the first spacing D1 between the plurality of first pads may satisfy a range of 25% to 85% of the first width W1 of the first pad 121.

[0171] If the first spacing D1 between the plurality of first pads is less than 20% of the first width W1 of the first pad 121, a circuit short may occur between the plurality of first pads 121 depending on process capabilities in the process of manufacturing the circuit board 100, thereby reducing the electrical reliability of the circuit board 100. In addition, if the first spacing D1 between the plurality of first pads is less than 20% of the first width W1 of the first pad 121, interference may occur between signals transmitted through the plurality of first pads 121. In addition, if interference occurs, signal transmission loss may increase, thereby deteriorating signal transmission characteristics.

[0172] In addition, if the first interval D1 between the plurality of first pads exceeds 90% of the first width W1 of the first pad 121 , the circuit integration enhancement effect in the first region R1 may not be significant compared to the comparative example.

[0173] At this time, in the comparative example, the spacing between the multiple first pads exceeds 95% of the first width of the first pad. This is because the opening size of the protective layer is included in one of the factors determining the spacing between the first pads. That is, the first protective layer of the comparative example includes multiple first openings that partially overlap vertically with the first region. Specifically, the first openings of the first protective layer of the comparative example are set corresponding to the number of first pads. In addition, the multiple first openings of the first protective layer of the comparative example have a structure in which multiple first pads are vertically overlapped at a ratio of 1:1. Therefore, in the comparative example, the first width of the multiple first pads and the first spacing between the multiple first pads are determined in consideration of the process capability and process error in the process of forming the multiple first openings in the first protective layer.

[0174] In contrast, the first protective layer 170 of the circuit board of the embodiment includes a first opening 171 that opens the first region R1 as a whole. At this time, the configuration that opens the first region R1 as a whole is referred to as the first opening 171 of the first protective layer 170, but the first protective layer 170 can actually be provided only in the second region R2 other than the first region R1. That is, the first protective layer 170 can be selectively provided only in the second region R2, and not in the first region R1.

[0175] Therefore, embodiments do not need to consider process capability and process error, etc. in the process of forming the plurality of first openings in the first protection layer 170. Therefore, embodiments may reduce the first width W1 of the first pad 121 and the first interval D1 between the plurality of first pads compared to the comparative example.

[0176] However, generally, the first width W1 of the first pad 121 is determined based on the width of the pad corresponding to the first external substrate provided in the main board and the width W3 of the column 190 corresponding thereto. Therefore, in an embodiment, the first width W1 of the first pad 121 can be reduced, but instead of reducing the first width W1 of the first pad 121, the first spacing D1 between the plurality of first pads is reduced. In this way, the embodiment can improve the circuit integration while maintaining the width of the existing first pad 121.

[0177] In addition, the second width W2 of the second pad 122 may be smaller than the first width W1 of the first pad 121 .

[0178] The second width W2 of the second pad 122 may be 15 μm to 50 μm. Preferably, the second width W2 of the second pad 122 may be 18 μm to 45 μm. More preferably, the second width W2 of the second pad 122 may be 20 μm to 40 μm.

[0179] If the second width W2 of the second pad 122 is less than 15 μm, the resistance of the signal transmitted through the second pad 122 will increase, thereby increasing the signal transmission loss. If the second width W2 of the second pad 122 exceeds 50 μm, the circuit integration will decrease. In addition, if the circuit integration decreases, it may not be possible to place all the second pads connected to the terminals of the chip in a limited space. In addition, if the second width W2 of the second pad 122 exceeds 50 μm, the spacing between the multiple second pads connected to the terminals of the chip will also increase. At this time, the second pad includes at least two second pads connected to each other. In addition, if the spacing increases, the signal transmission distance between the at least two second pads increases, and thus the signal transmission loss will increase. As a result, the signal transmission characteristics may be degraded.

[0180] In addition, refer to Figure 4 , the first protective layer 170 is partially disposed on the first insulating layer 111. Specifically, the first protective layer 170 is disposed in the second region R2 of the first insulating layer 111. That is, the first protective layer 170 is not disposed in the first region R1 of the first insulating layer 111.

[0181] In other words, the first protective layer 170 may be selectively disposed only in the second region R2 while including the first opening 171 that opens the first region R1 as a whole. Therefore, the first opening 171 may be referred to as an opening region or a non-disposed region of the first protective layer 170. In addition, the first protective layer 170 is not disposed in the region between the plurality of first pads. That is, the first protective layer 170 opens the first region R1 as a whole. Therefore, a structure in which the first protective layer 170 is not disposed between the plurality of first pads may be formed.

[0182] In addition, the first protective layer 170 may include a second opening 172 vertically overlapping the second pad 122 disposed in the second region R2 .

[0183] At this time, the plane area of ​​the first opening 171 of the first protective layer 170 may be different from the plane area of ​​the second opening 172 of the first protective layer 170. Preferably, the plane area of ​​the first opening 171 of the first protective layer 170 may be greater than the plane area of ​​the second opening 172. At this time, a plurality of second openings 172 may be provided in the first protective layer 170 vertically overlapping the second region R2. At this time, providing a plurality of openings may mean that the plurality of openings are not connected to each other but are spaced apart in the horizontal direction.

[0184] In addition, the first opening 171 is configured as one. Here, the fact that the first opening 171 is configured as one may mean that the first protective layer 170 does not exist in a region vertically overlapping with the first region R1.

[0185] Therefore, the outer side surface of the first protective layer 170 may be located inside the periphery 111a of the first insulating layer 111. Specifically, the outer side surface of the first protective layer 170 may be disposed inside the outer side surface of the first insulating layer 111 by the width of the first region R1.

[0186] In addition, the embodiment can improve the warping characteristics of the circuit board by setting the outer surface of the first protective layer 170 more inward than the outer surface of the first insulating layer 111. In other words, the first protective layer 170 is the outermost insulating layer of the circuit board 100. In addition, the process of forming the first protective layer 170 includes the process of exposing, developing and curing the first protective layer 170. In addition, in the process of exposing, developing and curing the first protective layer 170, stress is applied to the circuit board, and therefore, the side end of the circuit board may be bent in an upward direction or a downward direction. At this time, the embodiment can minimize the applied stress by setting the outer surface of the first protective layer 170 more inward than the outer surface of the first insulating layer 111. Therefore, the embodiment can improve the warping characteristics of the circuit board and the semiconductor package including the circuit board, and further improve the product reliability.

[0187] The outer side surface of the first protective layer 170 may have a step in the horizontal direction along the periphery. Specifically, the outer side surface of the first protective layer 170 may include a first portion 170a. In addition, the outer side surface of the first protective layer 170 may include a second portion 170b, which corresponds to a concave surface that is concave inwardly with the first portion 170a as a reference. In addition, the outer side surface of the first protective layer 170 may include a third portion 170c that is convex or protruding outwardly with the first portion 170a as a reference. Therefore, the separation area between the outer side of the substrate and the outer side surface of the first protective layer 170 may include a first separation area having a first width and a second separation area having a second width different from the first width. The first width may be greater than the second width, and the first separation area may refer to the width in the horizontal direction between the outer side of the substrate and the second portion 170b corresponding to the concave surface of the first protective layer 170. In addition, the second separation area may refer to the width in the horizontal direction between the outer side of the substrate and the third portion 170c corresponding to the convex surface of the first protective layer 170.

[0188] At this time, the first portion 170 a , the second portion 170 b , and the third portion 170 c of the first protective layer 170 may be designed based on the position of the first pad disposed adjacent to the first protective layer 170 .

[0189] For example, the second portion 170b of the first protective layer 170 may overlap the first pad adjacent to the first protective layer 170 in the length direction or the width direction. In addition, the third portion 170c of the first protective layer 170 may overlap the region between the plurality of first pads adjacent to the first protective layer 170 in the length direction or the width direction.

[0190] As described above, embodiments can improve the design freedom of the first pad arrangement in the first region R1 by including the second portion 170b and the third portion 170c in addition to the first portion 170a in the outer surface of the first protection layer 170. In this way, embodiments can further improve the integration of the first pad in the first region R1.

[0191] That is, the pillars 190 may be arranged along the periphery of the outer side surface of the first protective layer 170. At this time, the first protective layer 170 includes an upper surface, a lower surface, and a side surface arranged between the upper surface and the lower surface. At this time, the lower surface of the first protective layer 170 may face the upper surface of the insulating layer (e.g., the uppermost insulating layer). In addition, a plurality of pillars 190 may face the side surface of the first protective layer 170. In addition, the side surface of the first protective layer 170 may include a protruding portion protruding between the plurality of pillars.

[0192] For example, the side surface of the first protective layer 170 may include a first side surface extending in the first direction, a second side surface extending in the first direction and spaced apart from the first side surface, a third side surface extending in a second direction perpendicular to the first direction, and a fourth side surface extending in the second direction and spaced apart from the third side surface. At this time, the protruding surface of the first protective layer 170 may be provided on the first side surface and the third side surface.

[0193] Therefore, the third side surface of the first protective layer 170 may have a first surface, a second surface, and a third surface, the first surface having a first separation distance from the plurality of pillars along the first direction, the second surface having a second separation distance from the plurality of pillars along the first direction that is smaller than the first separation distance, and the third surface having a third separation distance from the plurality of pillars along the first direction that is larger than the first separation distance. This is because the third side surface of the first protective layer 170 may be provided with all of the first portion 170a, the second portion 170b, and the third portion 170c.

[0194] In addition, the separation distance between the fourth side surface of the first protective layer 170 and the plurality of pillars along the first direction may be uniform. This may be a design considering the bending direction of the circuit board, and at least one side surface of the first protective layer 170 may not have a protruding or recessed surface.

[0195] In addition, the second side surface of the first protective layer 170 may include a recessed surface recessed toward the first side surface of the first protective layer 170 .

[0196] In addition, refer to Figure 5 The pillar 190 is disposed on the first pad 121 located in the first region R1. The third width W3 of the pillar 190 may be smaller than the first width W1 of the first pad 121.

[0197] Specifically, the column 190 may be disposed on the first pad 121 that is completely opened by the first opening 171 of the first protective layer 170. In this way, the embodiment may use a separate dry film as a mask to form the column 190, rather than using the opening of the first protective layer 170 as a mask to form the column 190. At this time, compared to the solder resist layer, the dry film may have a greater thickness while allowing a smaller opening to be formed. In this way, the embodiment may allow the column 190 to have a smaller width than the first pad 121.

[0198] In addition, the embodiment may form the pillar 190 by using the seed layer for electroplating the first pad 121. In this way, there is no seed layer for electroplating the pillar 190 between the first pad 121 of the embodiment and the pillar 190. In addition, the embodiment may form the pillar 190 by removing the separate seed layer for electroplating the pillar 190 and only considering the opening size of the dry film. In this way, the embodiment may allow the third width W3 of the pillar 190 to be smaller than the first width W1 of the first pad 121.

[0199] The third width W3 of the pillar 190 may satisfy a range of 60% to 95% of the first width W1 of the first pad 121. Preferably, the third width W3 of the pillar 190 may satisfy a range of 65% to 92% of the first width W1 of the first pad 121. The third width W3 of the pillar 190 may satisfy a range of 70% to 90% of the first width W1 of the first pad 121.

[0200] If the third width W3 of the column 190 is less than 60% of the first width W1 of the first pad 121, the heat dissipation characteristics of the circuit board may be deteriorated. If the third width W3 of the column 190 is less than 60% of the first width W1 of the first pad 121, the first external substrate may not be stably disposed on the circuit board. If the third width W3 of the column 190 is less than 60% of the first width W1 of the first pad 121, the height H1 of the column 190 may not be formed above a certain level.

[0201] If the third width W3 of the pillar 190 is greater than 95% of the first width W1 of the first pad 121, the width of the pillar 190 may be greater than the first pad 121 due to a process error in the process of forming the pillar 190. In this case, a circuit short circuit problem may occur in which two adjacent pillars 190 are connected to each other. That is, as the interval between the two adjacent pillars 190 decreases, an electrical reliability problem may occur.

[0202] Specifically, refer to Figure 6 The pillar 190 is disposed on the first pad 121 with a width smaller than that of the first pad. In addition, the pillar 190 is disposed on the first pad 121 with a certain height H1.

[0203] The height H1 may represent a vertical distance from the upper surface of the column 190 to the lower surface of the column 190. The height H1 of the column 190 may exceed 100 μm, exceed 120 μm, exceed 140 μm, exceed 160 μm, or exceed 200 μm. For example, the height H1 of the column 190 may satisfy the range of 100 μm to 220 μm. Preferably, the height H1 of the column 190 may satisfy the range of 110 μm to 215 μm. More preferably, the height H1 of the column 190 may satisfy the range of 115 μm to 210 μm.

[0204] If the height H1 of the post 190 is less than 100 μm, the first external substrate may not be stably bonded to the post 190. If the height H1 of the post 190 is less than 100 μm, the distance between the first external substrate and the circuit board 100 is reduced, and therefore, the signal transmission characteristics may be degraded due to signal interference between the first external substrate and the circuit board 100. In addition, if the height H1 of the post 190 exceeds 220 μm, the rigidity of the post 190 may be degraded. In addition, if the rigidity of the post 190 is degraded, physical reliability problems such as collapse may occur during bonding with the first external substrate. If the height H1 of the post 190 exceeds 220 μm, the thickness of the circuit board 100 and the thickness of the semiconductor package may increase.

[0205] The pillar 190 is composed of one metal layer. Specifically, the pillar 190 may include only an electrolytic plating layer, and does not include an electroless plating layer such as a chemical copper plating layer.

[0206] In addition, the first circuit layer 120 is composed of at least two metal layers. The first pad 121 and the second pad 122 of the first circuit layer 120 may have the same layer structure. In addition, the first through electrode 161 may include two metal layers corresponding to the first circuit layer 120.

[0207] That is, each of the first pad 121 and the second pad 122 of the first circuit layer 120 may include a first metal layer 120 - 1 and a second metal layer 120 - 2 .

[0208] In addition, the first through electrode 161 may include a third metal layer 161 - 1 corresponding to the first metal layer 120 - 1 of the first circuit layer 120 and a fourth metal layer 161 - 2 corresponding to the second metal layer 120 - 2 .

[0209] At this time, the first metal layer 120-1 and the third metal layer 161-1 may be roughly referred to as one layer and may be distinguished according to the arrangement position. In addition, the second metal layer 120-2 and the fourth metal layer 161-2 may also be roughly referred to as one metal layer and may be distinguished according to the arrangement position.

[0210] In addition, the first metal layer 120 - 1 may be substantially two layers. The first metal layer 120 - 1 may be two metal layers including the same metal layer as the third metal layer 161 - 1 on a copper foil (Cufoil).

[0211] In addition, the first metal layer 120 - 1 may be a layer of copper foil (Cu foil).

[0212] Therefore, only the first metal layer 120 - 1 and the second metal layer 120 - 2 will be described below.

[0213] The first metal layer 120-1 of the first circuit layer 120 may be a seed layer. The first metal layer 120-1 of the first circuit layer 120 may be a chemically plated copper layer. The first metal layer 120-1 of the first circuit layer 120 may be a copper foil layer. The first metal layer 120-1 of the first circuit layer 120 may include a copper foil layer and a chemically plated copper layer.

[0214] The thickness of the first metal layer 120-1 of the first circuit layer 120 may be within a range of 1.0 μm to 3.0 μm. Preferably, the thickness of the first metal layer 120-1 of the first circuit layer 120 may be within a range of 1.2 μm to 2.8 μm. More preferably, the thickness of the first metal layer 120-1 of the first circuit layer 120 may be within a range of 1.5 μm to 2.5 μm.

[0215] If the thickness of the first metal layer 120-1 of the first circuit layer 120 is less than 1.0 μm, the first metal layer 120-1 of the first circuit layer 120 may not function as a seed layer. If the thickness of the first metal layer 120-1 of the first circuit layer 120 is less than 1.0 μm, it may be difficult to form the first metal layer 120-1 with a uniform thickness on the upper surface of the first insulating layer 110.

[0216] If the thickness of the first metal layer 120-1 of the first circuit layer 120 exceeds 3.0 μm, the process time of forming the first metal layer 120-1 of the first circuit layer 120 may increase, and the yield may decrease accordingly. In addition, if the thickness of the first metal layer 120-1 of the first circuit layer 120 exceeds 3.0 μm, the etching time of the first metal layer 120-1 may increase in the process of forming the first circuit layer 120. In addition, if the thickness of the first metal layer 120-1 of the first circuit layer 120 exceeds 3.0 μm, the second metal layer 120-2 of the first circuit layer may be deformed in the process of etching the first metal layer 120-1 of the first circuit layer 120. Here, the deformation of the second metal layer 120-2 of the first circuit pattern layer 120 may mean that since the side of the second metal layer 120-2 is also etched during the etching of the first metal layer 120-1, the difference between the width of the upper surface and the width of the lower surface of the second metal layer 120-2 increases. In addition, if the thickness of the first metal layer 120-1 of the first circuit layer 120 exceeds 3.0 μm, the etching amount in the etching process of the first metal layer 120-1 increases, and therefore, the depth of the recess (e.g., undercut) formed at the side of the first metal layer 120-1 and the side of the second metal layer 120-2 may increase. For example, if the etching amount in the etching process of the first metal layer 120-1 increases, the difference between the width of the first metal layer 120-1 and the width of the second metal layer 120-2 may increase. In addition, if the difference between the width of the first metal layer 120-1 and the width of the second metal layer 120-2 increases, the electrical characteristics may be degraded due to the increase in signal transmission loss. In addition, if the difference between the width of the first metal layer 120-1 and the width of the second metal layer 120-2 increases, dendrites may be formed by electromigration, thereby degrading the electrical characteristics and / or physical characteristics of the first circuit pattern layer 120.

[0217] The second metal layer 120-2 of the first circuit layer 120 may be an electrolytically plated layer in which the first metal layer 120-1 is electrolytically plated as a seed layer. The second metal layer 120-2 of the first circuit layer 120 may be formed on the first metal layer 120-1 with a predetermined thickness. The second metal layer 120-2 of the first circuit layer 120 may include the same metal as the first metal layer 120-1 of the first circuit layer 120, but is not limited thereto. For example, the first metal layer 120-1 and the second metal layer 120-2 of the first circuit layer 120 may each include copper.

[0218] The thickness of the second metal layer 120-2 of the first circuit layer 120 may correspond to a value obtained by subtracting the thickness of the first metal layer 120-1 from the thickness range of the first circuit layer. In addition, since the thickness range of the first circuit layer 120 has been described above, its description will be omitted.

[0219] In addition, the pillar 190 can be formed on the second metal layer 120-2 of the first circuit layer 120 by electrolytic plating the first metal layer 120-1 as a seed layer. For example, the pillar 190 may include only the third metal layer. In addition, by electrolytic plating the first metal layer 120-1 as a seed layer, a third metal layer having a predetermined height H1 can be formed on the second metal layer 120-2. That is, the lower surface of the third metal layer is in direct contact with the upper surface of the second metal layer 120-2. In addition, the upper surface of the third metal layer is located at a higher position than the upper surface of the first protective layer 170. This may mean that the pillar 190 does not include a seed layer between the second metal layer 120-2 and the third metal layer.

[0220] Figure 7 is a cross-sectional view showing a circuit board according to a second embodiment, Figure 8 It is shown Figure 7 A magnified view of a portion of the area.

[0221] Reference Figure 7 and Figure 8 , the circuit board of the second embodiment is Figure 2 The difference between the circuit board and the circuit board is that a surface treatment layer is provided. Figure 2 The circuit board is roughly the same as the part described above.

[0222] The circuit board of the second embodiment may include a surface treatment layer.

[0223] Specifically, the circuit board may include a first surface finishing layer 210 .

[0224] The first surface finish layer 210 may be disposed on the first pad 121 and the pillar 190 .

[0225] Specifically, the first protective layer 170 is not disposed in a region where the first pad 121 and the pillar 190 are disposed. Therefore, the first surface finish layer 210 may cover the exposed surfaces of the first pad 121 and the pillar 190 as a whole.

[0226] The first surface finish layer 210 may be divided into a plurality of parts.

[0227] For example, the first surface treatment layer 210 may include a first portion 210-1 disposed on a side surface of the first pad 121, a second portion 120-2 disposed on an upper surface of the first pad 121, a third portion 210-3 disposed on a side surface of the pillar 190, and a fourth portion 210-4 disposed on an upper surface of the pillar 190.

[0228] In addition, the circuit board may include a second surface treatment layer 220. The second surface treatment layer 220 may be disposed on the second pad 122. Specifically, the second surface treatment layer 220 may be disposed on the upper surface of the second pad 122 opened by the second opening 172 of the first protective layer 170.

[0229] In addition, the circuit board may include a third surface treatment layer 230. The third surface treatment layer 230 may be disposed under the pad of the second circuit layer 130. Specifically, the third surface treatment layer 230 may be disposed on the lower surface of the pad of the second circuit layer 130 opened by the opening of the second protective layer 180.

[0230] The first surface treatment layer 210, the second surface treatment layer 220 and the third surface treatment layer 230 may be an OSP (Organic Solderability Preservative, organic solderability protective agent) layer. For example, the first surface treatment layer 210, the second surface treatment layer 220 and the third surface treatment layer 230 may be an organic coating coated with an organic material such as benzimidazole (Benzimidazole). However, the embodiment is not limited thereto. For example, the first surface treatment layer 210, the second surface treatment layer 220 and the third surface treatment layer 230 may be a plating layer. For example, the first surface treatment layer 210, the second surface treatment layer 220 and the third surface treatment layer 230 may include at least one of a nickel (Ni) plating layer, a palladium (Pd) plating layer and a gold (Au) plating layer.

[0231] Fig. 9 2 is a diagram showing a semiconductor package according to a first embodiment.

[0232] Reference Fig. 9 and Fig.10 , semiconductor packaging includes Figure 2 The circuit board 100.

[0233] The semiconductor package of the first embodiment may have a structure in which a plurality of chips and a first external substrate are combined on a circuit board 100 .

[0234] To this end, the circuit board 100 includes a first pad 121 and a second pad 122 of the first circuit layer 120. In addition, the pillar 190 is disposed on the first pad 121.

[0235] In addition, the semiconductor package includes a first connection portion 310 disposed on the second pad 122. The first connection portion 310 may have a hexahedral shape. For example, the cross-section of the first connection portion 310 may include a square shape. The cross-section of the first connection portion 310 may include a rectangular or square shape. For example, the first connection portion 310 may include a spherical shape. For example, the cross-section of the first connection portion 310 may include a circular or semicircular shape. For example, the cross-section of the first connection portion 310 may include a partially or completely circular shape. The cross-sectional shape of the first connection portion 310 may be flat on one side surface and curved on the other side surface. The first connection portion 310 may be a solder ball, but is not limited thereto.

[0236] The semiconductor package may include a first chip 320 disposed on the first connection portion 310. The first chip 320 may include a terminal 325. The terminal 325 of the first chip 320 may be electrically connected to the second pad 122 through the first connection portion 310.

[0237] The semiconductor package may include a second connection portion 330 disposed under the pads of the first group in the second circuit layer 130. In addition, a second chip 340 may be mounted on the second connection portion 330. The second chip 340 may include a terminal 345. The terminal 345 of the second chip 340 may be electrically connected to the pads of the first group through the second connection portion 330.

[0238] The semiconductor package may include a third connection portion 350 disposed under the pads of the second group in the second circuit layer 130. In addition, a third chip 360 may be mounted on the third connection portion 350. The third chip 360 may include a terminal 365. The terminal 365 of the third chip 360 may be electrically connected to the pads of the second group through the third connection portion 350.

[0239] The semiconductor package may include a fourth connection portion 370 disposed under the pads of the third group in the second circuit layer 130. In addition, a fourth chip 380 may be mounted on the fourth connection portion 370. The fourth chip 380 may include a terminal 385. The terminal 385 of the fourth chip 380 may be electrically connected to the pads of the third group through the fourth connection portion 370.

[0240] At least one of the first chip 320, the second chip 340, the third chip 360, and the fourth chip 380 may include a logic chip. For example, at least one of the first chip 320, the second chip 340, the third chip 360, and the fourth chip 380 may include an application processor chip. For example, at least one of the first chip 320, the second chip 340, the third chip 360, and the fourth chip 380 may include an analog-to-digital converter or an ASIC (application-specific IC). For example, at least one of the first chip 320, the second chip 340, the third chip 360, and the fourth chip 380 may include a memory chip. The memory chip may be a stacked memory such as HBM. For example, the memory chip may include a volatile memory (e.g., DRAM), a non-volatile storage (e.g., ROM), a flash memory, etc. In addition, at least one of the first chip 320, the second chip 340, the third chip 360, and the fourth chip 380 may include at least one of a driver IC chip, a diode chip, a power IC chip, a touch sensor IC chip, a multilayer ceramic capacitor (MLCC, Multi layer ceramic condenser) chip, a ball grid array (BGA, Ball Grid Array) chip, and a chip capacitor. For example, at least one of the first chip 320, the second chip 340, the third chip 360, and the fourth chip 380 may be an active device, and at least one of the other chips may be a passive device.

[0241] The semiconductor package may include a first mold layer 390 .

[0242] The first mold layer 390 may mold the first chip 320 and the pillar 190. At this time, the first protection layer 170 is not disposed in the first region R1 of the first insulating layer 111. Therefore, the first mold layer 390 may mold the first region R1 of the first insulating layer 111. For example, the first mold layer 390 may mold the upper surface of the first region R1 of the first insulating layer 111. For example, accordingly, at least a portion of the upper surface of the first region R1 of the first insulating layer 111 may be in direct contact with the first mold layer 390. In addition, the first mold layer 390 may mold the first pad 121 disposed in the first region R1 and the pillar 190 disposed on the first pad 120. For example, at least a portion of the upper surface and the side surface of the first pad 121 may be in direct contact with the first mold layer 390. For example, the side surface of the pillar 190 may be in direct contact with the first mold layer 390. At this time, as Figure 7 As shown in , when the first surface treatment layer 210 is included, the first mold layer 390 may mold the upper surface of the first region R1 of the first insulating layer 111 and the first surface treatment layer 210 .

[0243] The first mold layer 390 may include an opening region. For example, the first mold layer 390 may include a first opening region that opens the upper surface of the pillar 190. For example, the first mold layer 390 may include a second opening region that opens the upper surface of the first chip 320. The first opening region and the second opening region may be formed by grinding the upper surface of the first mold layer 390 and the upper surface of the pillar 190, so that in a state where the first mold layer 390 is formed, the upper surface of the first mold layer 390 and the lower surface of the pillar 190 have the same height as the upper surface of the first chip 320.

[0244] However, the first mold layer 390 may entirely mold the upper surface of the first chip 320 , and thus may include only the first opening region opening the upper surface of the pillar 190 .

[0245] The semiconductor package may include a second molding layer 395 .

[0246] The second mold layer 395 may be disposed on a lower surface of the second insulating layer 112. The second mold layer 395 may mold the second chip 340, the third chip 360, and the fourth chip 380.

[0247] The first mold layer 390 and the second mold layer 395 may be EMC (Epoxy Mold Compound), but the embodiment is not limited thereto.

[0248] At this time, the first mold layer 390 and the second mold layer 395 may have a low dielectric constant to improve the heat dissipation characteristics. For example, the dielectric constant (Dk) of the first mold layer 390 and the second mold layer 395 may be 0.2 to 10. For example, the dielectric constant (Dk) of the first mold layer 390 and the second mold layer 395 may be 0.5 to 8. For example, the dielectric constant (Dk) of the first mold layer 390 and the second mold layer 395 may be 0.8 to 5. Therefore, in an embodiment, the first mold layer 390 and the second mold layer 395 have a low dielectric constant, so that the heat generated by the first chip 320, 340, 360 and 380 can be effectively dissipated to the outside.

[0249] The semiconductor package may include a fifth connection portion 410 . The fifth connection portion 410 may be disposed on an upper surface of the pillar 190 opened by the first opening region of the first mold layer 390 .

[0250] The semiconductor package may include a first external substrate 420 disposed on the fifth connection portion 410. The first external substrate 420 may be a main board. For example, the first external substrate 420 may be a motherboard of an electronic device.

[0251] Fig.10 is a cross-sectional view showing a circuit board according to a third embodiment.

[0252] Reference Fig.10 The circuit board 100A of the third embodiment and Figure 2 The difference between the circuit board 100 and the circuit board 100A is that the circuit board 100A has a vertically symmetrical structure. Figure 2 The circuit board is roughly the same as the part described above.

[0253] The circuit board 100A may have a first protective layer 170 including a first opening 171 and a second opening 172 disposed on the first insulating layer 111. In addition, a first pillar 190 may be disposed on the first pad 121 of the first circuit layer 120.

[0254] The circuit board 100A may have a second protection layer 180 a and a second pillar 195 corresponding to the first protection layer 170 and the first pillar 190 , and the second pillar 195 is disposed at a lower side of the circuit board 100A.

[0255] Specifically, the second insulating layer 112 may further include a first region R1 and a second region R2 corresponding to the first insulating layer 111. In addition, the second protective layer 180a may include a third opening 181 that completely opens the first region R1. In addition, the second protective layer 180a may include a fourth opening 182 that partially opens the second region R2. That is, the second protective layer 180a may have a structure corresponding to the first protective layer 170. At this time, the first region and the second region of the first insulating layer 111 and the second insulating layer 112 are described as overlapping each other in the vertical direction, but the embodiment is not limited thereto. For example, the first region in the first insulating layer and the first region in the second insulating layer may have different areas.

[0256] The second circuit layer 130 may include a third pad disposed under the first region R1 of the second insulating layer 112 and a fourth pad disposed under the second region R2 of the second insulating layer 112. In addition, the third pad of the second circuit layer 130 may have a structure corresponding to the first pad 121 of the first circuit layer 120. The fourth pad of the second circuit layer 130 may have a structure corresponding to the second pad 122 of the first circuit layer 120.

[0257] In addition, the second pillar 195 is disposed under the third pad of the second circuit layer 130. The second pillar 195 may have a structure corresponding to the first pillar 190. Since the first pillar 190 has been described in the foregoing embodiment, description of the second pillar will be omitted.

[0258] The circuit board 100A of the third embodiment may have pillars disposed on both sides of a substrate. The circuit board 100A of the third embodiment may be applied to a POP structure.

[0259] Fig.11 is a cross-sectional view showing a semiconductor package according to a second embodiment.

[0260] Reference Fig.11 , the semiconductor package according to the second embodiment may have a structure in which a second external substrate 520 is additionally provided in the semiconductor package of the first embodiment.

[0261] A sixth connection portion 510 may be provided on a lower surface of the second pillar 195 of the circuit board 100A.

[0262] To this end, the second mold layer 395 may include a third open region opening the lower surface of the second pillar 195 .

[0263] The second external substrate 520 may be coupled to the sixth connection portion 510. The second external substrate 520 may be a memory package. To this end, the second external substrate 520 may include a memory substrate 521, a memory chip 522 attached to the memory substrate 521, and a connection member 543 connecting the memory substrate 521 and the memory chip 522.

[0264] However, embodiments are not limited thereto, and the second external substrate 520 may be an interposer disposed between the memory package and the second pillars 195 .

[0265] Fig.12 is a cross-sectional view showing a circuit board according to a fourth embodiment, Fig.13 yes Fig.12 Top plan view of the circuit board, Fig.14 yes Fig.12 An enlarged view of a local area of ​​a circuit board.

[0266] Reference Figure 12 to Figure 14 The circuit board 100B of the fourth embodiment is Figure 2 The difference between the circuit board 100 and the circuit board 100B is that the first protection layer of the circuit board 100B includes a reinforcement pattern. Figure 2 The circuit board is roughly the same as the part described above.

[0267] In the circuit board of the first embodiment, the first protection layer 170 is not provided at all in the first region R1 including the periphery 111a of the upper surface of the first insulating layer 111. That is, the first protection layer 170 of the circuit board of the first embodiment includes the first opening 171 which completely opens the first region R1 including the periphery 111a of the upper surface of the first insulating layer 111.

[0268] Different from this, the first protective layer 170B in the fourth embodiment may include a plurality of protective members.

[0269] The first protective layer 170B may include an outer protective member 170B1 The outer protective member 170B1 of the first protective layer 170B may be disposed in a peripheral region or an edge region adjacent to the periphery 111 a of the upper surface of the first insulating layer 111 .

[0270] Specifically, the first insulating layer 111 may further include a third region R3 in addition to the first region R1 and the second region R2.

[0271] The third region R3 may refer to a peripheral region or an edge region adjacent to the periphery 111a while including the periphery 111a of the upper surface of the first insulating layer 111 in the first region R1 of the first embodiment. That is, the first protective layer 170B includes an outer protective member 170B1 disposed in the third region R3 adjacent to the periphery 111a while fully opening the first region R1. The first protective layer 170B may be disposed at an edge region of the upper surface of the first insulating layer 111 along the peripheral direction of the first insulating layer 111. That is, the outer protective member 170B1 of the first protective layer 170B may have a closed loop shape including an opening region that fully opens the first region R1 and the second region R2.

[0272] The outer protective member 170B1 of the first protective layer 170B may also be referred to as a reinforcing member that improves the rigidity of the circuit board 100B. The outer protective member 170B1 of the first protective layer 170B may be formed by controlling a sawing line in a sawing process of separating a substrate strip into units in a process of manufacturing the circuit board of the embodiment.

[0273] The protective member 170B2 of the first protective layer 170B may be disposed in the second region R2 of the first insulating layer 111. The protective member 170B2 of the first protective layer 170B corresponds to the first protective layer 170 of the first embodiment. Therefore, a detailed description thereof will be omitted.

[0274] The outer protective member 170B1 may be horizontally spaced apart from the protective member 170B2 with the first opening 171 therebetween. Here, the first opening 171 may be referred to as a separation area between the inner side surface of the outer protective member 170B1 and the outer side surface of the protective member 170B2.

[0275] That is, the first opening 171 may also be referred to as a separation space that separates the outer protective member 170B1 and the protective member 170B2. The outer protective member 170B1 may be provided in a closed loop shape along the peripheral direction of the first insulating layer 111. Therefore, the first opening 171 may be provided in a closed loop shape between the inner side surface of the outer protective member 170B1 and the outer side surface of the protective member 170B2.

[0276] At this time, as described in the previous embodiment, the outer side surface of the protection member 170B2 includes an outward protrusion portion and an inward recessed portion. Therefore, the horizontal width of the first opening 171 may include different widths along the outer side surface of the protection member 170B2.

[0277] That is, the outer protective member 170B1 is arranged along the edge of the upper surface of the substrate corresponding to the insulating layer, and the protective member 170B2 is arranged inside the outer protective member 170B1 and has a separation area therebetween. At this time, the separation area between the inner surface of the outer protective member 170B1 and the outer surface of the protective member 170B2 may include a first separation area having a first width in the horizontal direction and a second separation area having a second width different from the first width. This may be due to the concave surface and / or the convex surface provided at the outer surface of the protective member 170B2. In addition, the separation area is provided as a closed loop along the outer surface of the protective member 170B2.

[0278] At this time, the outer side surface of the protection member 170B2 includes a protruding surface protruding toward the inner side surface of the outer protection member 170B 1. In addition, the protruding surface of the protection member 170B2 is disposed in the second partition area, and the first width may be greater than the second width.

[0279] At this time, the protruding surface of the protection member 170B2 may include a first protruding surface protruding toward the inner side surface of the outer protection member 170B1 with a first protruding width, and a second protruding surface protruding toward the inner side surface of the outer protection member 170B1 with a second protruding width greater than the first protruding width. In this case, the first separation area may correspond to the first protruding surface, and the second separation area may correspond to the second protruding surface.

[0280] In addition, the outer side surface of the protection member 170B2 may include a recessed surface recessed toward the inner side of the protection member 170B2. At this time, the recessed surface of the protection member 170B2 is disposed in the first partition area, and the first width may be greater than the second width.

[0281] In addition, the inner side surface of the outer protection member 170B1 may include a first inner side surface, a second inner side surface facing the first inner side surface, and third and fourth inner side surfaces disposed between the first and second inner side surfaces and facing each other.

[0282] In addition, the outer side surface of the second protective member 170B2 may include a first outer side surface adjacent to the first inner side surface, a second outer side surface adjacent to the second inner side surface, a third outer side surface adjacent to the third inner side surface, and a fourth outer side surface adjacent to the fourth inner side surface.

[0283] At this time, a separation region between the first inner side surface of the outer protection member 170B1 and the first outer side surface of the second protection member 170B2 may include a first separation region and a second separation region.

[0284] In addition, the first circuit layer 120 includes first pads 121 and second pads 122 , respectively.

[0285] At this time, the first circuit layer 120 may include a dummy pattern 123. The dummy pattern 123 may be disposed in the third region R3 of the first insulating layer 111. The dummy pattern 123 may be covered by the outer protective member 170B1.

[0286] The dummy pattern 123 may have a planar shape corresponding to the outer protective member 170B1. For example, the dummy pattern 123 may be provided in a closed loop shape along the perimeter 111a.

[0287] The dummy pattern 123 may be a portion of a seed layer for electroplating the first pad 121 , the second pad 122 , and the pillar 190 .

[0288] That is, the electroplating process of the column 190 in the fourth embodiment can be performed in a state where the outer protective member 170B1 is set corresponding to the third region R3. In addition, since the seed layer is finally removed while the outer protective member 170B1 is set, the seed layer set under the outer protective member 170B1 is not removed. Therefore, the first circuit layer 120 of the circuit board of the fourth embodiment may also include a dummy pattern 123 set under the outer protective member 170B1 of the third region R3. The dummy pattern 123 may correspond to the first metal layer 120-1 of the first circuit layer 120. That is, the dummy pattern 123 may have the same thickness as the first metal layer 120-1 of the first pad 121 and the second pad 122 of the first circuit layer 120.

[0289] The embodiment has a structure in which the dummy pattern 123 is disposed in the third region R3 of the upper surface of the first insulating layer 111 of the circuit board. In addition, the dummy pattern 123 may have a function of suppressing bending of the circuit board and improving warpage characteristics. For example, the dummy pattern 123 may be used as a rigid member to improve the rigidity of the circuit board. In addition, the outer protective member 170B1 may have a protective function of protecting the outermost edge region of the upper surface of the first insulating layer 111.

[0290] The reason why the circuit board of the fourth embodiment may have the outer protection member 170B1 and the dummy pattern 123 will be described in more detail below in the description of the manufacturing method of the circuit board.

[0291] - Manufacturing method of circuit board -

[0292] Figures 15 to 28 It is described in order of process Figure 2 The following is a diagram of a method for manufacturing a circuit board according to a first embodiment of the present invention. Figures 15 to 28 The manufacturing method of the circuit board of the first embodiment is described. In addition, in the description of the manufacturing method of the circuit board of the first embodiment, a method of forming the dummy parts of the first circuit layer and the first protective layer of the fourth embodiment will also be described.

[0293] Furthermore, the following description will focus on a process of forming the first circuit layer 120 , the first protective layer 170 , and the pillars 190 on the upper side of the first insulating layer 111 in the circuit board.

[0294] Reference Fig.15 , the embodiment prepares the first insulating layer 111. Preferably, the process of preparing the first insulating layer 111 may refer to a process of stacking the first insulating layer 111 on the third insulating layer 113 while the third circuit layer 140 is disposed on the third insulating layer 113. Next, the embodiment may form a first metal layer 120-1 on the first insulating layer 111. The first metal layer 120-1 may refer to a copper foil layer disposed on the first insulating layer 111. Alternatively, the first metal layer 120-1 may be an electroless plating layer formed by performing electroless plating on the first insulating layer 111. For example, the first metal layer 120-1 may be a chemical copper plating layer. Alternatively, the first metal layer 120-1 may include both a copper foil layer and a chemical copper plating layer.

[0295] At this time, the circuit board of the embodiment can be manufactured as a strip unit or a panel unit. That is, the strip includes a plurality of circuit boards, and the panel includes a plurality of strips.

[0296] Therefore, the first insulating layer 111 may be divided into a plurality of regions. For example, the first insulating layer 111 includes a plurality of active regions AR corresponding to the circuit board regions and a dummy region DR disposed between the plurality of active regions AR. Finally, a plurality of circuit boards may be separated by sawing using the line between the active region AR and the dummy region DR as a sawing line. In addition, as described above, the active region AR may include a first region R1 and a second region R2 of the circuit board 100. The first region R1 of the circuit board 100 may refer to a region adjacent to the dummy region DR.

[0297] Next, refer to Fig.16 , the embodiment forms a first mask M1 on the first metal layer 120-1. The first mask M1 may be disposed on the active region AR and the dummy region DR. At this time, the first mask M1 may be disposed on the active region AR and may include an opening region OR1 that opens a region where the first circuit layer 120 is to be formed.

[0298] Next, refer to Fig.17, the embodiment forms the second metal layer 120 - 2 filling the opening region OR1 of the first mask M1 using the first metal layer 120 - 1 as a seed layer.

[0299] Next, refer to Fig.18 , embodiments may perform a process of removing the first mask M1.

[0300] Next, refer to Fig.19 , an embodiment may perform a process of forming a second mask M2. The second mask M2 may include an opening region OR2. The opening region OR2 of the second mask M2 may vertically overlap the first metal layer 120-1 and the second metal layer 120-2, and the first metal layer 120-1 and the second metal layer 120-2 may vertically overlap the second region R2 of the active region AR. For example, the second mask M2 may cover the first metal layer 120-1 and the second metal layer 120-2 disposed in the first region R1 of the active region AR. In addition, the first metal layer 120-1 of the first region R1 covered by the second mask M2 and the first metal layer 120-1 of the dummy region DR may be used later as a seed layer for electroplating the pillar 190.

[0301] Next, refer to Fig. 20 , the embodiment may perform a process of removing the first metal layer 120-1 exposed by the opening region OR2 of the second mask M2 by etching. Specifically, the embodiment may remove the portion of the first metal layer 120-1 disposed in the second region R2 that does not vertically overlap with the second metal layer 120-2 by etching. In this way, the embodiment may form the second pad 122 of the first circuit layer 120 including the first metal layer 120-1 and the second metal layer 120-2 in the second region R2.

[0302] Next, refer to Fig.21 , the embodiment may perform a process of removing the second mask M2. In this way, the first metal layer 120-1 disposed in the first region R1 and the first metal layer 120-1 disposed in the dummy region DR may be opened.

[0303] Next, refer to Fig. 22 , the embodiment may perform a process of completely forming the resist layer 170R on the effective area AR and the dummy area DR. The resist layer 170R may refer to a layer before the first opening 171 and the second opening 172 are formed in the first protection layer 170 of the embodiment. The resist layer 170R may cover the first metal layer 120-1 and the second metal layer 120-2 in the first area R1. The resist layer 170R may cover the first insulating layer 111 and the second pad 122 in the second area R2. In addition, the resist layer 170R may cover the first metal layer 120-1 in the dummy area DR.

[0304] Next, refer to Fig.23 , the embodiment may perform a process of forming the first opening 171 that completely opens the first region R1 by exposing and developing the resist layer 170R. In addition, the embodiment may perform a process of forming the second opening 172 that partially opens the second pad 122 disposed in the second region R2. At this time, when forming the first opening 171, the resist layer 170R on the dummy region DR may also be completely removed. However, the embodiment is not limited thereto.

[0305] For example, to manufacture the circuit board of the fourth embodiment, a portion of the resist layer 170R disposed in the dummy region DR adjacent to the first region R1 (eg, the third region R3 of the circuit board of the fourth embodiment) may not be removed.

[0306] Next, refer to Fig.24 , the embodiment may proceed with the process of forming the third mask M3. The third mask M3 may be completely disposed on the dummy region DR and the active region AR, and may include an opening region OR3 vertically overlapping a portion of the upper surface of the second metal layer 120-2 located in the first region R1. The width of the opening region OR3 may be smaller than the width of the second metal layer 120-2 of the first region R1. Therefore, the third mask M3 may partially open the upper surface of the second metal layer 120-2 of the first region R1.

[0307] Next, refer to Fig.25 , the embodiment may continue the process of forming the pillar 190 on the second metal layer 120-2 of the first region R1 opened by the opening region OR3 of the third mask M3. At this time, the pillar 190 may be formed by electroplating the first metal layer 120-1 disposed in the first region R1 as a seed layer and the first metal layer 120-1 disposed in the dummy region DR.

[0308] Specifically, the first region R1 is arranged to surround the second region R2. In addition, the dummy region DR is arranged to surround the first region R1. In addition, the first metal layer 120-1 in the first region R1 and the first metal layer 120-1 in the dummy region DR are not removed but remain. Therefore, the first metal layer 120-1 of the dummy region DR, the first metal layer 120-1 of the first region R1, and the second metal layer 120-2 in the first region R1 are electrically connected to each other. Therefore, electrolytic plating can be performed on the second metal layer 120-2 to form a pillar 190 that fills the opening region OR3 of the third mask M3.

[0309] Next, refer to Fig.26, the embodiment may perform a process of removing the third mask M3. In this way, the first metal layer 120-1 in the first region R1 and the first metal layer 120-1 in the dummy region DR may be opened. At this time, if the resist layer 170R is not removed from the portion of the dummy region DR adjacent to the first region R1 (ie, the third region R3), the first metal layer 120-1 in the third region R3 cannot be opened.

[0310] Next, refer to Fig. 27 , embodiments may form the first pad 121 of the first circuit layer 120 by removing the first metal layer 120-1 opened in the first region R1 and the dummy region DR by etching. At this time, if the resist layer 170R remains in the third region R3, the first metal layer 120-1 disposed in the third region R3 may not be removed.

[0311] Next, refer to Fig.28 , embodiments may separate the active area AR from the dummy area DR by using a line between the dummy area DR and the first area R1 as a sawing line. In this way, the circuit board 100 may be manufactured.

[0312] At this time, if the first metal layer 120-1 and the resist layer 170R remain in the third region R3, the saw line may be between the dummy region DR and the third region R3. Therefore, as in the fourth embodiment, a dummy pattern 123 corresponding to the first metal layer 120-1 in the third region R3 and a dummy protective layer corresponding to the resist layer 170R on the dummy pattern 123 may be formed. At this time, in the final circuit board, a portion of the dummy region DR may be included in the effective region AR.

[0313] The features, structures and effects described in the above embodiments are included in at least one embodiment, but are not limited to one embodiment. In addition, those skilled in the art may combine or modify the features, structures and effects shown in each embodiment for use in other embodiments. Therefore, it is understood that the content related to such combination and such modification is included within the scope of the present invention.

[0314] Most of the embodiments have been described above. However, they are merely examples and do not limit the present invention. It will be appreciated by those skilled in the art that several modifications and applications not given above may be made without departing from the basic features of the embodiments. For example, each component specifically indicated in the embodiments may be changed. In addition, it should be understood that the differences associated with such modifications and such applications are included in the scope of the present invention as defined in the appended claims.

Claims

1. A circuit board, comprising: Insulation layer; a protective member disposed on the insulating layer; as well as a plurality of pillars, the plurality of pillars being disposed on the insulating layer along a periphery of the protection member, wherein the protection member comprises an upper surface, a lower surface, and a side surface disposed between the upper surface and the lower surface, wherein the lower surface of the protection member faces the upper surface of the insulating layer, wherein side surfaces of the plurality of pillars face the side surface of the protection member, and wherein the side surface of the protection member includes a protruding portion protruding between the plurality of pillars.

2. The circuit board according to claim 1 , wherein the side surface of the protection member includes a first side surface extending in a first direction, a second side surface extending in the first direction and spaced apart from the first side surface, a third side surface extending in a second direction perpendicular to the first direction, and a fourth side surface extending in the second direction and spaced apart from the third side surface, wherein the protruding surface of the protection member is provided on the first side surface and the third side surface.

3. The circuit board according to claim 2, wherein the third side surface includes a first surface, a second surface and a third surface, the first surface having a first separation distance from the plurality of columns along the first direction, the second surface having a second separation distance smaller than the first separation distance, and the third surface having a third separation distance greater than the first separation distance. 4 . The circuit board of claim 2 , wherein a separation distance between the fourth side surface and the plurality of pillars along the first direction is uniform. 5 . The circuit board according to claim 2 , wherein the second side surface of the protection member includes a recessed surface recessed toward the first side surface of the protection member.

6. The circuit board according to claim 1, wherein the protection member comprises a plurality of through holes, and The width of the plurality of through holes is smaller than the width of the pillar.

7. The circuit board according to claim 1, further comprising: an outer protection member disposed on the insulating layer and having a through hole, and The column and the protection member are disposed in the through hole of the outer protection member.

8. The circuit board according to claim 6, further comprising: A surface treatment layer is disposed on the post.

9. The circuit board according to claim 8, further comprising: a plurality of pads disposed between the insulating layer and the protective member, wherein the width of the plurality of through holes of the protection member is smaller than the width of the plurality of pads, and The width of the column is smaller than the width of the pad.

10. The circuit board according to claim 9, further comprising: a surface treatment layer disposed on each of the plurality of through holes of the protection member, and wherein the surface treatment layer provided on each of the plurality of through holes of the protection member and the surface treatment layer provided on the pillar are provided with the same material.

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