Conversion method and conversion device for tiled display and tiled display system

Abstract

The embodiment of the invention relates to a conversion method and device for tiled display and a tiled display system. The conversion method comprises the following steps: receiving a first signal sent by a time sequence control device; recovering a first clock from the first signal; performing protocol analysis on the first signal according to a protocol corresponding to the first signal to obtain a second signal; performing protocol conversion on the second signal according to a protocol corresponding to a splicing panel, and generating a third signal in combination with a second clock used by the splicing panel; and sending the third signal to a source electrode chip of the splicing panel. The first signal sent by the time sequence control device is analyzed and converted into the third signal corresponding to each splicing panel, so that when the number of the splicing panels is increased, the number of interfaces of the time sequence control device does not need to be increased, board-level wiring is simplified, and electromagnetic interference is reduced.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the technical field of display signal transmission, and in particular to a conversion method, a conversion device and a splicing display system for splicing display. Background Art

[0002] LED (Light Emitting Diode) display screens have been widely used in outdoor advertising, outdoor performances, indoor conference halls and other scenarios due to their advantages such as high brightness, good flexibility and strong scalability, and have become the development trend of the display industry in the 21st century.

[0003] The LED display screens currently on the market can be simply summarized into three presentation methods: the first is to use PCB as the substrate and solder the LED lights to the PCB. The second is to use glass as the substrate and solder the LED to the glass drive circuit. The third is to use silicon wafers as the substrate and bond or transfer the LED to a silicon-based drive board.

[0004] The existing solutions follow the AMOLED driving architecture, mostly using the TCON chip + Source chip approach. There is also a GIA circuit on the glass panel. The Display Area contains the driving circuit for each LED lamp, and multiple glass panels are spliced ​​together to form a large screen. Since the glass substrate can be photolithographically processed similarly to silicon-based wafers, TFT circuits can be implemented on the glass to control the LEDs. Since the GIA voltage is usually higher than the operating voltage of the TCON chip, a levelshift chip is used to convert the low-voltage TCON control signal to the control signal of the high-voltage GIA circuit.

[0005] A P2P interface is commonly used between TCON and SourceIC. This interface is a high-speed interface. The communication rate of a single P2P interface is mostly between 0.6 and 2 Gbps. It does not require a clock along the way. The clock is recovered through the data transmitted on the differential pair, which is the CDR structure. For different resolutions carried by a single sourceIC, the number of P2P interfaces used is also different (the larger the load, the greater the number). When the number of spliced ​​screens increases, the number of P2P interfaces increases linearly, which is a challenge for the TCON chip. If one TCON is split into multiple TCONs, the cost will increase.

[0006] Regarding the above technical solution, the inventors found that there are at least the following technical problems: when the number of spliced ​​screens increases, the number of TCON chip interfaces is too large, the board-level routing is complicated, and EMI and EMC problems are serious.

[0007] Therefore, it is necessary to improve one or more problems existing in the above-mentioned related technical solutions.

[0008] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0009] The purpose of the embodiments of the present disclosure is to provide a conversion method, a conversion device and a splicing display system for splicing display, thereby at least solving the problem of too many TCON chip interfaces when the number of spliced ​​screens increases.

[0010] The purpose of the present invention is achieved by the following technical solutions:

[0011] In a first aspect, the present invention provides a conversion method for splicing display, the conversion method comprising:

[0012] receiving a first signal sent by a timing control device;

[0013] recovering a first clock from the first signal;

[0014] Performing protocol analysis on the first signal according to the protocol corresponding to the first signal to obtain a second signal;

[0015] Performing protocol conversion on the second signal according to the protocol corresponding to the splicing panel, and generating a third signal in combination with the second clock used by the splicing panel;

[0016] The third signal is sent to the source chip of the splicing panel.

[0017] Optionally, the step of receiving a first signal sent by the timing control device further includes:

[0018] The first signal includes information of a third signal of a plurality of splicing panels.

[0019] Optionally, the step of performing protocol conversion on the second signal according to the protocol corresponding to the splicing panel and generating the third signal in combination with the second clock used by the splicing panel further includes:

[0020] Performing protocol conversion on the second signal according to the protocol corresponding to the splicing panel to convert it into a fourth signal; wherein the fourth signal contains information of a plurality of the third signals;

[0021] Splitting the fourth signal into a plurality of third signals; wherein each of the third signals corresponds to a different splicing panel;

[0022] The third signal is sent to the source chip of the corresponding splicing panel.

[0023] Optionally, the step of performing protocol parsing on the first signal according to a protocol corresponding to the first signal to extract the second signal further includes:

[0024] The second signal is cached, and the cached second signal is converted into a protocol according to a protocol corresponding to the splicing panel, and a third signal is generated in combination with a second clock used by the splicing panel.

[0025] In a second aspect, the present invention provides a conversion device for splicing display, the conversion device comprising:

[0026] A receiving module, the receiving module is used to receive a first signal sent by the timing control device, the receiving module is provided with a clock recovery unit, the clock recovery unit is used to recover a first clock from the first signal;

[0027] A protocol analysis module, the protocol analysis module is used to perform protocol analysis on the first signal according to the protocol corresponding to the first signal to extract a second signal;

[0028] A protocol conversion module, the protocol conversion module is used to perform protocol conversion on the second signal according to the protocol corresponding to the splicing panel, and generate a third signal in combination with the second clock used by the splicing panel;

[0029] A sending module, wherein the sending module is used to send the third signal to the source chip of the splicing panel.

[0030] Optionally, it also includes: a protocol splitting module, which is arranged between the protocol conversion module and the sending module, and is used to split the fourth signal into multiple third signals, wherein each of the third signals corresponds to a different splicing panel, and the fourth signal contains information of the multiple third signals, and the second signal is converted into the fourth signal according to the protocol corresponding to the splicing panel.

[0031] Optionally, the sending module is provided with multiple sending units, and each sending unit corresponds to a source chip of a different splicing panel.

[0032] Optionally, each sending unit is provided with a clock transmission unit, and the clock transmission unit is used to add the second clock of the corresponding splicing panel to the third signal of each channel.

[0033] Optionally, it further includes: a cache module, which is arranged between the protocol parsing module and the protocol conversion module, and is used to cache the second signal and send the cached second signal to the protocol conversion module.

[0034] In a third aspect, the present invention provides a splicing display system, comprising:

[0035] A timing control device, the timing control device is used to generate a first signal;

[0036] A plurality of splicing panels, each of which is provided with a source chip, and receives corresponding display information through the source chip;

[0037] A conversion device, the conversion device is arranged between the timing control device and a plurality of splicing panels;

[0038] Wherein, the conversion device adopts the conversion device for splicing display described in any of the above-mentioned embodiments.

[0039] The technical solution provided by the embodiments of the present disclosure may have the following beneficial effects:

[0040] In the embodiment of the present disclosure, by first parsing the first signal sent by the timing control device and converting it into a third signal corresponding to each splicing panel, the number of interfaces of the timing control device does not need to be increased when the number of splicing panels increases, thereby simplifying the board-level routing and reducing electromagnetic interference.

[0041] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0043] Figure 1 A schematic flow chart showing a conversion method for splicing display in an exemplary embodiment of the present disclosure;

[0044] Figure 2 A schematic diagram of a driving architecture of spliced ​​display in related technology is shown;

[0045] Figure 3 A schematic diagram of a driving architecture of a spliced ​​display in an exemplary embodiment of the present disclosure is shown;

[0046] Figure 4 A schematic diagram showing the internal structure of a PCIC chip of an exemplary embodiment of the present disclosure is shown;

[0047] Figure 5 A schematic diagram showing a process of using cache in an exemplary embodiment of the present disclosure;

[0048] Figure 6 A schematic diagram showing a flow chart of sending a plurality of third signals in an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0050] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the disclosure will be more comprehensive and complete and to fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0051] In addition, the accompanying drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0052] This example implementation first provides a conversion method for splicing display. Figure 1 As shown in , the following steps are included:

[0053] Step S101: receiving a first signal sent by a timing control device.

[0054] Step S102: Recover a first clock from the first signal.

[0055] Step S103: performing protocol analysis on the first signal according to the protocol corresponding to the first signal to obtain a second signal.

[0056] Step S104: performing protocol conversion on the second signal according to the protocol corresponding to the splicing panel, and generating a third signal in combination with the second clock used by the splicing panel.

[0057] Step S105: Send the third signal to the source chip of the splicing panel.

[0058] It should be understood that the timing control device can be a TCON, and the first signal sent by it can include a video signal and a timing signal, and can also include some communication protocol signals. The decoded second signal is obtained by encoding and decoding the first signal, parsing the communication protocol, parsing the command parameters, etc. Therefore, the second signal can also include a video signal and a communication protocol signal, but the second signal is the expression form after the first signal is parsed. The third signal is the expression form after the second signal is converted to a protocol. The third signal is used to send to the source chip (SourceIC), so the protocol form of the third signal is adapted to the transmission form of the SourceIC.

[0059] It should also be understood that the first clock is obtained from the first signal, that is, it is also sent by TCON to the conversion device (Protocol Conversion IC (PCIC)). Specifically, the first clock is recovered by the CDR circuit. The second clock is used to add the second signal during protocol conversion to generate the third signal, that is, the second clock is included in the third signal and sent to SourceIC together.

[0060] It is also necessary to understand that a plurality of spliced ​​panels form a complete display screen, and the spliced ​​panels may be light panels.

[0061] It is also necessary to understand that in the related art, LED display screens include three types:

[0062] The first method uses PCB as the substrate and solders the LED lights to the PCB. This is the most common method in the field of large-screen commercial displays, where the majority of screens have LED dot pitches > 1mm. It features mature technology, low design costs, and solutions for large display screens in shopping malls, outdoors, concerts, and other places. Most of its driving methods and principles are PM driving methods, which rely on scanning to achieve display (not all images can be displayed at the same time), have high power consumption, and simple control principles.

[0063] The second method uses glass as a substrate and welds the LED to the driving circuit of the glass. It is most common in the field of small and medium-sized screen consumption. The screens with LED dot pitch > 0.1mm account for the majority, and are commonly used in mobile phones, televisions, computer monitors and other fields. In the past, the most common were glass-based OLED or LCD displays, and miniLEDs used as backlights (only white LEDs are used as background light, commonly known as backlights). Due to the advantages of LEDs such as long life, high brightness, and fast response, more and more businesses are now flocking to glass-based LED displays (RGB LEDs directly display images, commonly known as direct displays). This solution mostly uses the driving method of OLED (AM drive), with complex control principles, low power consumption, and good display effects (all images can be displayed at the same time).

[0064] The third method uses silicon wafers as substrates to bond or transfer LEDs to silicon-based driver boards. This is most common in the micro-display field, where screens with LED dot pitch <0.1mm account for the majority. This field is relatively cutting-edge and is characterized by being lightweight and compact, making it suitable for head-mounted displays and other scenarios. AM drive is also a common driving method.

[0065] It is also important to understand that the significant difference between passive drive (PM, Passive Matrix) and active drive (AM, Active Matrix) is whether each LED has an independent and controllable drive circuit. In PM drive, all LED lights share a set of drive circuits and use time-sharing multiplexing, so it is impossible to display all images at the same time. In AM drive, each LED has its own independent drive circuit, so the images can be displayed simultaneously without time-sharing multiplexing. In general, the display architectures of PM and AM are very different, and the problems introduced are also different.

[0066] Glass-based AM-driven LED display. Compared with the first method (PCB substrate), the initial investment of glass substrate is higher, but with the increase in sales, the average cost is lower than that of PCB substrate. In terms of performance, PCB substrate is prone to warping and deformation in large-scale applications due to its own heat dissipation limitations, while glass substrate has high thermal conductivity, strong heat dissipation, low thermal expansion rate, high flatness, and lower difficulty in LED transfer than PCB, which can achieve high-density LED welding.

[0067] It is also important to understand that reference Figure 2 As shown, Figure 2 This is a driver architecture that uses TCON chip + Source chip in related technologies. There are other architecture solutions, such as integrating TCON chip and Source chip into a DDIC, but the principles are similar. When the number of spliced ​​screens increases, the number of TCON chip interfaces is too large, the board-level routing is complicated, and EMI and EMC problems are serious.

[0068] It is also important to understand that reference Figure 3 As shown in the figure, a PCIC is added between TCON and SourceIC to perform protocol conversion and rate conversion. Figure 4 As shown, Figure 4 The specific internal structure of the PCIC chip. The conversion chip supports P2P related protocols.

[0069] It is also necessary to understand that when the number of spliced ​​screens increases, the number of TCON chip interfaces is reduced, the number of board-level traces is reduced, and EMI and EMC are reduced. The interface protocol is decoupled from the TCON chip, and the same TCON can be used for P2P interfaces of different protocols (P2P interfaces include iSP protocol, PHI protocol, CMPI protocol, etc.).

[0070] According to the above-mentioned conversion method for spliced ​​display, by first parsing the first signal sent by the timing control device and converting it into a third signal corresponding to each spliced ​​panel, when the number of spliced ​​panels increases, the number of interfaces of the timing control device does not need to be increased, thereby simplifying the board-level routing and reducing electromagnetic interference.

[0071] Next, we will refer to Figure 1 7 to 7, the various steps of the above-mentioned conversion method for splicing display in this example implementation are described in more detail.

[0072] refer to Figure 4 As shown, the first signal in step S101 specifically includes: the first signal includes information of the third signal of multiple splicing panels. It should be understood that TCON transmits the first signal to PCIC, which can then be converted into the third signal of multiple SourceICs through PCIC. That is, TCON drives multiple SourceICs by transmitting the first signal.

[0073] refer to Figure 5 As shown, step S103 also includes:

[0074] Step S501: caching the second signal, performing protocol conversion on the cached second signal according to the protocol corresponding to the splicing panel, and generating a third signal in combination with the second clock used by the splicing panel.

[0075] It is important to understand that reference Figure 4 As shown, the protocol parsing module temporarily stores the data received by RX_PHY in SRAM or FIFO. The protocol conversion module reads the data from SRAM, performs protocol encapsulation, and transmits it to the protocol splitting module.

[0076] refer to Figure 6 As shown, step S104 also includes:

[0077] Step S601: Perform protocol conversion on the second signal according to the protocol corresponding to the splicing panel to convert it into a fourth signal.

[0078] Step S602: split the fourth signal into multiple third signals; wherein each third signal corresponds to a different splicing panel.

[0079] Step S603: Send the third signal to the source chip of the corresponding splicing panel.

[0080] It should be understood that the fourth signal includes information of multiple third signals. Figure 4As shown, the protocol conversion module reads data from SRAM, performs protocol encapsulation, and transmits it to the protocol splitting module. The protocol splitting module splits it into various links according to certain rules, transmits it to TX_PHY through the data transmission link, and then transmits it to the subsequent sourceIC.

[0081] Furthermore, in this exemplary embodiment, a conversion device for splicing display is also provided. Figure 4 As shown, the conversion device includes:

[0082] A receiving module, the receiving module is used to receive a first signal sent by the timing control device, the receiving module is provided with a clock recovery unit, and the clock recovery unit is used to recover a first clock from the first signal;

[0083] A protocol analysis module, the protocol analysis module is used to perform protocol analysis on the first signal according to the protocol corresponding to the first signal to extract the second signal;

[0084] A protocol conversion module, the protocol conversion module is used to perform protocol conversion on the second signal according to the protocol corresponding to the splicing panel, and generate a third signal in combination with the second clock used by the splicing panel;

[0085] The sending module is used to send the third signal to the source chip of the splicing panel.

[0086] It should be understood that the high-speed signal of TCON, such as a line rate of 20Gbps, is sent to the RX_PHY of the PCIC chip, and the clock is recovered through the internal CDR circuit to the protocol parsing module. The protocol parsing module may include some functions such as encoding and decoding, communication protocol parsing, and command parameter parsing. The protocol parsing module temporarily stores the data received by RX_PHY in SRAM or FIFO. The protocol conversion module reads the data from SRAM, performs protocol encapsulation, and transmits it to the protocol splitting module. The protocol splitting module splits it into various links according to certain rules, transmits it to TX_PHY through the data transmission link, and then transmits it to the subsequent sourceIC. PLL is used to provide the system with a clock, the clock used for TX transmission.

[0087] It should also be understood that the RX_PHY and protocol parsing modules can be fixed to one protocol and are not limited to the protocol implemented by SourceIC.

[0088] Next, various parts of the above-mentioned conversion device for splicing display in this exemplary embodiment are described in more detail.

[0089] refer to Figure 4As shown, the conversion device also includes: a protocol splitting module, which is arranged between the protocol conversion module and the sending module, and is used to split the fourth signal into multiple third signals, wherein each third signal corresponds to a different splicing panel, and the fourth signal contains information of multiple third signals, and performs protocol conversion on the second signal according to the protocol corresponding to the splicing panel, and converts it into the fourth signal. It should be understood that, specifically, the protocol splitting module is split into each link according to a certain rule, transmitted to TX_PHY through the data transmission link, and then transmitted to the subsequent sourceIC.

[0090] refer to Figure 4 As shown, the sending module is provided with multiple sending units, and each sending unit corresponds to a different source chip of the splicing panel. It should be understood that TCON transmits a first signal to PCIC, which can then be converted into a third signal of multiple SourceICs through PCIC. Therefore, the protocol splitting module is split into various links according to certain rules, and each data transmission link corresponds to a sourceIC.

[0091] refer to Figure 4 As shown, each transmission unit is provided with a clock transmission unit, and the clock transmission unit is used to add the second clock of the corresponding splicing panel to the third signal of each channel. It should be understood that the clock transmission unit is TX_PHY. It is transmitted to TX_PHY through the data transmission link, and then transmitted to the subsequent sourceIC. The clock transmission unit is mainly used to transmit the clock to be used by the subsequent sourceIC.

[0092] refer to Figure 4 As shown, the conversion device also includes: a cache module, which is arranged between the protocol analysis module and the protocol conversion module, and is used to cache the second signal and send the cached second signal to the protocol conversion module. It should be understood that the cache module can be an SRAM or a FIFO. Specifically, the protocol analysis module temporarily stores the data received by RX_PHY in the SRAM or the FIFO. The protocol conversion module reads the data from the SRAM, performs protocol encapsulation, and transmits it to the protocol splitting module.

[0093] Furthermore, in this exemplary embodiment, a splicing display system is also provided, including:

[0094] A timing control device, the timing control device is used to generate a first signal;

[0095] A plurality of splicing panels, each of which is provided with a source chip, and receives corresponding display information through the source chip;

[0096] A conversion device, which is arranged between the timing control device and the plurality of splicing panels;

[0097] The conversion device adopts the conversion device for splicing display in any one of the above-mentioned implementation modes.

[0098] The specific method of the splicing display system has been described in detail in the embodiment of the conversion device for splicing display, and will not be elaborated here.

[0099] It should be noted that although several modules or units of the device for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to the embodiment of the present disclosure, the features and functions of two or more modules or units described above can be concretized in one module or unit. Conversely, the features and functions of a module or unit described above can be further divided into multiple modules or units for concretization. The components displayed as modules or units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the disclosed scheme. Those of ordinary skill in the art can understand and implement it without paying creative work.

[0100] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A conversion method for splicing display, characterized in that: The conversion method comprises: receiving a first signal sent by a timing control device; recovering a first clock from the first signal; Performing protocol analysis on the first signal according to the protocol corresponding to the first signal to obtain a second signal; Performing protocol conversion on the second signal according to the protocol corresponding to the splicing panel, and generating a third signal in combination with the second clock used by the splicing panel; The third signal is sent to the source chip of the splicing panel.

2. The conversion method according to claim 1, characterized in that: The step of receiving the first signal sent by the timing control device further includes: The first signal includes information of a third signal of a plurality of splicing panels.

3. The conversion method according to claim 2, characterized in that: The step of performing protocol conversion on the second signal according to the protocol corresponding to the splicing panel and generating the third signal in combination with the second clock used by the splicing panel further includes: Performing protocol conversion on the second signal according to the protocol corresponding to the splicing panel to convert it into a fourth signal; wherein the fourth signal contains information of a plurality of the third signals; Splitting the fourth signal into a plurality of third signals; wherein each of the third signals corresponds to a different splicing panel; The third signal is sent to the source chip of the corresponding splicing panel.

4. The conversion method according to any one of claims 1 to 3, characterized in that: The step of performing protocol parsing on the first signal according to the protocol corresponding to the first signal to extract the second signal further includes: The second signal is cached, and the cached second signal is converted into a protocol according to a protocol corresponding to the splicing panel, and a third signal is generated in combination with a second clock used by the splicing panel.

5. A conversion device for splicing display, characterized in that: The conversion device comprises: A receiving module, the receiving module is used to receive a first signal sent by the timing control device, the receiving module is provided with a clock recovery unit, the clock recovery unit is used to recover a first clock from the first signal; A protocol analysis module, the protocol analysis module is used to perform protocol analysis on the first signal according to the protocol corresponding to the first signal to extract a second signal; A protocol conversion module, the protocol conversion module is used to perform protocol conversion on the second signal according to the protocol corresponding to the splicing panel, and generate a third signal in combination with the second clock used by the splicing panel; A sending module, wherein the sending module is used to send the third signal to the source chip of the splicing panel.

6. The conversion device according to claim 5, characterized in that: Also includes: A protocol splitting module, which is arranged between the protocol conversion module and the sending module, is used to split the fourth signal into multiple third signals, wherein each of the third signals corresponds to a different splicing panel, and the fourth signal contains information of the multiple third signals. The second signal is subjected to protocol conversion according to the protocol corresponding to the splicing panel and converted into the fourth signal.

7. The conversion device according to claim 6, characterized in that: The sending module is provided with multiple sending units, and each sending unit corresponds to a source chip of a different splicing panel.

8. The conversion device according to claim 7, characterized in that: Each sending unit is provided with a clock transmission unit, and the clock transmission unit is used to add the second clock of the corresponding splicing panel to the third signal of each channel.

9. The conversion device according to any one of claims 5 to 7, characterized in that: Also includes: A cache module, which is arranged between the protocol parsing module and the protocol conversion module, and is used for caching the second signal and sending the cached second signal to the protocol conversion module.

10. A splicing display system, characterized in that: include: A timing control device, the timing control device is used to generate a first signal; A plurality of splicing panels, each of which is provided with a source chip, and receives corresponding display information through the source chip; A conversion device, the conversion device is arranged between the timing control device and a plurality of splicing panels; Wherein, the conversion device adopts the conversion device for splicing display described in any one of claims 5-9.

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