Pipeline phase ambiguity resolution method applied to FPGA (Field Programmable Gate Array)

Abstract

The invention belongs to the technical field of digital signal processing, particularly relates to a pipeline phase ambiguity resolution method applied to an FPGA (Field Programmable Gate Array), and aims to improve the accuracy and real-time performance of digital signal processing. The method is realized based on a three-section state machine, the state machine is started by setting an initial defuzzification coefficient and inputting a phase to be defuzzified, and input phase data is efficiently processed through state transition and condition judgment of the state machine. Test results show that the method can output the unambiguous phase within a certain clock period, realizes pipeline ambiguity resolution of the input ambiguous phase, and has the advantages of improving operation efficiency and reducing resource occupation.

Description

Technical Field

[0001] The invention belongs to the technical field of digital signal processing, and in particular relates to a pipeline phase defuzzification method applied in FPGA. Background Art

[0002] With the continuous advancement of industrial technology and the increasing social needs, the application of field programmable gate arrays (FPGAs) in information communication, aerospace, industrial control, intelligent vehicles and other fields is becoming more and more in-depth. FPGA has become an important tool in the field of digital signal processing with its high flexibility, high parallelism and reconfigurability. When performing digital signal processing in FPGA, trigonometric functions are often required, especially phase calculations. However, many FPGA chips, such as Xilinx's V7 / K7 series, can directly perform trigonometric functions in the CORDIC IP core in the official development environment Vivado, but when performing these operations, there are specific requirements for the input phase, that is, the input phase must meet certain conditions to ensure the accuracy and efficiency of the operation.

[0003] Since the input phase data in practical applications is often diverse and does not necessarily meet the input requirements of the CORDIC IP core, it is necessary to defuzzify the input phase to ensure that it meets the operation conditions of the CORDIC IP core. The research on the pipeline phase defuzzification method is to efficiently implement this function in FPGA, thereby ensuring the accuracy and real-time performance of digital signal processing.

[0004] In the prior art, when using FPGA for digital signal processing and calling IP cores such as CORDIC for trigonometric function calculations, the main technical problem faced is the ambiguity of the input phase. Specifically:

[0005] The CORDIC IP core requires that the input phase must meet certain conditions (such as phase range, step, etc.), but the input phase data in actual applications does not directly meet these conditions, resulting in the inability to perform accurate trigonometric operations. If the input phase is not defuzzified and trigonometric operations are performed directly, the operation results will be inaccurate or even cause errors. This requires additional judgment and processing logic to be added during the design, which reduces the operation efficiency.

[0006] Traditional defuzzification methods require a lot of logic resources and computing time, which is a huge challenge for FPGAs with limited resources. How to design a pipeline phase defuzzification method for FPGAs while ensuring the defuzzification effect, reducing resource usage and increasing processing speed has become an urgent problem to be solved. Summary of the invention

[0007] In view of this, the present invention proposes a pipeline phase defuzzification method applied in FPGA. The technical solution of the present invention is:

[0008] A pipeline phase defuzzification method applied in FPGA, comprising:

[0009] Step 1: Set the defuzzification coefficient n 1 With n 2 , the defuzzification coefficient n 1 With n 2 Initialization is set to 0;

[0010] Step 2: Input the phase to be resolved and render judgment;

[0011] Step 2.1: If the input phase Satisfy the conditions(1)

[0012]

[0013] Then jump to step 3;

[0014] Step 2.2: If the input phase does not meet condition (1), jump to step 4;

[0015] Step 3: Adjust the input phase to render judgment;

[0016] Step 3.1: If the input phase Satisfy the conditions (2)

[0017]

[0018] The output has no ambiguity phase

[0019] Step 3.2: If the input phase does not meet condition (2), jump to step 5;

[0020] Step 4: Phase the input to render judgment;

[0021] Step 4.1: If the input phase Satisfy the conditions (3)

[0022]

[0023] Then let the defuzzification coefficient n 2 =n 2 +1, let the phase addition and subtraction factor sub=1, and get the defuzzified intermediate value Jump to step 2;

[0024] Step 4.2: If the input phase If condition (3) is not satisfied, then let the defuzzification coefficient n 1 =n 1 +1, set the phase addition and subtraction factor sub=0, and get the defuzzified intermediate value Jump to step 2;

[0025] Step 5: Perform phase addition and subtraction decision on the phase addition and subtraction factor sub;

[0026] Step 5.1: If the phase addition and subtraction factors satisfy condition (4)

[0027] sub=1 (4)

[0028] The output has no ambiguity phase

[0029] Step 5.2: If the phase addition and subtraction factors do not satisfy condition (4), then the unambiguous phase is output

[0030] Furthermore, the method is implemented based on a three-stage state machine, wherein the state machine includes the following states:

[0031] Idle state: waiting for the start signal, and jumping to the decision state after receiving the start signal;

[0032] decide state: wait for phase addition / subtraction state, make addition / subtraction decisions, and update the phase addition / subtraction coefficient n;

[0033] ditto Same as above: Defuzzification is performed according to the defuzzification process of the previous phase;

[0034] add phase addition state: perform phase addition n*2π operation;

[0035] add_w phase plus waiting state: output phase plus the result of n*2π;

[0036] sub phase subtraction state: perform phase subtraction n*2π operation;

[0037] sub_w phase subtraction waiting state: output phase subtraction result of n*2π;

[0038] default state: jump to the decision state under certain conditions;

[0039] The state transition conditions of the state machine include:

[0040] start_i defuzzification start signal: when start_i is equal to 1, it jumps from the idle state to the decision state;

[0041] Delay wait signal: after the phase addition / subtraction operation is completed, the delay is greater than or equal to 3 clock cycles, and jumps to the corresponding output state add_w or sub_w;

[0042] phi defuzzified phase intermediate value: according to the phase intermediate value, it is decided to jump to the phase addition state add, the phase subtraction state sub or the same state ditto;

[0043] Phase addition / subtraction valid signal: When the valid signal is 1, jump from the phase addition state add or the phase subtraction state sub to the corresponding output state add_w or sub_w; otherwise, keep the current state unchanged.

[0044] The beneficial effects achieved by the present invention are:

[0045] First, the present invention realizes stream defuzzification, that is, it can prepare for the next input phase while processing the current input phase, significantly improving the operation efficiency and reducing the delay. In the defuzzification process, the present invention dynamically adjusts the defuzzification coefficients n1, n2 and the phase addition and subtraction factors according to the value of the input phase and the intermediate results in the defuzzification process; this dynamic adjustment ensures the flexibility and accuracy of the defuzzification process.

[0046] Second, the present invention adopts a three-stage state machine to implement pipeline phase defuzzification. The state machine includes multiple states, which makes the state transfer logic clearer and easier to manage. The present invention determines the defuzzification strategy of the input phase through multiple conditional judgments condition (2), condition (3), condition (4) and condition (5). These conditional judgments are based on the value of the input phase and the intermediate results in the defuzzification process to ensure the accuracy and efficiency of the phase defuzzification. The three-stage state machine is used to implement pipeline defuzzification, and the input phase data is efficiently processed through the state transfer and conditional judgment of the state machine. The unambiguous phase is output after a certain delay to ensure the accuracy of the operation. Compared with traditional defuzzification methods, the present invention has obvious advantages in resource occupancy. By optimizing the design of the state machine and the state transfer logic, the occupancy of FPGA resources is reduced, which is of great value to FPGA chips with limited resources.

[0047] Third, the present invention effectively solves the input phase ambiguity problem encountered when calling IP cores such as CORDIC to perform trigonometric functions by introducing a pipeline phase deambiguation method, ensuring that the input phase meets the operation requirements of the CORDIC IP core to avoid operation errors or inaccuracies.

[0048] Fourth, the present invention adopts a modular design, which is easy to integrate with other functional modules and is suitable for the case where the input phase to be defuzzified is an increasing or decreasing series, thereby improving the accuracy and real-time performance of digital signal processing, improving computational efficiency, reducing resource usage, and improving the flexibility and scalability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 Flow chart of the pipeline phase defuzzification method based on a three-stage state machine.

[0050] Figure 2 State transition diagram for pipeline phase defuzzification.

[0051] Figure 3 Screenshot of the water flow phase defuzzification test results. DETAILED DESCRIPTION

[0052] The technical solution of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the present invention. In addition, the forms of the various structures recorded in the following embodiments are merely illustrative, and the present invention is not limited to the various structures recorded in the following embodiments. All other embodiments obtained by ordinary technicians in this field without making creative work belong to the scope of protection of the present invention.

[0053] Reference Figure 1-Figure 3 The present invention uses a three-stage state machine to implement the stream phase defuzzification of the input phase. The flow chart of the stream phase defuzzification method based on the three-stage state machine is as follows: Figure 1 The state transition diagram of the state machine is shown in Figure 2 The definitions of different states of the state machine and the operations performed in different states are shown in Table 1. The definitions of the transition conditions of each state of the state machine are shown in Table 2.

[0054] The present invention is applicable to the input phase to be resolved as an increasing or decreasing series, and the step does not exceed π; the input starting phase needs to satisfy It can meet most of the scenarios in actual digital signal processing applications.

[0055] The present invention utilizes Figure 2 The three-stage state machine shown can output an unambiguous phase after a certain delay clock cycle when the input phase is any value within a certain range, thereby realizing stream defuzzification in FPGA software logic.

[0056] Table 1 Definition of each state of the state machine

[0057]

[0058]

[0059] Table 2 Definition of state transition conditions of state machine

[0060]

[0061] The technical solution of the present invention is a pipeline phase defuzzification method applied in FPGA, which comprises:

[0062] Step 1: Set the defuzzification coefficient n 1 With n 2 , the defuzzification coefficient n 1 With n 2 Initialization is set to 0;

[0063] Step 2: Input the phase to be resolved and render judgment;

[0064] Step 2.1: If the input phase Satisfy the conditions(1)

[0065]

[0066] Then jump to step 3;

[0067] Step 2.2: If the input phase does not meet condition (1), jump to step 4;

[0068] Step 3: Adjust the input phase to render judgment;

[0069] Step 3.1: If the input phase Satisfy the conditions (2)

[0070]

[0071] The output has no ambiguity phase

[0072] Step 3.2: If the input phase does not meet condition (2), jump to step 5;

[0073] Step 4: Phase the input to render judgment;

[0074] Step 4.1: If the input phase Satisfy the conditions (3)

[0075]

[0076] Then let the defuzzification coefficient n 2 =n 2 +1, let the phase addition and subtraction factor sub=1, and get the defuzzified intermediate value Jump to step 2;

[0077] Step 4.2: If the input phase If condition (3) is not satisfied, then let the defuzzification coefficient n 1 =n 1 +1, set the phase addition and subtraction factor sub=0, and get the defuzzified intermediate value Jump to step 2;

[0078] Step 5: Perform phase addition and subtraction decision on the phase addition and subtraction factor sub;

[0079] Step 5.1: If the phase addition and subtraction factors satisfy condition (4)

[0080] sub=1 (4)

[0081] The output has no ambiguity phase

[0082] Step 5.2: If the phase addition and subtraction factors do not satisfy condition (4), then the unambiguous phase is output

[0083] The method of the present invention is implemented based on a three-stage state machine, wherein the state machine includes the following states:

[0084] Idle state: waiting for the start signal, and jumping to the decision state after receiving the start signal;

[0085] decide state: wait for phase addition / subtraction state, make addition / subtraction decisions, and update the phase addition / subtraction coefficient n;

[0086] ditto Same as above: Defuzzification is performed according to the defuzzification process of the previous phase;

[0087] add phase addition state: perform phase addition n*2π operation;

[0088] add_w phase plus waiting state: output phase plus the result of n*2π;

[0089] sub phase subtraction state: perform phase subtraction n*2π operation;

[0090] sub_w phase subtraction waiting state: output phase subtraction result of n*2π;

[0091] default state: jump to the decision state under certain conditions;

[0092] The state transition conditions of the state machine include:

[0093] start_i defuzzification start signal: when start_i is equal to 1, it jumps from the idle state to the decision state;

[0094] Delay wait signal: after the phase addition / subtraction operation is completed, the delay is greater than or equal to 3 clock cycles, and jumps to the corresponding output state add_w or sub_w;

[0095] phi defuzzified phase intermediate value: according to the phase intermediate value, it is decided to jump to the phase addition state add, the phase subtraction state sub or the same state ditto;

[0096] Phase addition / subtraction valid signal: When the valid signal is 1, jump from the phase addition state add or the phase subtraction state sub to the corresponding output state add_w or sub_w; otherwise, keep the current state unchanged.

[0097] Embodiment 1: As shown in Table 3, the input phase of this embodiment is an increasing phase, the increment is π, and the initial input phase is 0.5π.

[0098] Table 3 Incremental phase deambiguation example

[0099]

[0100] According to the pipeline phase defuzzification method based on the three-stage state machine proposed in this patent, the steps for defuzzifying the input phase are as follows:

[0101] 1. Set the defuzzification coefficient n 1 With n 2 Initialized setting is 0.

[0102] 2. Input the first phase to be resolved 0.5π for judgment. 0.5π satisfies the following conditions:

[0103] -π+2n 1 π≤0.5π≤π+2n 2 π, that is, -π≤0.5π≤π, then proceed to the next step of judgment.

[0104] 3. The input phase 0.5π satisfies the condition -π≤0.5π≤π, then the output has no ambiguity phase Get the defuzzification coefficient n 1 With n 2 When it is 0, the delay is 4 clock cycles, and no phase addition or subtraction is performed.

[0105] 4. Input the second phase to be resolved 1.5π for judgment. 1.5π does not meet the condition -π+2n 1 π≤1.5π≤π+2n 2 π, that is, -π≤1.5π≤π, then jump to the next step.

[0106] 5. The input phase 1.5π satisfies the condition 1.5π>π+2n 2π, that is, 1.5π>π, then let the defuzzification coefficient n 2 =n 2 +1, that is, n 2 =1, let the phase addition and subtraction factor sub=1, and get the defuzzified intermediate value Right now Skip to the next step.

[0107] 6. Phase Satisfy the condition -π+2n 1 π≤-0.5π≤π+2n 2 π, that is, -π≤-0.5π≤3π, then proceed to the next step of judgment.

[0108] 7. Phase If the condition -π≤-0.5π≤π is met, the output is unambiguous phase Get the defuzzification coefficient n 1 =0, n 2 =1, delay 4 clock cycles, phase addition and subtraction factor sub=1.

[0109] 8. Input the third phase to be resolved 2.5π for judgment. 2.5π satisfies the condition -π+2n 1 π≤2.5π≤π+2n 2 π, that is, -π≤2.5π≤3π, then proceed to the next step of judgment.

[0110] 9. If the input phase 2.5π does not satisfy the condition -π≤-0.5π≤π, the next step of judgment is performed.

[0111] 10. Perform addition and subtraction judgment on the phase addition and subtraction factor sub. If the phase addition and subtraction factor satisfies the condition sub=1, then the unambiguous phase is output. Right now Get the defuzzification coefficient n 1 =0, n 2 =1, delay 4 clock cycles, phase addition and subtraction factor sub=1.

[0112] 11. Input the fourth phase to be resolved 3.5π for judgment. 3.5π does not meet the condition -π+2n 1 π≤3.5π≤π+2n 2 π, that is, -π≤3.5π≤3π, then jump to the next step.

[0113] 12. The input phase 3.5π satisfies the condition 3.5π>π+2n 2 π, that is, 3.5π>3π, then let the defuzzification coefficient n 2 =n 2 +1, that is, n 2=2, let the phase addition and subtraction factor sub=1, and get the defuzzified intermediate value Right now Skip to the next step.

[0114] 13. Phase Satisfy the conditions That is, -π≤-0.5π≤5π, then jump to the next step.

[0115] 14. Phase If the condition -π≤-0.5π≤π is met, the output is unambiguous phase Get the defuzzification coefficient n 1 =0, n 2 =2, delay of 4 clock cycles, phase addition and subtraction factor sub=1.

[0116] 15. Input the fifth phase to be resolved 4.5π for judgment. 4.5π satisfies the condition -π+2n 1 π≤4.5π≤π+2n 2 π, that is, -π≤4.5π≤5π, then jump to the next step.

[0117] 16. The phase 4.5π does not satisfy the condition -π≤4.5π≤π, so jump to the next step.

[0118] 17. If the phase addition and subtraction factor satisfies the condition sub=1, the output is unambiguous phase Right now Get the defuzzification coefficient n 1 =0, n 2 = 2, delay 4 clock cycles, phase addition and subtraction factor sub = 1. Then, the unambiguous phase after deambiguation by increasing the input phase can be obtained.

[0119] Embodiment 2: In this embodiment, as shown in Table 4, the input phase is a decreasing phase, the decreasing amplitude is π, and the initial input phase is -0.5π.

[0120] Similarly to Example 1, the input phase is defuzzified according to the pipeline phase defuzzification method based on the three-stage state machine proposed in this patent, and the unambiguous phase shown in Table 4 can be obtained.

[0121] When the input phase is -0.5π, the output phase is -0.5π, and the defuzzification coefficient n 1 is 0, the defuzzification coefficient n 2 is 0, the delay clock cycle is 4.

[0122] When the input phase is -1.5π, the output phase is 0.5π, and the defuzzification coefficient n 1 =1, the defuzzification coefficient n 2 is 0, the phase addition and subtraction factor is 0, and the delay clock cycle is 4.

[0123] When the input phase is -2.5π, the output phase is -0.5π, and the defuzzification coefficient n 1 =1, the defuzzification coefficient n 2 is 0, the phase addition and subtraction factor is 0, and the delay clock cycle is 4.

[0124] When the input phase is -3.5π, the output phase is 0.5π, and the defuzzification coefficient n 1 =2, the defuzzification coefficient n 2 is 0, the phase addition and subtraction factor is 0, and the delay clock cycle is 4.

[0125] When the input phase is -4.5π, the output phase is -0.5π, and the defuzzification coefficient n 1 =2, the defuzzification coefficient n 2 is 0, the phase addition and subtraction factor is 0, and the delay clock cycle is 4.

[0126] Table 4 Example of deambiguation of decreasing phase

[0127]

[0128] Example 3, experimental verification:

[0129] According to the method proposed in the present invention, an FPGA program is written to verify the effectiveness of the pipeline phase defuzzification method.

[0130] 1. Test conditions

[0131] Experimental platform: Vivado 2019.1;

[0132] Programming language: Verilog HDL;

[0133] Hardware platform: xc7v690tffg1927-2.

[0134] 2. Test results

[0135] The test results are shown in the screenshots Figure 3 In the figure, daijiemohu_data is the input phase to be resolved, jiemohu_data is the output data after resolution, and data_valid is the output data valid flag, which is high and effective.

[0136] The typical values ​​of the input phase to be resolved and the output phase after resolution of the test results are shown in Table 5 below.

[0137] Table 5 Flow phase defuzzification results

[0138]

[0139]

[0140] 3. Experimental conclusion

[0141] from Figure 3 As can be seen from the experimental results in Table 5, the pipeline phase defuzzification method applied to FPGA proposed in the invention can output an unambiguous phase within a certain clock cycle under the condition that the input phase is any value that satisfies the agreed conditions, thereby realizing the pipeline defuzzification of the input fuzzy phase.

[0142] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A pipeline phase defuzzification method applied in FPGA, characterized in that: It includes the following steps: Step 1: Set the defuzzification coefficients n1 and n2, and initialize the defuzzification coefficients n1 and n2 to 0; Step 2: Input the phase to be resolved and render judgment; Step 2.1: If the input phase Satisfy the conditions(1) Then jump to step 3; Step 2.2: If the input phase does not meet condition (1), jump to step 4; Step 3: Adjust the input phase to render judgment; Step 3.1: If the input phase Satisfy the conditions (2) The output has no ambiguity phase Step 3.2: If the input phase does not meet condition (2), jump to step 5; Step 4: Adjust the input phase to render judgment; Step 4.1: If the input phase Satisfy the conditions (3) Then let the defuzzification coefficient n2 = n2 + 1, let the phase addition and subtraction factor sub = 1, and get the defuzzification intermediate value Jump to step 2; Step 4.2: If the input phase If condition (3) is not satisfied, then let the defuzzification coefficient n1 = n1 + 1 and the phase addition and subtraction factor sub = 0 to obtain the defuzzification intermediate value Jump to step 2; Step 5: Perform phase addition and subtraction decision on the phase addition and subtraction factor sub; Step 5.1: If the phase addition and subtraction factors satisfy condition (4) sub=1 (4) The output has no ambiguity phase Step 5.2: If the phase addition and subtraction factors do not satisfy condition (4), then the unambiguous phase is output 2. The pipeline phase defuzzification method applied to FPGA according to claim 1, characterized in that: The method is implemented based on a three-stage state machine, where the state machine includes the following states: Idle state: waiting for the start signal, and jumping to the decision state after receiving the start signal; decide state: wait for phase addition / subtraction state, make addition / subtraction decisions, and update the phase addition / subtraction coefficient n; ditto Same as above: Defuzzification is performed according to the defuzzification process of the previous phase; add phase addition state: perform phase addition n*2π operation; add_w phase plus waiting state: output phase plus the result of n*2π; sub phase subtraction state: perform phase subtraction n*2π operation; sub_w phase subtraction waiting state: output phase subtraction result of n*2π; default state: jump to the decision state under certain conditions; The state transition conditions of the state machine include: start_i defuzzification start signal: when start_i is equal to 1, it jumps from the idle state to the decision state; Delay wait signal: after the phase addition / subtraction operation is completed, the delay is greater than or equal to 3 clock cycles, and jumps to the corresponding output state add_w or sub_w; phi defuzzified phase intermediate value: according to the phase intermediate value, it is decided to jump to the phase addition state add, the phase subtraction state sub or the same state ditto; Phase addition / subtraction valid signal: When the valid signal is 1, jump from the phase addition state add or the phase subtraction state sub to the corresponding output state add_w or sub_w; otherwise, keep the current state unchanged.

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