Data processing method, device and equipment and readable storage medium

Abstract

The invention discloses a data processing method, device and equipment and a readable storage medium, and the method comprises the steps: enabling instruction data type ranges, target operand ranges and source operand ranges corresponding to M business instructions to be mutually crossed and combined, and obtaining a first-dimensional orthogonal factor; obtaining service function types corresponding to the M service instructions respectively, determining instruction slot position ranges adapted to the M service function types, and performing mutual cross combination on the M instruction slot position ranges adapted to the M service function types to obtain a second-dimensional orthogonal factor; determining a register type called by the target instruction packet according to the second-dimensional orthogonal factor, and determining a third-dimensional orthogonal factor according to a port slot range mapped by the M service instructions under the register type; the first-dimensional orthogonal factor, the second-dimensional orthogonal factor and the third-dimensional orthogonal factor are jointly used for determining the functional coverage rate of the target instruction packet. By adopting the method, the efficiency of testing the function coverage rate can be improved, and the labor cost is reduced.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a data processing method, device, equipment and readable storage medium. Background Art

[0002] At present, the source code instructions of computer processors are becoming more and more numerous and complex. The source code instructions have evolved from the initial single-issue to concurrent, and from the initial microinstructions to the very long instruction word structure. They are highly coupled in hardware implementation, resulting in a sharp expansion in the packaging method of source code instructions, making the cross-combination of source code instruction verification infinite. Manually designing test cases to perform coverage testing will result in excessively high labor costs, while the method of randomly generating test cases will make it difficult to cover all functional points implemented by the source code instructions, resulting in low testing efficiency. Summary of the invention

[0003] The embodiments of the present application provide a data processing method, apparatus, device and readable storage medium, which can improve the efficiency of functional coverage testing and reduce labor costs.

[0004] On the one hand, an embodiment of the present application provides a data processing method, including:

[0005] Obtain a target instruction packet including M business instructions, wherein M is a positive integer, and the business instructions are source code instructions for a computer processor;

[0006] The instruction data type range, the destination operand range and the source operand range corresponding to the M business instructions are cross-combined to obtain a first-dimensional orthogonal factor; the first-dimensional orthogonal factor represents the instruction composition mode of the M business instructions in the target instruction packet;

[0007] Obtain the business function types corresponding to the M business instructions, determine the instruction slot ranges adapted by the M business function types, cross-combine the M instruction slot ranges adapted by the M business function types, and obtain the second-dimensional orthogonal factor; the second-dimensional orthogonal factor represents the packaging method of the business instructions adapted to the M instruction slot ranges;

[0008] The register type called by the target instruction packet is determined according to the second-dimensional orthogonal factor, and the third-dimensional orthogonal factor is determined according to the port slot range mapped by the M business instructions under the register type; the third-dimensional orthogonal factor represents the coupling relationship between the port slot ranges corresponding to the M business instructions respectively; the first-dimensional orthogonal factor, the second-dimensional orthogonal factor and the third-dimensional orthogonal factor are jointly used to determine the functional coverage of the target instruction packet.

[0009] Among them, the M business instructions include business instruction S i , i is a positive integer; the method further comprises:

[0010] The business instruction S i The type of instruction data type adapted is determined to be a business instruction S i The corresponding instruction data type range; the instruction data type includes the operand type of the destination operand and the operand type of the source operand;

[0011] Determine one or more register indexes covered by the destination operand as the service instruction S i The corresponding destination operand range;

[0012] Determine one or more register indexes covered by the source operand as the service instruction S i The corresponding source operand range.

[0013] Among them, the M business instructions include business instruction S i , i is a positive integer; determine the instruction slot range adapted by M business function types, including:

[0014] The business instruction S i One or more instruction slots adapted to the corresponding business function type are determined as business instructions S i The instruction slot range corresponding to the business function type; the instruction slot includes a scalar slot, a vector slot and a general slot, wherein the scalar slot, the vector slot and the general slot all have the function of being disassembled into multiple slots, the scalar slot adapter processes the business function type whose operand type is a scalar, and the vector slot adapter processes the business function type whose operand type is a vector.

[0015] The calling modes of the registers associated with the M business instructions include a non-port access mode, a single-port access mode, and a multi-port access mode. The third-dimensional orthogonal factor is determined according to the port slot range mapped by the M business instructions under the register type, including:

[0016] Among the M service instructions, one or more instruction slots adapted by the service instructions belonging to the portless access mode are determined as a first slot range;

[0017] Determine one or more instruction slots adapted by the service instructions belonging to the single port access as the second slot range;

[0018] Determine one or more instruction slots adapted by the service instructions belonging to the multi-port access as a third slot range;

[0019] The first slot range, the second slot range and the third slot range of the M business instructions are cross-combined to obtain a third-dimensional orthogonal factor; the third-dimensional orthogonal factor represents the port access relationship of the first slot range, the second slot range and the third slot range of the M business instructions.

[0020] Among them, it also includes:

[0021] Get Q instruction packets; Q is a positive integer, and Q instruction packets include a target instruction packet;

[0022] The first-dimensional orthogonal factors corresponding to the Q instruction packets are cross-combined to obtain the first-dimensional verification factor; the first-dimensional verification factor represents the instruction composition mode of the business instructions in the Q instruction packets;

[0023] The second-dimensional orthogonal factors corresponding to the Q instruction packets are cross-combined to obtain the second-dimensional verification factor; the second-dimensional verification factor represents the packaging method of the business instructions in the Q instruction packets;

[0024] The third-dimensional orthogonal factors corresponding to the Q instruction packets are cross-combined to obtain the third-dimensional verification factor; the third-dimensional verification factor represents the coupling relationship between the port slot ranges corresponding to the business instructions in the Q instruction packets;

[0025] The read pipeline position ranges corresponding to the Q instruction packets, the write pipeline position ranges corresponding to the Q instruction packets, the read pipeline position ranges corresponding to the Q instruction packets, and the write pipeline position ranges corresponding to the Q instruction packets are cross-combined to obtain a fourth-dimensional verification factor; the fourth-dimensional verification factor represents the read-write dependency relationship of the Q instruction packets, and the fourth-dimensional verification factor is used to determine the functional coverage of the Q instruction packets together with the first-dimensional verification factor, the second-dimensional verification factor, and the third-dimensional verification factor.

[0026] Among them, it also includes:

[0027] Based on the number of pipeline stages of the Q instruction packets, the pipeline position adapted by the read register instruction in each instruction packet is determined as Q read pipeline position ranges;

[0028] Determine the pipeline position adapted by the write register instruction in each instruction packet as Q write pipeline position ranges;

[0029] Determine the pipeline position adapted by the read register instruction in each instruction packet when obtaining the operand in the pipeline as Q read pipeline position ranges;

[0030] The pipeline position adapted by the write register instruction in each instruction packet when completing calculation in the pipeline is determined as Q write pipeline position ranges.

[0031] Among them, it also includes:

[0032] Obtaining a spatial coverage constraint range; the spatial coverage constraint range is set based on the functional points of the target instruction packet;

[0033] Generate an orthogonal cover group through the first dimension orthogonal factor, the second dimension orthogonal factor, the third dimension orthogonal factor and the spatial coverage constraint range, and perform coverage test on the target instruction package through the test cases in the orthogonal cover group;

[0034] If the functional coverage of the target instruction package does not meet the coverage completeness condition, the spatial coverage constraint range is adjusted until the functional coverage of the target instruction package meets the coverage completeness condition, and the coverage test of the target instruction package is completed. The functional coverage of the target instruction package is used to indicate the proportion of the function points of the instruction package that are executed during the coverage test process.

[0035] Among them, the first dimension orthogonal factor, the second dimension orthogonal factor and the third dimension orthogonal factor are used to generate and verify the orthogonal coverage group, test cases are randomly generated according to the spatial coverage constraint range, and the target instruction package is tested for coverage through the test cases, including:

[0036] Generate a first-dimensional orthogonal coverage group through the first-dimensional orthogonal factor and the spatial coverage constraint range, perform coverage test on the target instruction package through the test cases in the first-dimensional orthogonal coverage group to obtain the first-dimensional orthogonal coverage points, and determine the first-dimensional orthogonal coverage of the target instruction package through the first-dimensional orthogonal coverage points and the first-dimensional orthogonal coverage group;

[0037] Generate a second-dimensional orthogonal cover group through the second-dimensional orthogonal factor and the spatial coverage constraint range, perform coverage test on the instruction package through the test cases in the second-dimensional orthogonal cover group to obtain the second-dimensional orthogonal cover points, and determine the second-dimensional orthogonal coverage of the target instruction package through the second-dimensional orthogonal cover points and the second-dimensional orthogonal cover group;

[0038] A third-dimensional orthogonal coverage group is generated by using the third-dimensional orthogonal factor and the spatial coverage constraint range, and the coverage of the instruction package is tested by the test cases in the third-dimensional orthogonal coverage group to obtain the third-dimensional orthogonal coverage points. The third-dimensional orthogonal coverage of the target instruction package is determined by the third-dimensional orthogonal coverage points and the third-dimensional orthogonal coverage group; the first-dimensional orthogonal coverage, the second-dimensional orthogonal coverage and the third-dimensional orthogonal coverage are used together to determine the functional coverage of the target instruction package.

[0039] Among them, it also includes:

[0040] Obtaining a time coverage constraint range; the time coverage constraint range is set based on the function points of the Q instruction packets;

[0041] Generate a first-dimension verification coverage group through the first-dimension verification factor and the time coverage constraint range, perform coverage test on Q instruction packages through the test cases in the first-dimension verification coverage group, obtain first-dimension verification coverage points, and determine the first-dimension verification coverage of the Q instruction packages through the first-dimension verification coverage points and the first-dimension verification coverage group;

[0042] Generate a second-dimensional verification coverage group through the second-dimensional verification factor and the time coverage constraint range, perform coverage test on Q instruction packages through the test cases in the second-dimensional verification coverage group, obtain second-dimensional verification coverage points, and determine the second-dimensional verification coverage of the Q instruction packages through the second-dimensional verification coverage points and the second-dimensional verification coverage group;

[0043] Generate a third-dimensional verification coverage group through the third-dimensional verification factor and the time coverage constraint range, perform coverage test on Q instruction packages through the test cases in the third-dimensional verification coverage group, obtain the third-dimensional verification coverage points, and determine the third-dimensional verification coverage of the Q instruction packages through the third-dimensional verification coverage points and the third-dimensional verification coverage group;

[0044] Generate a fourth-dimensional verification coverage group through the fourth-dimensional verification factor and the time coverage constraint range, perform coverage test on Q instruction packages through the test cases in the fourth-dimensional verification coverage group, obtain fourth-dimensional verification coverage points, and determine the fourth-dimensional verification coverage of the Q instruction packages through the fourth-dimensional verification coverage points and the fourth-dimensional verification coverage group; the fourth-dimensional verification coverage is used to determine the functional coverage of the Q instruction packages together with the first-dimensional verification coverage, the second-dimensional verification coverage and the third-dimensional verification coverage; the functional coverage of the Q instruction packages is used to indicate the proportion of the functional points of the Q instruction packages that are executed during the coverage test process;

[0045] If the functional coverage of the Q instruction packages does not meet the coverage completeness condition, the time coverage constraint range is adjusted until the functional coverage of the Q instruction packages meets the coverage completeness condition, and the coverage test of the Q instruction packages is completed.

[0046] An embodiment of the present application provides a data processing device, including:

[0047] A first acquisition module is used to acquire a target instruction packet containing M business instructions; M is a positive integer, and the business instruction is a source code instruction for a computer processor;

[0048] The first-dimensional orthogonal module is used to cross-combine the instruction data type range, the destination operand range and the source operand range corresponding to the M business instructions to obtain a first-dimensional orthogonal factor; the first-dimensional orthogonal factor represents the instruction composition mode of the M business instructions in the target instruction packet;

[0049] The second-dimensional orthogonal module is used to obtain the business function types corresponding to the M business instructions, determine the instruction slot ranges adapted by the M business function types, cross-combine the M instruction slot ranges adapted by the M business function types, and obtain the second-dimensional orthogonal factor; the second-dimensional orthogonal factor represents the packaging method of the business instructions adapted to the M instruction slot ranges;

[0050] The third-dimensional orthogonal module is used to determine the register type called by the target instruction packet according to the second-dimensional orthogonal factor, and to determine the third-dimensional orthogonal factor according to the port slot range mapped by the M business instructions under the register type; the third-dimensional orthogonal factor represents the coupling relationship between the port slot ranges corresponding to the M business instructions respectively; the first-dimensional orthogonal factor, the second-dimensional orthogonal factor and the third-dimensional orthogonal factor are used together to determine the functional coverage of the target instruction packet.

[0051] Among them, the M business instructions include business instruction S i , i is a positive integer; the method further comprises:

[0052] The first dimension processing module is used to convert the business instruction S i The type of instruction data type adapted is determined to be a business instruction S i The corresponding instruction data type range; the instruction data type includes the operand type of the destination operand and the operand type of the source operand;

[0053] The first dimension processing module is also used to determine one or more register indexes covered by the destination operand as the service instruction S i The corresponding destination operand range;

[0054] The first dimension processing module is also used to determine one or more register indexes covered by the source operand as the business instruction S i The corresponding source operand range.

[0055] Among them, the M business instructions include business instruction S i , i is a positive integer; the second dimension orthogonal module is specifically used to convert the business instruction S i One or more instruction slots adapted to the corresponding business function type are determined as business instructions S i The instruction slot range corresponding to the business function type; the instruction slot includes a scalar slot, a vector slot and a general slot, wherein the scalar slot, the vector slot and the general slot all have the function of being disassembled into multiple slots, the scalar slot adapter processes the business function type whose operand type is a scalar, and the vector slot adapter processes the business function type whose operand type is a vector.

[0056] The calling modes of the registers associated with the M business instructions include a portless access mode, a single-port access mode, and a multi-port access mode. The third-dimensional orthogonal module includes:

[0057] A slot determination unit, configured to determine, among the M service instructions, one or more instruction slots adapted to the service instructions belonging to the portless access mode as a first slot range;

[0058] The slot determination unit is further used to determine one or more instruction slots adapted by the service instructions belonging to the single port access as the second slot range;

[0059] The slot determination unit is further used to determine one or more instruction slots adapted by the service instructions belonging to the multi-port access as a third slot range;

[0060] The slot combination unit is used to cross-combine the first slot range, the second slot range and the third slot range of the M business instructions to obtain a third-dimensional orthogonal factor; the third-dimensional orthogonal factor represents the port access relationship of the first slot range, the second slot range and the third slot range of the M business instructions.

[0061] Among them, it also includes:

[0062] The second acquisition module is used to acquire Q instruction packets, where Q is a positive integer, and the Q instruction packets include a target instruction packet;

[0063] The first dimension verification module is used to cross-combine the first dimension orthogonal factors corresponding to the Q instruction packets to obtain the first dimension verification factor; the first dimension verification factor represents the instruction composition mode of the business instructions in the Q instruction packets;

[0064] A second-dimensional verification module is used to cross-combine the second-dimensional orthogonal factors corresponding to the Q instruction packets to obtain a second-dimensional verification factor; the second-dimensional verification factor represents the packaging method of the business instructions in the Q instruction packets;

[0065] A third-dimensional verification module is used to cross-combine the third-dimensional orthogonal factors corresponding to the Q instruction packets to obtain a third-dimensional verification factor; the third-dimensional verification factor represents the coupling relationship between the port slot ranges corresponding to the business instructions in the Q instruction packets;

[0066] The fourth dimension verification module is used to cross-combine the read pipeline position ranges corresponding to the Q instruction packets, the write pipeline position ranges corresponding to the Q instruction packets, the read pipeline position ranges corresponding to the Q instruction packets, and the write pipeline position ranges corresponding to the Q instruction packets to obtain a fourth dimension verification factor; the fourth dimension verification factor represents the read and write dependency relationship of the Q instruction packets, and the fourth dimension verification factor is used to determine the functional coverage of the Q instruction packets together with the first dimension verification factor, the second dimension verification factor and the third dimension verification factor.

[0067] Among them, it also includes:

[0068] A pipeline processing module, for determining the pipeline position adapted by the read register instruction in each instruction packet as Q read pipeline position ranges based on the pipeline stages of the Q instruction packets;

[0069] The pipeline processing module is further used to determine the pipeline position adapted by the write register instruction in each instruction packet as Q write pipeline position ranges;

[0070] The pipeline processing module is used to determine the pipeline position adapted by the read register instruction in each instruction packet when obtaining the operand in the pipeline as Q read pipeline position ranges;

[0071] The pipeline processing module is also used to determine the pipeline position adapted by the write register instruction in each instruction packet when completing the calculation in the pipeline as Q write pipeline position ranges.

[0072] Among them, it also includes:

[0073] A space constraint acquisition module is used to acquire a space coverage constraint range; the space coverage constraint range is set based on the function points of the target instruction package;

[0074] A space constraint test module is used to generate an orthogonal cover group through a first-dimensional orthogonal factor, a second-dimensional orthogonal factor, a third-dimensional orthogonal factor and a space coverage constraint range, and to perform coverage test on a target instruction package through test cases in the orthogonal cover group;

[0075] The spatial constraint test module is also used to adjust the spatial coverage constraint range if the functional coverage of the target instruction package does not meet the coverage completeness condition, until the functional coverage of the target instruction package meets the coverage completeness condition, thereby completing the coverage test of the target instruction package. The functional coverage of the target instruction package is used to indicate the proportion of the functional points of the instruction package that are executed during the coverage test process.

[0076] Among them, the space constraint test module includes:

[0077] A first spatial test unit is used to generate a first-dimensional orthogonal coverage group through a first-dimensional orthogonal factor and a spatial coverage constraint range, perform coverage test on a target instruction package through test cases in the first-dimensional orthogonal coverage group to obtain first-dimensional orthogonal coverage points, and determine the first-dimensional orthogonal coverage of the target instruction package through the first-dimensional orthogonal coverage points and the first-dimensional orthogonal coverage group;

[0078] A second spatial test unit is used to generate a second dimensional orthogonal cover group through a second dimensional orthogonal factor and a spatial coverage constraint range, perform coverage test on the instruction package through the test cases in the second dimensional orthogonal cover group to obtain second dimensional orthogonal cover points, and determine the second dimensional orthogonal coverage of the target instruction package through the second dimensional orthogonal cover points and the second dimensional orthogonal cover group;

[0079] The third spatial test unit is used to generate a third-dimensional orthogonal coverage group through a third-dimensional orthogonal factor and a spatial coverage constraint range, perform coverage test on the instruction package through the test cases in the third-dimensional orthogonal coverage group, obtain third-dimensional orthogonal coverage points, and determine the third-dimensional orthogonal coverage of the target instruction package through the third-dimensional orthogonal coverage points and the third-dimensional orthogonal coverage group; the first-dimensional orthogonal coverage, the second-dimensional orthogonal coverage and the third-dimensional orthogonal coverage are jointly used to determine the functional coverage of the target instruction package.

[0080] Among them, it also includes:

[0081] A time constraint acquisition module is used to acquire a time coverage constraint range; the time coverage constraint range is set based on the function points of the Q instruction packets;

[0082] A first time test module is used to generate a first dimension verification coverage group through a first dimension verification factor and a time coverage constraint range, perform coverage test on Q instruction packages through test cases in the first dimension verification coverage group to obtain first dimension verification coverage points, and determine the first dimension verification coverage of the Q instruction packages through the first dimension verification coverage points and the first dimension verification coverage group;

[0083] A second time test module is used to generate a second dimension verification coverage group through the second dimension verification factor and the time coverage constraint range, perform coverage test on the Q instruction packages through the test cases in the second dimension verification coverage group to obtain the second dimension verification coverage points, and determine the second dimension verification coverage of the Q instruction packages through the second dimension verification coverage points and the second dimension verification coverage group;

[0084] A third time test module is used to generate a third-dimensional verification coverage group through a third-dimensional verification factor and a time coverage constraint range, perform coverage test on the Q instruction packages through the test cases in the third-dimensional verification coverage group, obtain third-dimensional verification coverage points, and determine the third-dimensional verification coverage of the Q instruction packages through the third-dimensional verification coverage points and the third-dimensional verification coverage group;

[0085] A fourth time test module is used to generate a fourth-dimensional verification coverage group through a fourth-dimensional verification factor and a time coverage constraint range, perform coverage test on Q instruction packages through test cases in the fourth-dimensional verification coverage group to obtain fourth-dimensional verification coverage points, and determine the fourth-dimensional verification coverage of the Q instruction packages through the fourth-dimensional verification coverage points and the fourth-dimensional verification coverage group; the fourth-dimensional verification coverage is used to determine the functional coverage of the Q instruction packages together with the first-dimensional verification coverage, the second-dimensional verification coverage and the third-dimensional verification coverage; the functional coverage of the Q instruction packages is used to indicate the proportion of the functional points of the Q instruction packages that are executed during the coverage test process;

[0086] The time constraint test module is used to adjust the time coverage constraint range if the functional coverage of the Q instruction packages does not meet the coverage completeness condition, until the functional coverage of the Q instruction packages meets the coverage completeness condition, thereby completing the coverage test of the Q instruction packages.

[0087] On the one hand, an embodiment of the present application provides a computer device, including: a processor, a memory, and a network interface;

[0088] The processor is connected to the memory and the network interface, wherein the network interface is used to provide a data communication function, and the memory is used to store a computer program. When the computer program is executed by the processor, the computer device executes the method provided in the embodiment of the present application.

[0089] On the one hand, an embodiment of the present application provides a computer-readable storage medium, which stores a computer program. The computer program is suitable for being loaded and executed by a processor so that a computer device having the processor executes the method provided by the embodiment of the present application.

[0090] In one aspect, an embodiment of the present application provides a computer program product, which includes a computer program stored in a computer-readable storage medium. A processor of a computer device reads the computer program from the computer-readable storage medium, and the processor executes the computer program, so that the computer device executes the method provided in the embodiment of the present application.

[0091] The embodiment of the present application obtains a target instruction packet containing M business instructions; M is a positive integer, and the business instruction is a source code instruction for a computer processor; the instruction data type range, the destination operand range and the source operand range corresponding to the M business instructions are cross-combined to obtain a first-dimensional orthogonal factor; the first-dimensional orthogonal factor represents the instruction composition method of the M business instructions in the target instruction packet; the business function types corresponding to the M business instructions are obtained, the instruction slot ranges adapted to the M business function types are determined, and the M instruction slot ranges adapted to the M business function types are cross-combined to obtain a second-dimensional orthogonal factor; the second-dimensional orthogonal factor represents the packaging method of the business instructions adapted to the M instruction slot ranges; the register type called by the target instruction packet is determined according to the second-dimensional orthogonal factor, and the third-dimensional orthogonal factor is determined according to the port slot range mapped by the M business instructions under the register type; the third-dimensional orthogonal factor represents the coupling relationship between the port slot ranges corresponding to the M business instructions; the first-dimensional orthogonal factor, the second-dimensional orthogonal factor and the third-dimensional orthogonal factor are used together to determine the functional coverage of the target instruction packet. It can be seen that the present application decomposes the business instructions in the instruction package into first-dimensional orthogonal factors, second-dimensional orthogonal factors and third-dimensional orthogonal factors, where the orthogonal factors are independent of each other, thereby avoiding the inability to determine the functional points required for testing due to the intersection of test requirements. Decomposing into orthogonal factors can isolate and separate highly complex and coupled problems, and can concretize the functional points (features) required for testing to be verified, thereby improving the efficiency and quality of functional coverage testing. At the same time, low-dimensional testing work belongs to highly efficient repetitive testing, which reduces the manpower cost of functional coverage testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0092] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0093] Figure 1 This is a data processing scenario provided by the embodiment of the present application. Figure 1 ;

[0094] Figure 2 This is a flow diagram of a data processing method provided in an embodiment of the present application. Figure 1 ;

[0095] Figure 3 This is a flow diagram of a data processing method provided in an embodiment of the present application. Figure 2 ;

[0096] Figure 4a This is a data processing scenario provided by the embodiment of the present application. Figure 2 ;

[0097] Figure 4b This is a data processing scenario provided by the embodiment of the present application. Figure 3 ;

[0098] Figure 5 This is a flow diagram of a data processing method provided in an embodiment of the present application. Figure 3 ;

[0099] Figure 6 is a structural schematic diagram of a data processing device provided in an embodiment of the present application;

[0100] Figure 7 It is a structural diagram of a computer device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0101] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0102] See also Figure 1 , Figure 1 This is a data processing scenario provided by the embodiment of the present application. Figure 1 ,exist Figure 1 In the process, the terminal device can obtain an instruction package consisting of several business instructions. The business instructions can be source code instructions of the computer processor, and the instruction package can be source code instructions that implement some or all functional points of the computer processor. Among them, the computer processor can be a chip for computer system operation, control, information processing, and program operation.

[0103] A business instruction may include a business function type, an instruction data type (data type, dtype), a destination operand (Register destination, Rd) and a source operand (Register source, Rs), which is not limited in the embodiments of the present application.

[0104] Take the example of a terminal device obtaining instruction package A consisting of business instruction 1, business instruction 2 and business instruction 3. Assuming that instruction package A can realize all functional points of computer processor A, business instruction 1, business instruction 2 and business instruction 3 can be shown in Table 1:

[0105] Table 1

[0106] Instruction Packet A Business function type Source operand range Destination operand range Business Instruction 1 ADD R5 R1 R2 Business Instruction 2 MUL R6 R5 R1 Business Instruction 3 DIV R7 R5 R6

[0107] Among them, the business function type of business instruction 1 is ADD, the source operand range 1 is R5, the source operand range 2 is R1, and the destination operand range is R2; the business function type of business instruction 2 is MUL, the source operand range 1 is R6, the source operand range 2 is R5, and the destination operand range is R1; the business function type of business instruction 3 is DIV, the source operand range 1 is R7, the source operand range 2 is R5, and the destination operand range is R6.

[0108] The source operand range and the destination operand range represent the register index covered by the service instruction. For example, the source operand range in service instruction 1 can be used to indicate that the index number of the general register storing the source operand R5 is 0 to 4. The destination operand range in service instruction 1 can be used to indicate that the index number of the general register storing the destination operand R2 is 5 to 9. The service data range of the service instruction is the type of instruction data type adapted by the service instruction. For example, the service data type of service instruction 1 can be a fixed-point integer and a fixed-point decimal.

[0109] The terminal device can perform first-dimensional verification, and can cross-combine the instruction data type range, destination operand range, and source operand range of the business instruction 1 to obtain several orthogonal factors 1 of the business instruction 1. The cross-combination method can be to arrange and combine the instruction data type range, destination operand range, and source operand range. For example, the instruction data type range of the business instruction 1 includes B1 and B2, the destination operand range includes C1 and C2, and the source operand range includes D1. Then, the four independent orthogonal factors 1 obtained by the cross-combination can include the orthogonal factor 1 of the combination of B1, C1 and D1, the orthogonal factor 1 of the combination of B1, C2 and D1, the orthogonal factor 1 of the combination of B2, C1 and D1, and the orthogonal factor 1 of the combination of B2, C2 and D1. Similarly, the instruction data type range, destination operand range and source operand range of business instruction 2 can be cross-combined to obtain several orthogonal factors 2 of business instruction 2, and the instruction data type range, destination operand range and source operand range of business instruction 3 can be cross-combined to obtain several orthogonal factors 3 of business instruction 3. Then, several orthogonal factors 1, several orthogonal factors 2 and several orthogonal factors 3 are cross-combined to obtain several first-dimensional orthogonal factors of instruction package A. The first-dimensional orthogonal factors can represent the composition of business instruction 1, business instruction 2 and business instruction 3 in instruction package A, that is, a first-dimensional orthogonal factor can represent a functional point in the composition of the business instructions in instruction package A.

[0110] The terminal device can perform second-dimensional verification, and can determine several instruction slots adapted by the business function type of the business instruction as the instruction slot range. The instruction slot range refers to several instruction slots adapted by the business instruction. For example, the instruction slot range 1 corresponding to the business instruction 1, the instruction slot range 2 corresponding to the business instruction 2, and the instruction slot range 3 corresponding to the business instruction 3 can be obtained. The terminal device can cross-combine the instruction slot range 1, the instruction slot range 2, and the instruction slot range 3 to obtain several second-dimensional orthogonal factors of the instruction package A. The second-dimensional orthogonal factors can represent the packaging method of the business instruction 1, the business instruction 2, and the business instruction 3 constituting the instruction package A when the instruction slot range 1, the instruction slot range 2, and the instruction slot range 3 are adapted.

[0111] The terminal device can perform third-dimensional verification, and can determine the register type called by the instruction packet through the second-dimensional orthogonal factor, that is, the way the business instructions form the instruction packet, and can determine the calling method of the register associated with the instruction packet call. For example, the port slot range 1 corresponding to business instruction 1, the port slot range 2 corresponding to business instruction 2, and the port slot range 3 corresponding to business instruction 3 can be obtained. The terminal device can cross-combine port slot range 1, port slot range 2, and port slot range 3 to obtain the third-dimensional orthogonal factor. The third-dimensional orthogonal factor represents the coupling relationship of the port slot range under the register type called by the instruction packet.

[0112] The terminal device can obtain the first dimension orthogonal factor, the second dimension orthogonal factor and the third dimension orthogonal factor through the first dimension verification, the second dimension verification and the third dimension verification, and generate the orthogonal coverage group through the first dimension orthogonal factor, and the orthogonal coverage group can count the functional coverage of the instruction package. Functional coverage refers to the proportion of function points contained in the instruction package that are executed during the coverage test process. The proportional relationship between the function points actually executed and the function points expected to be executed can be measured. Functional coverage can be used to evaluate the integrity and quality of the function points implemented by the instruction package (that is, the functions implemented by the chip of the computer processor), determine the scope of the test, follow up the test progress, and discover the functional modules that have not been executed or are not fully tested.

[0113] The present application decomposes the business instructions in the instruction package into first-dimensional orthogonal factors, second-dimensional orthogonal factors and third-dimensional orthogonal factors, where the orthogonal factors are independent of each other, thereby avoiding the inability to determine the functional points required for testing due to the intersection of test requirements. Decomposing them into orthogonal factors can isolate and separate highly complex and coupled problems, and can concretize the functional points required for testing and verification, thereby improving the efficiency and quality of functional coverage testing. At the same time, low-dimensional testing work is a highly efficient repetitive test, which reduces the manpower cost of functional coverage testing.

[0114] See also Figure 2 , Figure 2 This is a flow diagram of a data processing method provided in an embodiment of the present application. Figure 1 The data processing method can be executed by a computer device, which can be the terminal device in the above embodiment. Figure 2 As shown, the method may include:

[0115] Step S101, obtaining a target instruction packet including M business instructions; M is a positive integer, and the business instruction is a source code instruction for a computer processor;

[0116] Specifically, a computer device may obtain an instruction packet consisting of several business instructions, and a business instruction may be a source code instruction of a computer processor, and a business instruction may include a business function type, an instruction data type (data type, dtype), a destination operand (Register destination, Rd), and a source operand (Register source, Rs). Among them, the business function type may be a function type such as ADD (addition operation), MUL (multiplication operation), DIV (divide operation), etc. of the instruction, and the instruction data type refers to an operand type such as a floating point number (which may be a single-precision floating point number, a double-precision floating point number), a fixed-point number (which may be a fixed-point integer, a fixed-point decimal), etc., and the maximum number of bits of the operand may be 32 bits or 64 bits, which is not limited in the embodiments of the present application.

[0117] The instruction packet can be a source code instruction that implements some or all functions of a computer processor, which can be a general-purpose processor such as a central processing unit (CPU), a neural network processing unit (NPU), a graphics processing unit (GPU), or a field programmable gate array processor (FPGA), an application-specific integrated circuit processor (ASIC), etc., which are semi-customized or fully customized processors according to business needs. The chip hardware structure of a computer processor can include an arithmetic unit (Arithmetic and Logic Unit, ALU), a controller (Control Unit, CU), a register (Register), a cache (Cache), and a bus for communication data, control, and status, which is not limited in the present application embodiment. Among them, a computer processor can be a chip for computer system operation, control, information processing, and program operation.

[0118] It should be understood that business instructions can be either microinstructions or very long instruction words (VLIW) structures. The composition of instruction packages can be source code instructions that implement some or all functional points of a computer processor. When the business instructions are very long instruction word structures, they can be understood as multiple microinstructions. When the instruction package can implement all functions of a computer processor, it can be understood as multiple source code instruction packages that implement some functions of the computer processor.

[0119] Step S102, cross-combining the instruction data type ranges, destination operand ranges and source operand ranges respectively corresponding to the M business instructions to obtain a first-dimensional orthogonal factor; the first-dimensional orthogonal factor represents the instruction composition mode of the M business instructions in the instruction packet;

[0120] Specifically, the computer device may cross-combine the instruction data type ranges, destination operand ranges, and source operand ranges corresponding to a plurality of business instructions to obtain a first-dimensional orthogonal factor.

[0121] The process of the computer device obtaining the instruction data type range, the destination operand range and the source operand range may be: i The type of instruction data type adapted is determined to be a business instruction S iThe corresponding instruction data type range; the instruction data type includes the operand type of the destination operand and the operand type of the source operand; one or more register indexes covered by the destination operand are determined as the business instruction S i The corresponding destination operand range; one or more register indexes covered by the source operand are determined as the business instruction S i The corresponding source operand range.

[0122] Specifically, the computer device may determine the type of instruction data type adapted by the business instruction as the instruction data type range. For example, if the instruction data type adapted by the business instruction is a fixed-point number, then the instruction data type range may be a fixed-point integer and a fixed-point decimal.

[0123] The computer device may determine the destination operand range of the service instruction through several register indexes covered by the destination operand of the service instruction, and determine the source operand range through several register indexes covered by the source operand of the service instruction. For example, if the index number of the general register storing the source operand of the service instruction is 0 to 4, then the source operand range of the service instruction may be 0 to 4. If the index number of the general register storing the destination operand of the service instruction is 5 to 9, then the destination operand range of the service instruction may be 5 to 9.

[0124] Taking the example of a computer device obtaining an instruction packet A consisting of business instruction 1, business instruction 2, and business instruction 3, the computer device may cross-combine the instruction data type range, destination operand range, and source operand range of business instruction 1 to obtain a number of orthogonal factors 1 of business instruction 1. The cross-combination method may be to arrange and combine the instruction data type range, destination operand range, and source operand range. For example, the instruction data type range of business instruction 1 includes B1 and B2, the destination operand range includes C1 and C2, and the source operand range includes D1. Then, the four orthogonal factors 1 obtained by the cross-combination may include orthogonal factor 1 of a combination of B1, C1, and D1, orthogonal factor 1 of a combination of B1, C2, and D1, orthogonal factor 1 of a combination of B2, C1, and D1, and orthogonal factor 1 of a combination of B2, C2, and D1. Similarly, the instruction data type range, destination operand range and source operand range of business instruction 2 can be cross-combined to obtain several orthogonal factors 2 of business instruction 2, and the instruction data type range, destination operand range and source operand range of business instruction 3 can be cross-combined to obtain several orthogonal factors 3 of business instruction 3. Then, several orthogonal factors 1, several orthogonal factors 2 and several orthogonal factors 3 are cross-combined to obtain several first-dimensional orthogonal factors of instruction package A. The first-dimensional orthogonal factors can represent the composition of business instruction 1, business instruction 2 and business instruction 3 in instruction package A, that is, one first-dimensional orthogonal factor can represent a functional point in the composition of the business instructions in instruction package A.

[0125] Step S103, obtaining the business function types corresponding to the M business instructions respectively, determining the instruction slot ranges adapted by the M business function types, cross-combining the M instruction slot ranges adapted by the M business function types, and obtaining a second-dimensional orthogonal factor; the second-dimensional orthogonal factor represents the packaging method of the business instructions adapted to the M instruction slot ranges;

[0126] Specifically, the computer device may determine the instruction slot range adapted to the service function type according to the service function type of the service instruction.

[0127] The process of the computer device determining the instruction slot range adapted to the service function type may be: i One or more instruction slots adapted to the corresponding business function type are determined as business instructions S i The instruction slot range corresponding to the business function type; the instruction slot includes a scalar slot, a vector slot and a general slot, wherein the scalar slot, the vector slot and the general slot all have the function of being disassembled into multiple slots, the scalar slot adapter processes the business function type whose operand type is a scalar, and the vector slot adapter processes the business function type whose operand type is a vector.

[0128] Specifically, the computer device can determine a number of instruction slots adapted to the business function type corresponding to the business instruction as the instruction slot range. The instruction slot refers to a container for storing business instructions and related control information in the pipeline, which can be a storage unit or register in the chip hardware structure of the computer processor. Among them, the pipeline (also known as pipeline) refers to a way in which the computer processor divides the processing process of a business instruction or instruction packet into multiple steps and executes them in parallel through multiple hardware processing units to speed up the processing speed.

[0129] Instruction slots may include scalar slots (s_slot), vector slots (v_slot) and formal slots (f_slot). Scalar slots, vector slots and formal slots may be decomposed into multiple compressed slots with the same function. Scalar slots are adapted to the business function type whose operand type is scalar, vector slots are adapted to the business function type whose operand type is vector, and formal slots are adapted to all business function types.

[0130] For example, the business function type of business instruction 1 is ADD, and the operand type is scalar. The instruction slot range of business instruction 1 can be the adapted scalar slot and general slot, as well as the compressed slot with the same function in the scalar slot and general slot.

[0131] The computer device may determine a number of instruction slots adapted to the business function type of the business instruction as an instruction slot range, cross-combine a number of instruction slot ranges corresponding to a number of business instructions, and obtain a second-dimensional orthogonal factor.

[0132] For example, instruction slot range 1 corresponding to business instruction 1, instruction slot range 2 corresponding to business instruction 2, and instruction slot range 3 corresponding to business instruction 3 are obtained, and instruction slot range 1, instruction slot range 2, and instruction slot range 3 are cross-combined with each other to obtain several second-dimensional orthogonal factors of instruction package A. The second-dimensional orthogonal factors can represent the packaging method of business instructions 1, business instructions 2, and business instructions 3 on the pipeline to form instruction package A when instruction slot range 1, instruction slot range 2, and instruction slot range 3 are adapted.

[0133] It can be understood that the names, types and specific implementation methods of the instruction slots and registers in the embodiments of the present application may vary depending on the computer architecture system, and the embodiments of the present application are not limited here.

[0134] Step S104, determine the register type called by the instruction packet according to the second dimensional orthogonal factor, and determine the third dimensional orthogonal factor according to the port slot range mapped by the M business instructions under the register type; the third dimensional orthogonal factor represents the coupling relationship between the port slot ranges corresponding to the M business instructions respectively; the first dimensional orthogonal factor, the second dimensional orthogonal factor and the third dimensional orthogonal factor are used together to determine the functional coverage of the target instruction packet.

[0135] Specifically, the computer device can determine the register type called by the instruction packet through the second dimensional orthogonal factor, that is, the way in which the business instructions are packaged into instruction packets on the pipeline, and determine the calling method of the register associated with the instruction packet call.

[0136] The process of a computer device determining the register associated with the instruction packet call to obtain the third-dimensional orthogonal factor can be: among M business instructions, one or more instruction slots adapted to the business instructions belonging to the portless access mode are determined as the first slot range; one or more instruction slots adapted to the business instructions belonging to the single-port access are determined as the second slot range; one or more instruction slots adapted to the business instructions belonging to the multi-port access are determined as the third slot range; the first slot range, the second slot range and the third slot range of the M business instructions are cross-combined to obtain the third-dimensional orthogonal factor; the third-dimensional orthogonal factor characterizes the port access relationship of the first slot range, the second slot range and the third slot range of the M business instructions.

[0137] Specifically, the manner in which the instruction packet calls the associated register may include a non-port access manner, a single-port access manner, and a multi-port access manner.

[0138] Among them, the port is the address of the register that can be directly accessed by the computer processor in the interface circuit of the chip hardware structure of the computer processor. The no-port access (also known as "0 ports access register") mode means that the business instruction will not read any operands and related control information from the register. The single-port access (also known as "1 port access register") mode means that the business instruction reads the operands and related control information in the register through one address. The multi-port access (also known as "multiple ports access register", which can be 2 ports, 3 ports access register, etc.) mode means that the business instruction reads the operands and related control information in the register through multiple addresses.

[0139] The computer device can determine several instruction slots adapted to the business instructions belonging to a certain calling mode as the port slot range, cross-combine several instruction slot mapping ranges adapted to the business instructions belonging to different calling modes, and obtain several third-dimensional orthogonal factors.

[0140] For example, the instruction slots adapted by instruction packet A on the pipeline include the state control slot (stat controller, s_ctrl, a compressed slot) and the state processing slot (stat arithmetic and logic unit, salu, a compressed slot) in the scalar slot. Then it can be determined that the register associated with the instruction packet A call is the arithmetic interpretation register (arithmetic register, arg, register type used to store operands), the calling mode of the arithmetic interpretation register may include a portless access mode, a single-port access mode and a multi-port access mode, and the business instructions in the instruction packet A may be divided into an instruction set 1 (portless access mode) for accessing arg with 0 ports, an instruction set 2 (single-port access mode) for accessing arg with 1 port and an instruction set 3 (multi-port access mode) for accessing arg with 2 ports, and several instruction slots adapted by the instruction set 1 belonging to the portless access mode are determined as a first slot range, several instruction slots adapted by the instruction set 2 belonging to the single-port access mode are determined as a second slot range, and several instruction slots adapted by the instruction set 3 belonging to the multi-port access mode are determined as a third slot range, and the above-mentioned first slot range, second slot range and third slot range are cross-combined to obtain a third-dimensional orthogonal factor, and the third-dimensional orthogonal factor represents the coupling relationship between the first slot range, the second slot range and the third slot range in port access under the register type called by the instruction packet. Among them, the coupling relationship can be non-direct coupling (no coupling), that is, the access relationship between registers is realized through the call of the controller, or it can be common coupling (common coupling), that is, all registers access the same common data environment, etc., and the embodiments of the present application are not limited here.

[0141] The first dimension orthogonal factor, the second dimension orthogonal factor and the third dimension orthogonal factor can be used to generate an orthogonal cover group. The computer device can generate test cases through the orthogonal cover group, load the test cases into the instruction package, perform coverage testing, and obtain the functional coverage of the instruction package. Functional coverage refers to the proportion of function points contained in the instruction package that are executed during the coverage test. The proportional relationship between the function points actually executed and the function points expected to be executed can be measured. Functional coverage can be used to evaluate the integrity and quality of the function points implemented by the instruction package (i.e., the functions implemented by the chip of the computer processor), determine the scope of the test, follow up the progress of the test, and discover the functional modules that have not been executed or insufficiently tested. Among them, test cases can also be generated by seed randomization, constraint solving, model detection and other methods.

[0142] The embodiment of the present application obtains a target instruction packet containing M business instructions; M is a positive integer, and the business instruction is a source code instruction for a computer processor; the instruction data type range, the destination operand range and the source operand range corresponding to the M business instructions are cross-combined to obtain a first-dimensional orthogonal factor; the first-dimensional orthogonal factor represents the instruction composition method of the M business instructions in the target instruction packet; the business function types corresponding to the M business instructions are obtained, the instruction slot ranges adapted to the M business function types are determined, and the M instruction slot ranges adapted to the M business function types are cross-combined to obtain a second-dimensional orthogonal factor; the second-dimensional orthogonal factor represents the packaging method of the business instructions adapted to the M instruction slot ranges; the register type called by the target instruction packet is determined according to the second-dimensional orthogonal factor, and the third-dimensional orthogonal factor is determined according to the port slot range mapped by the M business instructions under the register type; the third-dimensional orthogonal factor represents the coupling relationship between the port slot ranges corresponding to the M business instructions; the first-dimensional orthogonal factor, the second-dimensional orthogonal factor and the third-dimensional orthogonal factor are used together to determine the functional coverage of the target instruction packet. It can be seen that the present application decomposes the business instructions in the instruction package into first-dimensional orthogonal factors, second-dimensional orthogonal factors and third-dimensional orthogonal factors, where the orthogonal factors are independent of each other, thereby avoiding the inability to determine the functional points required for testing due to the intersection of test requirements. Decomposing into orthogonal factors can isolate and separate highly complex and coupled problems, and can concretize the functional points required for testing and verification, thereby improving the efficiency and quality of functional coverage testing. At the same time, low-dimensional testing work is a highly efficient repetitive test, which reduces the manpower cost of functional coverage testing.

[0143] See also Figure 3 , Figure 3 This is a flow diagram of a data processing method provided in an embodiment of the present application. Figure 2 The data processing method may be executed by a computer device, which may be a terminal device or a computer device in the above-mentioned embodiment. Figure 3 As shown, the method may include:

[0144] Step S201, obtaining Q instruction packets; Q is a positive integer, and the Q instruction packets include a target instruction packet;

[0145] Specifically, the computer device can obtain Q instruction packets, and the Q instruction packets can be executed in parallel on the multi-stage pipeline of the computer processor, and there can be a coupling relationship between the Q instruction packets. Among them, the computer processor can be a chip for computer system operation, control, information processing, and program operation.

[0146] Among them, the Q instruction packets include the target instruction packet. The multi-stage pipeline refers to the number of pipelines (stages) that can be executed in parallel by the computer processor. The specific contents of the instruction packet and the business instruction can be found in the above Figure 2 The description of the instruction packet and the service instruction in S101 in the corresponding embodiment will not be repeated here.

[0147] Step S202, cross-combining the first-dimensional orthogonal factors corresponding to the Q instruction packets to obtain the first-dimensional verification factors; the first-dimensional verification factors represent the instruction composition mode of the business instructions in the Q instruction packets;

[0148] Specifically, each instruction packet in the Q instruction packets may correspond to a number of first-dimensional orthogonal factors of varying numbers. The computer device may cross-combine the first-dimensional orthogonal factors corresponding to the Q instruction packets to obtain the first-dimensional verification factor. The method of generating the first-dimensional orthogonal factor for each instruction packet is the same as the above. Figure 2 The corresponding embodiments generate the first-dimensional orthogonal factors in the same manner. For details of the first-dimensional orthogonal factors, see the above Figure 2 The description of the first-dimensional orthogonal factor in S102 in the corresponding embodiment will not be repeated here.

[0149] Step S203, cross-combining the second-dimensional orthogonal factors corresponding to the Q instruction packets to obtain a second-dimensional verification factor; the second-dimensional verification factor represents the packaging method of the business instructions in the Q instruction packets;

[0150] Specifically, each instruction packet in the Q instruction packets may correspond to a number of second-dimensional orthogonal factors of varying numbers. The computer device may cross-combine the second-dimensional orthogonal factors corresponding to the Q instruction packets to obtain the second-dimensional verification factor. The method of generating the second-dimensional orthogonal factor for each instruction packet is the same as the above method. Figure 2 The corresponding embodiment generates the second-dimensional orthogonal factor in the same manner. The specific content of the second-dimensional orthogonal factor can be found in the above Figure 2 The description of the second-dimensional orthogonal factor in S103 in the corresponding embodiment will not be repeated here.

[0151] Step S204, cross-combining the third-dimensional orthogonal factors corresponding to the Q instruction packets to obtain a third-dimensional verification factor; the third-dimensional verification factor represents the coupling relationship between the port slot ranges corresponding to the business instructions in the Q instruction packets;

[0152] Specifically, each of the Q instruction packets may correspond to a number of third-dimensional orthogonal factors of varying numbers. The computer device may cross-combine the third-dimensional orthogonal factors corresponding to the Q instruction packets to obtain a third-dimensional verification factor. The method of generating the third-dimensional orthogonal factor for each instruction packet is the same as the above method. Figure 2The corresponding embodiments generate the third-dimensional orthogonal factors in the same manner. The specific content of the third-dimensional orthogonal factors can be found in the above Figure 2 The description of the third-dimensional orthogonal factor in S104 in the corresponding embodiment will not be repeated here.

[0153] Please also refer to Figure 4a , Figure 4a This is a data processing scenario provided by the embodiment of the present application. Figure 2 , the data processor method can be executed by a computer device, in Figure 4a In the embodiment, the computer processor may have a multi-stage pipeline, that is, at the same time, the computer processor may execute multiple instruction packets in parallel. The scalar slot S may be decomposed into a scalar slot S0 and a scalar slot S1, the vector slots may be respectively vector slots L and vector slots V, the vector slot L may be decomposed into vector slots L0 and vector slots L1, and the general slot F may be decomposed into general slots F0 and general slots F1.

[0154] Specifically, the computer processor may execute instruction packages 1 to 5 in parallel, and the computer device may split the processing process of the service instruction in instruction package 1 into a scalar slot S, a vector slot L, a vector slot V, a general slot F0, and a general slot F1 in a first-level pipeline, and determine the above instruction slots as the third-dimensional orthogonal factors of instruction package 1;

[0155] The processing process of the service instruction in the instruction packet 2 can be divided into a scalar slot S0, a scalar slot S1, a vector slot L0, a vector slot L1, a vector slot V, and a general slot F in the secondary pipeline, and the above instruction slots are determined as the third-dimensional orthogonal factors of the instruction packet 2;

[0156] The processing process of the service instruction in the instruction package 3 can be divided into a scalar slot S, a vector slot L0, a vector slot L1, a vector slot V, and a general slot F in the three-stage pipeline, and the above instruction slots are determined as the third-dimensional orthogonal factors of the instruction package 3;

[0157] The processing process of the service instruction in the instruction packet 4 can be divided into a scalar slot S0, a scalar slot S1, a vector slot L, a vector slot V, and a general slot F in the four-stage pipeline, and the above instruction slots are determined as the third-dimensional orthogonal factors of the instruction packet 4;

[0158] The processing process of the business instructions in the instruction package 5 can be divided into a scalar slot S, a vector slot L, a vector slot V, and a general slot F in the five-stage pipeline, and the above instruction slots are determined as the third-dimensional orthogonal factors of the instruction package 5.

[0159] The computer device can cross-combine the third-dimensional orthogonal factor of instruction package 1, the third-dimensional orthogonal factor of instruction package 2, the third-dimensional orthogonal factor of instruction package 3, the third-dimensional orthogonal factor of instruction package 4 and the third-dimensional orthogonal factor of instruction package 5 to obtain the third-dimensional verification factor of instruction packages 1 to instruction 5.

[0160] Step S205, cross-combine the read pipeline position ranges corresponding to the Q instruction packets, the write pipeline position ranges corresponding to the Q instruction packets, the read pipeline position ranges corresponding to the Q instruction packets, and the write pipeline position ranges corresponding to the Q instruction packets to obtain a fourth-dimensional verification factor; the fourth-dimensional verification factor characterizes the read-write dependency relationship of the Q instruction packets, and the fourth-dimensional verification factor is used to determine the functional coverage of the Q instruction packets together with the first-dimensional verification factor, the second-dimensional verification factor, and the third-dimensional verification factor.

[0161] Specifically, the computer device may obtain the read pipeline position range, the write pipeline position range, the read pipeline position range, and the write pipeline position range corresponding to the Q instruction packets, respectively.

[0162] The specific process of determining the read pipeline position range, write pipeline position range, read pipeline position range and write pipeline position range by the computer device can be: based on the pipeline level of Q instruction packets, the pipeline position adapted by the read register instruction in each instruction packet is determined as Q read pipeline position ranges; the pipeline position adapted by the write register instruction in each instruction packet is determined as Q write pipeline position ranges; the pipeline position adapted by the read register instruction in each instruction packet when obtaining the operand in the pipeline is determined as Q read pipeline position ranges; the pipeline position adapted by the write register instruction in each instruction packet when completing the calculation in the pipeline is determined as Q write pipeline position ranges.

[0163] Specifically, the computer device may obtain pipeline stages corresponding to the Q instruction packets, where the pipeline stage refers to a certain stage of the instruction packet in a multi-stage pipeline of a computer processor.

[0164] The computer device can determine the execution direction of Q instruction packets in the pipeline through the number of pipeline stages, determine several pipeline positions adapted by the read register instructions in each instruction packet as the read pipeline position range, and obtain Q read pipeline position ranges, and determine several pipeline positions adapted by the write register instructions in each instruction packet as the write pipeline position range, and obtain Q write pipeline position ranges.

[0165] The pipeline position refers to the position of the business instruction in multiple stages of the pipeline (also known as pipeline depth). The multiple stages of the pipeline may include instruction fetch (getting business instructions from memory), decoding (decoding business instructions to determine the type of business function and operands to be executed), execution (executing business instructions), memory access (reading and writing memory data) and writeback (writing the execution results back to registers or memory), etc. The pipeline may refer to the specific hardware that implements the instruction pipeline in the chip hardware structure of the computer processor, and the business instructions are executed at different stages of the pipeline through different pipeline hardware units.

[0166] In a pipeline, multiple pipeline stages can be divided into multiple pipeline levels. Each pipeline level performs the operation of a stage through a dedicated hardware unit in the chip hardware structure of the computer processor. Instructions of different pipeline levels can be processed at different stages at the same time, thereby improving the processing efficiency of the computer processor chip.

[0167] Please also refer to Figure 4b , Figure 4b This is a data processing scenario provided by the embodiment of the present application. Figure 3 , the data processor method can be executed by a computer device, in Figure 4b In the figure, the instruction stream may include instruction package I1, instruction package I2, instruction package I3, instruction package I4 and instruction package I5 that are in a coupled relationship. Instruction package I1 may include business instruction 1, business instruction 6, business instruction 11, etc., instruction package I2 may include business instruction 2, business instruction 7, business instruction 12, etc., instruction package I3 may include business instruction 3, business instruction 8, business instruction 13, etc., and instruction package I4 may include business instruction 4, business instruction 9, business instruction 14, etc.

[0168] Among them, business instructions 1 to business instructions 5 may be as shown in Table 2:

[0169] Table 2

[0170] Instruction Flow Instruction content Business Instruction 1 LD R1 R3#0 Business Instruction 2 LD R1 R3#0 Business Instruction 3 ADD R5 R1 R2 Business Directive 4 MUL R6 R5 R1 Business Directive 5 DIV R7 R5 R6

[0171] Among them, business instruction 1 can be the load (LD, load) instruction at the 0th position of instruction packet I1 (that is, the first business instruction in the instruction packet), "#0" is the immediate number in the immediate addressing mode of business instruction 1, business instruction 2 can be the instruction at the 0th position in instruction packet I2, business instruction 3 can be the instruction at the 0th position in instruction packet I3, business instruction 4 can be the instruction at the 0th position in instruction packet I4, and business instruction 5 can be the instruction at the 0th position in instruction packet I5. The instruction content of the business instructions can refer to the specific description of the above embodiment, and will not be repeated here.

[0172] The read register instruction in the instruction packet can adapt to the pipeline position of each stage in the pipeline, and the write register instruction can adapt to the pipeline position after the stage where the read register instruction is located. Figure 4b In the instruction packet I1, the business instruction 1 at the 0th position may have a read-write dependency relationship with the business instruction 11 at the 2nd position (i.e., the third business instruction in the instruction packet). The read-write dependency relationship is also a write register instruction or a read register instruction. The destination register and the source register accessed are the same, so there is a dependency.

[0173] The read register instructions and write register instructions in the above instruction packets I1 to I5 can be shown in Table 3 in the instruction stream:

[0174] Table 3

[0175] Instruction Flow I5 I4 I3 I2 I1 Example 1 w r w r w Example 2 / w r / w Example 3 w r / / w Example 4 r / / / w …… / / / / w

[0176] Among them, w represents a write register instruction, r represents a read register instruction, Example 1 can represent the write register instruction and the read register instruction at the 0th position in instruction packets I1 to I5, and Example 2 can represent the write register instruction and the read register instruction at the 1st position.

[0177] like Figure 4b As shown, the computer processor can process the above instruction stream through pipeline 1, pipeline 2, ..., pipeline n, and the pipeline may include pipeline levels da, x1, x2, ca, and wa that respectively perform five stages of instruction fetching, decoding, execution, memory access, and write back.

[0178] The business instructions in the instruction stream can be executed in parallel by multiple pipelines. In the instruction stream, the coupling relationship between instruction packets I1 to I5 can be reflected on the same pipeline, and the read-write dependency relationship of different pipeline levels can also be reflected on the read-write dependency relationship on different pipelines.

[0179] In the pipeline, multiple pipeline stages can be called a pipeline level, and each pipeline level is performed by a corresponding hardware unit. These hardware units can be connected in the order of multiple pipeline stages to form a complete hardware pipeline. By decomposing the instruction execution process into multiple stages and executing different stages of multiple instructions at the same time, the processor resources can be fully utilized to improve the throughput and parallelism of business instructions.

[0180] The computer device may determine the several pipeline positions adapted by the read register instruction in each instruction packet when obtaining operands in the pipeline as the read pipeline position range, and obtain Q read pipeline position ranges. The computer device may determine the several pipeline positions adapted by the write register instruction in each instruction packet when completing calculations in the pipeline as the write pipeline position range, and obtain Q write pipeline position ranges.

[0181] The computer device may cross-combine the Q read pipeline position ranges, Q write pipeline position ranges, Q read pipeline position ranges, and Q write pipeline position ranges corresponding to the Q instruction packets to obtain a fourth-dimensional verification factor. The fourth-dimensional verification factor may represent the read-write dependency relationship of the Q instruction packets, and the read-write dependency relationship may include raw (read after write), waw (write after write), war (write after read), etc., which is not limited in the embodiments of the present application.

[0182] For example, if the first business instruction in the instruction stream is a read operation and the second business instruction is a write operation, then the read-write dependency relationship may be a read-after-write (war) dependency. If the first business instruction is a write operation and the second business instruction is a read operation, then the read-write dependency relationship may be a write-after-read (raw) dependency. If the first business instruction is a write operation and the second business instruction is also a write operation, then the read-write dependency relationship may be a write-after-write (waw) dependency. Among them, the write operation is a write-back in multiple stages of the pipeline, and the read operation may correspond to a non-write-back stage in multiple stages of the pipeline. The write operation and the read operation may be performed on registers or storage units in the chip hardware structure of the computer processor.

[0183] The fourth dimension verification factor can be used with the first dimension verification factor, the second dimension verification factor and the third dimension verification factor to generate a verification coverage group to test the functional coverage of the instruction package. Functional coverage refers to the proportion of function points contained in Q instruction packages that are executed during the coverage test process. It can measure the proportional relationship between the function points actually executed and the function points expected to be executed. Functional coverage can be used to evaluate the integrity and quality of the instruction package, determine the scope of the test, follow up the test progress, and discover the functional modules that have not been executed or are not fully tested.

[0184] The embodiment of the present application obtains Q instruction packets; Q is a positive integer, and the Q instruction packets include a target instruction packet; the first-dimensional orthogonal factors corresponding to the Q instruction packets are cross-combined to obtain a first-dimensional verification factor; the first-dimensional verification factor represents the instruction composition method of the business instructions in the Q instruction packets; the second-dimensional orthogonal factors corresponding to the Q instruction packets are cross-combined to obtain a second-dimensional verification factor; the second-dimensional verification factor represents the package method of the business instructions in the Q instruction packets; the third-dimensional orthogonal factors corresponding to the Q instruction packets are cross-combined to obtain a third-dimensional verification factor; the third-dimensional The verification factor represents the coupling relationship between the port slot ranges corresponding to the business instructions in the Q instruction packets; the read pipeline position ranges corresponding to the Q instruction packets, the write pipeline position ranges corresponding to the Q instruction packets, the read pipeline position ranges corresponding to the Q instruction packets, and the write pipeline position ranges corresponding to the Q instruction packets are cross-combined to obtain the fourth dimension verification factor; the fourth dimension verification factor represents the read-write dependency relationship of the Q instruction packets, and the fourth dimension verification factor is used to determine the functional coverage of the Q instruction packets together with the first dimension verification factor, the second dimension verification factor, and the third dimension verification factor. It can be seen that the present application decomposes the business instructions in the instruction packet into the first dimension verification factor, the second dimension verification factor, and the third dimension verification factor, and the verification factors of the same dimension are not related to each other, thereby avoiding the inability to determine the functional points required for verification in the test due to the intersection of test requirements. Decomposing into verification factors can isolate and separate highly complex and coupled problems, and can concretize the functional points required for verification in the test. At the same time, low-dimensional test work is a repetitive test with higher efficiency, which reduces the human cost of testing functional coverage. It can effectively verify the function points implemented by instruction packets or business instructions with read-write dependencies (i.e., the functions implemented by the chip of the computer processor), thereby improving the efficiency and quality of functional coverage testing.

[0185] See also Figure 5 , Figure 5 This is a flow diagram of a data processing method provided in an embodiment of the present application. Figure 3 The data processing method may be executed by a computer device, which may be a terminal device or a computer device in the above-mentioned embodiment. Figure 5 As shown, taking the function coverage of Q instruction packages as an example, the Q instruction packages may be source code instructions that implement all function points of computer processing. Among them, the computer processor may be a chip for computer system operation, control, information processing, and program operation.

[0186] The specific process of computer equipment verifying the functional coverage of Q instruction packages can be: obtaining a time coverage constraint range; the time coverage constraint range is set based on the functional points of the Q instruction packages; generating a first-dimensional verification coverage group through the first-dimensional verification factor and the time coverage constraint range, performing coverage tests on the Q instruction packages through the test cases in the first-dimensional verification coverage group to obtain first-dimensional verification coverage points, and determining the first-dimensional verification coverage of the Q instruction packages through the first-dimensional verification coverage points and the first-dimensional verification coverage group; generating a second-dimensional verification coverage group through the second-dimensional verification factor and the time coverage constraint range, performing coverage tests on the Q instruction packages through the test cases in the second-dimensional verification coverage group to obtain second-dimensional verification coverage points, and determining the second-dimensional verification coverage of the Q instruction packages through the second-dimensional verification coverage points and the second-dimensional verification coverage group; generating a third-dimensional verification coverage group through the third-dimensional verification factor and the time coverage constraint range, and performing coverage tests on the Q instruction packages through the test cases in the third-dimensional verification coverage group. The packages are tested for coverage to obtain third-dimensional verification coverage points, and the third-dimensional verification coverage of the Q instruction packages is determined by the third-dimensional verification coverage points and the third-dimensional verification coverage groups; the fourth-dimensional verification coverage groups are generated by the fourth-dimensional verification factors and the time coverage constraint range, and the Q instruction packages are tested for coverage by the test cases in the fourth-dimensional verification coverage groups to obtain fourth-dimensional verification coverage points, and the fourth-dimensional verification coverage of the Q instruction packages is determined by the fourth-dimensional verification coverage points and the fourth-dimensional verification coverage groups; the fourth-dimensional verification coverage is used to determine the functional coverage of the Q instruction packages together with the first-dimensional verification coverage, the second-dimensional verification coverage and the third-dimensional verification coverage; the functional coverage of the Q instruction packages is used to indicate the proportion of the functional points of the Q instruction packages that are executed during the coverage test process; if the functional coverage of the Q instruction packages does not meet the coverage completeness condition, the time coverage constraint range is adjusted until the functional coverage of the Q instruction packages meets the coverage completeness condition, and the coverage test of the Q instruction packages is completed.

[0187] Computer equipment can set time coverage constraint ranges, which are set by the functional points (i.e., the functions implemented by the chip of the computer processor) implemented by the design to be tested (Q instruction packets). The time coverage constraint range refers to the restriction conditions on the test cases, which can exclude some invalid inputs or operation sequences, thereby improving the effectiveness and correctness of the test cases, and can be adjusted and optimized through specific software features and test objectives.

[0188] The computer device can generate a first-dimensional verification coverage group through the first-dimensional verification factor and the time coverage constraint range. The first-dimensional verification coverage group can include test cases equal to the number of first-dimensional verification factors, and the functional points implemented by the first-dimensional verification factors are tested through the above test cases.

[0189] The computer device can perform coverage testing on Q instruction packages through the test cases in the first dimension verification coverage group to obtain first dimension verification coverage points. The first dimension verification coverage points are the functional points that can be achieved by testing the above test cases. The computer device can determine the first dimension verification coverage of the Q instruction packages through the ratio between the first dimension verification coverage points and the first dimension verification coverage group.

[0190] The computer device can generate a second-dimensional verification coverage group through the second-dimensional verification factor and the time coverage constraint range. The second-dimensional verification coverage group can contain test cases equal to the number of second-dimensional verification factors, and the functional points implemented by the second-dimensional verification factor are tested through the above test cases.

[0191] The computer device can perform coverage testing on Q instruction packages through the test cases in the second dimension verification coverage group to obtain second dimension verification coverage points. The second dimension verification coverage points are the functional points that can be achieved by testing the above test cases. The computer device can determine the second dimension verification coverage of the Q instruction packages through the ratio between the second dimension verification coverage points and the second dimension verification coverage group.

[0192] The computer device can generate a third-dimensional verification coverage group through the third-dimensional verification factor and the time coverage constraint range. The third-dimensional verification coverage group can contain test cases equal to the number of third-dimensional verification factors. The functional points implemented by the third-dimensional verification factor are tested through the above test cases.

[0193] The computer device can perform coverage testing on Q instruction packages through the test cases in the third-dimensional verification coverage group to obtain third-dimensional verification coverage points. The third-dimensional verification coverage points are the functional points that can be achieved by testing the above-mentioned test cases. The computer device can determine the third-dimensional verification coverage of the Q instruction packages through the ratio between the third-dimensional verification coverage points and the third-dimensional verification coverage group.

[0194] The computer device can generate a fourth-dimensional verification coverage group through the fourth-dimensional verification factor and the time coverage constraint range. The fourth-dimensional verification coverage group can contain test cases equal to the number of fourth-dimensional verification factors. The functional points implemented by the third-dimensional verification factor are tested through the above test cases.

[0195] The computer device can perform coverage testing on Q instruction packages through the test cases in the fourth dimension verification coverage group to obtain fourth dimension verification coverage points. The fourth dimension verification coverage points are the functional points that can be achieved by testing the above test cases. The computer device can determine the fourth dimension verification coverage of the Q instruction packages through the ratio between the fourth dimension verification coverage points and the fourth dimension verification coverage group.

[0196] The way in which the computer device generates test cases through the first verification coverage group, the second verification coverage group, the third verification coverage group, the fourth verification coverage group and the time constraint range can be through seed randomness, constraint solving, model detection and other methods and their combinations, and the embodiments of the present application are not limited here.

[0197] Taking Coverage-Driven Verification (CDV) as an example, a computer device can use the functional verification language (System Verilog) to load the test cases randomly generated by the verification factors and time constraints into the design to be tested (Q instruction packages), and perform corresponding simulation or hardware verification for coverage testing. During the test execution, the computer device can record the coverage information of the coverage points reached and the coverage points not reached by the test case. The computer device can test the correctness of the chip function of the computer processor through coverage-driven verification.

[0198] The computer device can calculate the verification coverage of each dimension (including the first dimension verification coverage, the second dimension verification coverage, the third dimension verification coverage and the fourth dimension verification coverage) through coverage points and coverage groups. If the verification coverage of each dimension does not meet the coverage completeness condition (the coverage completeness condition may be that the verification coverage of the dimension reaches 100%), the computer device can analyze the coverage information that has not reached the coverage point, modify the test case, or modify the time constraint range to generate a new test case, and perform coverage testing on the design to be tested (Q instruction packages) to improve the verification coverage of each dimension. When the verification coverage of each dimension meets the coverage completeness condition, it means that the functional coverage of the design to be tested (Q instruction packages) is complete (the functional coverage may reach 100%).

[0199] It can be understood that if there is no read-write dependency in the design to be tested (Q instruction packets), the computer device can also only decompose the Q instruction packets into first-dimensional verification factors, second-dimensional verification factors and third-dimensional verification factors to perform coverage testing.

[0200] Optionally, the computer device may perform coverage testing on an instruction package containing M business instructions, where the instruction package may contain source code instructions that implement some or all functional points of a computer processor. The specific process of the coverage testing may be: generating a first-dimensional orthogonal coverage group through a first-dimensional orthogonal factor and a spatial coverage constraint range, performing coverage testing on a target instruction package through test cases in the first-dimensional orthogonal coverage group to obtain first-dimensional orthogonal coverage points, and determining the first-dimensional orthogonal coverage of the target instruction package through the first-dimensional orthogonal coverage points and the first-dimensional orthogonal coverage group; generating a second-dimensional orthogonal coverage group through a second-dimensional orthogonal factor and a spatial coverage constraint range, and performing coverage testing on the target instruction package through test cases in the first-dimensional orthogonal coverage group to obtain first-dimensional orthogonal coverage points. The test cases in the two-dimensional orthogonal coverage group perform coverage tests on the instruction package to obtain the second-dimensional orthogonal coverage points, and the second-dimensional orthogonal coverage of the target instruction package is determined through the second-dimensional orthogonal coverage points and the second-dimensional orthogonal coverage group; a third-dimensional orthogonal coverage group is generated through the third-dimensional orthogonal factor and the spatial coverage constraint range, and the instruction package is covered by the test cases in the third-dimensional orthogonal coverage group to obtain the third-dimensional orthogonal coverage points, and the third-dimensional orthogonal coverage of the target instruction package is determined through the third-dimensional orthogonal coverage points and the third-dimensional orthogonal coverage group; the first-dimensional orthogonal coverage, the second-dimensional orthogonal coverage and the third-dimensional orthogonal coverage are used together to determine the functional coverage of the target instruction package.

[0201] Specifically, the computer device can set a spatial coverage constraint range, and the spatial coverage constraint range is obtained by setting the functional points implemented by the design to be tested (an instruction package containing M business instructions). The specific content of the spatial coverage constraint range can refer to the description of the time constraint range.

[0202] The computer device can generate an orthogonal coverage group of each dimension through the orthogonal factors of each dimension and the spatial coverage constraint range. The specific content of generating the orthogonal coverage group of each dimension can refer to the description of the verification coverage group. The computer device can calculate the orthogonal coverage of each dimension through the coverage points and the coverage group. If the orthogonal coverage of each dimension is insufficient to meet the coverage completeness condition, the computer device can analyze the coverage information that does not reach the coverage point to modify the test case or modify the spatial constraint range to generate a new test case to improve the orthogonal coverage of each dimension. When the orthogonal coverage of each dimension meets the coverage completeness condition, it means that the functional coverage of the instruction package containing M business instructions is complete (the functional coverage can reach 100%). Among them, the specific content of the orthogonal coverage can refer to the verification coverage.

[0203] The embodiments of the present application can split the business instructions or instruction packages into unrelated functional points by reasonably setting orthogonal factors or verification factors in each dimension, which can concretize the functional points that need to be verified in the test, effectively reduce the number of test cases, and ensure the comprehensiveness and effectiveness of the coverage test. The coverage test of each dimension can be carried out in stages according to the dimension, which improves the efficiency and quality of the functional coverage test. At the same time, the low-dimensional test work can automatically generate test cases as a repetitive test with higher efficiency, reducing the labor cost of the functional coverage test.

[0204] See also Figure 6 , Figure 6 Schematic diagram of a data processing device provided in an embodiment of the present application. Figure 6 As shown, the data processing device 1 includes a first acquisition module 500, a first dimensional orthogonal module 510, a second dimensional orthogonal module 520, a third dimensional orthogonal module 530, a first dimensional processing module 540, a second acquisition module 550, a first dimensional verification module 560, a second dimensional verification module 570, a third dimensional verification module 580, a fourth dimensional verification module 590, a pipeline processing module 600, a pipeline processing module 610, a space constraint acquisition module 620, a space constraint test module 630, a time constraint acquisition module 640, a first time test module 650, a second time test module 660, a third time test module 670, a fourth time test module 680 and a time constraint test module 690. The third dimensional orthogonal module 530 includes a slot determination unit 531 and a slot combination unit 532, and the space constraint test module 630 includes a first space test unit 631, a second space test unit 632 and a third space test unit 633.

[0205] The first acquisition module 500 is used to acquire a target instruction packet containing M business instructions; M is a positive integer, and the business instruction is a source code instruction for a computer processor; the specific functional implementation of the first acquisition module 500 can be found in Figure 2 The description of step S101 in the corresponding embodiment will not be repeated here.

[0206] The first-dimensional orthogonal module 510 is used to cross-combine the instruction data type range, the destination operand range and the source operand range corresponding to the M business instructions to obtain a first-dimensional orthogonal factor; the first-dimensional orthogonal factor represents the instruction composition method of the M business instructions in the target instruction packet; the specific function implementation method of the first-dimensional orthogonal module 510 can be found in Figure 2 The description of step S102 in the corresponding embodiment will not be repeated here.

[0207] The second-dimensional orthogonal module 520 is used to obtain the business function types corresponding to the M business instructions, determine the instruction slot ranges adapted by the M business function types, and cross-combine the M instruction slot ranges adapted by the M business function types to obtain the second-dimensional orthogonal factor; the second-dimensional orthogonal factor represents the packaging method of the business instructions adapted to the M instruction slot ranges;

[0208] The second dimensional orthogonal module 520 is specifically used to convert the service instruction S i One or more instruction slots adapted to the corresponding business function type are determined as business instructions S i The instruction slot range corresponding to the business function type; the instruction slot includes a scalar slot, a vector slot and a general slot, wherein the scalar slot, the vector slot and the general slot all have the function of being disassembled into multiple slots, the scalar slot is adapted to process the business function type of the scalar operand type, and the vector slot is adapted to process the business function type of the vector operand type. The specific functional implementation method of the second dimensional orthogonal module 520 can be found in Figure 2 The description of step S103 in the corresponding embodiment will not be repeated here.

[0209] The third-dimensional orthogonal module 530 is used to determine the register type called by the target instruction packet according to the second-dimensional orthogonal factor, and determine the third-dimensional orthogonal factor according to the port slot range mapped by the M business instructions under the register type; the third-dimensional orthogonal factor represents the coupling relationship between the port slot ranges corresponding to the M business instructions respectively; the first-dimensional orthogonal factor, the second-dimensional orthogonal factor and the third-dimensional orthogonal factor are used together to determine the functional coverage of the target instruction packet. The specific functional implementation of the third-dimensional orthogonal module 530 can be found in Figure 2 The description of step S104 in the corresponding embodiment will not be repeated here.

[0210] The slot determination unit 531 is used to determine, among the M service instructions, one or more instruction slots adapted to the service instructions belonging to the portless access mode as a first slot range;

[0211] The slot determination unit 531 is further configured to determine one or more instruction slots adapted to the service instruction belonging to the single port access as the second slot range;

[0212] The slot determination unit 531 is further configured to determine one or more instruction slots adapted by the service instruction belonging to the multi-port access as a third slot range;

[0213] The slot combination unit 532 is used to cross-combine the first slot range, the second slot range and the third slot range of the M business instructions to obtain a third-dimensional orthogonal factor; the third-dimensional orthogonal factor represents the port access relationship of the first slot range, the second slot range and the third slot range of the M business instructions.

[0214] The specific functional implementation of the slot determination unit 531 and the slot combination unit 532 can be found in Figure 2 The description of step S103 in the corresponding embodiment will not be repeated here.

[0215] The first dimension processing module 540 is used to convert the service instruction S i The type of instruction data type adapted is determined to be a business instruction S i The corresponding instruction data type range; the instruction data type includes the operand type of the destination operand and the operand type of the source operand;

[0216] The first dimension processing module 540 is further configured to determine one or more register indexes covered by the destination operand as the service instruction S i The corresponding destination operand range;

[0217] The first dimension processing module 540 is further configured to determine one or more register indexes covered by the source operand as the service instruction S i The corresponding source operand range.

[0218] The specific functional implementation of the first dimension processing module 540 can be found in Figure 2 The description of step S102 in the corresponding embodiment will not be repeated here.

[0219] The second acquisition module 550 is used to acquire Q instruction packets, where Q is a positive integer, and the Q instruction packets include a target instruction packet;

[0220] The specific functional implementation of the second acquisition module 550 can be found in Figure 3 The description of step S201 in the corresponding embodiment will not be repeated here.

[0221] The first dimension verification module 560 is used to cross-combine the first dimension orthogonal factors corresponding to the Q instruction packets to obtain the first dimension verification factor; the first dimension verification factor represents the instruction composition method of the business instructions in the Q instruction packets; the specific function implementation method of the first dimension verification module 560 can be found in Figure 3 The description of step S202 in the corresponding embodiment will not be repeated here.

[0222] The second dimension verification module 570 is used to cross-combine the second dimension orthogonal factors corresponding to the Q instruction packets to obtain the second dimension verification factor; the second dimension verification factor represents the packaging method of the business instructions in the Q instruction packets; the specific function implementation method of the second dimension verification module 570 can be found in Figure 3 The description of step S203 in the corresponding embodiment will not be repeated here.

[0223] The third dimension verification module 580 is used to cross-combine the third dimension orthogonal factors corresponding to the Q instruction packets to obtain the third dimension verification factor; the third dimension verification factor represents the coupling relationship between the port slot ranges corresponding to the business instructions in the Q instruction packets; the specific function implementation method of the third dimension verification module 580 can be found in Figure 3 The description of step S204 in the corresponding embodiment will not be repeated here.

[0224] The fourth dimension verification module 590 is used to cross-combine the read pipeline position ranges corresponding to the Q instruction packets, the write pipeline position ranges corresponding to the Q instruction packets, the read pipeline position ranges corresponding to the Q instruction packets, and the write pipeline position ranges corresponding to the Q instruction packets to obtain the fourth dimension verification factor; the fourth dimension verification factor represents the read-write dependency relationship of the Q instruction packets, and the fourth dimension verification factor is used to determine the functional coverage of the Q instruction packets together with the first dimension verification factor, the second dimension verification factor, and the third dimension verification factor. The specific functional implementation of the fourth dimension verification module 590 can be found in Figure 3 The description of step S204 in the corresponding embodiment will not be repeated here.

[0225] The pipeline processing module 600 is used to determine the pipeline position adapted by the read register instruction in each instruction packet as Q read pipeline position ranges based on the pipeline stages of the Q instruction packets;

[0226] The pipeline processing module 600 is further used to determine the pipeline position adapted by the write register instruction in each instruction packet as Q write pipeline position ranges;

[0227] The pipeline processing module 610 is used to determine the pipeline position adapted by the read register instruction in each instruction packet when obtaining the operand in the pipeline as Q read pipeline position ranges;

[0228] The pipeline processing module 610 is further used to determine the pipeline position adapted by the write register instruction in each instruction packet when completing the calculation in the pipeline as Q write pipeline position ranges.

[0229] The specific functional implementation of the pipeline processing module 600 and the pipeline processing module 610 can be found in Figure 3 The description of step S204 in the corresponding embodiment will not be repeated here.

[0230] The space constraint acquisition module 620 is used to acquire the space coverage constraint range; the space coverage constraint range is set based on the function points of the target instruction packet;

[0231] A space constraint test module 630 is used to generate an orthogonal cover group through a first dimension orthogonal factor, a second dimension orthogonal factor, a third dimension orthogonal factor and a space coverage constraint range, and to perform coverage test on a target instruction package through test cases in the orthogonal cover group;

[0232] The spatial constraint test module 630 is also used to adjust the spatial coverage constraint range if the functional coverage of the target instruction package does not meet the coverage completeness condition, until the functional coverage of the target instruction package meets the coverage completeness condition, thereby completing the coverage test of the target instruction package. The functional coverage of the target instruction package is used to indicate the proportion of the functional points of the instruction package that are executed during the coverage test process.

[0233] A first spatial test unit 631 is used to generate a first-dimensional orthogonal cover group through a first-dimensional orthogonal factor and a spatial coverage constraint range, perform coverage test on a target instruction package through test cases in the first-dimensional orthogonal cover group, obtain first-dimensional orthogonal cover points, and determine the first-dimensional orthogonal coverage of the target instruction package through the first-dimensional orthogonal cover points and the first-dimensional orthogonal cover group;

[0234] A second spatial test unit 632 is used to generate a second dimensional orthogonal cover group through a second dimensional orthogonal factor and a spatial coverage constraint range, perform coverage test on the instruction package through the test cases in the second dimensional orthogonal cover group to obtain second dimensional orthogonal cover points, and determine the second dimensional orthogonal coverage of the target instruction package through the second dimensional orthogonal cover points and the second dimensional orthogonal cover group;

[0235] The third spatial testing unit 633 is used to generate a third-dimensional orthogonal coverage group through the third-dimensional orthogonal factor and the spatial coverage constraint range, perform coverage test on the instruction package through the test cases in the third-dimensional orthogonal coverage group, and obtain third-dimensional orthogonal coverage points, and determine the third-dimensional orthogonal coverage of the target instruction package through the third-dimensional orthogonal coverage points and the third-dimensional orthogonal coverage group; the first-dimensional orthogonal coverage, the second-dimensional orthogonal coverage and the third-dimensional orthogonal coverage are jointly used to determine the functional coverage of the target instruction package.

[0236] The time constraint acquisition module 640 is used to acquire the time coverage constraint range; the time coverage constraint range is set based on the function points of the Q instruction packets;

[0237] A first time test module 650 is used to generate a first dimension verification coverage group through the first dimension verification factor and the time coverage constraint range, perform coverage test on the Q instruction packages through the test cases in the first dimension verification coverage group to obtain first dimension verification coverage points, and determine the first dimension verification coverage of the Q instruction packages through the first dimension verification coverage points and the first dimension verification coverage group;

[0238] A second time test module 660 is used to generate a second dimension verification coverage group through the second dimension verification factor and the time coverage constraint range, perform coverage test on the Q instruction packages through the test cases in the second dimension verification coverage group to obtain second dimension verification coverage points, and determine the second dimension verification coverage of the Q instruction packages through the second dimension verification coverage points and the second dimension verification coverage group;

[0239] A third time test module 670 is used to generate a third dimension verification coverage group through a third dimension verification factor and a time coverage constraint range, perform coverage test on the Q instruction packages through the test cases in the third dimension verification coverage group, obtain third dimension verification coverage points, and determine the third dimension verification coverage of the Q instruction packages through the third dimension verification coverage points and the third dimension verification coverage group;

[0240] The fourth time test module 680 is used to generate a fourth-dimensional verification coverage group through a fourth-dimensional verification factor and a time coverage constraint range, perform coverage test on the Q instruction packages through the test cases in the fourth-dimensional verification coverage group to obtain fourth-dimensional verification coverage points, and determine the fourth-dimensional verification coverage of the Q instruction packages through the fourth-dimensional verification coverage points and the fourth-dimensional verification coverage group; the fourth-dimensional verification coverage is used to determine the functional coverage of the Q instruction packages together with the first-dimensional verification coverage, the second-dimensional verification coverage and the third-dimensional verification coverage; the functional coverage of the Q instruction packages is used to indicate the proportion of the functional points of the Q instruction packages that are executed during the coverage test process;

[0241] The time constraint test module 690 is used to adjust the time coverage constraint range if the functional coverage of the Q instruction packages does not meet the coverage completeness condition, until the functional coverage of the Q instruction packages meets the coverage completeness condition, thereby completing the coverage test of the Q instruction packages.

[0242] See also Figure 7 , Figure 7 Schematic diagram of the structure of a computer device provided in an embodiment of the present application. Figure 7As shown, the computer device 1000 may include: a processor 1001, a network interface 1004 and a memory 1005. In addition, the above-mentioned computer device 1000 may also include: a user interface 1003, and at least one communication bus 1002. Among them, the communication bus 1002 is used to realize the connection and communication between these components. Among them, the user interface 1003 may include a display screen (Display), a keyboard (Keyboard), and the user interface 1003 may optionally include a standard wired interface and a wireless interface. The network interface 1004 may optionally include a standard wired interface and a wireless interface (such as a WI-FI interface). The memory 1005 may be a high-speed RAM memory, or it may be a non-volatile memory (non-volatile memory), such as at least one disk storage. The memory 1005 may optionally also be at least one storage device located away from the aforementioned processor 1001. As Figure 7 As shown, the memory 1005 as a computer-readable storage medium may include an operating system, a network communication module, a user interface module, and a device control application program.

[0243] In such Figure 7 In the computer device 1000 shown, the network interface 1004 can provide a network communication network element; the user interface 1003 is mainly used to provide an input interface for the user; and the processor 1001 can be used to call the device control application stored in the memory 1005 to achieve:

[0244] Obtain a target instruction packet including M business instructions, wherein M is a positive integer, and the business instructions are source code instructions for a computer processor;

[0245] The instruction data type range, the destination operand range and the source operand range corresponding to the M business instructions are cross-combined to obtain a first-dimensional orthogonal factor; the first-dimensional orthogonal factor represents the instruction composition mode of the M business instructions in the target instruction packet;

[0246] Obtain the business function types corresponding to the M business instructions, determine the instruction slot ranges adapted by the M business function types, cross-combine the M instruction slot ranges adapted by the M business function types, and obtain the second-dimensional orthogonal factor; the second-dimensional orthogonal factor represents the packaging method of the business instructions adapted to the M instruction slot ranges;

[0247] The register type called by the target instruction packet is determined according to the second-dimensional orthogonal factor, and the third-dimensional orthogonal factor is determined according to the port slot range mapped by the M business instructions under the register type; the third-dimensional orthogonal factor represents the coupling relationship between the port slot ranges corresponding to the M business instructions respectively; the first-dimensional orthogonal factor, the second-dimensional orthogonal factor and the third-dimensional orthogonal factor are jointly used to determine the functional coverage of the target instruction packet.

[0248] It should be understood that the computer device 1000 described in the embodiment of the present application can execute the above Figure 2 and Figure 3 The description of the data processing method in any corresponding embodiment will not be repeated here. In addition, the description of the beneficial effects of adopting the same method will not be repeated here.

[0249] In addition, it should be pointed out here that: the embodiment of the present application also provides a computer-readable storage medium, and the computer-readable storage medium stores a computer program, and when the processor executes the computer program, it can execute the above Figure 2 and Figure 3 The description of the above data processing method in any corresponding embodiment will not be repeated here. In addition, the description of the beneficial effects of the same method will not be repeated. For technical details not disclosed in the computer-readable storage medium embodiment involved in this application, please refer to the description of the method embodiment of this application.

[0250] The computer-readable storage medium may be the data processing device provided in any of the aforementioned embodiments or the internal storage unit of the computer device, such as a hard disk or memory of the computer device. The computer-readable storage medium may also be an external storage device of the computer device, such as a plug-in hard disk, a smart memory card (smart media card, SMC), a secure digital (secure digital, SD) card, a flash card (flash card), etc. equipped on the computer device. Further, the computer-readable storage medium may also include both the internal storage unit of the computer device and an external storage device. The computer-readable storage medium is used to store the computer program and other programs and data required by the computer device. The computer-readable storage medium may also be used to temporarily store data that has been displayed or is to be displayed.

[0251] In addition, it should be noted that: the embodiment of the present application also provides a computer program product, the computer program product includes a computer program, the computer program is stored in a computer-readable storage medium. The processor of the computer device reads the computer program from the computer-readable storage medium, and the processor executes the computer program, so that the computer device executes the above Figure 2 and Figure 3 Any method provided by the corresponding embodiment.

[0252] The terms "first", "second", etc. in the description, claims, and drawings of the embodiments of the present application are used to distinguish different objects, rather than to describe a specific order. In addition, the term "comprising" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, device, product, or equipment that includes a series of steps or units is not limited to the listed steps or modules, but optionally includes steps or modules that are not listed, or optionally includes other step units inherent to these processes, methods, devices, products, or equipment.

[0253] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of network elements in the above description. Whether these network elements are executed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described network elements for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0254] The above disclosure is only the preferred embodiment of the present application, which certainly cannot be used to limit the scope of rights of the present application. Therefore, equivalent changes made according to the claims of the present application are still within the scope covered by the present application.

Claims

1. A data processing method, characterized in that: include: Obtain a target instruction packet containing M business instructions; M is a positive integer, and the business instruction is a source code instruction for a computer processor; Cross-combining the instruction data type ranges, destination operand ranges and source operand ranges respectively corresponding to the M business instructions to obtain a first-dimensional orthogonal factor; the first-dimensional orthogonal factor represents the instruction composition mode of the M business instructions in the target instruction packet; Obtaining the business function types corresponding to the M business instructions respectively, determining the instruction slot ranges adapted by the M business function types, and cross-combining the M instruction slot ranges adapted by the M business function types to obtain a second-dimensional orthogonal factor; the second-dimensional orthogonal factor represents a packaging method of business instructions adapted to the M instruction slot ranges; Determine the register type called by the target instruction packet according to the second dimensional orthogonal factor, and determine the third dimensional orthogonal factor according to the port slot range mapped by the M business instructions under the register type; the third dimensional orthogonal factor represents the coupling relationship between the port slot ranges corresponding to the M business instructions respectively; The first-dimensional orthogonal factor, the second-dimensional orthogonal factor and the third-dimensional orthogonal factor are used together to determine the functional coverage of the target instruction packet.

2. The method according to claim 1, characterized in that The M service instructions include service instruction S i , i is a positive integer; the method further comprises: The business instruction S i The type of instruction data type adapted is determined to be the business instruction S i The corresponding instruction data type range; the instruction data type includes the operand type of the destination operand and the operand type of the source operand; One or more register indexes covered by the destination operand are determined as the service instruction S i The corresponding destination operand range; One or more register indexes covered by the source operand are determined as the service instruction S i The corresponding source operand range.

3. The method according to claim 1, characterized in that The M service instructions include service instruction S i , i is a positive integer; the determination of the instruction slot range adapted by the M business function types includes: The business instruction S i One or more instruction slots adapted by the corresponding business function type are determined as the business instruction S i The instruction slot range corresponding to the business function type; the instruction slot includes a scalar slot, a vector slot and a general slot, wherein the scalar slot, the vector slot and the general slot all have the function of being disassembled into multiple slots, the scalar slot is adapted to process the business function type whose operand type is a scalar, and the vector slot is adapted to process the business function type whose operand type is a vector.

4. The method according to claim 1, characterized in that The calling modes of the registers associated with the M business instructions include a portless access mode, a single-port access mode, and a multi-port access mode, and the determining of the third-dimensional orthogonal factor according to the port slot range mapped by the M business instructions under the register type includes: Among the M service instructions, one or more instruction slots adapted by the service instructions belonging to the portless access mode are determined as a first slot range; Determine one or more instruction slots adapted by the service instructions belonging to the single port access as a second slot range; Determine one or more instruction slots adapted by the service instructions belonging to the multi-port access as a third slot range; The first slot range, the second slot range and the third slot range of the M business instructions are cross-combined to obtain a third-dimensional orthogonal factor; the third-dimensional orthogonal factor characterizes the port access relationship of the first slot range, the second slot range and the third slot range of the M business instructions.

5. The method according to claim 1, characterized in that: Also includes: Acquire Q instruction packets, where Q is a positive integer, and the Q instruction packets include the target instruction packet; Cross-combining the first-dimensional orthogonal factors corresponding to the Q instruction packets to obtain a first-dimensional verification factor; the first-dimensional verification factor represents the instruction composition mode of the business instructions in the Q instruction packets; Cross-combining the second-dimensional orthogonal factors corresponding to the Q instruction packets to obtain a second-dimensional verification factor; the second-dimensional verification factor represents the packaging method of the business instructions in the Q instruction packets; Cross-combining the third-dimensional orthogonal factors corresponding to the Q instruction packets to obtain a third-dimensional verification factor; the third-dimensional verification factor represents the coupling relationship between the port slot ranges corresponding to the business instructions in the Q instruction packets; The read pipeline position ranges corresponding to the Q instruction packets, the write pipeline position ranges corresponding to the Q instruction packets, the read pipeline position ranges corresponding to the Q instruction packets, and the write pipeline position ranges corresponding to the Q instruction packets are cross-combined to obtain a fourth-dimensional verification factor; the fourth-dimensional verification factor characterizes the read-write dependency relationship of the Q instruction packets, and the fourth-dimensional verification factor is used to determine the functional coverage of the Q instruction packets together with the first-dimensional verification factor, the second-dimensional verification factor and the third-dimensional verification factor.

6. The method according to claim 5, characterized in that Also includes: Based on the pipeline stages of the Q instruction packets, the pipeline position adapted by the read register instruction in each instruction packet is determined as Q read pipeline position ranges; Determine the pipeline position adapted by the write register instruction in each instruction packet as Q write pipeline position ranges; Determine the pipeline position adapted by the read register instruction in each instruction packet when acquiring an operand in the pipeline as Q read pipeline position ranges; The pipeline position adapted by the write register instruction in each instruction packet when completing calculation in the pipeline is determined as Q write pipeline position ranges.

7. The method according to claim 1, characterized in that Also includes: Get the spatial coverage constraint range; The spatial coverage constraint range is set based on the functional points of the target instruction packet; Generate an orthogonal cover group by using the first dimensional orthogonal factor, the second dimensional orthogonal factor, the third dimensional orthogonal factor and the spatial coverage constraint range, and perform coverage test on the target instruction package by using the test cases in the orthogonal cover group; If the functional coverage of the target instruction package does not meet the coverage completion condition, the spatial coverage constraint range is adjusted until the functional coverage of the target instruction package meets the coverage completion condition, and the coverage test of the target instruction package is completed. The functional coverage of the target instruction package is used to indicate the proportion of the functional points of the instruction package that are executed during the coverage test process.

8. The method according to claim 7, characterized in that The step of generating a verification orthogonal coverage group by using the first dimensional orthogonal factor, the second dimensional orthogonal factor, and the third dimensional orthogonal factor, randomly generating a test case according to the spatial coverage constraint range, and performing coverage testing on the target instruction package by using the test case includes: Generate a first-dimensional orthogonal cover group by using the first-dimensional orthogonal factor and the spatial coverage constraint range, perform coverage test on the target instruction package by using the test cases in the first-dimensional orthogonal cover group to obtain first-dimensional orthogonal cover points, and determine the first-dimensional orthogonal coverage of the target instruction package by using the first-dimensional orthogonal cover points and the first-dimensional orthogonal cover group; Generate a second-dimensional orthogonal cover group through the second-dimensional orthogonal factor and the spatial coverage constraint range, perform coverage test on the instruction package through the test cases in the second-dimensional orthogonal cover group to obtain second-dimensional orthogonal cover points, and determine the second-dimensional orthogonal coverage of the target instruction package through the second-dimensional orthogonal cover points and the second-dimensional orthogonal cover group; A third-dimensional orthogonal coverage group is generated by the third-dimensional orthogonal factor and the spatial coverage constraint range, and the instruction package is tested for coverage using the test cases in the third-dimensional orthogonal coverage group to obtain third-dimensional orthogonal coverage points. The third-dimensional orthogonal coverage of the target instruction package is determined by the third-dimensional orthogonal coverage points and the third-dimensional orthogonal coverage group; the first-dimensional orthogonal coverage, the second-dimensional orthogonal coverage and the third-dimensional orthogonal coverage are used together to determine the functional coverage of the target instruction package.

9. The method according to claim 5, characterized in that Also includes: Acquire a time coverage constraint range; the time coverage constraint range is set based on the function points of the Q instruction packets; Generate a first-dimensional verification coverage group through the first-dimensional verification factor and the time coverage constraint range, perform coverage test on the Q instruction packages through the test cases in the first-dimensional verification coverage group to obtain first-dimensional verification coverage points, and determine the first-dimensional verification coverage of the Q instruction packages through the first-dimensional verification coverage points and the first-dimensional verification coverage group; Generate a second-dimensional verification coverage group through the second-dimensional verification factor and the time coverage constraint range, perform coverage test on the Q instruction packages through the test cases in the second-dimensional verification coverage group to obtain second-dimensional verification coverage points, and determine the second-dimensional verification coverage of the Q instruction packages through the second-dimensional verification coverage points and the second-dimensional verification coverage group; Generate a third-dimensional verification coverage group through the third-dimensional verification factor and the time coverage constraint range, perform coverage test on the Q instruction packages through the test cases in the third-dimensional verification coverage group to obtain third-dimensional verification coverage points, and determine the third-dimensional verification coverage of the Q instruction packages through the third-dimensional verification coverage points and the third-dimensional verification coverage group; Generate a fourth-dimensional verification coverage group through the fourth-dimensional verification factor and the time coverage constraint range, perform coverage test on the Q instruction packages through the test cases in the fourth-dimensional verification coverage group to obtain fourth-dimensional verification coverage points, and determine the fourth-dimensional verification coverage of the Q instruction packages through the fourth-dimensional verification coverage points and the fourth-dimensional verification coverage group; the fourth-dimensional verification coverage is used to determine the functional coverage of the Q instruction packages together with the first-dimensional verification coverage, the second-dimensional verification coverage and the third-dimensional verification coverage; the functional coverage of the Q instruction packages is used to indicate the proportion of the functional points of the Q instruction packages that are executed during the coverage test process; If the functional coverage of the Q instruction packages does not meet the coverage completeness condition, the time coverage constraint range is adjusted until the functional coverage of the Q instruction packages meets the coverage completeness condition, thereby completing the coverage test of the Q instruction packages.

10. A data processing device, characterized in that: include: A first acquisition module is used to acquire a target instruction packet containing M business instructions; M is a positive integer, and the business instruction is a source code instruction for a computer processor; A first-dimensional orthogonal module is used to cross-combine the instruction data type ranges, destination operand ranges and source operand ranges respectively corresponding to the M business instructions to obtain a first-dimensional orthogonal factor; the first-dimensional orthogonal factor represents the instruction composition mode of the M business instructions in the target instruction packet; A second-dimensional orthogonal module is used to obtain the business function types corresponding to the M business instructions, determine the instruction slot ranges adapted by the M business function types, and cross-combine the M instruction slot ranges adapted by the M business function types to obtain a second-dimensional orthogonal factor; the second-dimensional orthogonal factor represents the packaging method of the business instructions adapted to the M instruction slot ranges; A third-dimensional orthogonal module is used to determine the register type called by the target instruction packet according to the second-dimensional orthogonal factor, and determine the third-dimensional orthogonal factor according to the port slot range mapped by the M business instructions under the register type; the third-dimensional orthogonal factor represents the coupling relationship between the port slot ranges corresponding to the M business instructions respectively; The first-dimensional orthogonal factor, the second-dimensional orthogonal factor and the third-dimensional orthogonal factor are used together to determine the functional coverage of the target instruction packet.

11. A computer device, characterized in that: include: Processor, memory, and network interface; The processor is connected to the memory and the network interface, wherein the network interface is used to provide a data communication function, the memory is used to store a computer program, and the processor is used to call the program code so that the computer device executes the method described in any one of claims 1-9.

12. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and the computer program is suitable for being loaded and executed by a processor, so that a computer device having the processor executes the method according to any one of claims 1 to 9.

13. A computer program product, characterized in that The computer program product comprises a computer program, which is stored in a computer-readable storage medium and is suitable for being read and executed by a processor, so that a computer device having the processor executes the method according to any one of claims 1 to 9.

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