Page table cache invalidation method, data processing device and readable medium

Abstract

The invention provides a page table cache invalidation method, which is characterized in that a first data processing device in a first processing core sends invalidation operation information to a miscellaneous node, and the invalidation operation information at least comprises invalidation operation information which is not defined in an ARM instruction set and is defined in a non-ARM instruction set; the miscellaneous node notifies a second data processing device in the second processing core to execute a page table cache invalidation operation according to the invalidation operation information; according to the embodiment of the invention, the CHI protocol is expanded, page table cache invalid operation supported by the CHI protocol is supplemented, all-around TLBI operation can be supported, the CHI protocol and the instruction set adopted by the processing core are decoupled, the CHI protocol can be compatible with more instruction sets, the compatibility problem of a system on chip of a CPU (Central Processing Unit) containing a non-ARM instruction set can be solved, and the compatibility of the system on chip is improved. And the expansibility and the applicability are improved. The invention further provides a data processing device and a readable medium.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a page table cache invalidation method, a data processing device and a readable medium. Background Art

[0002] In a SOC (System On Chip) composed of a single processor, processor cluster, graphics processor, memory controller, etc., the CHI (Coherent Hub Interface) bus is one of the most commonly used interconnect bus protocols. It is highly flexible and scalable, and can meet different performance, power consumption and area requirements.

[0003] The CHI architecture provides a complete DVM (Distributed Virtual Memory) processing flow to achieve efficient management of virtual memory, but the supported TLBI (Translation Lookaside Buffer Invalidate, TLBI, page table cache invalidation operation) request types are limited to the ARM (Advanced RISCMachine) instruction set, that is, the various transactions defined by the CHI protocol are strongly related to the ARM instruction set. For TLBI operations that are not supported by the ARM instruction set, the CHI protocol does not provide a corresponding processing solution. For example, the CHI protocol does not support ASID (Address Space Identifier) ​​related TLBI operations at EL (Exception Level) 3, but some instruction sets, such as the RISC-V instruction set, support ASID related TLBI operations under M-mode (EL3), which leads to compatibility issues when the CHI protocol is implemented in a SOC containing a non-ARM instruction set CPU. Summary of the invention

[0004] The present disclosure provides a page table cache invalidation method, a data processing device and a readable medium.

[0005] In a first aspect, an embodiment of the present disclosure provides a page table cache invalidation method, the method being applied to a first data processing device in a first processing core, the method comprising:

[0006] Sending invalid operation information to a miscellaneous node so that the miscellaneous node notifies a second data processing device in a second processing core to perform a page table cache invalidation operation according to the invalid operation information; wherein the invalid operation information at least includes invalid operation information that is not defined in an ARM instruction set and is defined in a non-ARM instruction set.

[0007] On the other hand, an embodiment of the present disclosure also provides a data processing device, comprising: one or more processors; a storage device, on which one or more programs are stored; when the one or more programs are executed by the one or more processors, the one or more processors implement the page table cache invalidation method as described above; one or more I / O interfaces, connected between the processor and the storage device, configured to implement information interaction between the processor and the storage device.

[0008] On the other hand, an embodiment of the present disclosure further provides a computer-readable medium having a computer program stored thereon, wherein when the program is executed, the page table cache invalidation method as described above is implemented.

[0009] The page table cache invalidation method provided by the embodiment of the present disclosure comprises: a first data processing device in a first processing core sends invalid operation information to a miscellaneous node, wherein the invalid operation information at least includes invalid operation information that is not defined in an ARM instruction set and is defined in a non-ARM instruction set; the miscellaneous node notifies a second data processing device in a second processing core to perform a page table cache invalidation operation according to the invalid operation information; the embodiment of the present disclosure extends the CHI protocol, supplements the page table cache invalidation operation supported by the CHI protocol, supports a full range of TLBI operations, decouples the CHI protocol from the instruction set used by the processing core, and makes the CHI protocol compatible with more instruction sets, thereby solving the compatibility problem of the system-on-chip of the CPU containing the non-ARM instruction set and improving the scalability and applicability. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A schematic diagram of a page table cache invalidation process using a first data processing device as an execution subject provided in an embodiment of the present disclosure Figure 1 ;

[0011] Figure 2 A schematic diagram of a process of sending invalid operation information to miscellaneous nodes provided in an embodiment of the present disclosure;

[0012] Figure 3 A schematic diagram of a page table cache invalidation process using a first data processing device as an execution subject provided in an embodiment of the present disclosure Figure 2 ;

[0013] Figure 4 A schematic diagram of a page table cache invalidation process provided for a specific example of the present disclosure;

[0014] Figure 5 A schematic diagram of a page table cache invalidation process using a second data processing device as an execution subject provided in an embodiment of the present disclosure Figure 1 ;

[0015] Figure 6A schematic diagram of a page table cache invalidation process using a second data processing device as an execution subject provided in an embodiment of the present disclosure Figure 2 ;

[0016] Figure 7 A schematic diagram of the structure of a data processing device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0017] Example embodiments will be described more fully below with reference to the accompanying drawings, but the example embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, the purpose of providing these embodiments is to make the present disclosure thorough and complete and to enable those skilled in the art to fully understand the scope of the present disclosure.

[0018] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0019] The terms used herein are only used to describe specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will also be understood that when the terms "comprising" and / or "made of" are used in this specification, the presence of the features, wholes, steps, operations, elements and / or components is specified, but the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof is not excluded.

[0020] The embodiments described herein may be described with reference to plan views and / or cross-sectional views by means of idealized schematic diagrams of the present disclosure. Therefore, the example illustrations may be modified according to manufacturing techniques and / or tolerances. Therefore, the embodiments are not limited to the embodiments shown in the accompanying drawings, but include modifications of the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the accompanying drawings have schematic properties, and the shapes of the regions shown in the figures illustrate the specific shapes of the regions of the elements, but are not intended to be limiting.

[0021] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted as having an idealized or overly formal meaning unless explicitly defined as such herein.

[0022] In order to achieve efficient virtual memory management, the CHI protocol provides DVMOp (Distributed Virtual Memory operations), which includes the TLB maintenance instruction TLBI. The TLBI instruction can invalidate the page table at different granularities, thereby efficiently managing the virtual memory space of different processes, making the physical memory invisible to the application, and realizing the isolation of software and hardware.

[0023] TLBI operations are performed only according to EL, VA (Virtual Address) and ASID, that is, invalid operation information may include EL information, ASID information and VA information. The TLBI operations supported by the current CHI protocol are shown in Tables 1 and 2 below:

[0024] Table 1

[0025] ASID valid VA valid Operation ARM Instruction 0b0 0b0 TLBI ALL EL1 TLBI ALLE1 0b0 0b1 TLBI by VA EL1 TLBI VAAE1 0b1 0b0 TLBI by ASID EL1 TLBI ASIDE1 0b1 0b1 TLBI by ASID and VA EL1 TLBI VAE1

[0026] Table 1 shows the TLBI operations corresponding to the ARM instructions related to invalid operation information at the first exception level (EL1). As shown in Table 1, when both ASID and VA are invalid, the "TLBI ALLE1" instruction in the ARM instruction set is used to make all RNs (Request Nodes) in EL1 perform TLBI operations; when ASID is invalid and VA is valid, the "TLBI VAAE1" instruction in the ARM instruction set is used to make the RNs matching VA in EL1 perform TLBI operations; when ASID is valid and VA is invalid, the "TLBI ASIDE1" instruction in the ARM instruction set is used to make the RNs matching ASID in EL1 perform TLBI operations; when both ASID and VA are valid, the "TLBI VAE1" instruction in the ARM instruction set is used to make the RNs matching ASID and VA in EL1 perform TLBI operations.

[0027] Table 2

[0028] ASID valid VA valid Operation ARM Instruction 0b0 0b0 TLBI ALL EL3 TLBI ALLE3 0b0 0b1 TLBI by VA EL3 TLBI VAE3 0b1 0b0 Not Support NA 0b1 0b1 Not Support NA

[0029] Table 2 shows the TLBI operations corresponding to the ARM instructions related to invalid operation information at the third exception level (EL3). As shown in Table 2, when both ASID and VA are invalid, the "TLBI ALLE3" instruction in the ARM instruction set is used to make all RNs in EL3 perform TLBI operations; when ASID is invalid and VA is valid, the "TLBIVAE3" instruction in the ARM instruction set is used to make the RNs matching VA in EL3 perform TLBI operations; when ASID is valid and VA is invalid, and when both ASID and VA are valid, there is no corresponding operation instruction in the ARM instruction set, that is, the ARM instruction set does not define the corresponding operation, the ARM instruction set does not support the corresponding TLBI operation, and the CHI protocol does not provide a corresponding processing solution.

[0030] It can be seen from Table 1 and Table 2 that the CHI protocol does not support ASID-related TLBI operations in EL3, but some non-RAM instruction sets, such as the RISC-V instruction set, support ASID-related TLBI operations in M-mode (EL3). This leads to compatibility issues when the CHI protocol is implemented in a SOC containing a non-ARM instruction set CPU.

[0031] In order to solve the above problem, the embodiment of the present disclosure provides a page table cache invalidation method, which is applied to a first data processing device in a first processing core, and the first data processing device is a request node. It should be noted that different data processing devices are located in different processing cores of the same CPU. Figure 1 As shown, the page table cache invalidation method includes the following steps:

[0032] Step S11, sending invalid operation information to the miscellaneous node, so that the miscellaneous node notifies the second data processing device in the second processing core to perform a page table cache invalidation operation according to the invalid operation information; wherein the invalid operation information at least includes invalid operation information that is not defined in the ARM instruction set and is defined in the non-ARM instruction set.

[0033] The first data processing device in the first processing core sends invalid operation information to the miscellaneous node (MN), and the miscellaneous node forwards the invalid operation information to other data processing devices in other processing cores in the same CPU, so that the other data processing devices perform TLBI operations according to the invalid operation information. The invalid operation information is invalid operation information that is not defined in the ARM instruction set and defined in the non-ARM instruction set. Exemplarily, the invalid operation information is invalid operation information defined in the RISC-V instruction set but not defined in the ARM instruction set, that is, as shown in Table 2, ASID is valid and VA is invalid in EL3, and ASID and VA are both valid. In this way, the CHI protocol is extended, the ARM instruction set is supplemented and improved, and the compatibility problem of the system-on-chip of the CPU containing the non-ARM instruction set is solved.

[0034] The page table cache invalidation method provided by the embodiment of the present disclosure comprises: a first data processing device in a first processing core sends invalid operation information to a miscellaneous node, wherein the invalid operation information at least includes invalid operation information that is not defined in an ARM instruction set and is defined in a non-ARM instruction set; the miscellaneous node notifies a second data processing device in a second processing core to perform a page table cache invalidation operation according to the invalid operation information; the embodiment of the present disclosure extends the CHI protocol, supplements the page table cache invalidation operation supported by the CHI protocol, supports a full range of TLBI operations, decouples the CHI protocol from the instruction set used by the processing core, and makes the CHI protocol compatible with more instruction sets, thereby solving the compatibility problem of the system-on-chip of the CPU containing the non-ARM instruction set and improving the scalability and applicability.

[0035] In some embodiments, the non-ARM instruction set may be a RISC-V instruction set.

[0036] In some embodiments, the invalid operation information that is not defined in the ARM instruction set and defined in the non-ARM instruction set includes first invalid operation information, or first invalid operation information and second invalid operation information. The first invalid operation information may include EL information and ASID information, and the second invalid operation information may include VA information, wherein the EL information may be third exception level information (EL3). That is, the invalid operation information that is not defined in the ARM instruction set and defined in the non-ARM instruction set includes EL3 information and ASID information, or EL3 information, ASID information and VA information.

[0037] Taking the RISC-V instruction set as an example, the RISC-V instruction set provides the Sfence.VAM instruction and the Hfence.VVAM instruction to perform maintenance operations on the TLB, where the Sfence.VAM instruction supports operations in S-mode (corresponding to EL1 of the ARM architecture) and M-mode (corresponding to EL3 of the ARM architecture), and the above two instructions also have operations for ASID and VA. The mapping relationship between the TLBI operation of the RISC-V instruction set and the ARM instruction set is shown in Table 3:

[0038] Table 3

[0039] RISC-V ARM Operation CHI Support Sfence VAM All S TLBI ALLE1 TLBI ALL Y Sfence VAM VA S TLBI VAAE1 TLBI by VA Y Sfence VAM ASID S TLBI ASIDE1 TLBI by ASID Y Sfence VAM VAA S TLBI VAE1 TLBI by ASID and VA Y Sfence VAM All M TLBI ALLE3 TLBI ALL Y Sfence VAM VA M TLBI VAE3 TLBI by VA Y Sfence VAM ASID M NA TLBI by ASID N Sfence VAM VAA M NA TLBI by ASID and VA N

[0040] As shown in Table 3, the invalid operation information includes not only the invalid operation information that is not defined in the ARM instruction set and defined in the non-ARM instruction set, but also the invalid operation information defined in both the ARM instruction set and the non-ARM instruction set. That is, the invalid operation information also includes the third invalid operation information, or the third invalid operation information and the fourth invalid operation information. The third invalid operation information includes EL information, and the fourth invalid operation information includes VA information; wherein the third invalid operation information is the first abnormal level information or the third abnormal level information. That is, the invalid operation information also includes EL information (EL1 information or EL3 information), or the invalid operation information also includes EL information (EL1 information or EL3 information) and VA information. In addition, as shown in Table 3, the EL information in the first invalid operation information can also be EL1 information, that is, the first invalid operation information can also be EL1 information and ASID information.

[0041] It can be seen from Table 3 that the CHI protocol does not support TLBI operations related to ASID under EL3. After the CHI protocol is extended in the embodiments of the present disclosure, the Sfence VAM ASID M instruction and the Sfence VAM VAA M instruction in the RISC-V instruction set can also be correctly processed in the CHI protocol.

[0042] In some embodiments, Figure 2 As shown, the sending of invalid operation information to the miscellaneous node (i.e., step S11) includes the following steps:

[0043] Step S111: Send a distributed virtual memory operation request message to the miscellaneous node, wherein the distributed virtual memory operation request message carries first invalid operation information.

[0044] The first data processing device in the first processing core carries first invalid operation information (i.e., EL information and ASID information) in a distributed virtual memory operation request message (DVMOp) sent to the miscellaneous nodes, so that the miscellaneous nodes inform other data processing devices in other processing cores of the CPU to which the first data processing device belongs of the first invalid operation information.

[0045] Step S112: When the invalid operation information includes the second invalid operation information, after receiving the data packet identifier response message returned by the miscellaneous node, sending the target data and the second invalid operation information to the miscellaneous node.

[0046] After receiving the DVMOp message, the miscellaneous node returns a data packet identifier response message (DBIDResp) to the first data processing device. If the invalid operation information also includes the second invalid operation information, the first data processing device sends the second invalid operation information together with the target data (NCBWrData) to the miscellaneous node, so that the miscellaneous node informs the second invalid operation information to other data processing devices in other processing cores of the CPU to which the first data processing device belongs. The target data is the data to be processed by the first data processing device.

[0047] It should be noted that the miscellaneous node can broadcast the invalid operation information (first invalid operation information, or first invalid operation information and second invalid operation information) in a distributed virtual memory operation snoop response message (SnpDVMOp) to the second data processing device in the second processing core.

[0048] In the case where the invalid operation information is the third invalid operation information, or the third invalid operation information and the fourth invalid operation information, the first data processing device in the first processing core carries the third invalid operation information (i.e., EL1 information or EL3 information) in the distributed virtual memory operation request message (DVMOp) sent to the miscellaneous node. In the case where the invalid operation information also includes the fourth invalid operation information, the first data processing device in the first processing core sends the target data (NCBWrData) and the fourth invalid operation information (AV information) to the miscellaneous node after receiving the data packet identifier response message (DBIDResp) returned by the miscellaneous node.

[0049] In some embodiments, Figure 3 As shown, after sending the target data and the second invalidation operation information to the miscellaneous node (ie, step S112), the page table cache invalidation method may further include the following steps:

[0050] Step S113, receiving a completion response message sent by the miscellaneous node, where the second data processing device instructs the miscellaneous node to send the completion response message after completing the page table cache invalidation operation.

[0051] After receiving the invalid operation information sent by the miscellaneous node, the second data processing device in the second processing core performs a TLBI operation according to the invalid operation information and returns a distributed virtual memory operation snoop response message (SnpResp_I) to the miscellaneous node. After receiving the distributed virtual memory operation snoop response message, the miscellaneous node returns a completion response message (Comp) to the first data processing device in the first processing core to inform the first data processing device that the second data processing device has completed the corresponding TLBI operation.

[0052] To clearly illustrate the solution of the embodiment of the present disclosure, the following Figure 4 , the page table cache invalidation process is described in detail through a specific example. Figure 4 As shown, RN-F0 is the first data processing device in processing core 0, RN-F1 is the second data processing device in processing core 1, and the page table cache invalidation process includes the following steps:

[0053] Step 1: RN-F0 initiates a DVMOp request message to the MN in the bus. The DVMOp request message carries EL information and ASID information. The EL information and ASID information are carried in the address payload of the DVMOp request message.

[0054] Step 2: After receiving the DVMOp request message, the MN returns a DBIDResp response message to the RN-F0.

[0055] Step 3: After receiving the DBIDResp response message, RN-F0 carries the VA information in NCBWrData and sends it to MN.

[0056] Step 4: After receiving the NCBWrData message carrying the VA information, the MN broadcasts the SnpDVMOp message of the corresponding TLBI operation. The SnpDVMOp message is divided into two parts, namely the SnpDVMOp_P1 message and the SnpDVMOp_P2 message. The SnpDVMOp_P1 message and the SnpDVMOp_P2 message carry the EL information, ASID information and VA information.

[0057] Step 5: After receiving the SnpDVMOp_P1 message and the SnpDVMOp_P2 message, RN-F1 returns a SnpResp_I response message to the MN after completing the corresponding TLBI operation.

[0058] Step 6: After receiving the snpresp_I response message returned by RN-F1, MN returns a Comp response message to RN-F0, completing the entire transaction processing flow.

[0059] It can be seen from the above steps 1-6 that it is only necessary to modify the information carried by the DVMOp message and the message carrying NCBWrData to implement the ASID-related TLBI operation under EL3, and its processing flow can directly reuse the current CHI protocol's processing flow for conventional TLBI.

[0060] The disclosed embodiment is based on the CHI protocol, and expands the TLBI operation in the distributed virtual memory operation transaction supported by the CHI protocol, so that the CHI protocol can be compatible with more instruction set architectures. The disclosed embodiment can be applied to all SOC systems built based on the CHI protocol that need to maintain virtual memory.

[0061] The embodiment of the present disclosure also provides a page table cache invalidation method, the method is applied to a second data processing device in a second processing core, such as Figure 5 As shown, the page table cache invalidation method includes the following steps:

[0062] Step S21, receiving invalid operation information sent by the miscellaneous node; wherein the invalid operation message is sent by the first data processing device in the first processing core to the miscellaneous node, and the invalid operation information at least includes invalid operation information that is not defined in the ARM instruction set and is defined in the non-ARM instruction set.

[0063] In some embodiments, the non-ARM instruction set includes the RISC-V instruction set.

[0064] In some embodiments, the receiving of invalid operation information sent by the miscellaneous node includes: receiving a distributed virtual memory operation snoop message broadcast by the miscellaneous node, wherein the distributed virtual memory operation snoop message carries the invalid operation information. That is, the miscellaneous node can carry the invalid operation information in a distributed virtual memory operation snoop response message (SnpDVMOp) by broadcasting, and transmit it to the second data processing device in the second processing core.

[0065] Step S22: performing a page table cache invalidation operation according to the invalidation operation information.

[0066] After receiving the invalid operation information sent by the miscellaneous node, the second data processing device in the second processing core performs the TLBI operation according to the invalid operation information.

[0067] The page table cache invalidation method provided by the embodiment of the present disclosure, after receiving the invalid operation information sent by the miscellaneous node, the second data processing device in the second processing core performs the page table cache invalidation operation according to the invalid operation information, and the invalid operation information at least includes invalid operation information that is not defined in the ARM instruction set and defined in the non-ARM instruction set; the embodiment of the present disclosure extends the CHI protocol, supplements the page table cache invalidation operation supported by the CHI protocol, can support a full range of TLBI operations, decouples the CHI protocol from the instruction set used by the processing core, so that the CHI protocol can be compatible with more instruction sets, can solve the compatibility problem of the on-chip system of the CPU containing the non-ARM instruction set, and improves the scalability and applicability.

[0068] In some embodiments, the invalid operation information that is not defined in the ARM instruction set and is defined in the non-ARM instruction set includes first invalid operation information, or first invalid operation information and second invalid operation information, the first invalid operation information includes exception level EL information and ASID information, and the second invalid operation information includes VA information; wherein the EL information is the third exception level information or the first exception level information. That is, the invalid operation information that is not defined in the ARM instruction set and is defined in the non-ARM instruction set includes EL3 information and ASID information, or EL3 information, ASID information and VA information.

[0069] It should be noted that, as shown in Table 3, the invalid operation information may also include the third invalid operation information, or the third invalid operation information and the fourth invalid operation information, the third invalid operation information includes EL information, and the fourth invalid operation information includes VA information; wherein the third invalid operation information is the first abnormal level information or the third abnormal level information. That is, the invalid operation information also includes EL information (EL1 information or EL3 information), or the invalid operation information also includes EL information (EL1 information or EL3 information) and VA information. In addition, as shown in Table 3, the EL information in the first invalid operation information may also be EL1 information, that is, the first invalid operation information may also be EL1 information and ASID information.

[0070] In some embodiments, Figure 6 As shown, after performing the page table cache invalidation operation according to the invalidation operation information (i.e., step S22), the page table cache invalidation method may further include the following steps:

[0071] Step S23: Return the distributed virtual memory operation snoop response message to the miscellaneous node, so that the miscellaneous node can send a completion response message to the first data processing device.

[0072] After executing the TLBI operation according to the invalid operation information, the second data processing device in the second processing core returns a distributed virtual memory operation snoop response message (SnpResp_I) to the miscellaneous node. After receiving the distributed virtual memory operation snoop response message, the miscellaneous node returns a completion response message (Comp) to the first data processing device in the first processing core to inform the first data processing device that the second data processing device has completed the corresponding TLBI operation.

[0073] The present disclosure also provides a data processing device, such as Figure 7 As shown, including:

[0074] at least one processor 701;

[0075] A memory 702 storing at least one program, when the at least one program is executed by the at least one processor, the at least one processor implements the page table cache invalidation method provided in the above embodiments;

[0076] At least one I / O interface 703 is connected between the processor and the memory and is configured to implement information exchange between the processor and the memory.

[0077] Among them, the processor 701 is a device with data processing capabilities, including but not limited to a central processing unit (CPU); the memory 702 is a device with data storage capabilities, including but not limited to random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory (FLASH); the I / O interface (read-write interface) 703 is connected between the processor 701 and the memory 702, and can realize information interaction between the processor 701 and the memory 702, including but not limited to a data bus (Bus), etc.

[0078] In some embodiments, the processor 701 , the memory 702 , and the I / O interface 703 are connected to each other through a bus, and further connected to other components of the computing device.

[0079] The embodiments of the present disclosure further provide a computer-readable medium on which a computer program is stored, wherein when the computer program is executed, the page table cache invalidation method provided in the aforementioned embodiments is implemented.

[0080] It will be appreciated by those skilled in the art that all or some of the steps in the method disclosed above, the functional modules / units in the device may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some physical components or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those of ordinary skill in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0081] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for limiting purposes. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly stated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the scope of the invention as set forth in the appended claims.

Claims

1. A page table cache invalidation method, characterized in that: The method is applied to a first data processing device in a first processing core, and the method comprises: Sending invalid operation information to a miscellaneous node so that the miscellaneous node notifies a second data processing device in a second processing core to perform a page table cache invalidation operation according to the invalid operation information; wherein the invalid operation information at least includes invalid operation information that is not defined in an ARM instruction set and is defined in a non-ARM instruction set.

2. The method according to claim 1, characterized in that The invalid operation information that is not defined in the ARM instruction set and is defined in the non-ARM instruction set includes first invalid operation information, or first invalid operation information and second invalid operation information, the first invalid operation information includes exception level EL information and address space identifier ASID information, the second invalid operation information includes virtual address VA information; wherein the EL information is third exception level information.

3. The method according to claim 2, characterized in that The sending of invalid operation information to the miscellaneous node includes: Sending a distributed virtual memory operation request message to a miscellaneous node, wherein the distributed virtual memory operation request message carries the first invalid operation information; In a case where the invalid operation information includes the second invalid operation information, after receiving the data packet identifier response message returned by the miscellaneous node, the target data and the second invalid operation information are sent to the miscellaneous node.

4. The method according to claim 3, characterized in that After sending the target data and the second invalid operation information to the miscellaneous node, the method further includes: A completion response message sent by the miscellaneous node is received, where the second data processing device instructs the miscellaneous node to send the completion response message after completing the page table cache invalidation operation.

5. The method according to any one of claims 1 to 4, characterized in that: The non-ARM instruction set includes the RISC-V instruction set.

6. A page table cache invalidation method, characterized in that: The method is applied to a second data processing device in a second processing core, and the method comprises: Receiving invalid operation information sent by a miscellaneous node; wherein the invalid operation message is sent to the miscellaneous node by a first data processing device in a first processing core, and the invalid operation information at least includes invalid operation information that is not defined in an ARM instruction set and is defined in a non-ARM instruction set; A page table cache invalidation operation is performed according to the invalidation operation information.

7. The method according to claim 6, characterized in that The invalid operation information that is not defined in the ARM instruction set and is defined in the non-ARM instruction set includes first invalid operation information, or first invalid operation information and second invalid operation information, the first invalid operation information includes exception level EL information and address space identifier ASID information, and the second invalid operation information includes virtual address VA information; wherein the EL information is third exception level information or first exception level information.

8. The method according to claim 6, characterized in that The receiving of invalid operation information sent by the miscellaneous node includes: A distributed virtual memory operation snooping message broadcasted by a miscellaneous node is received, wherein the distributed virtual memory operation snooping message carries the invalid operation information.

9. The method according to claim 6, characterized in that After performing the page table cache invalidation operation according to the invalidation operation information, the method further includes: A distributed virtual memory operation snoop response message is returned to the miscellaneous node, so that the miscellaneous node can send a completion response message to the first data processing device.

10. The method according to any one of claims 6 to 9, characterized in that: The non-ARM instruction set includes the RISC-V instruction set.

11. A data processing device, comprising: one or more processors; a storage device having one or more programs stored thereon; When the one or more programs are executed by the one or more processors, the one or more processors implement the page table cache invalidation method according to any one of claims 1 to 5, or the page table cache invalidation method according to any one of claims 6 to 10; One or more I / O interfaces are connected between the processor and the storage device and are configured to implement information interaction between the processor and the storage device.

12. A computer readable medium having a computer program stored thereon, wherein: When the program is executed, the page table cache invalidation method according to any one of claims 1 to 5 is implemented, or the page table cache invalidation method according to any one of claims 6 to 10 is implemented.

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