Data Transmission Method, Device, Equipment and Medium for Memory Expansion Module

Abstract

The present application discloses a data transmission method, device, equipment and medium for a memory expansion module, which relates to the field of storage and data exchange design, and is applied to a memory expansion module including each memory expansion control chip and a programmable logic device. The programmable logic device is connected to the CXL controller of each memory expansion control chip, and the memory expansion module includes an X8 type slot and an X16 type slot; the method includes: when the X8 type slot is connected to the host through an X8 gold finger connector, triggering the programmable logic device to send a presence signal to each memory expansion control chip based on a first high-level hot plug detection signal; when the X16 type slot is connected to the host through an X16 gold finger connector, triggering the programmable logic device to send a presence signal to each memory expansion control chip based on a second high-level hot plug detection signal; the target memory expansion control chip selected based on the presence signal forwards the data transmitted by the host to the memory. The data transmission efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the field of storage and data exchange design, and particularly to a data transmission method, device, equipment and medium for a memory expansion module. Background Art

[0002] With the development of technologies such as big data, artificial intelligence, and machine learning, the demand for processing power in data centers and high-performance computing systems has increased sharply. The traditional CPU (Central Processing Unit) can no longer meet all computing needs, so various dedicated accelerators are required to assist in processing. To improve computing efficiency, heterogeneous computing has become a trend, and this computing mode requires an efficient and flexible interconnection technology to support data transmission between different computing units.

[0003] The performance of processors has been gradually improved, and the memory module and I / O (input / output) bandwidth have become bottlenecks in system performance. Although PCI Express (peripheral component interconnect express, a high-speed serial computer expansion bus standard) is a widely used system interconnection standard, it is mainly used to connect I / O devices and is not designed for efficient data exchange between processors and accelerators, and PCIe has certain limitations in supporting low-latency data transmission.

[0004] In summary, how to improve the data transmission efficiency of memory modules is a problem to be solved in this field. Summary of the Invention

[0005] In view of this, the purpose of the present invention is to provide a data transmission method, device, equipment and medium for a memory expansion module to improve the data transmission efficiency of the memory module. The specific solutions are as follows:

[0006] In a first aspect, the present application discloses a data transmission method for a memory expansion module, which is applied to a memory expansion module including a first memory expansion control chip, a second memory expansion control chip, and a programmable logic device. The programmable logic device is respectively connected to a first CXL controller in the first memory expansion control chip and a second CXL controller in the second memory expansion control chip. The first memory expansion control chip and the second memory expansion control chip are respectively connected to corresponding memories through memory connectors. The PICE slots of the memory expansion module include X8 type slots and X16 type slots; wherein, the method includes:

[0007] When the X8 type slot is connected to the host through the X8 gold finger connector, the programmable logic device is triggered based on the first high-level hot plug detection signal to send the presence signal to the first memory expansion control chip and the second memory expansion control chip;

[0008] When the X16 type slot is connected to the host through the X16 gold finger connector, the programmable logic device is triggered based on the second high-level hot plug detection signal to send the presence signal to the first memory expansion control chip and the second memory expansion control chip;

[0009] Based on the presence signal, a target memory expansion control chip is selected from the first memory expansion control chip and the second memory expansion control chip, so that the target memory expansion control chip forwards the data transmitted by the host to the corresponding memory.

[0010] Optionally, the memory expansion module includes a clock buffer; in the process of triggering the programmable logic device to send the presence signal to the first memory expansion control chip and the second memory expansion control chip based on the first high-level hot plug detection signal, it further includes:

[0011] The programmable logic device is triggered based on the first high-level hot plug detection signal to send a first enable signal to the clock buffer, so that the clock buffer selects a first clock signal path between the clock buffer and the X8 gold finger connector based on the first enable signal, receives the first clock signal sent by the X8 gold finger connector through the first clock signal path, and sends the first clock signal to the first memory expansion control chip;

[0012] Correspondingly, in the process of triggering the programmable logic device to send the presence signal to the first memory expansion control chip and the second memory expansion control chip based on the second high-level hot plug detection signal, it further includes:

[0013] The programmable logic device is triggered based on the second high-level hot plug detection signal to send a second enable signal to the clock buffer, so that the clock buffer selects a second clock signal path between the clock buffer and the X16 gold finger connector based on the second enable signal, receives the second clock signal sent by the X16 gold finger connector through the second clock signal path, and sends the second clock signal to the first memory expansion control chip and the second memory expansion control chip.

[0014] Optionally, the memory expansion module includes a multiplexer; in the process of triggering the programmable logic device to send the presence signal to the first memory expansion control chip and the second memory expansion control chip based on the first high-level hot plug detection signal, it further includes:

[0015] Trigger the programmable logic device to send a third enable signal to the multiplexer based on the first high-level hot plug detection signal, so that the multiplexer gates a first multiplexed signal path between the multiplexer and the X8 gold finger connector based on the third enable signal, receives a first multiplexed signal sent by the X8 gold finger connector through the first multiplexed signal path, and sends the first multiplexed signal to the first memory expansion control chip;

[0016] Correspondingly, in the process of triggering the programmable logic device to send a presence signal to the first memory expansion control chip and the second memory expansion control chip based on the second high-level hot plug detection signal, it further includes:

[0017] Trigger the programmable logic device to send a fourth enable signal to the multiplexer based on the first high-level hot plug detection signal, so that the multiplexer gates a second multiplexed signal path between the multiplexer and the X16 gold finger connector based on the fourth enable signal, receives a second multiplexed signal sent by the X16 gold finger connector through the second multiplexed signal path, and sends the second multiplexed signal to the first memory expansion control chip.

[0018] Optionally, the process of selecting a target memory expansion control chip from the first memory expansion control chip and the second memory expansion control chip based on the presence signal includes:

[0019] If the presence signal indicates that the X8 type slot is connected to the host through the X8 gold finger connector, then determine the first memory expansion control chip as the target memory expansion control chip, and control the second memory expansion control chip to switch to a low power consumption state;

[0020] If the presence signal indicates that the X16 type slot is connected to the host through the X16 gold finger connector, then determine both the first memory expansion control chip and the second memory expansion control chip as the target memory expansion control chips.

[0021] Optionally, the memory connector includes a first memory connector and a second memory connector corresponding to the first memory expansion control chip, and a third memory connector and a fourth memory connector corresponding to the second memory expansion control chip;

[0022] The process by which the target memory expansion control chip forwards the data transmitted by the host to the corresponding memory further includes:

[0023] Select a first target memory connector and a second target memory connector corresponding to the target memory expansion control chip from the first memory connector, the second memory connector, the third memory connector, and the fourth memory connector.

[0024] Optionally, the target memory expansion control chip forwards the data transmitted by the host to the corresponding memory, including:

[0025] The target memory expansion sends first data including chip control data signals, data strobe signals, ECC check signals, first chip select signals, and first differential clock signals to the first target memory connector through a first memory signal path between the target memory expansion and the first target memory connector, so that the first target memory connector sends the first data to the corresponding memory.

[0026] Optionally, the target memory expansion control chip forwards the data transmitted by the host to the corresponding memory, including:

[0027] The target memory expansion sends second data including chip control data signals, data strobe signals, ECC check signals, second chip select signals, and second differential clock signals to the second target memory connector through a second memory signal path between the target memory expansion and the second target memory connector, so that the second target memory connector sends the second data to the corresponding memory.

[0028] In a second aspect, the present application discloses a data transmission device for a memory expansion module, which is applied to a memory expansion module including a first memory expansion control chip, a second memory expansion control chip, and a programmable logic device. The programmable logic device is respectively connected to a first CXL controller in the first memory expansion control chip and a second CXL controller in the second memory expansion control chip. The first memory expansion control chip and the second memory expansion control chip are respectively connected to corresponding memories through memory connectors. The PICE slots of the memory expansion module include X8 type slots and X16 type slots; wherein, the device includes:

[0029] A first trigger module, configured to trigger the programmable logic device to send a presence signal to the first memory expansion control chip and the second memory expansion control chip based on a first high-level hot plug detection signal when the X8 type slot is connected to the host through an X8 gold finger connector;

[0030] A second trigger module, configured to trigger the programmable logic device to send a presence signal to the first memory expansion control chip and the second memory expansion control chip based on a second high-level hot plug detection signal when the X16 type slot is connected to the host through an X16 gold finger connector;

[0031] A data transmission module, configured to select a target memory expansion control chip from the first memory expansion control chip and the second memory expansion control chip based on the on-site signal, so that the target memory expansion control chip forwards the data transmitted by the host to the corresponding memory.

[0032] In a third aspect, the present application discloses an electronic device, including:

[0033] A memory, configured to store a computer program;

[0034] A processor, configured to execute the computer program to implement the steps of the data transmission method of the memory expansion module disclosed above.

[0035] In a fourth aspect, the present application discloses a computer-readable storage medium, configured to store a computer program; wherein, when the computer program is executed by a processor, the steps of the data transmission method of the memory expansion module disclosed above are implemented.

[0036] The beneficial effects of this application are as follows: This application is applied to a memory expansion module including a first memory expansion control chip, a second memory expansion control chip, and a programmable logic device. The programmable logic device is respectively connected to a first CXL controller in the first memory expansion control chip and a second CXL controller in the second memory expansion control chip. The first memory expansion control chip and the second memory expansion control chip are respectively connected to corresponding memories through memory connectors. The PICE slots of the memory expansion module include X8 type slots and X16 type slots; wherein, the method includes: when the X8 type slot is connected to the host through an X8 gold finger connector, triggering the programmable logic device to send a presence signal to the first memory expansion control chip and the second memory expansion control chip based on a first high-level hot plug detection signal; when the X16 type slot is connected to the host through an X16 gold finger connector, triggering the programmable logic device to send a presence signal to the first memory expansion control chip and the second memory expansion control chip based on a second high-level hot plug detection signal; selecting a target memory expansion control chip from the first memory expansion control chip and the second memory expansion control chip based on the presence signal, so that the target memory expansion control chip forwards the data transmitted by the host to the corresponding memory. Thus, it can be seen that a programmable logic device is newly added to the memory expansion module of this application, and the first memory expansion control chip and the second memory expansion control chip in the memory expansion module of this application respectively include a first CXL controller and a second CXL controller, that is, the CXL protocol is introduced in this application, and the CXL protocol can effectively improve the data transmission efficiency; further, the memory expansion module of this application can adapt to X8 gold finger connectors and X16 gold finger connectors. When the host is connected to the X8 type slot of the memory expansion module through an X8 gold finger connector, the memory expansion module can trigger the programmable logic device to send a presence signal to each memory expansion control chip based on the first high-level hot plug detection signal. When the host is connected to the X16 type slot of the memory expansion module through an X16 gold finger connector, the memory expansion module can trigger the programmable logic device to send a presence signal to each memory expansion control chip based on the second high-level hot plug detection signal, that is, the memory expansion module can trigger the programmable logic device to send a presence signal according to different high-level hot plug detection signals according to different host connection methods. Traditional host connection methods cannot be compatible with interface X8 and interface X16, while the memory expansion module of this application newly adds a programmable logic device, which can not only be compatible with the connections of X8 gold finger connectors and X16 gold finger connectors, but also can timely determine the current connection method between the memory expansion module and the host, improving the flexibility and convenience of data transmission. Description of the Drawings

[0037] To more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the accompanying drawings required for the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only the embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can also be obtained based on the provided drawings.

[0038] Figure 1 Flowchart of a data transmission method for a memory expansion module disclosed in the present application;

[0039] Figure 2 Schematic diagram of the connection between a specific RDIMM and a DDR5 controller disclosed in the present application;

[0040] Figure 3 Schematic diagram of the connection of a specific memory expansion module disclosed in the present application;

[0041] Figure 4 Schematic diagram of the structure of a data transmission device for a memory expansion module disclosed in the present application;

[0042] Figure 5 Structural diagram of an electronic device disclosed in the present application. Detailed implementation manners

[0043] The following will clearly and completely describe the technical solutions in the embodiments of the present application in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0044] With the development of technologies such as big data, artificial intelligence, and machine learning, the demand for processing capabilities in data centers and high-performance computing systems has increased sharply. Traditional CPUs can no longer meet all computing requirements, so various dedicated accelerators are needed to assist in processing. To improve computing efficiency, heterogeneous computing has become a trend, and this computing mode requires an efficient and flexible interconnection technology to support data transmission between different computing units.

[0045] The performance of processors has been gradually improved, and memory modules and I / O bandwidth have become bottlenecks in system performance. Although PCI Express is a widely used system interconnection standard, it is mainly used to connect I / O devices and is not designed for efficient data exchange between processors and accelerators, and PCIe has certain limitations in supporting low-latency data transmission.

[0046] Therefore, the present application correspondingly provides a data transmission solution for a memory expansion module to improve the data transmission efficiency of the memory module.

[0047] See Figure 1 As shown, an embodiment of the present application discloses a data transmission method for a memory expansion module, which is applied to a memory expansion module including a first memory expansion control chip, a second memory expansion control chip, and a programmable logic device. The programmable logic device is respectively connected to a first CXL controller in the first memory expansion control chip and a second CXL controller in the second memory expansion control chip. The first memory expansion control chip and the second memory expansion control chip are respectively connected to corresponding memories through memory connectors. The PICE slots of the memory expansion module include X8 type slots and X16 type slots; wherein, the method includes:

[0048] Step S11: When the X8 type slot is connected to the host through an X8 gold finger connector, trigger the programmable logic device to send a presence signal to the first memory expansion control chip and the second memory expansion control chip based on a first high-level hot plug detection signal.

[0049] It can be understood that when the X8 type slot is connected to the host through an X8 gold finger connector, the hot plug detection signal PRSNT0 is set to a high level, that is, a first high-level hot plug detection signal is obtained. After being processed by the programmable logic device, the programmable logic device sends a presence signal to the first memory expansion control chip MXC1 (CXL Memory Expansion Controller) and the second memory expansion control chip MXC2 through the SMBUS (System Management Bus), triggering their reset. The programmable logic device can specifically be an Erasable Programmable Logic Device (EPLD).

[0050] In this embodiment, the memory expansion module includes a clock buffer; in the process of triggering the programmable logic device to send the presence signal to the first memory expansion control chip and the second memory expansion control chip based on the first high-level hot-swap detection signal, it further includes: triggering the programmable logic device to send a first enable signal to the clock buffer based on the first high-level hot-swap detection signal, so that the clock buffer selects and enables the first clock signal path between it and the X8 gold finger connector based on the first enable signal, receives the first clock signal sent by the X8 gold finger connector through the first clock signal path, and sends the first clock signal to the first memory expansion control chip. When the memory expansion module includes a clock buffer A (CLK Buffer), PRSNT0 is set to high level, and the hot-swap detection signal PRSNT1 is set to low level, the programmable logic device is triggered to send a first enable signal to the clock buffer A based on the first high-level hot-swap detection signal, that is, the output MUX_EN[1:0] is equal to 01. The clock buffer A selects and enables the first clock signal path (i.e., PCI_CLK0) between it and the X8 gold finger connector based on the first enable signal, receives the first clock signal sent by the X8 gold finger connector through the first clock signal path, and sends the first clock signal to the first memory expansion control chip MXC1.

[0051] In this embodiment, the memory expansion module includes a multiplexer. During the process of triggering the programmable logic device to send the presence signal to the first memory expansion control chip and the second memory expansion control chip based on the first high-level hot-swap detection signal, it further includes: triggering the programmable logic device to send a third enable signal to the multiplexer based on the first high-level hot-swap detection signal, so that the multiplexer selects and enables the first multiplexing signal path between the multiplexer and the X8 gold finger connector based on the third enable signal, receives the first multiplexing signal sent by the X8 gold finger connector through the first multiplexing signal path, and sends the first multiplexing signal to the first memory expansion control chip. The memory expansion module includes a multiplexer (MUX0). When an X8 type slot is connected to the host through an X8 gold finger connector, PRSNT0 is set to high level, and the hot-swap detection signal PRSNT1 is set to low level, that is, a first high-level hot-swap detection signal is generated. Based on the first high-level hot-swap detection signal, the programmable logic device is triggered to send a third enable signal to the multiplexer (MUX0), that is, the output MUX_EN[1:0] is equal to 01, and the multiplexer MUX0 selects and enables the CXL0 / PCIE0_X8 side, that is, the multiplexer selects and enables the first multiplexing signal path between the multiplexer and the X8 gold finger connector. In this way, the first multiplexing signal sent by the X8 gold finger connector is received through the first multiplexing signal path, and the first multiplexing signal is sent to the first memory expansion control chip MXC1.

[0052] Step S12: When the X16 type slot is connected to the host through an X16 gold finger connector, trigger the programmable logic device to send the presence signal to the first memory expansion control chip and the second memory expansion control chip based on the second high-level hot-swap detection signal.

[0053] It can be understood that when the X16 type slot is connected to the host through an X16 gold finger connector, the hot-swap detection signal PRSNT1 is set to high level, that is, a second high-level hot-swap detection signal is obtained, and the hot-swap detection signal PRSNT0 is set to low level. In this way, it can be determined that the memory expansion module is connected to the host through the X16 gold finger connector. After the second high-level hot-swap detection signal is processed by the programmable logic device, the programmable logic device sends the presence signal to the first memory expansion control chip MXC1 and the second memory expansion control chip MXC2 through SMBUS to trigger their reset.

[0054] In this embodiment, during the process of triggering the programmable logic device to send the presence signal to the first memory expansion control chip and the second memory expansion control chip based on the second high-level hot-swap detection signal, the following steps are further included: triggering the programmable logic device to send a second enable signal to the clock buffer based on the second high-level hot-swap detection signal, so that the clock buffer can select and enable the second clock signal path between the clock buffer and the X16 gold finger connector based on the second enable signal, receive the second clock signal sent by the X16 gold finger connector through the second clock signal path, and send the second clock signal to the first memory expansion control chip and the second memory expansion control chip. When PRSNT0 is set to a low level and the hot-swap detection signal PRSNT1 is set to a high level, the programmable logic device is triggered to send a second enable signal to clock buffer A based on the second high-level hot-swap detection signal, that is, the output MUX_EN[1:0] is equal to 10. Clock buffer A selects and enables the second clock signal path (i.e., PCI_CLK1) between the clock buffer and the X16 gold finger connector based on the second enable signal, receives the second clock signal sent by the X16 gold finger connector through the second clock signal path, and sends the second clock signal to the first memory expansion control chip MXC1 and the second memory expansion control chip MXC2.

[0055] In this embodiment, during the process of triggering the programmable logic device to send the presence signal to the first memory expansion control chip and the second memory expansion control chip based on the second high-level hot-swap detection signal, the following steps are further included: triggering the programmable logic device to send a fourth enable signal to the multiplexer based on the first high-level hot-swap detection signal, so that the multiplexer selects the second multiplexing signal path between the multiplexer and the X16 gold finger connector based on the fourth enable signal, receives the second multiplexing signal sent by the X16 gold finger connector through the second multiplexing signal path, and sends the second multiplexing signal to the first memory expansion control chip. When the X16 type slot is connected to the host through the X16 gold finger connector, PRSNT1 is set to high level, and the hot-swap detection signal PRSNT0 is set to low level, that is, a second high-level hot-swap detection signal is generated. Based on the second high-level hot-swap detection signal, the programmable logic device is triggered to send a fourth enable signal to the multiplexer (MUX0), that is, the output MUX_EN[1:0] is equal to 10, and the multiplexer MUX0 selects the CXL1 / PCIE1_X8 side, that is, the multiplexer selects the second multiplexing signal path between the multiplexer and the X16 gold finger connector based on the fourth enable signal. In this way, the second multiplexing signal sent by the X16 gold finger connector is received through the second multiplexing signal path, and the second multiplexing signal is sent to the first memory expansion control chip MXC1. It should be noted that when the X16 type slot is connected to the host through the X16 gold finger connector, the second multiplexing signal received through the second multiplexing signal path is the low 8-bit data signal sent by the X16 gold finger connector. There is a direct connection path CXL1 / PCIE1_X8 directly connecting the X16 gold finger connector and the second memory expansion control chip MXC2. Therefore, the high 8-bit data signal sent by the X16 gold finger connector can be directly sent to the second memory expansion control chip MXC2.

[0056] Step S13: Select a target memory expansion control chip from the first memory expansion control chip and the second memory expansion control chip based on the presence signal, so that the target memory expansion control chip forwards the data transmitted by the host to the corresponding memory.

[0057] The reference clock source of the memory expansion control chip MXC can be 100MHz output by the clock generator (CLK Gener), or the differential reference clock of the PCIE, which is 100MHz. And the memory expansion control chip MXC supports JTAG (Joint Test Action Group) debugging, and the firmware version can be burned in an external Flash (flash memory) chip.

[0058] In this embodiment, selecting a target memory expansion control chip from the first memory expansion control chip and the second memory expansion control chip based on the on-site signal includes: if the on-site signal indicates that the X8 type slot is connected to the host through the X8 gold finger connector, determining the first memory expansion control chip as the target memory expansion control chip and controlling the second memory expansion control chip to convert to a low power state; if the on-site signal indicates that the X16 type slot is connected to the host through the X16 gold finger connector, determining both the first memory expansion control chip and the second memory expansion control chip as the target memory expansion control chips. It can be understood that if the on-site signal indicates that the X8 type slot is connected to the host through the X8 gold finger connector, the first memory expansion control chip is determined as the target memory expansion control chip and the second memory expansion control chip is controlled to convert to a low power state; if the on-site signal indicates that the X16 type slot is connected to the host through the X16 gold finger connector, both the first memory expansion control chip and the second memory expansion control chip are determined as the target memory expansion control chips.

[0059] In this embodiment, the memory connector includes a first memory connector, a second memory connector corresponding to the first memory expansion control chip, and a third memory connector, a fourth memory connector corresponding to the second memory expansion control chip. The memory connector includes a first memory connector RDIMM0, a second memory connector RDIMM1 corresponding to the first memory expansion control chip, and also includes a third memory connector RDIMM2, a fourth memory connector RDIMM3 corresponding to the second memory expansion control chip, where, for example Figure 2 As shown in a specific connection schematic diagram of the RDIMM and the DDR5 controller, taking the connection of the RDIMM of the first memory expansion control chip and the DDR (Double Data Rate) 5 controller as an example, the A channel of the DDR5 controller and the B channel of the DDR5 controller of the first memory expansion control chip are respectively connected to the first memory connector RDIMM0 and the second memory connector RDIMM1. Similarly, the A channel of the DDR5 controller and the B channel of the DDR5 controller of the second memory expansion control chip are respectively connected to the third memory connector RDIMM2 and the fourth memory connector RDIMM3.

[0060] In this embodiment, the target memory expansion control chip forwards the data transmitted by the host to the corresponding memory, and further includes: selecting a first target memory connector and a second target memory connector corresponding to the target memory expansion control chip from the first memory connector, the second memory connector, the third memory connector, and the fourth memory connector. It can be understood that if only the first memory expansion control chip is the target memory expansion control chip, the first memory connector and the second memory connector are the first target memory connector and the second target memory connector respectively. If both the first memory expansion control chip and the second memory expansion control chip are target memory expansion control chips, then the first memory connector and the third memory connector are the first target memory connectors, and the second memory connector and the fourth memory connector are the second target memory connectors.

[0061] In this embodiment, the target memory expansion control chip forwards the data transmitted by the host to the corresponding memory, including: the target memory expansion sends first data including chip control data signals, data strobe signals, ECC check signals, first chip select signals, and first differential clock signals to the first target memory connector through a first memory signal path between the target memory expansion and the first target memory connector, so that the first target memory connector sends the first data to the corresponding memory. Taking the first memory expansion control chip as the target memory expansion control chip as an example, as Figure 2 shown, the target memory expansion sends first data including chip control data signals, data strobe signals, ECC check signals, first chip select signals, and first differential clock signals to the first target memory connector through a first memory signal path between the target memory expansion and the first target memory connector RDIMM0, so that the first target memory connector sends the first data to the corresponding memory. The specific process is as follows:

[0062] 1) In the A channel between the first memory expansion control chip MXC1 and RDIMM0: The X32-bit wide data signal DQ[0:31]_A is directly connected to RDIMM0, the data strobe signals DQS[0:3]_A and DQS[5:8]_A are directly connected to RDIMM0, the ECC check signals DQ[32:39]_A, DQS4_A, and DQS9_A are also directly connected to RDIMM0, and the address and command signal CA[0:6]_A is directly connected to RDIMM0;

[0063] 2) Similarly, in Channel B, the data signal DQ[0:31]_B with an X32 bit width is directly connected to RDIMM0, the data strobe signals DQS[0:3]_B and DQS[5:8]_B are directly connected to RDIMM0, and the ECC check signals DQ[32:39]_B, DQS4_B, and DQS9_B are also directly connected to RDIMM0. The address and command signals CA[0:6]_B are directly connected to RDIMM0;

[0064] 3) The chip select signals CS_A[2:3], CS_B[2:3] and the differential clock signal CK_A0 are connected to the RDIMM0 connector. CS_A[2] is used to select Channel A of Rank0, CS_A[3] is used to select Channel A of Rank1, CS_B[2] is used to select Channel B of Rank0, and CS_A[3] is used to select Channel B of Rank1.

[0065] In this embodiment, the target memory expansion control chip forwards the data transmitted by the host to the corresponding memory, including: the target memory expansion sends second data including chip control data signals, data strobe signals, ECC check signals, second chip select signals, and second differential clock signals to the second target memory connector through a second memory signal path between the target memory expansion and the second target memory connector, so that the second target memory connector sends the second data to the corresponding memory. As Figure 2 shown, the target memory expansion sends second data including chip control data signals, data strobe signals, ECC check signals, second chip select signals, and second differential clock signals to the second target memory connector through a second memory signal path between the target memory expansion and the second target memory connector RDIMM1. The specific process is as follows:

[0066] 1) In Channel A, the data signal DQ[0:31]_A with an X32 bit width is directly connected to the RDIMM1 connector, the data strobe signals DQS[0:3]_A and DQS[5:8]_A are directly connected to the RDIMM1 connector, and the ECC check signals DQ[32:39]_A, DQS4_A, and DQS9_A are also directly connected to the RDIMM1 connector. The address and command signals CA[0:6]_A are directly connected to the RDIMM1 connector;

[0067] 2) Similarly, in Channel B, the data signal DQ[0:31]_B with an X32 bit width is directly connected to the RDIMM1 connector, the data strobe signals DQS[0:3]_B and DQS[5:8]_B are directly connected to the RDIMM1 connector, and the ECC check signals DQ[32:39]_B, DQS4_B, and DQS9_B are also directly connected to the RDIMM1 connector. The address and command signals CA[0:6]_B are directly connected to the RDIMM1 connector;

[0068] 3) The chip chip select signals CS_A[0:1], CS_B[0:1] and the differential clock signal CK_A1 are connected to the RDIMM1 connector. Among them, CS_A[0] is used to select and enable the A channel of Rank0, CS_A[1] is used to select and enable the A channel of Rank1, CS_B[0] is used to select and enable the B channel of Rank0, and CS_B[1] is used to select and enable the B channel of Rank1.

[0069] The beneficial effects of this application are as follows: This application is applied to a memory expansion module including a first memory expansion control chip, a second memory expansion control chip, and a programmable logic device. The programmable logic device is respectively connected to a first CXL controller in the first memory expansion control chip and a second CXL controller in the second memory expansion control chip. The first memory expansion control chip and the second memory expansion control chip are respectively connected to corresponding memories through memory connectors. The PICE slots of the memory expansion module include X8 type slots and X16 type slots; wherein, the method includes: when the X8 type slot is connected to the host through an X8 gold finger connector, triggering the programmable logic device to send a presence signal to the first memory expansion control chip and the second memory expansion control chip based on a first high-level hot plug detection signal; when the X16 type slot is connected to the host through an X16 gold finger connector, triggering the programmable logic device to send a presence signal to the first memory expansion control chip and the second memory expansion control chip based on a second high-level hot plug detection signal; selecting a target memory expansion control chip from the first memory expansion control chip and the second memory expansion control chip based on the presence signal, so that the target memory expansion control chip forwards the data transmitted by the host to the corresponding memory. It can be seen that this application's memory expansion module adds a programmable logic device, and the first memory expansion control chip and the second memory expansion control chip in this application's memory expansion module respectively include a first CXL controller and a second CXL controller, that is, this application introduces the CXL protocol, and the CXL protocol can effectively improve data transmission efficiency; further, this application's memory expansion module can adapt to X8 gold finger connectors and X16 gold finger connectors. When the host is connected to the X8 type slot of the memory expansion module through an X8 gold finger connector, the memory expansion module can trigger the programmable logic device to send a presence signal to each memory expansion control chip based on the first high-level hot plug detection signal. When the host is connected to the X16 type slot of the memory expansion module through an X16 gold finger connector, the memory expansion module can trigger the programmable logic device to send a presence signal to each memory expansion control chip based on the second high-level hot plug detection signal, that is, the memory expansion module can trigger the programmable logic device to send a presence signal according to different high-level hot plug detection signals based on different host connection methods. Traditional host connection methods cannot be compatible with interface X8 and interface X16, while this application's memory expansion module adds a programmable logic device, which can not only be compatible with the connections of X8 gold finger connectors and X16 gold finger connectors, but also can timely determine the current connection method between the memory expansion module and the host, improving the flexibility and convenience of data transmission.

[0070] The following takes Figure 3Taking the connection schematic diagram of a specific memory expansion module shown as an example, the present application will be described accordingly. The memory expansion module includes a first memory expansion control chip MXC1, a second memory expansion control chip MXC2, a programmable logic device (EPLD), a clock buffer 1 (CLK Buffer1), a clock buffer 2 (CLK Buffer2), a multiplexer (MUX0), a first memory connector RDIMM0 corresponding to the first memory expansion control chip, a second memory connector RDIMM1, a third memory connector RDIMM2 corresponding to the second memory expansion control chip, a fourth memory connector RDIMM3, and also includes a clock generator (CLK Gener), JTAG, SPI (Serial Peripheral Interface), SPI Flash1, SPI Flash2; wherein, the specific connection relationships are as follows:

[0071] The first memory expansion control chip MXC1 is connected to SPI Flash1, MXC1 is connected to JTAG through the JTAG1 interface, MXC1 is respectively connected to RDIMM0 and RDIMM1 through DDR5-A and DDR5-B, MXC1 is connected to EPLD through the MXC1-SMBUS interface and the RESET interface, connected to CLK Buffer1 through MXC1-CLK, and connected to MUX0 through the CXL / PCIE-X8 interface. Correspondingly, the second memory expansion control chip MXC2 is connected to SPI Flash2, MXC2 is connected to JTAG through the JTAG2 interface, MXC2 is respectively connected to RDIMM2 and RDIMM3 through DDR5-A and DDR5-B, MXC2 is connected to EPLD through the MXC2-SMBUS interface and the RESET interface, connected to CLK Buffer1 through MXC2-CLK, and connected to MUX0 through the CXL / PCIE-X8 interface;

[0072] CLK Gener is respectively connected to the first memory expansion control chip MXC1 and the second memory expansion control chip MXC2 through the REF (Reference) CLK1 (i.e., reference clock) and REFCLK2 of CLK Buffer2;

[0073] Further, the EPLD is connected to the X8 gold finger connector through the SMBUS0 interface, PRSNT0 interface, and RESET0 interface respectively, and the EPLD is connected to the X16 gold finger connector through the SMBUS1 interface, PRSNT1 interface, and RESET1 interface respectively. The CLKBuffer1 is connected to the X8 gold finger connector and the X16 gold finger connector through the PCI-CLK0 interface and PCI-CLK1 interface respectively. The MUX0 is connected to the X8 gold finger connector and the X16 gold finger connector through the CXL0 / PCIE0-X8 interface and CXL1 / PCIE1-X8 interface respectively.

[0074] The MXC chip is a memory expansion controller chip, and specifically, M88MX5891 can be selected. It integrates a CXL Type3 controller, a single-channel DDR4, a dual-channel DDR5 memory controller, and a RISC-V microprocessor inside. It supports the PCIE5.0 interface, conforms to the CXL2.0 specification, and provides an SPI interface to connect to an external Flash, an I2C (Inter-Integrated Circuit) to connect to the memory system, and an SMBus to connect to the CPU. One side of the MXC chip is connected to the X8 gold finger connector or the X16 gold finger connector, and the other side is connected to the connector of the RDIMM DDR5. The host CPU can access the MXC chip based on the CXL protocol / PCIE protocol. After the MXC chip processes the message, it writes or reads the message signal to / from the corresponding multiple memory particles.

[0075] The memory is connected to the MXC chip through the RDIMM connector. The RDIMM connector adopts a 288-pin form, with Rank0 on the front and Rank1 on the back. Each Rank supports Channel A and Channel B, and the data bit width of each channel is X32. One MXC supports up to 4 RDIMM memory modules at most.

[0076] The X8 gold finger connector supports 8 lanes of PCIE5.0 and can be connected to different hosts through the CXL protocol / PCIE protocol externally. The host can send messages to the MXC chip through the X8 gold finger connector.

[0077] The X16 gold finger connector supports 16 lanes of PCIE5.0 and can be connected to different hosts through the CXL protocol / PCIE protocol externally. The host can send messages to the MXC chip through the X16 gold finger connector.

[0078] See Figure 4As shown in the figure, an embodiment of the present application discloses a data transmission device for a memory expansion module, which is applied to a memory expansion module including a first memory expansion control chip, a second memory expansion control chip, and a programmable logic device. The programmable logic device is respectively connected to a first CXL controller in the first memory expansion control chip and a second CXL controller in the second memory expansion control chip. The first CXL controller and the second CXL controller are respectively connected to corresponding memories through memory connectors. The PICE slots of the memory expansion module include X8 type slots and X16 type slots; wherein, the device includes:

[0079] A first trigger module 11, configured to, when the X8 type slot is connected to the host through an X8 gold finger connector, trigger the programmable logic device to send a presence signal to the first memory expansion control chip and the second memory expansion control chip based on a first high-level hot-swap detection signal;

[0080] A second trigger module 12, configured to, when the X16 type slot is connected to the host through an X16 gold finger connector, trigger the programmable logic device to send a presence signal to the first memory expansion control chip and the second memory expansion control chip based on a second high-level hot-swap detection signal;

[0081] A data transmission module 13, configured to select a target memory expansion control chip from the first memory expansion control chip and the second memory expansion control chip based on the presence signal, so that the target memory expansion control chip forwards the data transmitted by the host to the corresponding memory.

[0082] The beneficial effects of this application are as follows: This application is applied to a memory expansion module including a first memory expansion control chip, a second memory expansion control chip, and a programmable logic device. The programmable logic device is respectively connected to a first CXL controller in the first memory expansion control chip and a second CXL controller in the second memory expansion control chip. The first memory expansion control chip and the second memory expansion control chip are respectively connected to corresponding memories through memory connectors. The PICE slots of the memory expansion module include X8 type slots and X16 type slots; wherein, the method includes: when the X8 type slot is connected to the host through an X8 gold finger connector, triggering the programmable logic device to send a presence signal to the first memory expansion control chip and the second memory expansion control chip based on a first high-level hot plug detection signal; when the X16 type slot is connected to the host through an X16 gold finger connector, triggering the programmable logic device to send a presence signal to the first memory expansion control chip and the second memory expansion control chip based on a second high-level hot plug detection signal; selecting a target memory expansion control chip from the first memory expansion control chip and the second memory expansion control chip based on the presence signal, so that the target memory expansion control chip forwards the data transmitted by the host to the corresponding memory. It can be seen that this application's memory expansion module adds a programmable logic device, and the first memory expansion control chip and the second memory expansion control chip in this application's memory expansion module respectively include a first CXL controller and a second CXL controller, that is, this application introduces the CXL protocol, and the CXL protocol can effectively improve data transmission efficiency; further, this application's memory expansion module can adapt to X8 gold finger connectors and X16 gold finger connectors. When the host is connected to the X8 type slot of the memory expansion module through an X8 gold finger connector, the memory expansion module can trigger the programmable logic device to send a presence signal to each memory expansion control chip based on the first high-level hot plug detection signal. When the host is connected to the X16 type slot of the memory expansion module through an X16 gold finger connector, the memory expansion module can trigger the programmable logic device to send a presence signal to each memory expansion control chip based on the second high-level hot plug detection signal, that is, the memory expansion module can use different high-level hot plug detection signals to trigger the programmable logic device to send a presence signal according to different host connection methods. Traditional host connection methods cannot be compatible with interface X8 and interface X16, while this application's memory expansion module adds a programmable logic device, which can not only be compatible with the connections of X8 gold finger connectors and X16 gold finger connectors, but also can timely determine the current connection method between the memory expansion module and the host, improving the flexibility and convenience of data transmission.

[0083] Furthermore, an embodiment of this application also provides an electronic device. Figure 5It is a structural diagram of an electronic device 20 shown according to an exemplary embodiment. The content in the figure should not be regarded as any limitation on the scope of use of this application.

[0084] Figure 5 It is a schematic structural diagram of an electronic device provided by an embodiment of this application. Specifically, it may include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. Among them, the memory 22 is used to store a computer program, and the computer program is loaded and executed by the processor 21 to implement the relevant steps in the data transmission method of the memory expansion module executed by the electronic device disclosed in any of the foregoing embodiments.

[0085] In this embodiment, the power supply 23 is used to provide operating voltage for each hardware device on the electronic device; the communication interface 24 can create a data transmission channel between the electronic device and external devices, and the communication protocol it follows is any communication protocol applicable to the technical solution of this application, and no specific limitation is imposed on it here; the input / output interface 25 is used to obtain external input data or output data to the outside, and its specific interface type can be selected according to specific application needs, and no specific limitation is made here.

[0086] Among them, the processor 21 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 21 can be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor 21 may also include a main processor and a coprocessor. The main processor is a processor used to process data in the wake state, also known as the CPU (Central Processing Unit); the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor 21 may be integrated with a GPU (Graphics Processing Unit), and the GPU is responsible for the rendering and drawing of the content to be displayed on the display screen. In some embodiments, the processor 21 may also include an AI (Artificial Intelligence) processor, and the AI processor is used to process computational operations related to machine learning.

[0087] In addition, as a carrier for storing resources, the memory 22 can be a read-only memory, a random access memory, a magnetic disk, an optical disc, etc. The resources stored thereon include an operating system 221, a computer program 222, data 223, etc. The storage method can be temporary storage or permanent storage.

[0088] Among them, the operating system 221 is used to manage and control each hardware device and the computer program 222 on the electronic device, so as to enable the processor 21 to perform operations and processing on the massive data 223 in the memory 22. It can be Windows, Unix, Linux, etc. In addition to the computer program that can be used to complete the data transmission method of the memory expansion module executed by the electronic device disclosed in any of the foregoing embodiments, the computer program 222 can further include computer programs that can be used to complete other specific tasks. In addition to the data transmitted by external devices received by the electronic device, the data 223 can also include data collected by its own input / output interface 25, etc.

[0089] Furthermore, the present application also discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, it implements the data transmission method of the memory expansion module disclosed above. For the specific steps of this method, reference can be made to the corresponding content disclosed in the foregoing embodiments, and details will not be repeated here.

[0090] In this specification, the various embodiments are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the various embodiments, reference can be made to each other. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple, and reference can be made to the description of the method part for related parts.

[0091] Those skilled in the art may further realize that the units and algorithm steps of each example described in connection with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods for each specific application to implement the described functions, but such implementation should not be considered to exceed the scope of this application. The steps of the methods or algorithms described in connection with the embodiments disclosed herein can be directly implemented by hardware, software modules executed by a processor, or a combination of the two. The software modules can be placed in a random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable EPROM (Erasable Programmable Read Only Memory), electrically erasable programmable EEPROM (Electrically Erasable Programmable read only memory), registers, hard disks, removable disks, CD-ROM (Compact Disc Read-Only Memory), or any other form of storage medium well-known in the technical field.

[0092] Finally, it should also be noted that in this document, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variation thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the existence of additional identical elements in the process, method, article or device comprising the element.

[0093] The above has introduced in detail a data transmission method, device, equipment and medium of a memory expansion module provided by the present invention. Specific examples are used in this article to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A data transmission method for a memory expansion module, characterized in that: The invention is applied to a memory expansion module including a first memory expansion control chip, a second memory expansion control chip and a programmable logic device, wherein the programmable logic device is respectively connected to a first CXL controller in the first memory expansion control chip and a second CXL controller in the second memory expansion control chip, the first memory expansion control chip and the second memory expansion control chip are respectively connected to corresponding memories through memory connectors, and the PICE slot of the memory expansion module includes an X8 slot and an X16 slot; the programmable logic device is an erasable and editable logic device; The memory expansion module includes a multiplexer; wherein the method includes: When the X8 slot is connected to the host through the X8 gold finger connector, the programmable logic device is triggered to send a presence signal to the first memory expansion control chip and the second memory expansion control chip through the system management bus based on the first high-level hot plug detection signal; When the X16 slot is connected to the host through the X16 gold finger connector, triggering the programmable logic device to send a presence signal to the first memory expansion control chip and the second memory expansion control chip through the system management bus based on the second high-level hot plug detection signal; Selecting a target memory expansion control chip from the first memory expansion control chip and the second memory expansion control chip based on the in-place signal, so that the target memory expansion control chip forwards the data transmitted by the host to the corresponding memory; The step of selecting a target memory expansion control chip from the first memory expansion control chip and the second memory expansion control chip based on the in-place signal includes: If the in-place signal indicates that the X8 slot is connected to the host through an X8 gold finger connector, the first memory expansion control chip is determined as the target memory expansion control chip, and the second memory expansion control chip is controlled to be switched to a low power consumption state; if the in-place signal indicates that the X16 slot is connected to the host through an X16 gold finger connector, the first memory expansion control chip and the second memory expansion control chip are both determined as the target memory expansion control chip; The process of triggering the programmable logic device to send a presence signal to the first memory expansion control chip and the second memory expansion control chip through the system management bus based on the second high-level hot plug detection signal also includes: The programmable logic device is triggered to send a fourth enable signal to the multiplexer based on the second high-level hot plug detection signal, so that the multiplexer selects the second multiplexed signal path between the X16 gold finger connector based on the fourth enable signal, receives the second multiplexed signal of the lower 8 bits sent by the X16 gold finger connector through the second multiplexed signal path, and sends the second multiplexed signal to the first memory expansion control chip; the second multiplexed signal of the upper 8 bits sent by the X16 gold finger connector is sent to the second memory expansion control chip through a path where the X16 gold finger connector and the second memory expansion control chip are directly interconnected.

2. The data transmission method of the memory expansion module according to claim 1, characterized in that: The memory expansion module includes a clock buffer; the process of triggering the programmable logic device to send a presence signal to the first memory expansion control chip and the second memory expansion control chip based on the first high-level hot plug detection signal also includes: The programmable logic device is triggered to send a first enable signal to the clock buffer based on a first high-level hot plug detection signal, so that the clock buffer selects a first clock signal path between the clock buffer and the X8 gold finger connector based on the first enable signal, receives a first clock signal sent by the X8 gold finger connector through the first clock signal path, and sends the first clock signal to the first memory expansion control chip; Correspondingly, the process of triggering the programmable logic device to send a presence signal to the first memory expansion control chip and the second memory expansion control chip based on the second high-level hot plug detection signal also includes: The programmable logic device is triggered based on the second high-level hot plug detection signal to send a second enable signal to the clock buffer, so that the clock buffer selects the second clock signal path between the clock buffer and the X16 gold finger connector based on the second enable signal, receives the second clock signal issued by the X16 gold finger connector through the second clock signal path, and sends the second clock signal to the first memory extension control chip and the second memory extension control chip.

3. The data transmission method of the memory expansion module according to claim 1, characterized in that: The process of triggering the programmable logic device to send a presence signal to the first memory expansion control chip and the second memory expansion control chip based on the first high-level hot plug detection signal also includes: The programmable logic device is triggered based on the first high-level hot plug detection signal to send a third enable signal to the multiplexer, so that the multiplexer selects the first multiplexed signal path between the X8 gold finger connector and the multiplexer based on the third enable signal, receives the first multiplexed signal sent by the X8 gold finger connector through the first multiplexed signal path, and sends the first multiplexed signal to the first memory expansion control chip.

4. The data transmission method of the memory expansion module according to claim 1, characterized in that: The memory connector includes a first memory connector and a second memory connector corresponding to the first memory expansion control chip, and a third memory connector and a fourth memory connector corresponding to the second memory expansion control chip; The target memory expansion control chip forwards the data transmitted by the host to the corresponding memory, and also includes: A first target memory connector and a second target memory connector corresponding to the target memory expansion control chip are selected from the first memory connector, the second memory connector, the third memory connector and the fourth memory connector.

5. The data transmission method of the memory expansion module according to claim 4, characterized in that: The target memory expansion control chip forwards the data transmitted by the host to the corresponding memory, including: The target memory expansion sends first data including a chip control data signal, a data selection signal, an ECC check signal, a first chip select signal, and a first differential clock signal to the first target memory connector through a first memory signal path between the target memory expansion and the first target memory connector, so that the first target memory connector sends the first data to the corresponding memory.

6. The data transmission method of the memory expansion module according to claim 4, characterized in that: The target memory expansion control chip forwards the data transmitted by the host to the corresponding memory, including: The target memory expansion sends second data including a chip control data signal, a data selection signal, an ECC check signal, a second chip select signal, and a second differential clock signal to the second target memory connector through a second memory signal path between the target memory expansion and the second target memory connector, so that the second target memory connector sends the second data to the corresponding memory.

7. A data transmission device for a memory expansion module, characterized in that: The invention is applied to a memory expansion module including a first memory expansion control chip, a second memory expansion control chip and a programmable logic device, wherein the programmable logic device is respectively connected to a first CXL controller in the first memory expansion control chip and a second CXL controller in the second memory expansion control chip, the first memory expansion control chip and the second memory expansion control chip are respectively connected to corresponding memories through memory connectors, and the PICE slot of the memory expansion module includes an X8 slot and an X16 slot; the programmable logic device is an erasable and editable logic device; The memory expansion module includes a multiplexer; wherein the device includes: A first trigger module is used for triggering the programmable logic device to send a presence signal to the first memory expansion control chip and the second memory expansion control chip through a system management bus based on a first high-level hot plug detection signal when the X8 slot is connected to the host through an X8 gold finger connector; A second trigger module is used for triggering the programmable logic device to send a presence signal to the first memory expansion control chip and the second memory expansion control chip through a system management bus based on a second high-level hot plug detection signal when the X16 slot is connected to the host through the X16 gold finger connector; a data transmission module, configured to select a target memory expansion control chip from the first memory expansion control chip and the second memory expansion control chip based on the in-place signal, so that the target memory expansion control chip forwards the data transmitted by the host to the corresponding memory; Wherein, the data transmission module is specifically used for: If the in-place signal indicates that the X8 slot is connected to the host through an X8 gold finger connector, the first memory expansion control chip is determined as the target memory expansion control chip, and the second memory expansion control chip is controlled to be switched to a low power consumption state; if the in-place signal indicates that the X16 slot is connected to the host through an X16 gold finger connector, the first memory expansion control chip and the second memory expansion control chip are both determined as the target memory expansion control chip; The data transmission device of the memory expansion module is specifically used for: The programmable logic device is triggered to send a fourth enable signal to the multiplexer based on the second high-level hot plug detection signal, so that the multiplexer selects the second multiplexed signal path between the X16 gold finger connector based on the fourth enable signal, receives the second multiplexed signal of the lower 8 bits sent by the X16 gold finger connector through the second multiplexed signal path, and sends the second multiplexed signal to the first memory expansion control chip; the second multiplexed signal of the upper 8 bits sent by the X16 gold finger connector is sent to the second memory expansion control chip through a path where the X16 gold finger connector and the second memory expansion control chip are directly interconnected.

8. An electronic device, characterized in that: include: Memory, used to store computer programs; A processor is used to execute the computer program to implement the steps of the data transmission method of the memory expansion module as described in any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that: Used to store computer programs; wherein, when the computer program is executed by a processor, the steps of the data transmission method of the memory expansion module as described in any one of claims 1 to 6 are implemented.

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