DMA engine module design method and system based on FPGA

Abstract

The invention belongs to the technical field of PCIE high-speed serial interfaces, and discloses a DMA engine module design method and system based on an FPGA. The system comprises a DMA sending engine module, a DMA receiving engine module and a DMA interruption module. According to the invention, two channels are preset for frequency selection or different mode selection, the channels are in a full duplex mode, and transmission-in and transmission-out do not interfere with each other and are completely controllable. And a return comparison self-checking function is added, so that whether the current channel operates normally or not can be judged quickly and conveniently. According to the DMA sending and receiving state machine transfer method provided by the invention, more efficient transmission can be realized on the premise of using fewer resources.

Description

Technical Field

[0001] The invention belongs to the technical field of PCIE high-speed serial interface, and in particular relates to a DMA engine module design method and system based on FPGA. Background Art

[0002] As modern communication systems have higher and higher requirements for bandwidth, bus performance is also gradually upgraded. Traditional buses have been eliminated because they cannot adapt to the requirements of high-speed data transmission. After continuous revision and development, the application field of PCI technology has been greatly limited. PCIE bus has become mainstream because it has greatly improved the transmission rate and has a good application prospect. PCIE can effectively solve the defects of PCI bus and provide a larger bus bandwidth. The bus frequency of PCIE V3.0 can reach up to 4Ghz.

[0003] Through the above analysis, the problems and defects of the prior art are: the prior art communication cannot utilize less FPGA logic resources to implement the DMA receiving function and sending function of PCIE, and the transmission efficiency is low. Summary of the invention

[0004] In order to overcome the problems existing in the related art, the disclosed embodiments of the present invention provide a DMA engine module design method and system based on FPGA, and specifically relate to a DMA engine module design method based on FPGA k7 series PCIE interface.

[0005] The technical solution is as follows: a DMA engine module design system based on FPGA, the system comprising:

[0006] The DMA sending engine module determines the invalid state of the DMA write arbitration request and the read arbitration request, and determines the valid indication signal of the internal cache space of the IP core, executes the corresponding enable control mode, and determines the binary count size of the flow control counter;

[0007] The DMA receiving engine module is used to execute the receiving packet TLP header data and the receiving packet TLP data load by judging the length signal identifier and the receiving error indication signal identifier, and store them in the memory;

[0008] The DMA interrupt module is used to execute the corresponding read and write interrupt request signals and execute the corresponding interrupt responses by judging whether the MSI interrupt is enabled and the legacy interrupt is enabled.

[0009] The signal transmission of the DMA transmission engine module and the signal reception of the DMA reception engine module (2) do not interfere with each other and operate independently.

[0010] The FPGA-based DMA engine module design system adopts bus-master DMA, which uses the device on the bus as a DMA controller. The DMA controller controls the entire DMA transmission process by configuring the user-configured DMA registers and directly moves the data to a storage unit in the computer memory.

[0011] Another object of the present invention is to provide a DMA engine module design method based on FPGA, comprising:

[0012] The designed DMA sending engine module is used to determine the invalid status of DMA write arbitration request and read arbitration request, as well as the valid indication signal of the internal cache space of the IP core, to execute the corresponding enable control mode, and to determine the binary count size of the flow control counter;

[0013] Receive the signal sent by the DMA sending engine module, use the designed DMA receiving engine module to judge the length signal identifier and the receiving error indication signal identifier, execute the receiving packet TLP header data and the receiving packet TLP data load, and store them in the memory;

[0014] The designed DMA interrupt module is used to judge the MSI interrupt enable and legacy interrupt enable, and execute the corresponding read and write interrupt request signals and the corresponding interrupt responses respectively.

[0015] Furthermore, the DMA send engine module design includes:

[0016] (1) Wait for the PCIE link indication signal to be pulled high;

[0017] (2) DMA write arbitration request and read arbitration request are invalid, DMA write start signal is pulled high, cache data FIFO data is not empty, the IP core internal cache space valid indication signal is 1, and bus master mode is enabled;

[0018] (3) DMA write arbitration request and read arbitration request are invalid, DMA read start signal is pulled high, IP core internal cache space valid indication signal is 1, bus master mode is enabled, non-forwarding mode is enabled, flow control counter is not equal to 16;

[0019] (4) DMA write arbitration request and read arbitration request are invalid, the valid indication signal of the internal cache space of the IP core is 1, and the bar0 read operation request signal is pulled high;

[0020] (5) DMA write arbitration request and read arbitration request are invalid, the valid indication signal of the IP core internal cache space is 1, and the bar1 read operation request signal is pulled high;

[0021] (6) Send the header information of the TIP message, which lasts for one clock cycle;

[0022] (7) Send the header information and data information of the TIP message, maintaining one clock cycle;

[0023] (8) Send the data information of the TIP message, maintaining 254 clock cycles;

[0024] (9) Send the last 32 bits of data of the TLP message and calculate the number of TLP messages to maintain one clock cycle;

[0025] (10) The TLP message is sent and enters the next state.

[0026] Further, after step (10), the following steps are performed:

[0027] (11) The valid indication signal of the internal cache space of the IP core is 1, and the bar0 read operation request signal is pulled high;

[0028] (12) The valid indication signal of the internal cache space of the IP core is 1, and the bar1 read operation request signal is pulled high;

[0029] (13) DMA read arbitration request is invalid, DMA read start signal is pulled high, IP core internal cache space valid indication signal is 1, bus master mode is enabled, non-forwarding mode is enabled, flow control counter is not equal to 16;

[0030] (14) The DMA write arbitration request is invalid, the DMA write start signal is pulled high, the cache data FIFO data is not empty, the IP core internal cache space valid indication signal is 1, and the bus master mode is enabled.

[0031] Furthermore, after step (14), it is necessary to carry out:

[0032] (a) Send the memory read request packet header 1, which lasts for one clock cycle;

[0033] (b) Sending memory read request packet header 2, maintaining one clock cycle;

[0034] (c) Sending the number of memory read request messages is completed, and it lasts for one clock cycle;

[0035] (d) The valid indication signal of the internal cache space of the IP core is 1, and the bar0 read operation request signal is pulled high;

[0036] The valid indication signal of the internal cache space of the IP core is 1, and the bar1 read operation request signal is pulled high;

[0037] DMA write arbitration request is invalid, DMA write start signal is pulled high, cache data FIFO data is not empty, IP core internal cache space valid indication signal is 1, bus master mode is enabled;

[0038] DMA read arbitration request is invalid, DMA read start signal is pulled high, IP core internal cache space valid indication signal is 1, bus master mode is enabled, non-forwarding mode is enabled, flow control counter is not equal to 16.

[0039] (e) Maintain one clock cycle;

[0040] Send read bar0 CPLD to complete the message packet header 1, maintaining one clock cycle;

[0041] Send read bar0 CPLD to complete the message packet header 2, maintaining one clock cycle;

[0042] The valid indication signal of the internal cache space of the IP core is 1, and the bar1 read operation request signal is pulled high;

[0043] DMA write arbitration request is invalid, DMA write start signal is pulled high, cache data FIFO data is not empty, IP core internal cache space valid indication signal is 1, bus master mode is enabled;

[0044] DMA read arbitration request is invalid, DMA read start signal is pulled high, IP core internal cache space valid indication signal is 1, bus master mode is enabled, non-forwarding mode is enabled, flow control counter is not equal to 16;

[0045] (f) Send the bar1 CPLD to complete the message packet header 1, which lasts for one clock cycle;

[0046] Send read bar1 CPLD to complete packet header 2, maintaining one clock cycle;

[0047] The valid indication signal of the internal cache space of the IP core is 1, and the bar0 read operation request signal is pulled high;

[0048] DMA write arbitration request is invalid, DMA write start signal is pulled high, cache data FIFO data is not empty, IP core internal cache space valid indication signal is 1, bus master mode is enabled;

[0049] DMA read arbitration request is invalid, DMA read start signal is pulled high, IP core internal cache space valid indication signal is 1, bus master mode is enabled, non-forwarding mode is enabled, flow control counter is not equal to 16.

[0050] Furthermore, the DMA receiving engine module design includes:

[0051] (i) Wait for the PCIE link indication signal to be pulled high;

[0052] (ii) TYPE is the completion packet format type, CS is 0, the receive error indication signal is 0, and the read start signal is pulled high;

[0053] The length signal flag is 1, the receive error indication signal is 0, and TYPE is the memory write request packet format, and the bar0 write operation indication signal is pulled high;

[0054] The length signal flag is 1, the receive error indication signal is 0, and TYPE is the memory write request packet format, and the bar1 write operation indication signal is pulled high;

[0055] The length signal flag is 1, the receive error indication signal is 0, and TYPE is the memory read request packet format, and the bar0 read operation indication signal is pulled high;

[0056] The length signal flag is 1, the receive error indication signal is 0, and TYPE is the memory read request packet format, and the bar1 read operation indication signal is pulled high;

[0057] (iii) bar0 write operation completed;

[0058] bar1 write operation completed;

[0059] bar0 read arbitration;

[0060] bar0 read completed;

[0061] bar1 read arbitration;

[0062] bar1 read completed;

[0063] (iv) receiving the TLP header data of the completion packet;

[0064] The receiving completion packet TLP data payload is completed.

[0065] Furthermore, the DMA interrupt module design includes:

[0066] Step 1, wait for the PCIE link indication signal to be pulled high;

[0067] Step 2, MSI interrupt is enabled, and the MSI interrupt request signal is pulled high after DMA writing is completed;

[0068] MSI interrupt is enabled, and the MSI interrupt request signal is pulled high after DMA read is completed;

[0069] MSI interrupt is enabled, and the DMA external request interrupt request signal is pulled high;

[0070] Step 3, legacy interrupt is enabled, and the legacy interrupt request signal is pulled high after DMA write is completed;

[0071] The legacy interrupt is enabled, and the DMA read completion legacy interrupt request signal is pulled high;

[0072] The legacy interrupt is enabled, and the DMA external legacy interrupt request signal is pulled high;

[0073] The legacy interrupt is enabled, and the DMA write completion legacy interrupt release request signal is pulled high;

[0074] The legacy interrupt is enabled, and the DMA read completion legacy interrupt release request signal is pulled high;

[0075] Legacy interrupt is enabled, please release the request signal of DMA external legacy interrupt and pull it high;

[0076] Step 3, maintain one clock cycle;

[0077] Step 4, receiving the MSI interrupt response signal;

[0078] Maintain one clock cycle;

[0079] Step 5, receiving the legacy interrupt response signal;

[0080] Maintain one clock cycle to release the interrupt information configuration;

[0081] Receive legacy interrupt response signal.

[0082] Furthermore, the FPGA-based DMA engine module design method runs on a functional logic state machine to perform communication transmission.

[0083] Combined with all the above technical solutions, the beneficial effects of the present invention are as follows: PCIE mainly has two working modes, one is PIO working mode, and the other is DMA working mode. PIO is mainly used for small data volume or double word transmission, and DMA is mainly used for data block transmission, which is suitable for large data volume transmission. The larger the data volume, the more obvious the advantages of the DMA working mode. In order to realize PCIE transmission of high-speed data, the present invention provides an FPGA-based Endpoint state machine transfer and design method based on FPGA. The DMA receiving function and sending function of PCIE are realized by using fewer FPGA logic resources. Dual channels are preset for frequency selection or different mode selection. The channel is in full-duplex mode, and the outgoing and incoming transmissions do not interfere with each other and are fully controllable. The return comparison self-test function is added, so that it can quickly and conveniently determine whether the current channel is operating normally. The DMA sending and receiving state machine transfer method provided by the present invention can achieve more efficient transmission under the premise of using fewer resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0084] The accompanying drawings herein are incorporated in and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the description, serve to explain the principles of the present disclosure;

[0085] Figure 1 It is a schematic diagram of a DMA engine module design system based on FPGA provided by an embodiment of the present invention;

[0086] In the figure: 1. DMA sending engine module; 2. DMA receiving engine module; 3. DMA interrupt module. DETAILED DESCRIPTION

[0087] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present invention, so the present invention is not limited by the specific implementation disclosed below.

[0088] Embodiment 1, because need to transmit a large amount of data with computer end, if adopt common PIO (Programming I / O) transmission mechanism, can only send one double word at a time, need CPU in computer to participate in. When carrying out transmission of large amount of data, CPU just can not carry out other work, will seriously affect computer performance like this.

[0089] Therefore, the FPGA-based DMA engine module design system provided by the embodiment of the present invention adopts the DMA (Direct Memory Access) mechanism to perform large-capacity data transmission, bypassing the CPU through DMA transmission. The essence of DMA transmission is to directly copy data from one address space to another address space. The CPU is only used to perform initialization-related controls, and the transmission process is completed by the DMA controller. DMA can be divided into two types: system DMA and bus master DMA (Bus Master DMA), which are respectively described as follows: one is that system DMA uses a separate DMA controller on the bus to control the DMA transmission of two devices on the bus. The other is that bus master DMA uses the device on the bus to act as a DMA controller to control the DMA transmission of the master device and the slave device itself.

[0090] The FPGA-based DMA engine module design system of the present invention adopts bus master DMA, and the user configures the DMA register. The DMA controller controls the entire DMA transmission process by configuring the register, that is, directly moving the data to a certain storage unit in the computer memory.

[0091] Theoretically, a large amount of data can be moved at one time, but in actual transmission, the CPU cannot allocate a large continuous memory space at one time. Therefore, it is necessary to perform multiple DMA transfers, and the CPU processor needs to be interrupted after each transfer is completed, and then the CPU reconfigures the DMA. The following are the core steps to implement the DMA receiving and sending functions, which are responsible for the control of the DMA transmission process. The functional logic state machine of the FPGA-based DMA engine module is analyzed below.

[0092] like Figure 1 As shown, the FPGA-based DMA engine module design system includes: a DMA sending engine module 1, which executes the corresponding enable control mode and determines the binary count size of the flow control counter by judging the invalid state of the DMA write arbitration request and the read arbitration request, and judging the valid indication signal of the internal cache space of the IP core;

[0093] DMA receiving engine module 2, used for executing receiving packet TLP header data and receiving packet TLP data load by judging length signal identifier and receiving error indication signal identifier, and storing them in memory;

[0094] The DMA interrupt module 3 is used to execute the corresponding read and write interrupt request signals and execute the corresponding interrupt responses by judging whether the MSI interrupt is enabled and the legacy interrupt is enabled.

[0095] The present invention also provides a DMA engine module design method based on FPGA, comprising:

[0096] The designed DMA sending engine module is used to determine the invalid status of DMA write arbitration request and read arbitration request, as well as the valid indication signal of the internal cache space of the IP core, to execute the corresponding enable control mode, and to determine the binary count size of the flow control counter;

[0097] Receive the signal sent by the DMA sending engine module, use the designed DMA receiving engine module to judge the length signal identifier and the receiving error indication signal identifier, execute the receiving packet TLP header data and the receiving packet TLP data load, and store them in the memory;

[0098] The designed DMA interrupt module is used to judge the MSI interrupt enable and legacy interrupt enable, and execute the corresponding read and write interrupt request signals and the corresponding interrupt responses respectively.

[0099] Among them, the DMA sending engine module 1 is designed as follows:

[0100] First, wait for the PCIE link indication signal to be pulled high;

[0101] Furthermore, the DMA write arbitration request and the read arbitration request are invalid, the DMA write start signal is pulled high, the cache data FIFO data is in a non-empty state, the IP core internal cache space valid indication signal is 1, and the bus master mode is enabled.

[0102] Furthermore, the DMA write arbitration request and read arbitration request are invalid, the DMA read start signal is pulled high, the IP core internal cache space valid indication signal is 1, the bus master mode is enabled, the non-forwarding mode is enabled, and the flow control counter is not equal to 16.

[0103] Furthermore, the DMA write arbitration request and read arbitration request are invalid, the valid indication signal of the internal cache space of the IP core is 1, and the bar0 read operation request signal is pulled high;

[0104] Furthermore, the DMA write arbitration request and read arbitration request are invalid, the valid indication signal of the internal cache space of the IP core is 1, and the bar1 read operation request signal is pulled high;

[0105] Further, the header information of the TIP message is sent, and one clock cycle is maintained;

[0106] Further, the header information and data information of the TIP message are sent, and one clock cycle is maintained;

[0107] Furthermore, the data information of the TIP message is sent, maintaining 254 clock cycles;

[0108] Further, the last 32 bits of data of the TLP message are sent, and the number of TLP messages is calculated to maintain one clock cycle;

[0109] Further, the TLP message is sent and enters the next state;

[0110] Furthermore, the valid indication signal of the internal cache space of the IP core is 1, and the bar0 read operation request signal is pulled high;

[0111] Furthermore, the valid indication signal of the cache space inside the IP core is 1, and the bar1 read operation request signal is pulled high;

[0112] Furthermore, the DMA read arbitration request is invalid, the DMA read start signal is pulled high, the IP core internal cache space valid indication signal is 1, the bus master mode is enabled, the non-forwarding mode is enabled, and the flow control counter is not equal to 16.

[0113] Furthermore, the DMA write arbitration request is invalid, the DMA write start signal is pulled high, the cache data FIFO data is in a non-empty state, the IP core internal cache space valid indication signal is 1, and the bus master mode is enabled.

[0114] Further, a memory read request message packet header 1 is sent, and a clock cycle is maintained;

[0115] Further, a memory read request message packet header 2 is sent, and one clock cycle is maintained;

[0116] Further, the number of memory read request messages sent is completed and maintained for one clock cycle;

[0117] Furthermore, the valid indication signal of the internal cache space of the IP core is 1, and the bar0 read operation request signal is pulled high;

[0118] Furthermore, the valid indication signal of the cache space inside the IP core is 1, and the bar1 read operation request signal is pulled high;

[0119] Furthermore, the DMA write arbitration request is invalid, the DMA write start signal is pulled high, the cache data FIFO data is in a non-empty state, the IP core internal cache space valid indication signal is 1, and the bus master mode is enabled.

[0120] Furthermore, the DMA read arbitration request is invalid, the DMA read start signal is pulled high, the IP core internal cache space valid indication signal is 1, the bus master mode is enabled, the non-forwarding mode is enabled, and the flow control counter is not equal to 16.

[0121] Further, one clock cycle is maintained;

[0122] Further, the CPLD sends a read bar0 completion message packet header 1, which lasts for one clock cycle;

[0123] Further, the CPLD sends a read bar0 completion message packet header 2, which lasts for one clock cycle;

[0124] Furthermore, the valid indication signal of the cache space inside the IP core is 1, and the bar1 read operation request signal is pulled high;

[0125] Furthermore, the DMA write arbitration request is invalid, the DMA write start signal is pulled high, the cache data FIFO data is in a non-empty state, the IP core internal cache space valid indication signal is 1, and the bus master mode is enabled.

[0126] Furthermore, the DMA read arbitration request is invalid, the DMA read start signal is pulled high, the IP core internal cache space valid indication signal is 1, the bus master mode is enabled, the non-forwarding mode is enabled, and the flow control counter is not equal to 16.

[0127] Further, the CPLD sends a read bar1 to complete the message packet header 1, which lasts for one clock cycle;

[0128] Further, the CPLD sends a read bar1 to complete the message packet header 2, which lasts for one clock cycle;

[0129] Furthermore, the valid indication signal of the internal cache space of the IP core is 1, and the bar0 read operation request signal is pulled high;

[0130] Furthermore, the DMA write arbitration request is invalid, the DMA write start signal is pulled high, the cache data FIFO data is in a non-empty state, the IP core internal cache space valid indication signal is 1, and the bus master mode is enabled.

[0131] Furthermore, the DMA read arbitration request is invalid, the DMA read start signal is pulled high, the IP core internal cache space valid indication signal is 1, the bus master mode is enabled, the non-forwarding mode is enabled, and the flow control counter is not equal to 16.

[0132] DMA receiving engine module design:

[0133] First, wait for the PCIE link indication signal to be pulled high;

[0134] Furthermore, TYPE is the completion packet format type, CS is 0, the receive error indication signal is 0, and the read start signal is pulled high;

[0135] Furthermore, the length signal flag is 1, the receive error indication signal is 0, and TYPE is the memory write request packet format, and the bar0 write operation indication signal is pulled high.

[0136] Furthermore, the length signal flag is 1, the receive error indication signal is 0, and TYPE is the memory write request packet format, and the bar1 write operation indication signal is pulled high.

[0137] Furthermore, the length signal flag is 1, the reception error indication signal is 0, and the TYPE is the memory read request packet format, and the bar0 read operation indication signal is pulled high.

[0138] Furthermore, the length signal flag is 1, the reception error indication signal is 0, and the TYPE is the memory read request packet format, and the bar1 read operation indication signal is pulled high.

[0139] Furthermore, the bar0 write operation is completed.

[0140] Furthermore, the write operation of bar1 is completed.

[0141] Further, bar0 reads arbitration.

[0142] Furthermore, the reading of bar0 is completed.

[0143] Further, bar1 reads arbitration.

[0144] Further, the reading of bar1 is completed.

[0145] Furthermore, the receiving completion packet TLP header data is completed.

[0146] Furthermore, the receiving completion packet TLP data load is completed.

[0147] DMA interrupt module design:

[0148] First, wait for the PCIE link indication signal to be pulled high;

[0149] Further, the MSI interrupt is enabled, and the MSI interrupt request signal is pulled high when the DMA write is completed;

[0150] Further, the MSI interrupt is enabled, and the DMA read completes the MSI interrupt request signal and pulls high;

[0151] Further, the MSI interrupt is enabled, and the DMA external request interrupt request signal is pulled high;

[0152] Furthermore, the legacy interrupt is enabled, and the DMA write completion legacy interrupt request signal is pulled high;

[0153] Furthermore, the legacy interrupt is enabled, and the DMA read completion legacy interrupt request signal is pulled high;

[0154] Furthermore, the legacy interrupt is enabled, and the DMA external legacy interrupt request signal is pulled high;

[0155] Furthermore, the legacy interrupt is enabled, and the DMA write completion legacy interrupt release request signal is pulled high;

[0156] Furthermore, the legacy interrupt is enabled, and the DMA read completion legacy interrupt release request signal is pulled high;

[0157] Furthermore, the legacy interrupt is enabled, and the DMA external legacy interrupt release request signal is pulled high;

[0158] Further, one clock cycle is maintained;

[0159] Further, an MSI interrupt response signal is received;

[0160] Further, one clock cycle is maintained;

[0161] Further, a legacy interrupt response signal is received;

[0162] Further, a clock cycle is maintained to release the interrupt information configuration;

[0163] Furthermore, a legacy interrupt response signal is received.

[0164] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0165] Since the information interaction, execution process, etc. between the above-mentioned devices / units are based on the same concept as the method embodiment of the present invention, their specific functions and technical effects can be found in the method embodiment part and will not be repeated here.

[0166] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated in one processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of the present invention. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment.

[0167] An embodiment of the present invention further provides a computer device, which includes: at least one processor, a memory, and a computer program stored in the memory and executable on the at least one processor, wherein the processor implements the steps in any of the above-mentioned method embodiments when executing the computer program.

[0168] An embodiment of the present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in the above-mentioned method embodiments can be implemented.

[0169] An embodiment of the present invention further provides an information data processing terminal, which, when executed on an electronic device, provides a user input interface to implement the steps in the above method embodiments. The information data processing terminal is not limited to mobile phones, computers, and switches.

[0170] An embodiment of the present invention further provides a server, which is used to provide a user input interface to implement the steps in the above method embodiments when executed on an electronic device.

[0171] An embodiment of the present invention provides a computer program product. When the computer program product runs on an electronic device, the electronic device can implement the steps in the above-mentioned method embodiments when executing the computer program product.

[0172] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the processes in the above-mentioned embodiment method, which can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may at least include: any entity or device that can carry the computer program code to the camera / terminal device, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium. For example, a USB flash drive, a mobile hard disk, a disk or an optical disk.

[0173] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any modifications, equivalent substitutions and improvements made by any technician familiar with the technical field within the technical scope disclosed by the present invention and within the spirit and principles of the present invention should be covered within the protection scope of the present invention.

Claims

1. A DMA engine module design system based on FPGA, characterized in that: The system includes: The DMA sending engine module (1) executes the corresponding enabling control mode and determines the binary count size of the flow control counter by judging the invalid state of the DMA write arbitration request and the read arbitration request and judging the valid indication signal of the internal cache space of the IP core; The DMA receiving engine module (2) is used to execute receiving packet TLP header data and receiving packet TLP data load by judging the length signal identifier and the receiving error indication signal identifier, and store them in the memory; The DMA interrupt module (3) is used to execute corresponding read and write interrupt request signals and execute corresponding interrupt responses respectively by judging whether the MSI interrupt is enabled and the legacy interrupt is enabled.

2. The FPGA-based DMA engine module design system according to claim 1, characterized in that: The signal transmission of the DMA transmission engine module (1) and the signal reception of the DMA reception engine module (2) do not interfere with each other and operate independently.

3. The FPGA-based DMA engine module design system according to claim 1, characterized in that: The system adopts bus master DMA, which uses the device on the bus as a DMA controller. The DMA controller controls the entire DMA transmission process by configuring the DMA registers configured by the user, and directly moves the data to a storage unit in the computer memory.

4. A DMA engine module design method based on FPGA, characterized in that: The method is applied to the FPGA-based DMA engine module design system according to any one of claims 1 to 3, and the method comprises: The designed DMA sending engine module (1) is used to determine the invalid state of the DMA write arbitration request and the read arbitration request, and to determine the valid indication signal of the internal cache space of the IP core, to execute the corresponding enable control mode, and to determine the binary count size of the flow control counter; Receive the signal sent by the DMA sending engine module (1), and use the designed DMA receiving engine module (2) to judge the length signal identifier and the receiving error indication signal identifier, execute the receiving packet TLP header data and the receiving packet TLP data load, and store them in the memory; The designed DMA interrupt module (3) is used to judge whether the MSI interrupt is enabled and the legacy interrupt is enabled, and then the corresponding read and write interrupt request signals and the corresponding interrupt responses are respectively executed.

5. The FPGA-based DMA engine module design method according to claim 4, characterized in that: The DMA send engine module design includes: (1) Wait for the PCIE link indication signal to be pulled high; (2) DMA write arbitration request and read arbitration request are invalid, DMA write start signal is pulled high, cache data FIFO data is not empty, the IP core internal cache space valid indication signal is 1, and bus master mode is enabled; (3) DMA write arbitration request and read arbitration request are invalid, DMA read start signal is pulled high, IP core internal cache space valid indication signal is 1, bus master mode is enabled, non-forwarding mode is enabled, flow control counter is not equal to 16; (4) DMA write arbitration request and read arbitration request are invalid, the valid indication signal of the internal cache space of the IP core is 1, and the bar0 read operation request signal is pulled high; (5) DMA write arbitration request and read arbitration request are invalid, the valid indication signal of the IP core internal cache space is 1, and the bar1 read operation request signal is pulled high; (6) Send the header information of the TIP message, which lasts for one clock cycle; (7) Send the header information and data information of the TIP message, maintaining one clock cycle; (8) Send the data information of the TIP message, maintaining 254 clock cycles; (9) Send the last 32 bits of data of the TLP message and calculate the number of TLP messages to maintain one clock cycle; (10) The TLP message is sent and enters the next state.

6. The FPGA-based DMA engine module design method according to claim 5, characterized in that: After step (10), proceed with: (11) The valid indication signal of the internal cache space of the IP core is 1, and the bar0 read operation request signal is pulled high; (12) The valid indication signal of the internal cache space of the IP core is 1, and the bar1 read operation request signal is pulled high; (13) DMA read arbitration request is invalid, DMA read start signal is pulled high, IP core internal cache space valid indication signal is 1, bus master mode is enabled, non-forwarding mode is enabled, flow control counter is not equal to 16; (14) The DMA write arbitration request is invalid, the DMA write start signal is pulled high, the cache data FIFO data is not empty, the IP core internal cache space valid indication signal is 1, and the bus master mode is enabled.

7. The FPGA-based DMA engine module design method according to claim 6, characterized in that: After step (14), you need to do the following: (a) Send the memory read request packet header 1, which lasts for one clock cycle; (b) Sending memory read request packet header 2, maintaining one clock cycle; (c) Sending the number of memory read request messages is completed, and it lasts for one clock cycle; (d) The valid indication signal of the internal cache space of the IP core is 1, and the bar0 read operation request signal is pulled high; The valid indication signal of the internal cache space of the IP core is 1, and the bar1 read operation request signal is pulled high; DMA write arbitration request is invalid, DMA write start signal is pulled high, cache data FIFO data is not empty, IP core internal cache space valid indication signal is 1, bus master mode is enabled; DMA read arbitration request is invalid, DMA read start signal is pulled high, IP core internal cache space valid indication signal is 1, bus master mode is enabled, non-forwarding mode is enabled, flow control counter is not equal to 16; (e) Maintain one clock cycle; Send read bar0 CPLD to complete the message packet header 1, maintaining one clock cycle; Send read bar0 CPLD to complete the message packet header 2, maintaining one clock cycle; The valid indication signal of the internal cache space of the IP core is 1, and the bar1 read operation request signal is pulled high; DMA write arbitration request is invalid, DMA write start signal is pulled high, cache data FIFO data is not empty, IP core internal cache space valid indication signal is 1, bus master mode is enabled; DMA read arbitration request is invalid, DMA read start signal is pulled high, IP core internal cache space valid indication signal is 1, bus master mode is enabled, non-forwarding mode is enabled, flow control counter is not equal to 16; (f) Send the bar1 CPLD to complete the message packet header 1, which lasts for one clock cycle; Send read bar1 CPLD to complete packet header 2, maintaining one clock cycle; The valid indication signal of the internal cache space of the IP core is 1, and the bar0 read operation request signal is pulled high; DMA write arbitration request is invalid, DMA write start signal is pulled high, cache data FIFO data is not empty, IP core internal cache space valid indication signal is 1, bus master mode is enabled; DMA read arbitration request is invalid, DMA read start signal is pulled high, IP core internal cache space valid indication signal is 1, bus master mode is enabled, non-forwarding mode is enabled, flow control counter is not equal to 16.

8. The FPGA-based DMA engine module design method according to claim 4, characterized in that: The DMA receiving engine module design includes: (i) Wait for the PCIE link indication signal to be pulled high; (ii) TYPE is the completion packet format type, CS is 0, the receive error indication signal is 0, and the read start signal is pulled high; The length signal flag is 1, the receive error indication signal is 0, and TYPE is the memory write request packet format, and the bar0 write operation indication signal is pulled high; The length signal flag is 1, the receive error indication signal is 0, and TYPE is the memory write request packet format, and the bar1 write operation indication signal is pulled high; The length signal flag is 1, the receive error indication signal is 0, and TYPE is the memory read request packet format, and the bar0 read operation indication signal is pulled high; The length signal flag is 1, the receive error indication signal is 0, and TYPE is the memory read request packet format, and the bar1 read operation indication signal is pulled high; (iii) bar0 write operation completed; bar1 write operation completed; bar0 read arbitration; bar0 read completed; bar1 read arbitration; bar1 read completed; (iv) receiving the TLP header data of the completion packet; The receiving completion packet TLP data payload is completed.

9. The FPGA-based DMA engine module design method according to claim 4, characterized in that: The DMA interrupt module design includes: Step 1, wait for the PCIE link indication signal to be pulled high; Step 2, MSI interrupt is enabled, and the MSI interrupt request signal is pulled high after DMA writing is completed; MSI interrupt is enabled, and the MSI interrupt request signal is pulled high after DMA read is completed; MSI interrupt is enabled, and the DMA external request interrupt request signal is pulled high; Step 3, legacy interrupt is enabled, and the legacy interrupt request signal is pulled high after DMA write is completed; The legacy interrupt is enabled, and the DMA read completion legacy interrupt request signal is pulled high; The legacy interrupt is enabled, and the DMA external legacy interrupt request signal is pulled high; The legacy interrupt is enabled, and the DMA write completion legacy interrupt release request signal is pulled high; The legacy interrupt is enabled, and the DMA read completion legacy interrupt release request signal is pulled high; Legacy interrupt is enabled, please release the request signal of DMA external legacy interrupt and pull it high; Step 3, maintain one clock cycle; Step 4, receiving the MSI interrupt response signal; Maintain one clock cycle; Step 5, receiving the legacy interrupt response signal; Maintain one clock cycle to release the interrupt information configuration; Receive legacy interrupt response signal.

10. The FPGA-based DMA engine module design method according to claim 4, characterized in that: The method runs on the functional logic state machine for communication transmission.

Images