DRAM (Dynamic Random Access Memory) repair method, test equipment, storage medium and computer program product

Abstract

The invention discloses a DRAM (Dynamic Random Access Memory) repair method, test equipment, a storage medium and a computer program product, relates to the technical field of memory repair, and discloses the DRAM repair method, which can find and locate potential fault points in the DRAM in real time by dynamically acquiring an error unit address of the DRAM to provide an accurate target for subsequent repair work. And judging whether the error unit is really damaged or not by performing a repeated read-write test on the error unit. According to the invention, when the number of errors reported by the error unit reaches the preset number of times, it is judged that the error unit is damaged, misjudgment caused by a single test error is avoided, meanwhile, invalid or excessive tests on the damaged unit are prevented, and the test time and resources are saved. And finally, through a remapping technology, the service life of the chip is prolonged, the system shutdown risk caused by chip faults is reduced, and the stability of the DRAM is improved.

Description

Technical Field

[0001] The present application relates to the field of memory repair technology, and in particular to a DRAM repair method, a test device, a storage medium, and a computer program product. Background Art

[0002] As the number of uses increases, some storage cells in the dynamic random access memory (DRAM) may indeed have data errors. This phenomenon is mainly caused by a variety of factors, usually including increased erase and write times, electromagnetic interference, voltage noise, read interference and temperature, which reduce the stability and reliability of DRAM.

[0003] Data errors in DRAM can cause data corruption or loss, which can result in huge losses for both individual and corporate users. If sensitive information (such as keys) is stored in DRAM, data errors can cause this information to be incorrectly read or tampered with, causing security issues. Summary of the invention

[0004] The main purpose of the present application is to provide a DRAM repair method, test equipment, storage medium and computer program product, aiming to solve the technical problems of DRAM storage unit damage errors and poor stability.

[0005] To achieve the above-mentioned purpose, the present application proposes a DRAM repair method, the method comprising: dynamically obtaining the error unit address of the DRAM; obtaining the error unit address of the DRAM; addressing the error unit according to the error unit address, and performing repeated read and write tests on the error unit; when the error unit reports an error a preset number of times, stopping the test and determining that the error unit is damaged; and remapping the damaged error unit to repair the DRAM.

[0006] In one embodiment, the step of obtaining the address of the error unit of the DRAM includes: detecting data information of the DRAM and obtaining a detection result; locating the error unit of the DRAM based on the detection result; and obtaining the address of the error unit of the DRAM.

[0007] In one embodiment, the step of detecting DRAM data information and obtaining detection results includes: inserting verification information into the DRAM data information to obtain target detection information; verifying the number of error bits of the target detection information; when the number of error bits of the target detection information is single bit, correcting the number of error bits; and generating a detection result when the number of error bits of the target detection information exceeds single bit.

[0008] In one embodiment, the step of performing repeated read and write tests on the error unit according to the address of the error unit includes: locating the error unit according to the address of the error unit; performing read and write tests on the error unit; when the read and write test results are erroneous, reporting an error and returning to execute the step of performing read and write tests on the error unit.

[0009] In one embodiment, the step of remapping the damaged erroneous unit to repair the DRAM chip includes: establishing a mapping relationship between the erroneous unit and the spare unit; storing the mapping relationship in a mapping relationship table; and repairing the DRAM chip by accessing the mapping relationship table.

[0010] In one embodiment, the step of remapping the damaged erroneous unit to repair the DRAM also includes: periodically performing background read and write tests on the DRAM; locating the read and write erroneous unit when the background read and write test results are erroneous; and remapping the read and write erroneous unit to repair the DRAM.

[0011] In addition, to achieve the above-mentioned purpose, the present application also proposes a DRAM repair device, which includes: a data acquisition module, used to obtain the error unit address of the DRAM; a test module, which addresses the error unit according to the error unit address and performs repeated read and write tests on the error unit; when the error unit reports an error a preset number of times, stops the test and determines that the error unit is damaged; and a repair module, which is used to remap the damaged error unit to repair the DRAM.

[0012] In addition, to achieve the above-mentioned purpose, the present application also proposes a DRAM repair test device, which includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program is configured to implement the steps of the DRAM repair method as described above.

[0013] In addition, to achieve the above-mentioned purpose, the present application also proposes a storage medium, which is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by the processor, the steps of the DRAM repair method described above are implemented.

[0014] In addition, to achieve the above-mentioned purpose, the present application also provides a computer program product, which includes a computer program, and when the computer program is executed by a processor, the steps of the DRAM repair method described above are implemented.

[0015] One or more technical solutions proposed in this application have at least the following technical effects: By dynamically acquiring the address of the DRAM's error unit, the potential fault point in the DRAM can be discovered and located in real time, providing a precise target for subsequent repair work. By repeatedly reading and writing the error unit, it is determined whether the error unit is truly damaged. When the error unit reports an error for a preset number of times, it is determined to be damaged, avoiding misjudgment caused by a single test error, and also preventing invalid or excessive testing of damaged units, saving test time and resources. Finally, through the remapping technology, the service life of the chip is extended, the risk of system downtime caused by chip failure is reduced, and the stability of DRAM is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings herein are incorporated in and constitute a part of the specification, illustrate embodiments consistent with the present application, and together with the description, are used to explain the principles of the present application.

[0017] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0018] Figure 1 A flowchart of the first embodiment of the DRAM repair method of the present application is provided; Figure 2 A flow chart of the second embodiment of the DRAM repair method of the present application; Figure 3 This is a schematic diagram of the module structure of the DRAM repair device according to an embodiment of the present application; Figure 4 Schematic diagram of the device structure of the hardware operating environment involved in the DRAM repair method in the embodiment of the present application.

[0019] The purpose, features and advantages of this application will be further described in conjunction with the embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0020] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of the present application and are not used to limit the present application.

[0021] In order to better understand the technical solution of the present application, a detailed description will be given below in conjunction with the accompanying drawings and specific implementation methods.

[0022] DRAM memory cell damage errors are mainly attributed to the combined effects of several key factors. First, the aging and wear of the physical structure is an important reason. As time goes by and the number of uses increases, the physical structure inside the memory cell will gradually degrade, resulting in performance degradation and weakened data retention capabilities. Secondly, the interference and fluctuations of electrical signals cannot be ignored. These interferences may come from the external electromagnetic environment or the instability of the internal circuit. They will interfere with the normal operation of the memory cell and increase the error rate when reading and writing data. In addition, environmental factors such as temperature and humidity also have a significant impact on the stability of DRAM. Too high or too low temperature and humidity changes may accelerate the aging process of the memory cell and reduce its reliability. Finally, the inconsistency of materials and manufacturing processes is also an important factor leading to DRAM stability problems. Minor differences or defects in the manufacturing process may have a significant impact on the performance of the memory cell.

[0023] In summary, these factors work together to reduce the stability of DRAM storage cells and increase the risk of data errors.

[0024] Based on this, the embodiment of the present application provides a DRAM repair method, referring to Figure 1 , Figure 1 A flowchart of the first embodiment of the DRAM repair method of the present application is provided.

[0025] In this embodiment, the DRAM repair method includes steps S10 to S40: Step S10, obtaining the error unit address of the DRAM.

[0026] It should be noted that repairing DRAM first requires accurately locating the damaged memory cell. This is because there are a large number of memory cells in DRAM. If the damaged memory cell cannot be accurately found, effective repair cannot be performed.

[0027] It should be noted that in this embodiment, a damaged storage unit does not necessarily mean an error unit. An error unit refers to a DRAM storage unit that is detected to have an abnormality or error during memory testing, read / write operations, or system operation. These errors may include data read errors, data write errors, access delay anomalies, etc. An error unit is an error unit that is actually manifested under current operating or test conditions.

[0028] It should be noted that damaged cells refer to cells whose DRAM storage cells cannot work properly or whose performance has significantly decreased due to physical wear, electrical failure, environmental factors or manufacturing process problems. Damaged cells are potential or existing failure points in DRAM, which may cause system crashes or data loss at any time.

[0029] It is understandable that a damaged unit may lead to an erroneous unit, but an erroneous unit does not necessarily mean that the unit is damaged, because the error may be caused by a variety of reasons, including temporary electrical interference, software errors, or inaccurate test conditions.

[0030] Specifically, the faulty cells are dynamic and transient, and they depend on specific test conditions, operating environment, or system status. The damaged cells are static and persistent, and they describe the inherent state of the storage cells in the DRAM. The faulty cells may only be temporary and may return to normal by retesting or adjusting the operating conditions. The damaged cells usually require physical repair or replacement to solve the problem. Therefore, we need to prioritize finding the faulty cells in the test and further distinguish the damaged cells from the faulty cells.

[0031] It can be understood that in this embodiment, the error unit address is dynamically acquired, and the dynamic refers to introducing a detection algorithm in the DRAM so as to detect and identify the error unit in the DRAM in real time or near real time.

[0032] It is understood that the dynamic detection algorithm is embedded in the control logic of DRAM, and it is automatically executed when the DRAM performs read and write operations. The algorithm detects potential errors by monitoring the response and data consistency of read and write operations. Once an error is detected, the algorithm records the address of the erroneous unit and may trigger a series of error handling mechanisms, such as retry operations, error reporting, or calling spare redundant storage units.

[0033] Specifically, this embodiment provides an implementation method for dynamically obtaining the address of the error unit of the DRAM: detecting data information of the DRAM and obtaining the detection result; locating the error unit of the DRAM based on the detection result; and obtaining the address of the error unit of the DRAM.

[0034] It should be noted that dynamically detecting DRAM data information is to obtain the internal data information of the DRAM in real time during its operation. The detection result can be obtained by: inserting verification information into the DRAM data information to obtain target detection information; verifying the number of error bits of the target detection information; correcting the number of error bits when the number of error bits of the target detection information is single bit; generating the detection result when the number of error bits of the target detection information exceeds single bit.

[0035] It should be noted that, according to the characteristics and application scenarios of the data stored in DRAM, different verification information can be selected to ensure the integrity of the data. Common verification information includes checksum, check code, etc. The checksum is obtained by performing a certain mathematical operation (such as addition, XOR, etc.) on all bytes in the data to obtain a fixed value as the checksum. When the data is read, the same operation is performed again. If the obtained checksum is consistent with the stored checksum, it means that there is no error in the data. The check code is a more complex verification method, which is usually generated based on a certain mathematical algorithm (such as CRC cyclic redundancy check). The check code can not only detect errors in the data, but also correct errors to a certain extent.

[0036] It should be noted that the target detection information is formed by combining the calculated verification information with the original data, which is usually achieved by appending the verification information to the end of the original data, but other combinations can also be selected as needed.

[0037] It should be noted that the number of error bits of the target detection information is checked by reading data and corresponding verification information from the DRAM during the data reading process. According to the stored verification method and algorithm, the same operation is performed on the read data to obtain new verification information. The new verification information is then compared with the verification information of the stored target detection information. If the new verification information is inconsistent with the verification information of the stored target detection information, it means that an error has occurred in the data storage or reading process. At this time, corresponding error handling can be adopted, as described below.

[0038] It is understandable that when the number of error bits in the target detection information is only a single bit, this usually means that a single bit of data has been flipped or damaged during transmission or storage. At this time, you can use error correction code (ECC). If the DRAM or storage system supports error correction code, you can use its error correction capability to automatically correct single-bit errors. ECC detects and corrects a certain number (usually single) of bit errors by adding additional check bits. If the DRAM or storage system does not support ECC or error correction fails, you can request the data source to retransmit the correct data. In some cases, you can also try to restore data from backup or rewrite the affected storage area.

[0039] It is understandable that when the number of error bits in the target detection information exceeds a single bit, it means that the data has been more seriously damaged during transmission or storage. At this time, it is necessary to record the detection results in preparation for subsequent repairs.

[0040] It is understood that the detection results may include the number of error bits, location, error type (such as single-bit error, multi-bit error, address decoding error, etc.) and related diagnostic information. Special error location technology or algorithms are used to locate the error unit in the DRAM based on the error location information in the detection results. These technologies may involve processes such as address decoding, data verification, and logic analysis.

[0041] It should be noted that in order to obtain more accurate results, DRAM test software or hardware test tools, such as memtest86+ and Rowhammer test programs, can be used to conduct more in-depth testing and analysis of DRAM. By adjusting test parameters and observing test results, the error range can be gradually narrowed until the error unit is accurately located. Once the error unit is located, the address of the unit can be extracted from the address mapping information.

[0042] Specifically, you can choose to add the SECDED algorithm (Single Error Correction, Double Error Detection) to detect DRAM data. The SECDED algorithm is an error correction code technology based on Hamming code, which is widely used in data protection of DRAM and other memories. The algorithm can not only correct single-bit errors, but also detect double-bit errors, thereby greatly improving the reliability and integrity of data.

[0043] The specific process is as follows: The SECDED algorithm first uses the principle of Hamming code to generate a set of check bits for the data. These check bits are distributed in the data so that they can cover all possible single-bit and double-bit errors. In addition to the Hamming code, SECDED also generates additional ECC check bits (commonly called parity bits). These check bits are obtained by operating the data through a specific algorithm to further increase the ability of error detection and correction.

[0044] It can be understood that the encoded data (including the original data and the generated check bits) are stored in DRAM together. When data needs to be read from DRAM, the original data and the corresponding check bits are read at the same time. Then, the same algorithm as the encoding stage is used to perform a check calculation on the read data to obtain a new check value. At this time, if the new check value is inconsistent with the stored check bit, and the difference indicates that only one bit has an error, the SECDED algorithm can locate and correct the error. If the difference indicates that two or more bits have errors, although the SECDED algorithm cannot correct these errors, it can detect their existence and issue an error alarm.

[0045] Step S20, performing repeated read and write tests on the error unit according to the address of the error unit.

[0046] Step S30, when the error unit reports an error for a preset number of times, stop the test and determine that the error unit is damaged.

[0047] It is understood that once the address of the error unit is determined, the address information needs to be sent to the storage device through the device's address bus. This process is called addressing. The purpose of addressing is to ensure that the read and write operations can accurately locate the error unit.

[0048] It is understood that the repeated read and write test detects whether the DRAM unit is damaged by repeatedly performing read and write operations on the unit and checking the correctness of the data. If the unit continues to report errors in multiple tests, it can be considered that the unit is damaged and can no longer reliably store data.

[0049] Based on this, this embodiment provides a feasible implementation method: locating the error unit according to the address of the error unit; performing a read and write test on the error unit; when the read and write test results are wrong, reporting an error and returning to execute the step of performing a read and write test on the error unit.

[0050] It should be noted that the DRAM error unit address obtained in the previous step is accurately located. Then determine the number of tests, the mode of reading and writing data (such as all 0, all 1, alternating 01, etc.), read and write speed and other parameters. Repeat the read and write operations on the located error unit, and check the correctness of the data after each read and write. At this point, you can use special test software or hardware to automate this process.

[0051] It should be noted that after each read / write test, if a data error is detected, an error is recorded. The recorded number of errors is compared with a preset threshold. The preset threshold can be determined based on DRAM specifications, test requirements, and actual application scenarios.

[0052] It is understandable that if the number of error reports reaches or exceeds a preset threshold, the read and write test of the error unit is stopped, and it is determined that the error unit is damaged and needs to be repaired.

[0053] Step S40, re-map the damaged error cells to repair the DRAM.

[0054] It is understandable that in a DRAM (Dynamic Random Access Memory) chip, when a cell is detected to be damaged, the entire chip is not discarded directly. Remapping can be used to replace the damaged cell with a spare cell inside the chip to restore the chip.

[0055] Based on this, this embodiment provides a feasible implementation method: establishing a mapping relationship between the error unit and the spare unit; storing the mapping relationship in a mapping relationship table; and repairing the DRAM by accessing the mapping relationship table.

[0056] It should be noted that the mapping relationship between the erroneous cells and the spare cells is established as follows: First, determine which cells are damaged through the previous test steps such as steps S20 and S30. Then, select available spare cells in the spare area of ​​DRAM. Spare cells are usually reserved during chip design to replace the main cells that may be damaged. Next, establish a mapping relationship between each damaged cell and its corresponding spare cell. This means that when software or hardware attempts to access the address of the damaged cell, they will be redirected to the address of the spare cell.

[0057] It should be noted that the mapping table is a data structure used to store the mapping information between all damaged cells and their corresponding spare cells. This table can be stored in a specific area of ​​DRAM or in a memory outside the chip. For example, in the memory of the DRAM controller. The mapping table must be able to be accessed and updated efficiently to ensure that the correct spare cell can be found quickly when needed.

[0058] It is understandable that, since DRAM cell damage is accidental, the mapping relationship table needs to be re-established after each test confirms the damage to cope with newly added damaged erroneous cells.

[0059] It should be noted that when DRAM receives a memory access request, it first checks whether the request is for a damaged cell. If the request is for a damaged cell, DRAM will use the mapping table to find the corresponding spare cell and redirect the request to the spare cell. In this way, even if the original cell is damaged, the data can still be correctly read or written to the spare cell, thus achieving DRAM repair.

[0060] Specifically, the address of the damaged DRAM cell and the remapped address can be stored in a hash table. Through the hash table, the system can quickly find and locate the damaged DRAM cell and its corresponding redundancy cell, thereby quickly restoring memory access capabilities.

[0061] In this embodiment, by dynamically acquiring the address of the DRAM's error unit, the potential fault point in the DRAM can be discovered and located in real time to provide an accurate target for subsequent repair work. By repeatedly performing read and write tests on the error unit, it is determined whether the error unit is truly damaged. When the error unit reports an error for a preset number of times, it is determined to be damaged, avoiding misjudgment caused by a single test error, and also preventing invalid or excessive testing of the damaged unit, saving test time and resources. Finally, through the remapping technology, the service life of the chip is extended, the risk of system downtime caused by chip failure is reduced, and the stability of DRAM is improved.

[0062] Furthermore, in order to improve the stability of DRAM, periodic background testing can be introduced. This mechanism can regularly check the health of DRAM without affecting the normal operation of the system, and promptly detect and handle damaged units. Please refer to Figure 2 , Figure 2 A flow chart of the second embodiment of the DRAM repair method of the present application.

[0063] In this embodiment, after step S40, the following steps are also included: steps S50 to S70: Step S50, periodically performing background read and write tests on the DRAM.

[0064] In this step, the system periodically performs read and write tests on the DRAM in the background. These tests are low-overhead and are designed to detect the health of the DRAM without affecting the normal operation of the system. The frequency of the test cycle can be adjusted based on the use of the DRAM, the working environment, and the expected stability requirements.

[0065] Step S60, when the background read / write test result is erroneous, locate the read / write error unit.

[0066] It should be noted that if a read / write error is detected during the background test, the system will immediately locate the erroneous DRAM cell, i.e., the read / write error cell. This usually involves a detailed analysis of the test results to determine the specific location of the error cell, which can be referred to the discussion of the previous embodiment.

[0067] Step S70, re-map the read / write error unit to repair the DRAM.

[0068] It is understood that once the faulty DRAM cells are identified, the system will replace these cells with spare cells according to the previous remapping process. This includes updating hash tables or other data structures to ensure that subsequent memory access requests can be correctly redirected to spare cells.

[0069] In this embodiment, through regular background testing, the system can timely detect and handle potential fault points before DRAM fails, thereby avoiding more serious faults. The background testing mechanism helps to maintain the health of DRAM, reduce system downtime caused by memory failure, and improve the overall stability of the system, thereby more effectively utilizing DRAM resources and extending its service life. At the same time, it reduces system crashes or data loss caused by memory failures, and improves the continuity and satisfaction of user experience.

[0070] It should be noted that the above examples are only used to understand the present application and do not constitute a limitation on the DRAM repair method of the present application. More simple transformations based on this technical concept are all within the protection scope of the present application.

[0071] This application also provides a DRAM repair device, please refer to Figure 3 The DRAM repair device includes: a data acquisition module 10, used to dynamically obtain the error unit address of the DRAM; a test module 20, based on the error unit address, repeatedly read and write tests on the error unit; and also used to stop the test and determine that the error unit is damaged when the error unit reports an error a preset number of times; a repair module 30, used to remap the damaged error unit to repair the DRAM.

[0072] The DRAM repair device provided by the present application adopts the DRAM repair method in the above embodiment, which can solve the technical problem of poor stability caused by storage unit damage errors in DRAM. Compared with the prior art, the beneficial effects of the DRAM repair device provided by the present application are the same as the beneficial effects of the DRAM repair method provided by the above embodiment, and other technical features in the DRAM repair device are the same as the features disclosed in the above embodiment method, which will not be repeated here.

[0073] The present application provides a DRAM repair test device, which includes: at least one processor; and a memory that is communicatively connected to the at least one processor; wherein the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the DRAM repair method in the above-mentioned embodiment one.

[0074] Reference below Figure 4, which shows a schematic diagram of the structure of a DRAM repair test device suitable for implementing the embodiment of the present application. The DRAM repair test device in the embodiment of the present application may include but is not limited to mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Descriptions), PMPs (Portable Media Players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 4 The DRAM repair test device shown is merely an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0075] like Figure 4 As shown, the DRAM repair test device may include a processing device 1001 (such as a central processing unit, a graphics processor, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM: Read Only Memory) 1002 or a program loaded from a storage device 1003 to a random access memory (RAM: Random Access Memory) 1004. In RAM1004, various programs and data required for the operation of the DRAM repair test device are also stored. The processing device 1001, ROM1002 and RAM1004 are connected to each other through a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Generally, the following systems can be connected to the I / O interface 1006: an input device 1007 including, for example, a touch screen, a touch pad, a keyboard, a mouse, an image sensor, a microphone, an accelerometer, a gyroscope, etc.; an output device 1008 including, for example, a liquid crystal display (LCD: Liquid Crystal Display), a speaker, a vibrator, etc.; a storage device 1003 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1009. The communication device 1009 can allow the DRAM repair test device to communicate with other devices wirelessly or by wire to exchange data. Although the DRAM repair test device with various systems is shown in the figure, it should be understood that it is not required to implement or have all the systems shown. More or fewer systems can be implemented or have alternatively.

[0076] In particular, according to the embodiments disclosed in the present application, the process described above with reference to the flowchart can be implemented as a computer software program. For example, the embodiments disclosed in the present application include a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through a communication device, or installed from a storage device 1003, or installed from a ROM 1002. When the computer program is executed by the processing device 1001, the above-mentioned functions defined in the method of the embodiment disclosed in the present application are executed.

[0077] The DRAM repair test device provided by the present application adopts the DRAM repair method in the above embodiment, which can solve the technical problem of poor stability caused by storage unit damage errors in DRAM. Compared with the prior art, the beneficial effects of the DRAM repair test device provided by the present application are the same as the beneficial effects of the DRAM repair method provided by the above embodiment, and the other technical features in the DRAM repair test device are the same as the features disclosed in the method of the previous embodiment, which will not be repeated here.

[0078] It should be understood that the various parts disclosed in this application can be implemented by hardware, software, firmware or a combination thereof. In the description of the above embodiments, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0079] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0080] The present application provides a computer-readable storage medium having computer-readable program instructions (ie, computer programs) stored thereon, and the computer-readable program instructions are used to execute the DRAM repair method in the above-mentioned embodiment.

[0081] The computer-readable storage medium provided in the present application may be, for example, a USB flash drive, but is not limited to electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, systems or devices, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM: Random Access Memory), a read-only memory (ROM: Read Only Memory), an erasable programmable read-only memory (EPROM: Erasable Programmable Read Only Memory or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM: CD-Read Only Memory), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program, which may be used by or in combination with an instruction execution system, system or device. The program code contained on the computer-readable storage medium may be transmitted using any appropriate medium, including but not limited to: wires, optical cables, RF (Radio Frequency: Radio Frequency), etc., or any suitable combination of the above.

[0082] The computer-readable storage medium may be included in the DRAM repair test device; or may exist independently without being assembled into the DRAM repair test device.

[0083] The computer-readable storage medium carries one or more programs. When the one or more programs are executed by a DRAM repair test device, the DRAM repair test device: dynamically obtains the error unit address of the DRAM; based on the error unit address, performs repeated read and write tests on the error unit; when the error unit reports an error a preset number of times, stops the test and determines that the error unit is damaged; and remaps the damaged error unit to repair the DRAM.

[0084] Computer program code for performing the operations of the present application may be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0085] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present application. In this regard, each square box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0086] The modules involved in the embodiments described in this application may be implemented by software or hardware, wherein the name of the module does not constitute a limitation on the unit itself in some cases.

[0087] The readable storage medium provided in the present application is a computer-readable storage medium, which stores computer-readable program instructions (i.e., computer programs) for executing the above-mentioned DRAM repair method, and can solve the technical problems of DRAM storage unit damage errors and poor stability. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in the present application are the same as the beneficial effects of the DRAM repair method provided in the above-mentioned embodiment, and will not be repeated here.

[0088] The present application also provides a computer program product, including a computer program, which implements the steps of the above-mentioned DRAM repair method when executed by a processor.

[0089] The computer program product provided by the present application can solve the technical problem of poor stability caused by storage unit damage errors in DRAM. Compared with the prior art, the beneficial effects of the computer program product provided by the present application are the same as the beneficial effects of the DRAM repair method provided by the above embodiment, which will not be elaborated here.

[0090] The above descriptions are only some embodiments of the present application, and are not intended to limit the patent scope of the present application. All equivalent structural changes made using the contents of the present application specification and drawings under the technical concept of the present application, or direct / indirect applications in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A DRAM repair method, characterized in that: The method comprises: Get the error unit address of DRAM; According to the addressing of the error unit, repeated reading and writing tests are performed on the error unit; When the error unit reports an error for a preset number of times, the test is stopped and the error unit is determined to be damaged; The damaged erroneous cells are remapped to repair the DRAM.

2. The DRAM repair method according to claim 1, wherein: The step of obtaining the error unit address of the DRAM includes: Detect DRAM data information and obtain detection results; Based on the detection result, locate the error unit of the DRAM; The address of the error unit of the DRAM is obtained.

3. The DRAM repair method according to claim 2, characterized in that: The steps of detecting DRAM data information and obtaining detection results include: Inserting verification information into the data information of the DRAM to obtain target detection information; Checking the number of error bits of the target detection information; When the number of error bits in the target detection information is a single bit, correcting the number of error bits; When the number of error bits of the target detection information exceeds a single bit, a detection result is generated.

4. The DRAM repair method according to any one of claims 1 to 3, characterized in that: The step of performing repeated read and write tests on the error unit according to the address of the error unit includes: Addressing the error unit according to the error unit address to locate the error unit; Performing a read and write test on the error unit; When the read-write test result is erroneous, an error is reported and the process returns to execute the step of performing the read-write test on the erroneous unit.

5. The DRAM repair method according to claim 4, characterized in that: The step of remapping the damaged error unit to repair the DRAM chip includes: Establishing a mapping relationship between the error unit and the spare unit; Storing the mapping relationship in a mapping relationship table; The DRAM chip is repaired by accessing the mapping relationship table.

6. The DRAM repair method according to claim 5, characterized in that: The step of remapping the damaged error unit to repair the DRAM also includes: Periodically perform background read and write tests on DRAM; When the background read / write test result is wrong, locate the read / write error unit; The read and write error cells are remapped to repair the DRAM.

7. A DRAM repair device, characterized in that: The DRAM repair device comprises: A data acquisition module, used to acquire the error unit address of the DRAM; A test module, addressing the error unit according to the address of the error unit, and performing repeated read and write tests on the error unit; when the error unit reports an error for a preset number of times, the test is stopped and the error unit is determined to be damaged; The repair module is used for remapping the damaged error cells to repair the DRAM.

8. A DRAM repair test device, characterized in that: The DRAM repair test device comprises: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program is configured to implement the steps of the DRAM repair method according to any one of claims 1 to 6.

9. A storage medium, characterized in that: The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, the steps of the DRAM repair method according to any one of claims 1 to 6 are implemented.

10. A computer program product, characterized in that The computer program product comprises a computer program, and when the computer program is executed by a processor, the steps of the DRAM repair method according to any one of claims 1 to 6 are implemented.

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