Method, circuit and system for reducing bus voltage by adopting single-stage PFC (Power Factor Correction) architecture

Abstract

The invention relates to the technical field of quick charging conversion circuits, in particular to a method, a circuit and a system for reducing bus voltage by adopting a single-stage PFC (Power Factor Correction) architecture. The method for reducing the bus voltage comprises the following steps of: detecting output voltages of C1 / C2 ports in a circuit, and judging whether the output voltages are smaller than a preset threshold value 16V or not; when it is detected that the output voltages are all smaller than a preset threshold value 16 V or no equipment is connected in a standby mode, the output IO is set to be in a low level through an MCU instruction so as to trigger a voltage reduction mechanism of the circuit, and the bus voltage is reduced from 31 V to 22 V and then reduced to 17 V. According to the invention, by introducing elements such as the MCU and the optocoupler, a method and a circuit capable of intelligently adjusting the bus voltage according to load requirements are designed, and the problem of low efficiency of application of a single-stage PFC architecture in a PD fast charging product is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of fast charging conversion circuits, and in particular to a bus voltage reduction method, circuit and system using a single-stage PFC architecture. Background Art

[0002] In modern electronic devices, AC-DC conversion circuits are often used to convert mains electricity into a DC voltage suitable for use in electronic devices. Traditional AC-DC conversion circuits usually adopt a multi-level PFC architecture to achieve efficient power transmission by gradually improving and stabilizing the power factor in multiple stages. However, this multi-level architecture not only increases the complexity and cost of the circuit, but also has a negative impact on the overall efficiency of the system. In a single-stage PFC architecture, due to the lack of secondary detection and regulation mechanisms, it is difficult to achieve precise control of the bus voltage under different load conditions, especially in PD fast charging products. The bus voltage needs to be flexibly adjusted according to different PD voltage charging conditions to improve the AC-DC conversion efficiency.

[0003] At present, the existing technical solutions usually adjust the secondary reference voltage through secondary detection to achieve different AC-DC bus voltage outputs. In a single-stage PFC line, due to the lack of a secondary detection mechanism, this dynamic adjustment of voltage cannot be achieved. This is a major technical challenge for PD fast charging products that require multiple output voltages. For example, when the product needs to work in 15V mode, the efficiency cannot be optimized through the existing single-stage PFC architecture, resulting in low conversion efficiency of the product under high load conditions. It also increases the operating temperature and affects the stability and life of the equipment. In addition, the existing technical solutions have high power consumption in no-load or standby states, and it is difficult to meet the requirements of the energy efficiency regulations Level VI energy efficiency standards. Summary of the invention

[0004] The present invention provides a bus voltage reduction method, circuit and system using a single-stage PFC architecture to solve the technical problem of how to achieve intelligent regulation of the bus voltage in a single-stage PFC architecture, especially in PD fast charging products, how to optimize the output of the bus voltage according to different PD voltage charging conditions, thereby reducing the operating temperature and no-load power consumption while ensuring high efficiency.

[0005] The technical solution of the present invention to solve the above technical problems is as follows: On the one hand, a bus voltage reduction method using a single-stage PFC architecture is provided, and the steps of the bus voltage reduction method include: Detect the output voltage of C1 / C2 port in the circuit to determine whether the output voltage is less than the preset threshold value of 16V; When it is detected that the output voltage is less than the preset threshold value of 16V or no device is connected in standby mode, the output IO is set to a low level through the MCU instruction to trigger the voltage reduction mechanism of the circuit, reducing the bus voltage from 31V to 22V and then to 17V; When it is detected that any end of the output voltage is greater than or equal to the preset threshold value of 16V, the output IO is set to a high level of 3V through the MCU instruction to maintain the bus voltage rising to 22V and then to 31V; The voltage switching transition process is controlled by adjusting the duty cycle of the PWM signal output by the MCU and the resistance value in the circuit to smoothly switch between different working modes and reduce the impact of voltage mutation on circuit components; During the entire voltage switching and maintenance process, the output state of the bus voltage is successively evaluated and adjusted through a feedback mechanism to achieve optimal AC-DC conversion efficiency.

[0006] On the other hand, a bus voltage reduction circuit using a single-stage PFC architecture is provided, and the bus voltage reduction circuit includes: The MCU is used to output PWM signals and high / low level commands, and controls the rise and fall of the bus voltage according to the output voltage status of the C1 / C2 port detected; An optocoupler connected to the MCU, and MOS tubes Q7 and Q8 connected to the optocoupler, the optocoupler is used to isolate the signal path between the MCU and the MOS tubes Q7 and Q8, and forward the level signal according to the received MCU instruction; MOS tube Q7 receives the signal from the optocoupler. When the optocoupler transmits a high level, MOS tube Q7 is turned on, and the voltage regulator LDO charges the capacitor C9 through the diode D10. When the optocoupler transmits a low level, MOS tube Q7 is turned on and off, and the capacitor C9 is discharged to the ground through the resistors R39 and R35. The charging and discharging state of the capacitor C9 is controlled by adjusting the PWM duty cycle to ensure the driving state of the MOS tube Q7. MOS tube Q8 receives the signal transmitted from the optocoupler. When the optocoupler transmits a high level, MOS tube Q8 is turned on, and the voltage regulator LDO charges the capacitor C15 through the resistor R12, the voltage regulator ZD2 and the fast recovery diode D14. When the optocoupler transmits a low level, MOS tube Q8 is turned off, and the capacitor C11 is discharged to the ground through the fast recovery diode D13 and the resistor R35. The charge and discharge state of the capacitor C11 is controlled by adjusting the PWM duty cycle and the parameters of the resistor R12, the capacitor C11 and the fast recovery diode D13 to ensure that the MOS tube Q8 is not turned on when the voltage of the capacitor C11 is less than the threshold voltage of the voltage regulator ZD2, 5.1V. The rise and fall process of bus voltage includes: When the output voltage of C1 / C2 port is less than 16V or there is no device in standby mode, MCU outputs low level 0V, and the bus voltage drops from 31V to 17V, first to 22V and then to 17V; When the output voltage of any port C1 / C2 is greater than 16V, the MCU outputs a high level of 3V, and the bus voltage remains at 31V or increases from 17V to 31V. The boost process first increases to 22V and then to 31V.

[0007] On the other hand, a bus voltage reduction system using a single-stage PFC architecture is provided, including the bus voltage reduction circuit using the single-stage PFC architecture as described above. The system also includes a power adapter, a load device, a temperature monitoring module and a transient voltage protection module connected to the bus voltage reduction circuit. The bus voltage reduction system automatically adjusts the bus voltage according to the needs of the load device and maintains high efficiency and low power consumption characteristics in any operating mode.

[0008] The beneficial effects of the present invention are: The present invention introduces components such as MCU and optocoupler to design a method and circuit that can intelligently adjust the bus voltage according to load demand, solving the problem of low efficiency of single-stage PFC architecture in PD fast charging products. The bus voltage reduction method using a single-stage PFC architecture of the present invention can realize dynamic switching of the bus voltage between 31V and 17V, ensuring that the bus voltage drops to 17V under low load or standby state, thereby significantly reducing standby power consumption and meeting the requirements of energy efficiency regulations VI level standards. Under high load conditions, the bus voltage can quickly return to 31V, ensuring high efficiency and stability of power transmission.

[0009] Furthermore, the PWM signal and high / low level command output by the MCU controls the charging and discharging process of the MOS tube and capacitor, achieving a smooth transition of voltage switching. In particular, during the voltage switching process, the impact of voltage mutation on circuit components is effectively reduced by accurately adjusting the duty cycle of the PWM signal and the resistance value of the resistor in the circuit.

[0010] In addition, the present invention further improves the safety performance and service life of the circuit by introducing transient voltage suppression circuits and temperature monitoring elements. Under different PD voltage charging conditions, the circuit can adaptively adjust the control strategy, optimize the AC-DC conversion efficiency, and ensure the efficient operation of the product in a variety of application scenarios. It not only improves the energy efficiency of PD fast charging products, but also significantly improves the safety and stability of the products. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a flow chart of a bus voltage reduction method using a single-stage PFC architecture in one embodiment of the present invention; Figure 2A diagram showing the relationship between temperature and PWM duty cycle in an embodiment of the present invention; Figure 3 A diagram showing the relationship between noise interference and voltage detection accuracy in one embodiment of the present invention; Figure 4 is a graph of conversion efficiency under different load conditions in one embodiment of the present invention; Figure 5 A diagram showing the relationship between standby power consumption and bus voltage in one embodiment of the present invention; Figure 6 is a relationship diagram of transient voltage protection performance in one embodiment of the present invention; Figure 7 The circuit principle of reducing bus voltage using a single-stage PFC architecture in one embodiment of the present invention is shown in FIG. Figure 1 ; Figure 8 The circuit principle of reducing bus voltage using a single-stage PFC architecture in one embodiment of the present invention is shown in FIG. Figure 2 ; Fig. 9 A diagram showing the relationship between the PWM duty cycle and the charge and discharge time in one embodiment of the present invention; Fig.10 This is the circuit diagram of the USB interface C1 pin; Fig.11 This is the circuit diagram of the USB interface C2 pin. DETAILED DESCRIPTION

[0012] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0013] In order to facilitate understanding of the technical solution of the present invention, some features are briefly explained first: C1 / C2: Two pins used for Power Delivery Handshake in the Type-C USB interface.

[0014] PFC: Power Factor Correction, power factor correction.

[0015] PD: Power Delivery.

[0016] MCU: Microcontroller Unit, microcontroller.

[0017] The present invention provides the following preferred embodiments: Embodiment 1 In order to solve the problem that the single-stage PFC architecture cannot achieve different AC-DC bus voltage outputs in PD fast charging products, this embodiment proposes a bus voltage reduction method using a single-stage PFC architecture to ensure efficient AC-DC conversion under different PD voltage charging conditions and meet the energy efficiency requirements of energy efficiency regulations VI. Figure 1 As shown, the steps of the bus voltage reduction method include: S100, detecting the output voltage of the C1 / C2 port in the circuit to determine whether the output voltage is less than a preset threshold value of 16V.

[0018] S200: When it is detected that the output voltage is less than the preset threshold value 16V or no device is connected in standby mode, the output IO is set to a low level through the MCU instruction to trigger the voltage reduction mechanism of the circuit to reduce the bus voltage from 31V to 22V and then to 17V.

[0019] S300, when it is detected that any end of the output voltage is greater than or equal to the preset threshold value 16V, the output IO is set to a high level of 3V through the MCU instruction to maintain the bus voltage rising to 22V and then to 31V.

[0020] S400, controlling the voltage switching transition process by adjusting the duty cycle of the PWM signal output by the MCU and the resistance value in the circuit, so as to smoothly switch between different working modes and reduce the impact of voltage mutation on circuit components.

[0021] S500, during the entire voltage switching and maintenance process, the output state of the bus voltage is successively evaluated and adjusted through a feedback mechanism to achieve the best AC-DC conversion efficiency.

[0022] Specifically, the bus voltage reduction circuit in this embodiment includes an MCU, an optocoupler, two small signal MOS tubes (Q7 and Q8), fast recovery diodes (D10, D13, D14), a voltage regulator LDO, and related resistors and capacitors. The specific models and connection relationships of these components are as follows: MCU (MCU-1): STM32F103 microcontroller is used, which has multiple IO ports for outputting PWM signals and high / low level instructions. MCU-1 controls the rise and fall of the bus voltage by detecting the output voltage status of the C1 / C2 port.

[0023] Optocoupler: Use TLP250 type optocoupler, whose input end is connected to MCU-1 IO port, and whose output end is connected to MOS tubes Q7 and Q8. The optocoupler is used to isolate the signal path between MCU and MOS tube, and forward the level signal according to the received MCU instruction.

[0024] MOS tube Q7: Small signal MOS tube Q7 (such as IRF9530) is used to receive signals from the optocoupler. When the optocoupler transmits a high level of 3V, MOS tube Q7 is turned on, and the voltage regulator LDO charges capacitor C9 through fast recovery diode D10, so that MOS tube Q7 remains in a high level on state. When the optocoupler transmits a low level of 0V, MOS tube Q7 is turned off, and capacitor C9 discharges to the ground through resistors R39 and R35, so that MOS tube Q7 remains in a low level off state. By adjusting the duty cycle of the PWM signal output by the MCU, the on and off states of Q7 can be accurately controlled, thereby adjusting the bus voltage.

[0025] MOS tube Q8: The small signal MOS tube Q8 (such as IRF530) is used to receive the signal from the optocoupler. When the optocoupler transmits a high level of 3V, the MOS tube Q8 is turned on, and the voltage regulator LDO charges the capacitor C15 through the resistor R12, the voltage regulator ZD2 and the fast recovery diode D14, so that the MOS tube Q8 remains in a high level on state. When the optocoupler transmits a low level of 0V, the MOS tube Q8 is turned off, and the capacitor C11 is discharged to the ground through the fast recovery diode D13 and the resistor R35, so that the MOS tube Q8 remains in a low level off state. By adjusting the duty cycle of the PWM signal output by the MCU and the parameters of R12, C11, and D13, the on and off states of Q8 can be accurately controlled, thereby adjusting the bus voltage.

[0026] Fast recovery diodes (D10, D13, D14): Fast recovery diodes, such as 1N4148, are used to form the charge and discharge loop. The fast recovery characteristics of these diodes help reduce energy loss during voltage switching and improve the efficiency of the circuit.

[0027] Regulator LDO: TLV7031 regulator LDO is used to provide a stable low voltage source for the optocoupler, MOS tube and related resistors and capacitors. The output voltage of the regulator LDO is 10V, ensuring the stable operation of the circuit in different modes.

[0028] Resistors (R12, R35, R39) and capacitors (C9, C11, C15): These resistors and capacitors form different feedback paths to control the on and off states of the MOS tube. The parameter selection of R12, C11, and D13 needs to be optimized according to the specific application scenario to achieve precise control of the bus voltage.

[0029] Furthermore, when it is detected that the output voltage of the C1 / C2 port is less than 16V or there is no device in standby mode, the IO port of MCU-1 outputs a low level of 0V, the optocoupler is not turned on, and the MOS tube Q7 and the MOS tube Q8 are both turned off. At this time, the bus voltage drops from 31V to 22V and then to 17V through the feedback mechanism. In this process, the voltage regulator LDO discharges the capacitor C9 through the resistors R39 and R35, so that the MOS tube Q7 remains in the off state. At the same time, the voltage regulator LDO discharges the capacitor C11 through the fast recovery diode D13 and the resistor R35, so that Q8 remains in the off state. The discharge process of capacitors C9 and C11 ensures a smooth drop in the bus voltage and reduces the impact of voltage mutations on circuit components.

[0030] Furthermore, when it is detected that the output voltage of any port C1 / C2 is greater than or equal to 16V, the IO port of MCU-1 outputs a high level of 3V, the optocoupler is fully turned on, and both MOS tubes Q7 and Q8 are turned on. At this time, the bus voltage rises from 17V to 22V and then to 31V through the feedback mechanism. In this process, the voltage regulator LDO charges the capacitor C9 through the fast recovery diode D10 to keep Q7 in the on state. At the same time, the voltage regulator LDO charges the capacitor C15 through the resistor R12, the voltage regulator ZD2 and the fast recovery diode D14 to keep the MOS tube Q8 in the on state. The charging process of capacitors C9 and C15 ensures the smooth rise of the bus voltage and improves the AC-DC conversion efficiency.

[0031] Furthermore, MCU-1 controls the on-time of MOS tube Q7 and MOS tube Q8 by adjusting the duty cycle of the PWM signal, thereby realizing precise control of the bus voltage. When the bus voltage needs to be reduced from 31V to 17V, MCU-1 outputs a PWM signal with a low duty cycle, so that MOS tube Q7 and MOS tube Q8 remain in the off state for a long time at a low level. When the bus voltage needs to be increased from 17V to 31V, MCU-1 outputs a PWM signal with a high duty cycle, so that MOS tube Q7 and MOS tube Q8 remain in the on state for a long time at a high level. In this way, through the fine control of the PWM signal, it is possible to switch smoothly between different working modes to ensure the stability and efficiency of the circuit.

[0032] Furthermore, the feedback resistor (R11 in parallel with R36 and R27) and capacitors C9, C11, and C15 together form a feedback path for successively evaluating and adjusting the output state of the bus voltage. When the bus voltage needs to drop to 17V, the resistance of the feedback resistor is the smallest, so that the Vout output voltage is 17V. When the bus voltage needs to rise to 31V, the resistance of the feedback resistor is large, so that the Vout output voltage is 31V. Through this feedback mechanism, the changes in the bus voltage can be monitored in real time and adjusted to ensure that the best AC-DC conversion efficiency can be achieved in different operating modes.

[0033] Furthermore, the value of resistor R12 needs to be optimized according to the specific application scenario. In this embodiment, the value of R12 is 10kΩ to ensure that when the MOS tube Q8 is turned on, the voltage regulator LDO charges C15 through R12, ZD2 and D14 at a suitable speed, neither too fast to cause voltage mutation, nor too slow to affect the response speed of voltage regulation. The value of capacitor C11 is selected to be 100nF to ensure that when the MOS tube Q8 is turned off, the speed at which C11 discharges to the ground through D13 and R35 is suitable to maintain a smooth transition of the voltage. The selection of D13 and D14 needs to consider their fast recovery characteristics to ensure that energy loss is reduced during voltage switching.

[0034] The benefit of this embodiment is that, through sophisticated circuit design and feedback mechanism, efficient voltage regulation of the single-stage PFC architecture in PD fast charging products is achieved, ensuring the stability and energy efficiency of the product in different operating modes. Especially in no-load or light-load conditions, the bus voltage can be reduced to 17V, significantly reducing no-load power consumption and meeting the energy efficiency requirements of energy efficiency regulations VI. When the load is large, the bus voltage can be increased to 31V, which improves the AC-DC conversion efficiency, reduces the product's operating temperature, and ensures the product's service life.

[0035] Through this embodiment, the invention not only solves the problem that the single-stage PFC architecture cannot achieve different AC-DC bus voltage outputs in PD fast charging products, but also further improves the performance of the circuit through fine regulation and feedback mechanism.

[0036] Embodiment 2 In order to solve the problem of decreased efficiency caused by excessive temperature during the bus voltage boosting process of a single-stage PFC architecture in PD fast charging products, this embodiment further optimizes the method of monitoring the circuit temperature through an ambient temperature detector and dynamically adjusting the PWM signal duty cycle to ensure that the conversion efficiency of the circuit is optimized under high temperature conditions.

[0037] In this embodiment, MCU-1 is connected to the ambient temperature detector through the AD interface to monitor the temperature change of the circuit in real time. When it is detected that the output voltage of the C1 / C2 port is greater than or equal to 16V, the IO port of MCU-1 outputs a high level of 3V, the optocoupler is fully turned on, and the MOS tube Q7 and MOS tube Q8 are turned on accordingly. The bus voltage is increased from 17V to 22V in stages, and then to 31V. The output signal of the ambient temperature detector is proportional to the circuit temperature, and changes by 10mV per degree Celsius. MCU-1 calculates the current ambient temperature by reading the voltage value of the AD interface, and dynamically adjusts the duty cycle of the PWM signal according to the temperature.

[0038] Furthermore, when the ambient temperature detector detects that the circuit temperature is high, MCU-1 will appropriately reduce the duty cycle of the PWM signal, such as Figure 2 As shown, the conduction time of the MOS tube and the speed of increasing the bus voltage are reduced, thereby reducing the power consumption and heat generation of the circuit. This dynamic adjustment strategy enables the circuit to maintain a low operating temperature under high temperature conditions, avoiding performance degradation and component damage caused by overheating. It should be understood that temperature monitoring and duty cycle adjustment are achieved through algorithms, which are calculated based on the preset temperature threshold and the frequency of the PWM signal to ensure that the duty cycle is adjusted accurately and in a timely manner.

[0039] Furthermore, when the ambient temperature detector detects that the circuit temperature is low, MCU-1 will appropriately increase the duty cycle of the PWM signal, speed up the bus voltage increase, and improve the circuit's response speed and energy efficiency. This adjustment strategy not only optimizes the performance of the circuit under different temperature conditions, but also ensures that the circuit works efficiently under no-load or light-load conditions. It can be understood that through the coordinated work of the temperature detector and MCU-1, the circuit can maintain stable conversion efficiency under a variety of environmental conditions.

[0040] The benefit of this embodiment is that by introducing an ambient temperature detector and dynamically adjusting the duty cycle of the PWM signal according to the temperature, the performance of the circuit under high temperature conditions is optimized, the conversion efficiency and stability are improved, and the power consumption and heat generation are reduced. In addition, this method also ensures the fast response and high energy efficiency of the circuit under low temperature conditions, and is suitable for a variety of working environments.

[0041] Embodiment 3 In order to solve the problem that the single-stage PFC architecture is easily interfered by noise when detecting the output voltage of C1 / C2 port in PD fast charging products, such as Figure 3 As shown, this embodiment further optimizes the detection accuracy, adopts a dual-channel differential amplifier to improve the detection accuracy, and prevents erroneous operation caused by noise interference.

[0042] In this embodiment, the output voltage of the C1 / C2 port is amplified and processed by a dual-channel differential amplifier, and then the amplified signal is transmitted to the AD interface of MCU-1 for accurate detection. The effective gain of the dual-channel differential amplifier can be adjusted according to actual needs to improve the sensitivity and accuracy of output voltage detection. When MCU-1 detects that the output voltage of any port of the C1 / C2 port is greater than or equal to 16V, the IO port of MCU-1 outputs a high level of 3V, the optical coupler is fully turned on, and the MOS tube Q7 and MOS tube Q8 are turned on accordingly, and the bus voltage is increased from 17V to 22V in stages, and then to 31V.

[0043] Furthermore, in order to ensure the detection accuracy, the dual-channel differential amplifier uses the low-noise, high-precision LM358 model. The two channels of LM358 are respectively connected to the output voltage of the C1 / C2 port, and the two voltage signals are compared and amplified through differential amplification technology, thereby effectively suppressing noise interference. MCU-1 reads the amplified voltage signal through the AD interface to accurately determine the output voltage state of the C1 / C2 port. When it is detected that the output voltage of the C1 / C2 port is less than 16V or there is no device in standby, the IO port of MCU-1 outputs a low level of 0V, the optocoupler is not turned on, the MOS tube Q7 and the MOS tube Q8 are both turned off, and the bus voltage is reduced to 17V through the feedback mechanism.

[0044] Furthermore, in order to avoid misoperation caused by noise interference, MCU-1 can perform filtering after receiving the amplified voltage signal. The filtering algorithm can use a digital filter, such as a low-pass filter, to further improve the detection accuracy. It should be understood that the combination of the dual-channel differential amplifier and the filtering algorithm not only improves the detection accuracy, but also enhances the stability of the circuit, especially in a complex electromagnetic environment.

[0045] The benefit of this embodiment is that the accuracy of output voltage detection is improved by using a dual-channel differential amplifier, which effectively prevents erroneous operation caused by noise interference and ensures the reliability and stability of the circuit. In addition, high-precision voltage detection helps to achieve more accurate voltage regulation, improves AC-DC conversion efficiency, and meets the energy efficiency requirements of energy efficiency regulations VI.

[0046] Embodiment 4 In order to solve the power loss problem of the single-stage PFC architecture when the bus voltage is switched in the PD fast charging product, this embodiment further optimizes the charging and discharging time of capacitor C9 and capacitor C11, and adopts a time adjustment algorithm to reduce the power loss during the voltage switching process.

[0047] In this embodiment, MCU-1 calculates the charge and discharge time of capacitor C9 and capacitor C11 through the time adjustment algorithm in the process of controlling the bus voltage switching to optimize the voltage switching process. When it is detected that the output voltage of the C1 / C2 port is less than 16V or there is no device in standby mode, the IO port of MCU-1 outputs a low level of 0V, the optocoupler is not turned on, and the MOS tube Q7 and MOS tube Q8 are both turned off. At this time, the bus voltage gradually drops from 31V to 22V, and then to 17V. The expression of the time adjustment algorithm is: , where T min is the minimum charge and discharge time of the capacitor, f is the PWM signal frequency, V th is the voltage threshold, V in is the input voltage, and V out is the output voltage.

[0048] Furthermore, MCU-1 calculates the current capacitor charge and discharge time by reading the output voltage of the C1 / C2 port. When it is detected that the output voltage of any port of the C1 / C2 port is greater than or equal to 16V, the IO port of MCU-1 outputs a high level of 3V, the optocoupler is fully turned on, and the MOS tubes Q7 and Q8 are turned on accordingly. At this time, the bus voltage is increased from 17V to 22V in stages, and then to 31V. Through the time adjustment algorithm, MCU-1 can accurately control the charge and discharge time of capacitors C9 and C11 to ensure stability and low loss during the voltage switching process.

[0049] Furthermore, the time adjustment algorithm not only considers the voltage difference, but also the frequency of the PWM signal. By adjusting the frequency of the PWM signal, MCU-1 can further optimize the charge and discharge time of the capacitor and reduce the heat and power loss generated during the charge and discharge process. It should be understood that the use of this algorithm not only improves the efficiency of voltage switching, but also extends the service life of the capacitor and improves the stability of the entire circuit.

[0050] The benefit of this embodiment is that by introducing a time adjustment algorithm to optimize the charge and discharge time of the capacitor, the power loss during the voltage switching process is significantly reduced, and the energy efficiency and stability of the circuit are improved. In addition, this algorithm can also effectively reduce the heat generated during the charge and discharge process, extend the service life of the circuit, and is suitable for high-frequency switching application scenarios.

[0051] Embodiment 5 In order to solve the conversion efficiency fluctuation problem of the single-stage PFC architecture during the voltage switching transition process in PD fast charging products, this embodiment further optimizes the method of stabilizing the conversion efficiency by adjusting the duty cycle of the PWM signal output by the MCU and the resistance value in the circuit, and adopts a duty cycle optimization algorithm to achieve the goal.

[0052] In this embodiment, MCU-1 detects the output voltage of C1 / C2 port in real time through AD interface, and dynamically adjusts the duty cycle of PWM signal and related resistance value according to the detection result. The expression of duty cycle optimization algorithm is: , where D opt represents the optimal PWM duty cycle, V load is the load voltage, V offset is the voltage offset, V input is the input voltage, V output is the output voltage, and K is the comparator gain factor. MCU-1 calculates the optimal PWM duty cycle through this algorithm, thereby stabilizing the conversion efficiency during voltage switching.

[0053] Furthermore, when MCU-1 detects that the output voltage of C1 / C2 port is less than 16V or there is no device in standby mode, the IO port outputs a low level of 0V, the optocoupler is not conducting, MOS tubes Q7 and Q8 are both cut off, and the bus voltage gradually drops from 31V to 22V, and then to 17V. MCU-1 reads the output voltage of C1 / C2 port through the AD interface, and calculates the optimal PWM duty cycle according to the duty cycle optimization algorithm, thereby maintaining a stable conversion efficiency during the voltage switching process.

[0054] Furthermore, in order to further improve the conversion efficiency, MCU-1 can also adjust the load voltage V load and voltage offset V offset Dynamically adjust the resistance value in the circuit. The resistance value can be adjusted by a digital potentiometer, such as the AD5206 digital potentiometer. The digital potentiometer is connected to MCU-1 via the SPI interface, and MCU-1 can adjust the resistance value as needed to optimize the performance of the circuit. It should be understood that the dynamic adjustment strategy not only improves the conversion efficiency of the circuit, but also enhances the adaptability of the circuit under different load conditions.

[0055] The benefit of this embodiment is that by introducing a duty cycle optimization algorithm and dynamically adjusting the resistance value, the stability of the conversion efficiency during the voltage switching process is significantly improved, the efficiency fluctuation is reduced, and the overall performance of the circuit is improved. In addition, this optimization method also enables the circuit to maintain high conversion efficiency under different load conditions, such as Figure 4 shown.

[0056] Embodiment 6 In order to solve the problem of excessive power consumption in the standby state of the single-stage PFC architecture in PD fast charging products, this embodiment further optimizes the deep sleep mechanism when entering the standby state, keeps the bus voltage at 17V, and meets the requirements of energy efficiency standard VI by reducing the standby power consumption, such as Figure 5 As shown, a transient voltage suppression circuit is added to the control circuit to protect circuit components from damage by voltage transients.

[0057] In this embodiment, when it is detected that the output voltage of the C1 / C2 port is less than 16V or there is no device in standby mode, MCU-1 will automatically activate the deep sleep mechanism. In deep sleep mode, the IO port of MCU-1 outputs a low level of 0V, the optocoupler is not conducting, and both MOS tube Q7 and MOS tube Q8 are cut off. At this time, the bus voltage is reduced to 17V through the feedback mechanism to reduce the power consumption in the standby state. After entering the deep sleep state, MCU-1 will shut down most of the internal functional modules to further reduce power consumption.

[0058] Furthermore, in order to protect the circuit components from damage when the voltage changes transiently, this embodiment adds a transient voltage suppression (TVS) circuit to the control circuit. The TVS circuit uses a fast-response transient voltage suppressor, such as the SM110CA model. When the circuit voltage changes transiently, the TVS suppressor will respond quickly and clamp the voltage within a safe range to prevent the circuit components from being damaged due to overvoltage, such as Figure 6 As shown in the figure, MCU-1 can monitor the output voltage and circuit temperature of C1 / C2 ports and activate the TVS circuit when necessary to ensure the safe operation of the circuit.

[0059] Furthermore, when MCU-1 detects that the output voltage of any port of C1 / C2 is greater than or equal to 16V, it will switch from deep sleep mode to normal working mode. During the switching process, MCU-1 reads the voltage clamping state of the TVS circuit through the AD interface to ensure the smooth increase of the bus voltage. It should be understood that the combination of this deep sleep mechanism and the TVS circuit not only significantly reduces the standby power consumption, but also protects the circuit components from damage caused by voltage transients, thereby improving the reliability and safety of the circuit.

[0060] The benefit of this embodiment is that by introducing a deep sleep mechanism and a transient voltage suppression circuit, the power consumption in the standby state is significantly reduced, meeting the requirements of energy efficiency standard VI. In addition, the addition of the TVS circuit effectively protects the circuit components from damage by transient voltage.

[0061] Embodiment 7 In order to solve the problem of low conversion efficiency of the single-stage PFC architecture under different PD voltage charging conditions in PD fast charging products, this embodiment further optimizes the method of dynamically adjusting the PWM signal and related resistance values ​​through an adaptive control algorithm, realizes the optimization of the adaptive response under different load conditions, and improves the AC-DC conversion efficiency.

[0062] In this embodiment, MCU-1 monitors the performance parameters of the circuit in real time through the AD interface, including load voltage, current and temperature. Based on these parameters, MCU-1 dynamically adjusts the duty cycle and related resistance value of the PWM signal through an adaptive control algorithm to optimize the conversion efficiency under different PD voltage charging conditions. The adaptive control algorithm monitors the performance parameters of the circuit under different load conditions and adjusts the control strategy to ensure that the circuit can maintain high conversion efficiency under various working conditions.

[0063] Furthermore, when it is detected that the output voltage of the C1 / C2 port is less than 16V or there is no device in standby mode, the IO port of MCU-1 outputs a low level of 0V, the optocoupler is not conducting, the MOS tube Q7 and the MOS tube Q8 are both cut off, and the bus voltage drops to 17V through the feedback mechanism. After entering the standby state, MCU-1 will shut down most of the internal functional modules to reduce power consumption. When it is detected that the output voltage of any port of the C1 / C2 port is greater than or equal to 16V, MCU-1 will switch from the standby state to the normal working mode, and the adaptive control algorithm will start to work.

[0064] Furthermore, the adaptive control algorithm calculates the optimal PWM signal duty cycle and resistance value by analyzing the load voltage, current and temperature. MCU-1 connects to the digital potentiometer through the SPI interface and dynamically adjusts the resistance value to optimize the performance of the circuit. For example, when the load increases, MCU-1 will increase the duty cycle of the PWM signal and increase the speed of the bus voltage increase; when the load decreases, MCU-1 will reduce the duty cycle of the PWM signal and reduce the speed of the bus voltage increase to reduce power loss. It should be understood that this adaptive control strategy enables the circuit to dynamically adjust parameters according to actual working conditions to ensure high conversion efficiency under different load conditions.

[0065] The benefit of this embodiment is that by introducing the adaptive control algorithm and the digital potentiometer, the adaptive response under different PD voltage charging conditions is optimized, and the AC-DC conversion efficiency is significantly improved. In addition, this dynamic adjustment method not only improves the adaptability and flexibility of the circuit, but also ensures the stability of the circuit under various working conditions.

[0066] Embodiment 8 In order to solve the problem of accurate control of the MOS tube driving state during the bus voltage rise and fall process in the single-stage PFC architecture of PD fast charging products, this embodiment proposes a bus voltage reduction circuit using a single-stage PFC architecture, such as Figures 7 to 9 As shown, the coordinated work of the optocoupler and MOS tubes Q7 and Q8 ensures that the rise and fall process of the bus voltage is accurate and smooth.

[0067] In this embodiment, MCU-1 is responsible for outputting PWM signals and high / low level instructions, and controls the rise and fall process of the bus voltage according to the detected output voltage state of the C1 / C2 port. The optocoupler connects MCU-1 and MOS tubes Q7 and Q8 to isolate the signal path and ensure the reliability and safety of signal transmission. When MCU-1 detects that the output voltage of the C1 / C2 port is less than 16V or there is no device in standby mode, the IO port of MCU-1 outputs a low level of 0V, the optocoupler is not turned on, and the MOS tubes Q7 and Q8 are both cut off. At this time, the bus voltage gradually drops from 31V to 17V, and the step-down process first drops to 22V and then to 17V.

[0068] Furthermore, MOS tube Q7 receives the signal from the optocoupler. When the optocoupler transmits a high level, MOS tube Q7 is turned on, and the voltage regulator LDO charges capacitor C9 through diode D10. When the optocoupler transmits a low level, MOS tube Q7 is turned off, and capacitor C9 is discharged to the ground through resistors R39 and R35. Fig. 9 As shown, the charge and discharge state of capacitor C9 is precisely controlled by the duty cycle of the PWM signal, ensuring that the driving state of MOS tube Q7 is always in the best state. It should be understood that this design improves the reliability and stability of the circuit through the isolation effect of the optocoupler and the precise control of the MOS tube.

[0069] Furthermore, the MOS tube Q8 receives the signal from the optocoupler. When the optocoupler transmits a high level, the MOS tube Q8 is turned on, and the voltage regulator LDO charges the capacitor C15 through the resistor R12, the voltage regulator ZD2 and the fast recovery diode D14. When the optocoupler transmits a low level, the MOS tube Q8 is turned off, and the capacitor C11 is discharged to the ground through the fast recovery diode D13 and the resistor R35. Fig. 9 As shown, the charge and discharge state of capacitor C11 is not only controlled by the duty cycle of the PWM signal, but also optimized by adjusting the parameters of resistor R12, capacitor C11 and fast recovery diode D13 to ensure that MOS tube Q8 is not turned on when the voltage of capacitor C11 is less than the threshold voltage of 5.1V of voltage regulator tube ZD2. It can be understood that this multi-parameter adjustment strategy enables the circuit to maintain high conversion efficiency and stable output voltage under various working conditions.

[0070] The benefit of this embodiment is that, through the coordinated work of the optocoupler and the MOS tube, the bus voltage rise and fall process is precisely controlled, which improves the reliability and stability of the circuit. In addition, through the multi-parameter optimization of the capacitor charging and discharging state, the circuit is ensured to have efficient conversion and low power consumption characteristics in different working modes, which is suitable for high-performance PD fast charging application scenarios.

[0071] Embodiment 9 In order to solve the problem of integrity and reliability of system functions in the process of bus voltage regulation of single-stage PFC architecture in PD fast charging products, this embodiment proposes a bus voltage reduction system using a single-stage PFC architecture, which ensures the high efficiency and low power consumption characteristics of the system in any working mode by integrating the power adapter, load equipment, temperature monitoring module and transient voltage protection module.

[0072] In this embodiment, the bus voltage reduction circuit is the core part of the system. MCU-1 detects the output voltage of the C1 / C2 port in real time through the AD interface, and controls the rise and fall process of the bus voltage according to the detection result. The optocoupler connects MCU-1 and MOS tubes Q7 and Q8 to isolate the signal path and ensure the reliability and safety of signal transmission. When it is detected that the output voltage of the C1 / C2 port is less than 16V or there is no device in standby mode, the IO port of MCU-1 outputs a low level of 0V, the optocoupler is not turned on, the MOS tube Q7 and the MOS tube Q8 are both cut off, and the bus voltage is gradually reduced from 31V to 17V. The voltage reduction process first drops to 22V and then to 17V.

[0073] Furthermore, the system also includes a power adapter connected to the bus voltage reduction circuit to provide a stable input voltage. The power adapter adopts a switching power supply design, and the output voltage is stabilized at 24V to ensure the normal operation of the system under various input voltage conditions. The load device is connected to the system through the C1 / C2 port. MCU-1 dynamically adjusts the duty cycle and bus voltage of the PWM signal by detecting the needs of the load device to meet the voltage requirements under different load conditions. It should be understood that this dynamic adjustment strategy enables the system to maintain efficient energy conversion under different load conditions.

[0074] Furthermore, the system also integrates a temperature monitoring module, which monitors the temperature of the circuit in real time through a temperature sensor and feeds back the temperature data to MCU-1. MCU-1 adjusts the duty cycle of the PWM signal according to the temperature data to optimize the conversion efficiency under high temperature conditions. In addition, the system also adds a transient voltage protection module, which protects circuit components from voltage transients through a transient voltage suppressor (TVS). The transient voltage protection module uses a fast-response TVS suppressor, such as the SM110CA model. When the circuit voltage changes transiently, the TVS suppressor will respond quickly and clamp the voltage within a safe range to prevent the circuit components from being damaged by overvoltage. It can be understood that the addition of the temperature monitoring module and the transient voltage protection module further improves the safety of the system.

[0075] The benefit of this embodiment is that by integrating the power adapter, load device, temperature monitoring module and transient voltage protection module, a complete bus voltage reduction system is constructed, achieving efficient energy conversion and stable voltage output under different load conditions. In addition, the multi-module collaborative work of the system improves the overall reliability and safety, and is suitable for a variety of complex charging application scenarios.

[0076] Embodiment 10 In order to solve the high efficiency and low standby power consumption problems of the power adapter in the single-stage PFC architecture of PD fast charging products, this embodiment further optimizes the design of the power adapter and achieves efficient energy conversion, low standby power consumption and compliance with the requirements of Energy Efficiency Regulation VI by adopting a bus voltage reduction system.

[0077] In this embodiment, the power adapter integrates a bus voltage reduction system. MCU-1 detects the output voltage of the C1 / C2 port in real time through the AD interface, and controls the rise and fall process of the bus voltage according to the detection result. The optocoupler connects MCU-1 and MOS tubes Q7 and Q8 to isolate the signal path and ensure the reliability and safety of signal transmission. When it is detected that the output voltage of the C1 / C2 port is less than 16V or there is no device in standby mode, the IO port of MCU-1 outputs a low level of 0V, the optocoupler is not turned on, the MOS tube Q7 and the MOS tube Q8 are both cut off, and the bus voltage is gradually reduced from 31V to 17V. The voltage reduction process first drops to 22V and then to 17V.

[0078] Furthermore, the power adapter adopts a multi-stage filtering design to ensure the purity and stability of the output voltage. The primary filter adopts an LC filter, and the secondary filter adopts an RC filter. Through the design of the multi-stage filter, the high-frequency noise and electromagnetic interference in the input voltage are effectively filtered out. This design not only improves the output quality of the power adapter, but also extends the service life of the load equipment. It should be understood that the design of the multi-stage filter enables the power adapter to maintain stable performance in a complex electromagnetic environment.

[0079] Furthermore, the power adapter also integrates a variety of safety protection mechanisms, including over-temperature protection, over-voltage protection and short-circuit protection. Over-temperature protection is achieved through a temperature sensor integrated inside the power adapter. When the temperature is detected to exceed the preset threshold, MCU-1 will automatically reduce the duty cycle of the PWM signal to reduce power consumption and heat. Overvoltage protection is achieved through the voltage regulator LDO and fast recovery diode D14. When the output voltage exceeds the set value, the voltage regulator LDO will automatically adjust the output to keep the voltage within a safe range. Short-circuit protection is achieved through the current detection module. When it is detected that the load current exceeds the safety threshold, MCU-1 will automatically cut off the output to prevent damage to the load device and the power adapter. It can be understood that the addition of these protection mechanisms significantly improves the safety and reliability of the power adapter.

[0080] The benefit of this embodiment is that by integrating an excellent bus voltage reduction system, high-efficiency energy conversion and low standby power consumption of the power adapter are achieved, meeting the requirements of Energy Efficiency Regulation VI. In addition, the addition of multi-stage filtering design and multiple safety protection mechanisms further improves the output quality and safety of the power adapter.

[0081] The above embodiments further illustrate the purpose, technical solutions and beneficial effects of the present invention. It should be understood that the above are only specific implementation methods of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made on the basis of the technical solutions of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for reducing bus voltage using a single-stage PFC architecture, characterized in that: The steps of the bus voltage reduction method include: Detect the output voltage of the C1 / C2 port in the circuit to determine whether the output voltage is less than a preset threshold value of 16V; When it is detected that the output voltages are all less than the preset threshold value 16V or no device is connected in standby mode, the output IO is set to a low level through the MCU instruction to trigger the voltage reduction mechanism of the circuit to reduce the bus voltage from 31V to 22V and then to 17V; When it is detected that any end of the output voltage is greater than or equal to the preset threshold value 16V, the output IO is set to a high level of 3V through the MCU instruction to maintain the bus voltage rising to 22V and then to 31V; The voltage switching transition process is controlled by adjusting the duty cycle of the PWM signal output by the MCU and the resistance value in the circuit to smoothly switch between different working modes and reduce the impact of voltage mutation on circuit components; During the entire voltage switching and maintenance process, the output state of the bus voltage is successively evaluated and adjusted through the feedback mechanism.

2. The bus voltage reduction method using a single-stage PFC architecture according to claim 1, characterized in that: In the process of maintaining the bus voltage to rise to 22V and then to 31V, the temperature of the circuit is monitored by an ambient temperature detector, and the duty cycle of the PWM signal is dynamically adjusted according to the temperature change.

3. The bus voltage reduction method using a single-stage PFC architecture according to claim 1, characterized in that: In the step of detecting the output voltage of the C1 / C2 port in the circuit, a dual-channel differential amplifier is used to improve the detection accuracy.

4. The bus voltage reduction method using a single-stage PFC architecture according to claim 1, characterized in that: The output IO is set to a low level through the MCU instruction, and a time adjustment algorithm is used in the process to optimize the charging and discharging time of the capacitor C9 and the capacitor C11. The expression of the time adjustment algorithm is: , where T min is the minimum charge and discharge time of the capacitor, f is the PWM signal frequency, V th is the voltage threshold, V in is the input voltage, and V out is the output voltage.

5. The bus voltage reduction method using a single-stage PFC architecture according to claim 1, characterized in that: The duty cycle optimization algorithm is used in the transition process of controlling the voltage switching by adjusting the duty cycle of the PWM signal output by the MCU and the resistance value in the circuit. The expression of the duty cycle optimization algorithm is: , where D opt represents the optimal PWM duty cycle, V load is the load voltage, V offset is the voltage offset, V input is the input voltage, V output is the output voltage, and K is the comparator gain factor.

6. The method for reducing bus voltage using a single-stage PFC architecture according to claim 1, characterized in that: The method further comprises the following steps: When entering the standby state, the deep sleep mechanism is automatically activated to maintain the bus voltage at 17V; A transient voltage suppression circuit is added to the control circuit to protect circuit components when the voltage rises or drops instantly.

7. The method for reducing bus voltage using a single-stage PFC architecture according to claim 1, characterized in that: An adaptive control algorithm is used to dynamically adjust the PWM signal and related resistance value based on the current working state of the circuit to adaptively respond to different PD voltage charging conditions. The adaptive control algorithm includes adjusting the control strategy by monitoring the performance parameters of the circuit under different load conditions.

8. A bus voltage reduction circuit using a single-stage PFC architecture, characterized in that: The bus voltage reduction circuit comprises: The MCU is used to output PWM signals and high / low level commands, and controls the rise and fall of the bus voltage according to the output voltage status of the C1 / C2 port detected; An optocoupler connected to the MCU, and a MOS transistor Q7 and a MOS transistor Q8 connected to the optocoupler, wherein the optocoupler is used to isolate the signal path between the MCU and the MOS transistor Q7 and the MOS transistor Q8, and forward a level signal according to a received MCU instruction; The MOS tube Q7 receives the signal transmitted from the optical coupler. When the optical coupler transmits a high level, the MOS tube Q7 is turned on, and the voltage regulator LDO charges the capacitor C9 through the diode D10. When the optical coupler transmits a low level, the MOS tube Q7 is turned on and off, and the capacitor C9 is discharged to the ground through the resistor R39 and the resistor R35. The charging and discharging state of the capacitor C9 is controlled by adjusting the PWM duty cycle to ensure the driving state of the MOS tube Q7. The MOS tube Q8 receives the signal transmitted from the optical coupler. When the optical coupler transmits a high level, the MOS tube Q8 is turned on, and the voltage regulator LDO charges the capacitor C15 through the resistor R12, the voltage regulator ZD2 and the fast recovery diode D14. When the optical coupler transmits a low level, the MOS tube Q8 is turned off, and the capacitor C11 is discharged to the ground through the fast recovery diode D13 and the resistor R35. The charging and discharging state of the capacitor C11 is controlled by adjusting the PWM duty cycle and the parameters of the resistor R12, the capacitor C11 and the fast recovery diode D13 to ensure that the MOS tube Q8 is not turned on when the voltage of the capacitor C11 is less than the threshold voltage 5.1V of the voltage regulator ZD2. The bus voltage rise and fall process includes: When the output voltage of C1 / C2 port is less than 16V or there is no device in standby mode, MCU outputs low level 0V, and the bus voltage drops from 31V to 17V, first to 22V and then to 17V; When the output voltage of any port C1 / C2 is greater than 16V, the MCU outputs a high level of 3V, and the bus voltage remains at 31V or increases from 17V to 31V. The boost process first increases to 22V and then to 31V.

9. A bus voltage reduction system using a single-stage PFC architecture, comprising the bus voltage reduction circuit using a single-stage PFC architecture as claimed in claim 8, characterized in that: The system also includes a power adapter, a load device, a temperature monitoring module and a transient voltage protection module connected to the bus voltage reduction circuit. The bus voltage reduction system automatically adjusts the bus voltage according to the needs of the load device.

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