Clock signal generating circuit with fixed duty ratio and chip
By designing a fixed duty cycle clock signal generation circuit, using capacitor charge and discharge and pulse signal generation techniques, the problem of slow response time in traditional clock signal generation methods is solved, and fast response and efficient clock signal generation are achieved.
Patent Information
- Application Number
- CN202411953357.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-27
- Publication Date
- 2025-03-04
AI Technical Summary
In the traditional parallel interleaved clock signal generation method, the phase-locked loop circuit has a complex structure and a slow response time, making it difficult to quickly adjust the clock frequency, which affects the current equalization and parallel effect of the output voltage.
A fixed duty cycle clock signal generation circuit is designed, and output signals with the same frequency as the input signal and a fixed duty cycle are generated through the capacitor charge and discharge circuit, the pulse signal generation circuit, the peak holding circuit, the signal processing circuit and the comparison output circuit, thereby avoiding the need for negative feedback loops and high-frequency clocks.
It realizes rapid response to the frequency changes of the input signal, generates an output signal with the same frequency as the input signal and a fixed duty cycle, simplifies the circuit structure, reduces costs, and improves the response speed of the parallel interleaved clock.
Smart Images
Figure CN119561525A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuits, and in particular to a fixed duty cycle clock signal generating circuit and chip. Background Art
[0002] Traditional switching power supplies are mostly single-module power supplies that can provide limited power. With the development of technology, electronic equipment often requires large-capacity DC power supplies. When large-capacity power supply is required, using a single power supply makes it difficult to handle the switching stress of the switch tube and the rectifier tube, and the heat dissipation problem is also difficult to solve, making the design and implementation very difficult.
[0003] Compared with the traditional single power supply, parallel power supply has many advantages, such as large capacity, high efficiency, high reliability, and can be configured as a redundant system as needed. It can realize the modularization of power supply, the expandability of power supply capacity, and reduce cost investment. In parallel form, a high-power power supply system is built with small-power power modules. Since each power module in the system only shares a small part of the total power capacity, it is easier to implement. Therefore, the parallel power supply system is convenient for realizing large capacity. In addition, multi-channel parallel interleaved operation can greatly reduce the ripple of output current and output voltage.
[0004] Interleaved parallel power supplies need to provide clock signals with the same frequency but different phases.
[0005] The traditional parallel interleaved clock is generated by a phase-locked loop (PLL), which detects the input signal clock frequency and generates an output signal with the same clock frequency as the input signal but with a different phase. The PLL circuit structure is relatively complex, and loop compensation is required for the PLL circuit. Its output response time is slow. When the clock frequency of the main power module changes, the clock provided to the slave module cannot respond quickly, which will affect the output voltage ripple and the current sharing between the modules, resulting in a poor parallel effect.
[0006] The traditional parallel interleaved clock can also be generated by dividing the high-frequency clock signal, but this solution requires a high-frequency digital clock. The cost of designing a high-frequency clock inside the power chip is too high, and the clock division is a discrete signal with a minimum step, which cannot produce an accurate interleaved phase, affecting the output voltage ripple and the current distribution between modules, resulting in a poor parallel effect. Summary of the invention
[0007] In view of this, the technical problem to be solved by the present invention is to provide a fixed duty cycle clock signal generating circuit and chip, which at least solves one of the technical problems existing in the prior art to a certain extent.
[0008] As a first aspect of the present invention, the technical solution of the embodiment of the fixed duty cycle clock signal generating circuit provided is as follows: A fixed duty cycle clock signal generating circuit is used to generate an output signal with the same frequency as an input signal and a fixed duty cycle, including: A capacitor charging and discharging circuit comprises a constant current source I1, a capacitor C1, a switch tube S1 and a switch tube S2, wherein the input end of the constant current source I1 is used to input a power supply voltage, the output end of the constant current source I1 is simultaneously connected to one end of the capacitor C1, one end of the switch tube S1 and one end of the switch tube S2, the other end of the switch tube S1 outputs a first signal, and the other end of the capacitor C1 and the other end of the switch tube S2 are used for grounding; A pulse signal generating circuit, used for generating a first control signal and a second control signal according to the input signal, to control the on and off of the switch tube S1 and the switch tube S2 respectively, wherein the control strategy is: in each cycle of the input signal, when the rising edge or the falling edge of the input signal arrives, the switch tube S1 is turned on for a first time length and then turned off; when the switch tube S1 is turned off, the switch tube S2 is turned on for a second time length and then turned off; a peak holding circuit, connected to the other end of the switch tube S1, for extracting the maximum value of the first signal when the switch tube S1 is turned on, and after the switch tube S1 is turned off, holding the maximum value of the first signal and outputting it as a first reference voltage; A signal processing circuit connected to the output end of the peak holding circuit, used for enhancing the driving capability of the first reference voltage and then scaling it down to output a second reference voltage; The comparison output circuit is used to compare the first signal with the second reference voltage and output the output signal with the same frequency as the input signal and a fixed duty cycle.
[0009] Preferably, the circuit for controlling the switching on and off of the switch tube S1 in the pulse signal generating circuit comprises a NOR gate NOR1, a NOR gate NOR2, a current source I2, a PMOS tube M2, an NMOS tube M3 and a capacitor C3; the first input end of the NOR gate NOR1 is used to input the input signal, the input end of the current source I2 is used to input the power supply voltage, and the output end is connected to the source of the PMOS tube M2, the drain of the PMOS tube M2 is simultaneously connected to the first input end of the NOR gate NOR2, the drain of the NMOS tube M3 and one end of the capacitor C3, the source of the NMOS tube M3 and the other end of the capacitor C3 are connected together for grounding, the output end of the NOR gate NOR1 is simultaneously connected to the gate of the PMOS tube M2, the gate of the NMOS tube M3 and the second input end of the NOR gate NOR2, and the second input end of the NOR gate NOR1 and the output end of the NOR gate NOR2 are connected together for outputting the first control signal.
[0010] Preferably, the circuit for controlling the on and off of the switch tube S2 in the pulse signal generating circuit includes an inverter INV1, a NOR gate NOR3, a NOR gate NOR4, a current source I3, a PMOS tube M4, an NMOS tube M5 and a capacitor C4; the input end of the inverter INV1 inputs the first control signal, and the output end is connected to the first input end of the NOR gate NOR3; the input end of the current source I3 is used to input the power supply voltage, and the output end is connected to the source of the PMOS tube M4, and the drain of the PMOS tube M4 is connected to the drain of the PMOS tube M4. The first input end of the NOR gate NOR4, the drain of the NMOS tube M5 and one end of the capacitor C4 are connected at the same time, the source of the NMOS tube M5 and the other end of the capacitor C4 are connected together and used for grounding, the output end of the NOR gate NOR3 is simultaneously connected to the gate of the PMOS tube M4, the gate of the NMOS tube M5 and the second input end of the NOR gate NOR4, the second input end of the NOR gate NOR3 and the output end of the NOR gate NOR4 are connected together to output the second control signal.
[0011] Preferably, the peak holding circuit comprises a capacitor C2, one end of the power supply C2 is connected to the other end of the switch tube S1, and the other end is grounded.
[0012] Preferably, the signal processing circuit includes an operational amplifier, an NMOS tube M1, a resistor R1 and a resistor R2, the first reference voltage is inputted into the same-direction input terminal of the operational amplifier, and the output terminal is connected to the gate of the NMOS tube M1, the drain of the NMOS tube M1 is used to input the power supply voltage, and the source is simultaneously connected to the reverse input terminal of the operational amplifier and one end of the resistor R1, the other end of the resistor R1 and one end of the resistor R2 are connected together to output the second reference voltage, and the other end of the resistor R2 is used for grounding.
[0013] Preferably, the comparison output circuit comprises a comparator, wherein the comparator receives the second reference voltage at its non-inverting input, receives the first signal at its inverting input, and outputs the output signal having the same frequency as the input signal and a fixed duty cycle at its output.
[0014] As a second aspect of the present invention, the embodiment and technical solution of the chip provided are as follows: A chip, comprising: a fixed duty cycle clock signal generating circuit as described in any one of the first aspects above.
[0015] Compared with the prior art, the present invention has the following beneficial effects: (1) The capacitor charging and discharging circuit, pulse signal generating circuit, peak holding circuit, signal processing circuit, and comparison output circuit provided in the fixed duty cycle clock signal generating circuit embodiment of the present invention have an input signal flow direction only from input to output, and there is no negative feedback loop, and the signal frequency of the pulse signal generating circuit is the same as the input signal frequency, so loop compensation and high-frequency clock are not required, the circuit structure is simple, and the cost is lower than that of the prior art; (2) In the embodiment of the fixed duty cycle clock signal generating circuit of the present invention, a switch tube S2 is provided. The switch tube S2 discharges the voltage on the capacitor C1 once every cycle. Therefore, the first reference voltage is updated in each working cycle (i.e., each charging and discharging cycle of the capacitor). When the frequency of the input signal changes, the output signal only needs one working cycle to complete the frequency adjustment. Therefore, the embodiment of the fixed duty cycle clock signal generating circuit of the present invention has a faster response speed than the prior art and can respond quickly when the frequency of the input signal changes. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 The fixed duty cycle clock signal generating circuit schematic diagram of the first embodiment of the present invention; Figure 2 A specific schematic diagram of a fixed duty cycle clock signal generating circuit according to a first embodiment of the present invention; Figure 3 for Figure 2 The working waveform when the frequency of the circuit input signal is fixed; Figure 4 for Figure 2 The working waveform when the frequency of the circuit input signal changes; Figure 5 A specific schematic diagram of a pulse signal generating circuit for controlling switch S1; Figure 6 The pulse signal generating circuit working waveform for controlling switch S1; Figure 7 A specific schematic diagram of a pulse signal generating circuit for controlling switch S2; Figure 8 The pulse signal generating circuit working waveform for controlling switch S2. DETAILED DESCRIPTION
[0017] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application may be combined with each other.
[0018] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.
[0019] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application are described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, the process, method, system, product or equipment comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or equipment.
[0020] It should be understood that, in the specification, claims and drawings, when a step is described as being connected to another step, the step may be directly connected to the other step, or be connected to the other step through a third step; when an element / unit is described as being "connected" to another element / unit, the element / unit may be "directly connected" to the other element / unit, or be "connected" to the other element / unit through a third element / unit.
[0021] In addition, the drawings of the present disclosure are only schematic diagrams of the present disclosure and are not necessarily drawn to scale. The same symbols in the drawings represent the same or similar parts, and thus repeated descriptions thereof will be omitted. Some of the block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented using software, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontrollers.
[0022] First embodiment The present embodiment provides a fixed duty cycle clock signal generating circuit, the purpose of which is to generate an output signal with the same frequency as the input signal and a fixed duty cycle by detecting the frequency of the input signal. The inventive concept of the fixed duty cycle clock signal generating circuit of the present embodiment is: by detecting the frequency of the input signal, a sawtooth wave (RAMP) signal with the same frequency as the input signal is generated by controlling the charging and discharging of the capacitor, and then the peak value of the RAMP signal is maintained by a sampling and holding circuit, and the peak voltage after maintenance is divided as a reference benchmark, and the RAMP is compared with the reference benchmark to generate an output clock signal with the same frequency as the input signal and a different duty cycle. Since the circuit responds to the frequency change of the input signal in each cycle and the circuit has no negative feedback loop, it can quickly respond to the change of the input signal frequency and generate an output signal with the same frequency as the input signal and a fixed duty cycle.
[0023] This embodiment is based on the charging and discharging principle of capacitors, and the specific analysis is as follows: The current-voltage relationship of a capacitor is as follows: (1) where i C is the current on the capacitor, C is the capacitance value, dU C is the voltage change on the capacitor, and dt is the time change. When the current on the capacitor is a fixed current, the following formula (2) is obtained: (2) Among them U C is the voltage on the capacitor, I is the fixed current for charging the capacitor, t is the charging time of the capacitor, and C is the capacitance of the capacitor. When a charge and discharge cycle is the same as the cycle of the input signal, a sawtooth wave signal with the same frequency as the input signal can be generated.
[0024] The peak voltage of the sawtooth wave is sampled and held, and the held signal is used as the first reference VREF1. VREF1 is enhanced in driving capability through a buffer, and the enhanced signal is scaled down. The scaled-down signal is used as the second reference VREF2. The RAMP signal is compared with VREF2 to obtain an output signal that is the same as the input signal but has a different duty cycle. The duty cycle of the output signal is determined by VREF2.
[0025] Figure 1 The fixed duty cycle clock signal generating circuit schematic diagram of the first embodiment of the present invention is shown in FIG. Figure 1 , including: A capacitor charging and discharging circuit includes a constant current source I1, a capacitor C1, a switch tube S1 and a switch tube S2, wherein the input end of the constant current source I1 is used to input a power supply voltage, the output end of the constant current source I1 is simultaneously connected to one end of the capacitor C1, one end of the switch tube S1 and one end of the switch tube S2, the other end of the switch tube S1 outputs a first signal RAMP, and the other ends of the capacitor C1 and the other ends of the switch tube S2 are used for grounding; The pulse signal generating circuit is used to generate a first control signal and a second control signal according to an input signal CLK_IN, and respectively control the on and off of the switch tube S1 and the switch tube S2. The control strategy is: in each cycle of the input signal CLK_IN, when the rising edge or the falling edge of the input signal CLK_IN arrives, the switch tube S1 is turned on for a first time length and then turned off; when the switch tube S1 is turned off, the switch tube S2 is turned on for a second time length and then turned off; A peak holding circuit connected to the other end of the switch tube S1, used for extracting the maximum value of the first signal RAMP when the switch tube S1 is turned on, and after the switch tube S1 is turned off, holding the maximum value of the first signal RAMP and outputting it as the first reference voltage VREF1; A signal processing circuit connected to the output end of the peak holding circuit, used to enhance the driving capability of the first reference voltage VREF1 and then scale it down to output a second reference voltage VREF2; The comparison output circuit is used for comparing the first signal RAMP with the second reference voltage VREF2, and outputting an output signal CLK_OUT having the same frequency as the input signal CLK_IN and a fixed duty cycle.
[0026] In the present embodiment, the capacitor charging and discharging circuit, the pulse signal generating circuit, the peak holding circuit, the signal processing circuit, and the comparison output circuit provided in the embodiment of the fixed duty cycle clock signal generating circuit of the present invention have an input signal flow direction only from input to output, wherein there is no negative feedback loop, and the signal frequency of the pulse signal generating circuit is the same as the input signal frequency, so no loop compensation or high-frequency clock is required, the circuit structure is simple, and the cost is lower than that of the prior art; in addition, the fixed duty cycle clock signal generating circuit of the present embodiment is provided with a switch tube S2, and the switch tube S2 discharges the voltage on the capacitor C1 once per cycle, so the first reference voltage is updated in each working cycle (i.e., each charging and discharging cycle of the capacitor), and when the frequency of the input signal changes, the output signal only needs one working cycle to complete the frequency adjustment, so the embodiment of the fixed duty cycle clock signal generating circuit of the present invention has a faster response speed than that of the prior art, and can respond quickly when the frequency of the input signal changes.
[0027] Figure 2A specific schematic diagram of a fixed duty cycle clock signal generating circuit of the first embodiment of the present invention. In which: the peak holding circuit includes a capacitor C2, one end of the power supply C2 is connected to the other end of the switch tube S1, and the other end is used for grounding; the signal processing circuit includes an operational amplifier, an NMOS tube M1, a resistor R1 and a resistor R2, the same-direction input end of the operational amplifier inputs the first reference voltage VREF1, the output end is connected to the gate of the NMOS tube M1, the drain of the NMOS tube M1 is used to input the power supply voltage VCC, the source is simultaneously connected to the reverse input end of the operational amplifier and one end of the resistor R1, the other end of the resistor R1 and one end of the resistor R2 are connected together to output the second reference voltage VREF2, and the other end of the resistor R2 is used for grounding; the comparison output circuit includes a comparator, the same-direction input of the comparator inputs the second reference voltage VREF2, the reverse input end inputs the first signal RAMP, and the output end outputs the output signal CLK_OUT with the same frequency as the input signal CLK_IN and a fixed duty cycle.
[0028] Figure 2 The working principle of the circuit is analyzed as follows: (1) When the input signal is a fixed frequency The working waveform of the fixed duty cycle clock signal generating circuit is as follows Figure 2 As shown. When the rising edge of the input signal CLK_IN arrives, the switch tube S1 is turned on and the first signal RAMP voltage is sampled to the capacitor C2; when the pulse time of the switch tube S1 ends, the switch tube S1 is turned off, and the maximum value of the first signal RAMP voltage is maintained on the capacitor C2 as the first reference voltage VREF1, and the switch tube S2 is turned on at the same time to discharge the capacitor C1 to 0V; when the pulse time of the switch tube S2 ends, the switch tube S2 is turned off, and the current source I1 recharges the capacitor C1 to generate the first signal RAMP. The first reference voltage VREF1 is processed by the operational amplifier, NMOS tube M1, resistor R1 and resistor R2 to generate the second reference voltage VREF2. According to the virtual short and virtual open principle of the operational amplifier, the second reference voltage VREF2 is as shown in formula (3).
[0029] (3) The first signal RAMP is compared with the second reference voltage VREF2 to generate a new clock signal CLK_OUT. The frequency of CLK_OUT is the same as that of CLK_IN. The duty cycle is determined by the second reference voltage VREF2. The duty cycle of CLK_OUT can be adjusted by adjusting the resistance values of resistors R1 and R2. When R1=R2 is set, the duty cycle of CLK_OUT is 50%. The duty cycle D of the CLK_OUT signal is shown in Formula 4.
[0030] (4) (2) When the input signal frequency changes The working waveform of the fixed duty cycle clock signal generating circuit is as follows Figure 3 As shown. The frequency of the input signal CLK_IN does not change in the first three cycles, and the circuit working state is the same as the fixed frequency working state of the input signal. The frequency of the input signal CLK_IN decreases in the fourth cycle, and the first reference voltage VREF1 still uses the RAMP maximum value maintained in the third cycle. The duty cycle of CLK_OUT does not change in time and is less than the set duty cycle, but the frequency is consistent with the CLK_IN signal; at the end of the fourth working cycle, the first reference voltage VREF1 sampled and held by capacitor C2 increases, and the second reference voltage VREF2 increases synchronously; in the fifth cycle, CLK_OUT is a clock signal with the same frequency as CLK_IN and the same duty cycle as the set duty cycle, and the adjustment can be completed in only one working cycle.
[0031] Figure 5 For a specific schematic diagram of the pulse signal generating circuit for controlling switch S1, please refer to Figure 5 The circuit for controlling the switch tube S1 to be turned on and off in the pulse signal generating circuit includes a NOR gate NOR1, a NOR gate NOR2, a current source I2, a PMOS tube M2, an NMOS tube M3 and a capacitor C3; the first input end of the NOR gate NOR1 is used to input an input signal, the input end of the current source I2 is used to input a power supply voltage, and the output end is connected to the source of the PMOS tube M2, the drain of the PMOS tube M2 is simultaneously connected to the first input end of the NOR gate NOR2, the drain of the NMOS tube M3 and one end of the capacitor C3, the source of the NMOS tube M3 and the other end of the capacitor C3 are connected together for grounding, the output end of the NOR gate NOR1 is simultaneously connected to the gate of the PMOS tube M2, the gate of the NMOS tube M3 and the second input end of the NOR gate NOR2, the second input end of the NOR gate NOR1 and the output end of the NOR gate NOR2 are connected together for outputting a first control signal.
[0032] Figure 6 For the pulse signal generating circuit working waveform of the control switch S1, please refer to Figure 6 When the input signal CLK_IN rises, the output of NOR1 becomes low, that is, the voltage at point A turns low, and the control signal of switch tube S1 becomes high; at the same time, PMOS tube M2 is turned on, NMOS tube M3 is turned off, and capacitor C3 is charged by constant current source I2. When the voltage at point B is charged to the flip threshold of NOR gate NOR2, the output of NOR gate NOR2 is low, and the control signal of switch tube S1 becomes low. The control signal pulse time of switch tube S1 is related to the current source I2 and the capacitance of capacitor C3. The control signal pulse width of switch tube S1 can be adjusted by adjusting the current value of constant current source I2 and the capacitance of C3.
[0033] Figure 7For a specific schematic diagram of the pulse signal generating circuit for controlling switch S2, please refer to Figure 6 The circuit for controlling the switch tube S2 to be turned on and off in the pulse signal generating circuit includes an inverter INV1, a NOR gate NOR3, a NOR gate NOR4, a current source I3, a PMOS tube M4, an NMOS tube M5 and a capacitor C4; the input end of the inverter INV1 inputs the first control signal, and the output end is connected to the first input end of the NOR gate NOR3; the input end of the current source I3 is used to input the power supply voltage, and the output end is connected to the source of the PMOS tube M4; the drain of the PMOS tube M4 is simultaneously connected to the first input end of the NOR gate NOR4, the drain of the NMOS tube M5 and one end of the capacitor C4; the source of the NMOS tube M5 and the other end of the capacitor C4 are connected together and then grounded; the output end of the NOR gate NOR3 is simultaneously connected to the gate of the PMOS tube M4, the gate of the NMOS tube M5 and the second input end of the NOR gate NOR4; the second input end of the NOR gate NOR3 and the output end of the NOR gate NOR4 are connected together to output the second control signal.
[0034] Figure 8 To control the pulse signal of switch S2, please refer to Figure 8 , when the control signal of switch tube S1 falls, the output of inverter INV1 becomes high, and the output of NOR gate NOR3 becomes low, that is, the voltage at point C turns low, and the control signal of switch tube S2 becomes high; at the same time, PMOS tube M4 is turned on, NMOS tube M5 is turned off, and capacitor C4 is charged by constant current source I3. When the voltage at point D is charged to the flip threshold of NOR gate NOR4, the output of NOR gate NOR4 is low, and the control signal of switch tube S2 becomes low. The control signal pulse time of switch tube S2 is related to the current source I3 and the capacitance of capacitor C4. The control signal pulse width of switch tube S2 can be adjusted by adjusting the current value of I3 and the capacitance of C4.
[0035] It should be noted that Figure 3 The waveform diagram uses the rising edge of the input signal CLK_IN to trigger the switch tube S1 to turn on. As an equivalent replacement, the falling edge of the input signal CLK_IN can also be used to trigger the switch tube S1 to turn on. In this case, the input signal CLK_IN only needs to be reversed and then input into the existing embodiment, which can also achieve the purpose of the invention.
[0036] Second embodiment This embodiment provides a chip, which comprises any fixed duty cycle clock signal generating circuit in the first embodiment.
[0037] Since this embodiment includes any one of the fixed duty cycle clock signal generating circuits in the first embodiment, it has low cost and fast response.
[0038] The above are only preferred embodiments of the present invention, and it should be noted that the above preferred embodiments should not be regarded as limiting the present invention. For those skilled in the art, several equivalent substitutions, improvements and modifications can be made without departing from the spirit and scope of the present invention, and these equivalent substitutions, improvements and modifications should also be regarded as the protection scope of the present invention. The embodiments will not be repeated here, and the protection scope of the present invention shall be based on the scope defined by the claims.
Claims
1. A fixed duty cycle clock signal generating circuit, used to generate an output signal with the same frequency as an input signal and a fixed duty cycle, characterized in that: include: A capacitor charging and discharging circuit comprises a constant current source I1, a capacitor C1, a switch tube S1 and a switch tube S2, wherein the input end of the constant current source I1 is used to input a power supply voltage, the output end of the constant current source I1 is simultaneously connected to one end of the capacitor C1, one end of the switch tube S1 and one end of the switch tube S2, the other end of the switch tube S1 outputs a first signal, and the other end of the capacitor C1 and the other end of the switch tube S2 are used for grounding; A pulse signal generating circuit, used for generating a first control signal and a second control signal according to the input signal, to control the on and off of the switch tube S1 and the switch tube S2 respectively, wherein the control strategy is: in each cycle of the input signal, when the rising edge or the falling edge of the input signal arrives, the switch tube S1 is turned on for a first time length and then turned off; when the switch tube S1 is turned off, the switch tube S2 is turned on for a second time length and then turned off; a peak holding circuit, connected to the other end of the switch tube S1, for extracting the maximum value of the first signal when the switch tube S1 is turned on, and after the switch tube S1 is turned off, holding the maximum value of the first signal and outputting it as a first reference voltage; A signal processing circuit connected to the output end of the peak holding circuit, used for enhancing the driving capability of the first reference voltage and then scaling it down to output a second reference voltage; The comparison output circuit is used to compare the first signal with the second reference voltage and output the output signal with the same frequency as the input signal and a fixed duty cycle.
2. The fixed duty cycle clock signal generating circuit according to claim 1, characterized in that: The circuit for controlling the switching on and off of the switch tube S1 in the pulse signal generating circuit includes a NOR gate NOR1, a NOR gate NOR2, a current source I2, a PMOS tube M2, an NMOS tube M3 and a capacitor C3; the first input end of the NOR gate NOR1 is used to input the input signal, the input end of the current source I2 is used to input the power supply voltage, and the output end is connected to the source of the PMOS tube M2, the drain of the PMOS tube M2 is simultaneously connected to the first input end of the NOR gate NOR2, the drain of the NMOS tube M3 and one end of the capacitor C3, the source of the NMOS tube M3 and the other end of the capacitor C3 are connected together for grounding, the output end of the NOR gate NOR1 is simultaneously connected to the gate of the PMOS tube M2, the gate of the NMOS tube M3 and the second input end of the NOR gate NOR2, the second input end of the NOR gate NOR1 and the output end of the NOR gate NOR2 are connected together for outputting the first control signal.
3. The fixed duty cycle clock signal generating circuit according to claim 1, characterized in that: The circuit for controlling the switching on and off of the switch tube S2 in the pulse signal generating circuit includes an inverter INV1, a NOR gate NOR3, a NOR gate NOR4, a current source I3, a PMOS tube M4, an NMOS tube M5 and a capacitor C4; the input end of the inverter INV1 inputs the first control signal, and the output end is connected to the first input end of the NOR gate NOR3; the input end of the current source I3 is used to input the power supply voltage, and the output end is connected to the source of the PMOS tube M4; the drain of the PMOS tube M4 is simultaneously connected to the first input end of the NOR gate NOR4, the drain of the NMOS tube M5 and one end of the capacitor C4; the source of the NMOS tube M5 and the other end of the capacitor C4 are connected together for grounding; the output end of the NOR gate NOR3 is simultaneously connected to the gate of the PMOS tube M4, the gate of the NMOS tube M5 and the second input end of the NOR gate NOR4; the second input end of the NOR gate NOR3 and the output end of the NOR gate NOR4 are connected together for outputting the second control signal.
4. The fixed duty cycle clock signal generating circuit according to claim 1, characterized in that: The peak holding circuit includes a capacitor C2, one end of the power supply C2 is connected to the other end of the switch tube S1, and the other end is grounded.
5. The fixed duty cycle clock signal generating circuit according to claim 1, characterized in that: The signal processing circuit includes an operational amplifier, an NMOS tube M1, a resistor R1 and a resistor R2. The first reference voltage is input to the same-direction input terminal of the operational amplifier, and the output terminal is connected to the gate of the NMOS tube M1. The drain of the NMOS tube M1 is used to input the power supply voltage, and the source is simultaneously connected to the reverse input terminal of the operational amplifier and one end of the resistor R1. The other end of the resistor R1 and one end of the resistor R2 are connected together to output the second reference voltage, and the other end of the resistor R2 is used for grounding.
6. The fixed duty cycle clock signal generating circuit according to claim 1, characterized in that: The comparison output circuit comprises a comparator, wherein the comparator receives the second reference voltage at its non-inverting input terminal, receives the first signal at its inverting input terminal, and outputs an output signal having the same frequency as the input signal and a fixed duty cycle at its output terminal.
7. A chip, characterized in that: The invention comprises the fixed duty cycle clock signal generating circuit as described in any one of claims 1 to 6.