Pulse trigger and phase detector

Abstract

The present disclosure provides a pulse trigger and a phase discriminator. The pulse trigger includes a logic module, a first input stage module, and a second input stage module; the circuit structures of the first input stage module and the second input stage module are the same; the logic module includes a first charging path corresponding to the positive terminal signal of the differential signal of the first clock signal, and a second charging path corresponding to the positive terminal signal of the differential signal of the second clock signal; the second clock signal and the first clock signal are clock signals with the same frequency, and there is a phase difference between the second clock signal and the first clock signal; the logic module is respectively connected to the first input stage module and the second input stage module. When the first clock signal is a rising edge signal, the logic module conducts based on the input signals of the first input stage module and the second input stage module, and the inverted output terminal of the pulse trigger outputs a high-level signal. By accelerating the charge and discharge stages of the pulse trigger, shortening the dead time, and improving the resolution of the pulse trigger, static errors are eliminated.

Description

Technical Field

[0001] The present disclosure relates to the field of digital circuits, and in particular to a pulse trigger and a phase detector. Background Art

[0002] In digital circuit design, the phase detector is a key component used to compare the phase relationship of two clock signals of the same frequency. Its basic function is to use the rising edge of one input clock signal to sample another clock signal and output a digital signal based on the relative position of the two.

[0003] In order to achieve high-precision phase detection, it is necessary to ensure that the static error of the phase detector is as small as possible. Static error refers to the deviation between the output value of the phase detector and the actual phase difference in the absence of external interference. Static error is the delay time caused by gate circuit delay in the phase detector. In the existing phase detector circuit structure, static error exists, and when the rising edges of the two clock signals are close, the phase detector will make a misjudgment and fail to work. Summary of the invention

[0004] The technical problem to be solved by the present disclosure is to overcome the defect of static error in the phase detector in the prior art, and to provide a pulse trigger and a phase detector.

[0005] The present invention solves the above technical problems through the following technical solutions:

[0006] In a first aspect, a pulse trigger is provided, comprising a logic module, a first input stage module and a second input stage module;

[0007] The circuit structures of the first input stage module and the second input stage module are the same;

[0008] The first input stage module is used to receive the differential signal positive end signal and the differential signal negative end signal of the first clock signal, and the differential signal positive end signal of the second clock signal;

[0009] The second input stage module is used to receive the differential signal positive end signal and the differential signal negative end signal of the second clock signal, and the differential signal positive end signal of the first clock signal;

[0010] The logic module includes a first charging path corresponding to the positive end of the differential signal of the first clock signal, and a second charging path corresponding to the positive end of the differential signal of the second clock signal;

[0011] The second clock signal and the first clock signal are clock edge signals with the same frequency, and there is a phase difference between the second clock signal and the first clock signal;

[0012] The logic module is connected to the first input stage module and the second input stage module respectively. When the first clock signal is a rising edge signal, the logic module turns on the inverting output end of the pulse trigger to output a high level signal based on the input signals of the first input stage module and the second input stage module.

[0013] Preferably, the first input stage module includes a first differential input unit for receiving a differential signal positive end signal and a differential signal negative end signal of a first clock signal, and a first grounding unit for receiving a differential signal positive end signal of a second clock signal.

[0014] Preferably, the second input stage module includes a second differential input unit for receiving a differential signal positive end signal and a differential signal negative end signal of the second clock signal, and a second grounding unit for receiving a differential signal positive end signal of the first clock signal.

[0015] Preferably, the first differential input unit includes a first transistor and a second transistor, and the first grounding unit includes a third transistor;

[0016] The gate of the first transistor is connected to the positive end signal of the differential signal of the first clock signal, the source of the first transistor is connected to the drain of the third transistor, and the drain of the first transistor is connected to the logic module;

[0017] The gate of the second transistor is connected to the negative end of the differential signal of the first clock signal, the source of the second transistor is connected to the drain of the third transistor, and the drain of the second transistor is connected to the logic module;

[0018] A gate of the third transistor is connected to a positive end signal of a differential signal of the second clock signal, and a source of the third transistor is grounded.

[0019] Preferably, the second differential input unit includes a fourth transistor and a fifth transistor, and the second grounding unit includes a sixth transistor;

[0020] The gate of the fourth transistor is connected to the positive end signal of the differential signal of the second clock signal, the source of the fourth transistor is connected to the drain of the sixth transistor, and the drain of the fourth transistor is connected to the logic module;

[0021] The gate of the fifth transistor is connected to the negative end of the differential signal of the second clock signal, the source of the fifth transistor is connected to the drain of the sixth transistor, and the drain of the fifth transistor is connected to the logic module;

[0022] A gate of the sixth transistor is connected to a positive end signal of a differential signal of the first clock signal, and a source of the sixth transistor is grounded.

[0023] Preferably, the logic module includes a pre-charge unit and a latch unit;

[0024] The pre-charging unit is connected to the latch unit, and the pre-charging unit is used to pre-charge the latch unit to a maximum voltage;

[0025] The latch unit is used to latch the transmission signals of the first input stage module and the second input stage module in corresponding nodes, and only latch the level information of the second clock corresponding to the clock flipping moment of the positive end of the differential signal of the first clock, to generate a corresponding latch signal.

[0026] Preferably, the pre-charging unit includes a seventh transistor, an eighth transistor, a ninth transistor and a tenth transistor; the latch unit includes an eleventh transistor, a twelfth transistor, a thirteenth transistor and a fourteenth transistor;

[0027] The gate of the seventh transistor is connected to the positive end signal of the differential signal of the first clock signal, the source of the seventh transistor is connected to the power supply, and the drain of the seventh transistor is connected to the source of the eighth transistor;

[0028] The gate of the eighth transistor is connected to the positive end signal of the differential signal of the second clock signal, and the drain of the eighth transistor is connected to the first output end of the logic module;

[0029] The gate of the ninth transistor is connected to the positive end signal of the differential signal of the first clock signal, the source of the ninth transistor is connected to the power supply, and the drain of the ninth transistor is connected to the source of the tenth transistor;

[0030] The gate of the tenth transistor is connected to the positive end signal of the differential signal of the second clock signal, and the drain of the tenth transistor is connected to the second output end of the logic module;

[0031] The gate of the eleventh transistor is connected to the set signal, the source of the eleventh transistor is connected to a power supply, and the drain of the eleventh transistor is connected to the first output terminal of the logic module;

[0032] The gate of the twelfth transistor is connected to the reset signal, the source of the twelfth transistor is connected to a power supply, and the drain of the twelfth transistor is connected to the second output terminal of the logic module;

[0033] The gate of the thirteenth transistor is connected to the reset signal, the source of the thirteenth transistor is connected to the first input stage module and the second input stage module, and the drain of the thirteenth transistor is connected to the first output terminal of the logic module;

[0034] The gate of the fourteenth transistor is connected to the set signal, the source of the fourteenth transistor is connected to the first input stage module and the second input stage module, and the drain of the fourteenth transistor is connected to the second output terminal of the logic module.

[0035] Preferably, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the thirteenth transistor and the fourteenth transistor are N-type MOS transistors (N-Metal-Oxide-Semiconductor), and the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor and the twelfth transistor are P-type MOS transistors (P-Channel-Oxide-Semiconductor).

[0036] Preferably, the first clock signal obtains a differential signal positive end signal of the first clock signal and a differential signal negative end signal of the first clock signal based on a first single-ended to differential circuit;

[0037] The second clock signal obtains a corresponding differential signal positive end signal of the second clock signal and a differential signal negative end of the second clock signal based on the second single-ended to differential circuit.

[0038] In a second aspect, a phase detector is provided, comprising the pulse trigger described in the first aspect.

[0039] The positive and progressive effect of the present disclosure is that by adding a second input stage module symmetrical to the first input stage module in the pulse trigger, and a charging path for the second clock signal in the logic module, the charging and discharging phases of the pulse trigger are accelerated, the dead time of the pulse trigger is shortened, the resolution of the pulse trigger is improved, and the static error of the phase detector is eliminated. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 A schematic diagram of the circuit structure of a pulse trigger provided by an exemplary embodiment of the present disclosure;

[0041] Figure 2 A schematic diagram of a clock signal of a pulse trigger provided by an exemplary embodiment of the present disclosure;

[0042] Figure 3 A schematic diagram of the circuit structure of a phase detector provided by an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0043] The present disclosure is further described below by way of examples, but the present disclosure is not limited to the scope of the examples.

[0044] Prefixes such as "first" and "second" are used in the embodiments of the present disclosure only to distinguish different description objects, and have no limiting effect on the position, order, priority, quantity or content of the described objects. The use of prefixes such as ordinal numbers to distinguish description objects in the embodiments of the present disclosure does not constitute a limitation on the described objects. For the statement of the described objects, please refer to the description in the context of the embodiments, and no unnecessary limitation should be constituted due to the use of such prefixes. In addition, in the description of the present embodiment, unless otherwise specified, the meaning of "plurality" is two or more.

[0045] Example 1

[0046] This embodiment provides a pulse trigger, such as Figure 1 As shown, it includes a logic module 3, a first input stage module 1 and a second input stage module 2;

[0047] The circuit structures of the first input stage module 1 and the second input stage module 2 are the same;

[0048] The first input stage module 1 is used to receive the differential signal positive end signal and the differential signal negative end signal of the first clock signal, and the differential signal positive end signal of the second clock signal;

[0049] The second input stage module 2 is used to receive the differential signal positive end signal and the differential signal negative end signal of the second clock signal, and the differential signal positive end signal of the first clock signal;

[0050] The logic module 3 includes a first charging path corresponding to the positive end signal of the differential signal of the first clock signal, and a second charging path corresponding to the high level signal of the second clock signal;

[0051] The second clock signal and the first clock signal are clock edge signals with the same frequency, and there is a phase difference between the second clock signal and the first clock signal;

[0052] The logic module 3 is connected to the first input stage module 1 and the second input stage module 2 respectively. When the first clock signal CLKA is a rising edge signal, the logic module 3 turns on the inverting output end of the pulse trigger to output a high level signal based on the input signals of the first input stage module 1 and the second input stage module 2.

[0053] In this scheme, the positive end signal of the differential signal of the first clock signal is usually a high-level signal CLKA_P corresponding to the first clock signal, the negative end signal of the differential signal of the first clock signal is usually a low-level signal CLKA_N corresponding to the first clock signal, the positive end signal of the differential signal of the second clock signal is usually a high-level signal CLKB_P corresponding to the second clock signal, and the negative end signal of the differential signal of the second clock signal is usually a low-level signal CLKB_N corresponding to the second clock signal.

[0054] By adding a second input stage module 2 symmetrical to the first input stage module 1 in the pulse trigger, and a charging path of the second clock signal CLKB in the logic module 3, an additional charging path can be added before and after the second clock signal CLKB samples the first clock signal CLKA, so that the charging and discharging of the A and B nodes can be completed quickly, the charging and discharging phases of the pulse trigger can be accelerated, the dead time of the pulse trigger can be shortened, the resolution of the pulse trigger can be improved, and the static error of the phase detector can be eliminated.

[0055] In one embodiment, Figure 2 As shown, the phase of the second clock signal CLKB is later than that of the first clock signal CLKA, and the interval therebetween may be a quarter of a phase. During stage 1 10, when the first clock signal CLKA is at a rising edge, the second clock signal CLKB is at a low level. At this time, the positive end part CLKB_P of the differential signal receiving the second clock signal in the second input stage module 2 is cut off, and the negative end part CLKB_N of the differential signal receiving the second clock signal is partially turned on, and the second charging path corresponding to the negative end CLKB_N of the differential signal of the second clock signal in the logic module 3 is charged. At this time, the B node outputs a high level, and the corresponding inverted output end of the pulse trigger outputs a high level signal; During stage 2 20, when the first clock signal CLKA is at a high level, the second clock signal CLKB is at a rising edge. At this time, the positive end CLKA_P of the differential signal receiving the first clock signal in the first input stage module 1 is partially turned on, and the negative end CLKA_N of the differential signal receiving the first clock signal is partially cut off, and the first charging path corresponding to the positive end signal CLKA_P of the differential signal of the first clock signal in the logic module 3 is charged, providing a charge discharge charging path for the A node, and a charging path for the B node, and the inverted output end of the pulse trigger outputs a high level signal. Compared with the existing phase detector circuit which has only one stage of charging and one stage of discharging, the pulse trigger in this embodiment has twice the charging and discharging stages of the existing phase detector, and can charge and discharge faster to shorten the dead time and eliminate the static error of the phase detector.

[0056] As an implementable manner, the first input stage module 1 includes a first differential input unit for receiving a differential signal positive end signal CLKA_P and a differential signal negative end signal CLKA_N of a first clock signal, and a first grounding unit for receiving a differential signal positive end signal CLKB_P of a second clock signal.

[0057] In this solution, in the first input stage module 1, when the first clock signal CLKA is connected, if the clock signal CLKA is at a high level, the output of the first differential input unit is at a low level; conversely, if the first clock signal CLKA is at a low level, the output of the first differential input unit is at a high level. The first grounding unit is used to stabilize the working state of the first input stage module 1, prevent erroneous operation caused by current fluctuations through the grounding terminal, and control the level transfer of the first differential input unit through the second clock signal CLKB received by the first grounding unit.

[0058] As an implementable manner, the second input stage module 2 includes a second differential input unit for receiving a differential signal positive end signal CLKB_P and a differential signal negative end signal CLKB_N of a second clock signal, and a second grounding unit for receiving a differential signal positive end signal CLKA_P of a first clock signal.

[0059] In this solution, in the second input stage module 2, when the second clock signal CLKB is connected, if the second clock signal CLKB is at a high level, the output of the second differential input unit is at a low level; conversely, if the second clock signal CLKB is at a low level, the output of the second differential input unit is at a high level. The second grounding unit is used to stabilize the working state of the second input stage module 2, prevent erroneous operation caused by current fluctuations through the grounding terminal, and control the level transfer of the second differential input unit through the first clock signal received by the second grounding unit.

[0060] As an implementable manner, the first differential input unit includes a first transistor MN1 and a second transistor MN2, and the first grounding unit includes a third transistor MN3;

[0061] The gate of the first transistor MN1 is connected to the differential signal positive end signal CLKA_P of the first clock signal, the source of the first transistor MN1 is connected to the drain of the third transistor MN3, and the drain of the first transistor MN1 is connected to the logic module 3;

[0062] The gate of the second transistor MN2 is connected to the negative end of the differential signal of the first clock signal CLKA_N, the source of the second transistor MN2 is connected to the drain of the third transistor MN3, and the drain of the second transistor MN2 is connected to the logic module 3;

[0063] A gate of the third transistor MN3 is connected to the differential signal positive end signal CLKB_P of the second clock signal, and a source of the third transistor MN3 is grounded.

[0064] In this solution, the first transistor MN1 is turned on at the positive end signal CLKA_P of the differential signal of the first clock signal, the second transistor MN2 is turned on at the negative end CLKA_N of the differential signal of the first clock signal, and the third transistor MN3 is turned on and grounded at the positive end signal CLKB_P of the differential signal of the second clock signal. Since the second clock signal samples the first clock signal, the second clock signal is later than the first clock signal, and the period of the positive end signal of the differential signal of the second clock signal corresponds to the falling edge or low level signal period of the first clock signal, that is, the first input stage module 1 is controlled to be turned on at the positive end signal CLKA_P of the differential signal of the first clock signal by the third transistor MN3. At the same time, in cooperation with the second charging path corresponding to the positive end signal CLKB_P of the differential signal of the second clock signal in the logic module 3, when the positive end signal CLKA_P of the differential signal of the first clock signal and the high level signal CLKB_P of the second clock signal are realized, a charge discharge charging path is provided to the A node, a charging path is provided to the B node, and a high level signal is output at the inverting output end of the control pulse trigger.

[0065] As an implementable manner, the second differential input unit includes a fourth transistor MN4 and a fifth transistor MN5, and the second grounding unit includes a sixth transistor MN6;

[0066] The gate of the fourth transistor MN4 is connected to the positive end signal CLKB_P of the differential signal of the second clock signal, the source of the fourth transistor MN4 is connected to the drain of the sixth transistor MN6, and the drain of the fourth transistor MN4 is connected to the logic module 3;

[0067] The gate of the fifth transistor MN5 is connected to the differential signal negative end level signal CLKB_N of the second clock signal, the source of the fifth transistor MN5 is connected to the drain of the sixth transistor MN6, and the drain of the fifth transistor MN5 is connected to the logic module 3;

[0068] A gate of the sixth transistor MN6 is connected to the differential signal positive end signal CLKA_P of the first clock signal, and a source of the sixth transistor MN6 is grounded.

[0069] In this solution, the fourth transistor MN4 is turned on when the differential signal positive end signal CLKB_P of the second clock signal, the fifth transistor MN5 is turned on when the differential signal negative end CLKB_N of the second clock signal, and the sixth transistor MN6 is turned on and grounded when the differential signal positive end signal CLKA_P of the first clock signal, that is, the second input stage module 2 is controlled by the sixth transistor MN6 to be turned on when the partial low-level signal corresponding to the second clock signal. At the same time, in conjunction with the second charging path corresponding to the high-level signal CLKB_P of the second clock signal in the logic module 3, when the non-high-level signal of the first clock signal and the negative end CLKB_N of the differential signal of the second clock signal are reached, a charge discharge charging path is provided to the A node, and a charging path is provided to the B node, and the inverting output end of the control pulse trigger outputs a high-level signal.

[0070] As an implementable manner, the logic module 3 includes a pre-charging unit and a latch unit;

[0071] The pre-charging unit is connected to the latch unit, and the pre-charging unit is used to pre-charge the latch unit to a maximum voltage;

[0072] The latch unit is used to latch the transmission signals of the first input stage module and the second input stage module in corresponding nodes, and only latch the level information of the second clock corresponding to the clock flipping moment of the positive end of the differential signal of the first clock, to generate a corresponding latch signal.

[0073] In this solution, at the initial stage of the circuit, when the first clock signal CLKA_P and the second clock signal CLKB_P are at a low level, the latch unit Input and The input end is charged through the pre-charge unit. Input and The high level at the input end will keep the latch unit in the open state and precharge the latch unit to the maximum voltage. The first input stage module 1 and the second input stage module 2 are precharged through the latch unit so that all capacitors in the data differential path are precharged before the rising edge of the first clock signal CLKA_P arrives.

[0074] As an implementable manner, the pre-charging unit includes a seventh transistor MP7, an eighth transistor MP8, a ninth transistor MP9 and a tenth transistor MP10; the latch unit includes an eleventh transistor MP11, a twelfth transistor MP12, a thirteenth transistor MN13 and a fourteenth transistor MN14;

[0075] The gate of the seventh transistor MP7 is connected to the differential signal positive end signal CLKA_P of the first clock signal, the source of the seventh transistor MP7 is connected to the power supply, and the drain of the seventh transistor MP7 is connected to the source of the eighth transistor MP8;

[0076] The gate of the eighth transistor MP8 is connected to the high level signal CLKB_P of the second clock signal, and the drain of the eighth transistor MP8 is connected to the first output terminal of the logic module 3;

[0077] The gate of the ninth transistor MP9 is connected to the differential signal positive end signal CLKA_P of the first clock signal, the source of the ninth transistor MP9 is connected to the power supply, and the drain of the ninth transistor MP9 is connected to the source of the tenth transistor MP10;

[0078] The gate of the tenth transistor MP10 is connected to the differential signal positive end signal CLKB_P of the second clock signal, and the drain of the tenth transistor MP10 is connected to the second output end of the logic module 3;

[0079] The gate of the eleventh transistor MP11 is connected to the set signal The source of the eleventh transistor MP11 is connected to the power supply, and the drain of the eleventh transistor MP11 is connected to the first output terminal of the logic module 3;

[0080] The gate of the twelfth transistor MP12 is connected to the reset signal The source of the twelfth transistor MP12 is connected to the power supply, and the drain of the twelfth transistor MP12 is connected to the second output terminal of the logic module 3;

[0081] The gate of the thirteenth transistor MN13 is connected to the reset signal The source of the thirteenth transistor MN13 is connected to the first input stage module 1 and the second input stage module 2, and the drain of the thirteenth transistor MN13 is connected to the first output terminal of the logic module 3;

[0082] The gate of the fourteenth transistor MN14 is connected to the set signal The source of the fourteenth transistor MN14 is connected to the first input stage module 1 and the second input stage module 2 , and the drain of the fourteenth transistor MN14 is connected to the second output end of the logic module 3 .

[0083] In this solution, the pre-charging module adds an eighth transistor MP8 and a tenth transistor MP10 to the existing structure as a second charging control path corresponding to the high level CLKB_P of the second clock signal, and a seventh transistor MP7 and a ninth transistor MP9 as a first charging control path corresponding to the positive end CLKA_P of the differential signal of the first clock signal. Charging can only be performed when both CLKA_P and CLKB_P are at low levels. The eleventh transistor MP11 and the twelfth transistor MP12 serve as pre-charging switches. Input and first input stage module 1 or The level signal of the input end and the second input stage module 2 charges and discharges the node A or the node B. The latch structure composed of the thirteenth transistor MN13 and the fourteenth transistor MN14 can latch the transmission signals of the first input stage module and the second input stage module at the corresponding nodes A and B, and only latch the CLKB_P level information at the CLKA_P clock flipping moment, which has nothing to do with the subsequent CLKA_P high level duration.

[0084] In one embodiment, the pulse trigger also includes a third grounding unit, which provides a loop to the ground. The third grounding unit is the fifteenth transistor MN15. The fifteenth transistor MN15 adopts an N-type MOS tube, which is used to prevent the risk of charging the output low level of the pulse trigger stage due to leakage current after the clock signal changes. This cannot be ignored in low-power design. The size of the fifteenth transistor MN15 is controlled within a preset size range to use smaller transistors as much as possible to prevent the delay of the pulse trigger stage from worsening.

[0085] As an implementable manner, the first transistor MN1, the second transistor MN2, the third transistor MN3, the fourth transistor MN4, the fifth transistor MN5, the sixth transistor MN6, the thirteenth transistor MN13 and the fourteenth transistor MN14 are N-type MOS transistors, and the seventh transistor MP7, the eighth transistor MP8, the ninth transistor MP9, the tenth transistor MP10, the eleventh transistor MP11 and the twelfth transistor MP12 are P-type MOS transistors.

[0086] In the present solution, the first transistor MN1, the second transistor MN2, the third transistor MN3, the fourth transistor MN4, the fifth transistor MN5 and the sixth transistor MN6 are components of the first input stage module 1 and the second input stage module 2, and adopt N-type MOS tubes with lower on-resistance, which are suitable for low power consumption and high efficiency applications, and for source grounding applications; the thirteenth transistor MN13 and the fourteenth transistor MN14 are components of the latch unit, and adopt N-type MOS tubes to realize data transmission, and the characteristics of the N-type MOS tubes being cut off when the gate is at a low level and turned on when the gate is at a high level are utilized, which is helpful to realize data transmission and isolation under the control of the clock signal; the seventh transistor MP7, the eighth transistor MP8, the ninth transistor MP9, the tenth transistor MP10, the eleventh transistor MP11 and the twelfth transistor MP12 are components of the pre-charging unit, and adopt P-type MOS tubes to pre-charge the internal nodes to VDD under the control of the clock signal, so as to provide preparation for subsequent data sampling and transmission.

[0087] As an implementable manner, the first clock signal CLKA obtains a corresponding differential signal positive end signal CLKA_P of the first clock signal and a differential signal negative end CLKA_N of the first clock signal based on a first single-ended to differential circuit;

[0088] The second clock signal CLKB obtains a corresponding differential signal positive end signal CLKB_P of the second clock signal and a differential signal negative end CLKB_N of the second clock signal based on the second single-ended to differential circuit.

[0089] In this solution, the first clock signal CLKA is processed by a first single-ended to differential circuit, and the second clock signal CLKB is processed by a second single-ended to differential circuit. The inherent anti-interference characteristics of the single-ended to differential circuit are utilized to effectively resist external interference, and the corresponding first clock signal CLKA or second clock signal CLKB is made more accurate in timing positioning, suitable for high-speed data transmission, and the influence of ground potential difference and ground consistency problems on signal quality is reduced, thereby improving signal stability and reliability.

[0090] The pulse trigger provided in this embodiment accelerates the charging and discharging phases of the pulse trigger, shortens the dead time of the pulse trigger, and improves the resolution of the pulse trigger by adding a second input stage module symmetrical to the first input stage module and a charging path of the second clock signal in the logic module.

[0091] Example 2

[0092] This embodiment provides a phase detector 100, including the pulse trigger 101 provided in Embodiment 1.

[0093] In this scheme, if Figure 3 As shown, the phase detector 100 includes a pulse trigger 101, and a first clock signal CLKA is converted into a differential signal positive end signal CLKA_P of the first clock signal and a differential signal negative end CLKA_N of the first clock signal through a first single-ended to differential circuit 103, and a second clock signal CLKB is converted into a differential signal positive end signal CLKB_P of the second clock signal and a differential signal negative end CLKB_N of the second clock signal based on a second single-ended to differential circuit 104, and the pulse trigger 101 is input, and the pulse trigger sends the trigger result to the latch circuit 102 based on the first clock signal CLKA and the second clock signal CLKB, and outputs the positive output end CLKA_P of the second clock signal and the negative output end CLKB_N of the second clock signal. and the inverting output Output the corresponding phase detection result.

[0094] The phase detector provided in this embodiment accelerates the charge and discharge phase of the pulse trigger, shortens the dead time of the pulse trigger, and improves the resolution of the pulse trigger by adding a second input stage module symmetrical to the first input stage module in the pulse trigger and a charging path of the second clock signal in the logic module, thereby eliminating the static error of the phase detector.

[0095] Although the specific embodiments of the present disclosure are described above, those skilled in the art should understand that this is only an example, and the protection scope of the present disclosure is defined by the appended claims. Those skilled in the art may make various changes or modifications to these embodiments without departing from the principles and essence of the present disclosure, but these changes and modifications all fall within the protection scope of the present disclosure.

Claims

1. A pulse trigger, characterized in that: including a logic module, a first input stage module and a second input stage module; The circuit structures of the first input stage module and the second input stage module are the same; The first input stage module is used to receive the differential signal positive end signal and the differential signal negative end signal of the first clock signal, and the differential signal positive end signal of the second clock signal; The second input stage module is used to receive the differential signal positive end signal and the differential signal negative end signal of the second clock signal, and the differential signal positive end signal of the first clock signal; The logic module includes a first charging path corresponding to the positive end signal of the differential signal of the first clock signal, and a second charging path corresponding to the positive end signal of the differential signal of the second clock signal; The second clock signal and the first clock signal are clock edge signals with the same frequency, and there is a phase difference between the second clock signal and the first clock signal; The logic module includes a precharge unit and a latch unit; The pre-charging units are connected to the latch units respectively, and the pre-charging units are used to pre-charge the latch units to a maximum voltage; The latch unit is used to latch the transmission signals of the first input stage module and the second input stage module in corresponding nodes, and only latch the level information of the second clock corresponding to the clock flipping moment of the positive end of the differential signal of the first clock, and generate a corresponding latch signal; The logic module is connected to the first input stage module and the second input stage module respectively. When the first clock signal is a rising edge signal, the logic module outputs a high-level latch signal at the first output end and a low-level set signal at the second output end based on the input signals of the first input stage module and the second input stage module.

2. The pulse trigger according to claim 1, characterized in that: The first input stage module includes a first differential input unit for receiving a differential signal positive end signal and a differential signal negative end signal of a first clock signal, and a first grounding unit for receiving a differential signal positive end signal of a second clock signal.

3. The pulse trigger according to claim 2, characterized in that: The second input stage module includes a second differential input unit for receiving a differential signal positive end signal and a differential signal negative end signal of a second clock signal, and a second grounding unit for receiving a differential signal positive end signal of a first clock signal.

4. The pulse trigger according to claim 3, characterized in that: The first differential input unit includes a first transistor and a second transistor, and the first grounding unit includes a third transistor; The gate of the first transistor is connected to the positive end of the differential signal of the first clock signal, the source of the first transistor is connected to the drain of the third transistor, and the drain of the first transistor is connected to the logic module; The gate of the second transistor is connected to the negative end of the differential signal of the first clock signal, the source of the second transistor is connected to the drain of the third transistor, and the drain of the second transistor is connected to the logic module; A gate of the third transistor is connected to a positive end of a differential signal of the second clock signal, and a source of the third transistor is grounded.

5. The pulse trigger according to claim 4, characterized in that: The second differential input unit includes a fourth transistor and a fifth transistor, and the second grounding unit includes a sixth transistor; The gate of the fourth transistor is connected to the positive end of the differential signal of the second clock signal, the source of the fourth transistor is connected to the drain of the sixth transistor, and the drain of the fourth transistor is connected to the logic module; The gate of the fifth transistor is connected to the negative end of the differential signal of the second clock signal, the source of the fifth transistor is connected to the drain of the sixth transistor, and the drain of the fifth transistor is connected to the logic module; A gate of the sixth transistor is connected to a positive end of a differential signal of the first clock signal, and a source of the sixth transistor is grounded.

6. The pulse trigger according to claim 5, characterized in that: The pre-charging unit includes a seventh transistor, an eighth transistor, a ninth transistor and a tenth transistor; the latch unit includes an eleventh transistor, a twelfth transistor, a thirteenth transistor and a fourteenth transistor; The gate of the seventh transistor is connected to the positive end of the differential signal of the first clock signal, the source of the seventh transistor is connected to a power supply, and the drain of the seventh transistor is connected to the source of the eighth transistor; The gate of the eighth transistor is connected to the positive end signal of the differential signal of the second clock signal, and the drain of the eighth transistor is connected to the first output end of the logic module; The gate of the ninth transistor is connected to the positive end of the differential signal of the first clock signal, the source of the ninth transistor is connected to a power supply, and the drain of the ninth transistor is connected to the source of the tenth transistor; The gate of the tenth transistor is connected to the positive end of the differential signal of the second clock signal, and the drain of the tenth transistor is connected to the second output end of the logic module; The gate of the eleventh transistor is connected to the set signal, the source of the eleventh transistor is connected to the power supply, and the drain of the eleventh transistor is connected to the first output terminal of the logic module; The gate of the twelfth transistor is connected to the latch signal, the source of the twelfth transistor is connected to a power supply, and the drain of the twelfth transistor is connected to the second output terminal of the logic module; The gate of the thirteenth transistor is connected to the set signal, the source of the thirteenth transistor is connected to the first input stage module and the second input stage module, and the drain of the thirteenth transistor is connected to the first output terminal of the logic module; The gate of the fourteenth transistor is connected to the latch signal, the source of the fourteenth transistor is connected to the first input stage module and the second input stage module, and the drain of the fourteenth transistor is connected to the second output end of the logic module.

7. The pulse trigger according to claim 6, characterized in that: The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the thirteenth transistor and the fourteenth transistor are N-type MOS transistors, and the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor and the twelfth transistor are P-type MOS transistors.

8. The pulse trigger according to claim 1, characterized in that: The first clock signal obtains a differential signal positive end signal of the first clock signal and a differential signal negative end of the first clock signal based on a first single-ended to differential circuit; The second clock signal obtains a corresponding differential signal positive end signal of the second clock signal and a differential signal negative end of the second clock signal based on the second single-ended to differential circuit.

9. A phase detector, characterized in that: A pulse trigger comprising the pulse trigger described in any one of claims 1 to 8.

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