Distortion calibration circuit, method, electronic device, medium for analog-to-digital conversion

Abstract

The application provides a distortion calibration circuit, method, electronic equipment and medium for analog-to-digital conversion, characterized in that the circuit comprises a dithering signal generation module, a first signal calculation module, a first input end of the first signal calculation module being used for connecting an analog input signal, a second input end of the first signal calculation module being connected with an output end of the dithering signal generation module, a target input buffer, an output end of the first signal calculation module being connected with an input end of the target input buffer, a compensation module, a first input end of the compensation module being connected with an output end of the target input buffer, an analog-to-digital converter, an input end of the analog-to-digital converter being connected with an output end of the compensation module, a second signal calculation module, a first input end of the second signal calculation module being connected with an output end of the analog-to-digital converter, a second input end of the second signal calculation module being connected with the output end of the dithering signal generation module, and a harmonic coefficient generation module, an input end of the harmonic coefficient generation module being connected with an output end of the second signal calculation module, and an output end of the harmonic coefficient generation module being connected with a second input end of the compensation module. The signal distortion caused by the nonlinearity of the input buffer can be improved.

Description

Technical Field

[0001] This invention relates to the field of distortion calibration technology for analog-to-digital conversion, and particularly to a distortion calibration circuit, method, electronic device, and medium for analog-to-digital conversion. Background Technology

[0002] Linearity is an important metric for measuring the relationship between the output and input of a system or device. Linearity is typically expressed as a percentage or in decibels (dB). Higher linearity means that the system or device responds to changes in the input signal more linearly, while lower linearity indicates greater non-linear distortion.

[0003] Currently, high-bandwidth analog-to-digital converters (ADCs) place significant loads on their inputs, thus requiring high drive capability at the front-end input stages to input signals into a wideband ADC without sacrificing signal integrity. These requirements stem from the fact that driving a large number of sampling capacitors (~pF) within a very short sampling time (hundreds of picoseconds) can cause dynamic distortion in the input buffer. Furthermore, similar power supply voltage margins with similar input swing can also lead to significant static distortion. Therefore, it is crucial to calibrate the input buffer to reduce distortion and mitigate nonlinearity. Summary of the Invention

[0004] This invention aims to at least solve one of the technical problems existing in the prior art. To this end, this invention proposes a distortion calibration circuit, method, electronic device, and medium for analog-to-digital conversion, which can improve signal distortion caused by nonlinearity in the input buffer.

[0005] In a first aspect, embodiments of the present invention provide a distortion calibration circuit for analog-to-digital conversion, comprising:

[0006] Jitter signal generation module, used to generate jitter signals;

[0007] A first signal calculation module, wherein a first input terminal of the first signal calculation module is used to connect to an analog input signal, and a second input terminal of the first signal calculation module is connected to the output terminal of the jitter signal generation module, and the first signal calculation module is used to add the analog input signal and the jitter signal;

[0008] A target input buffer, wherein the input terminal of the target input buffer is connected to the output terminal of the first signal calculation module;

[0009] A compensation module, wherein the first input terminal of the compensation module is connected to the output terminal of the target input buffer;

[0010] An analog-to-digital converter, wherein the input terminal of the analog-to-digital converter is connected to the output terminal of the compensation module;

[0011] The second signal calculation module has a first input terminal connected to the output terminal of the analog-to-digital converter and a second input terminal connected to the output terminal of the jitter signal generation module. It is used to subtract the signal output by the analog-to-digital converter from the output result of the jitter signal generation module.

[0012] The harmonic coefficient generation module has its input terminal connected to the output terminal of the second signal calculation module, and its output terminal connected to the second input terminal of the compensation module.

[0013] In some embodiments of the present invention, the jitter signal generation module includes:

[0014] The first jitter signal generation submodule is used to generate the first jitter sub-signal;

[0015] The second jitter signal generation submodule is used to generate the second jitter sub-signal;

[0016] The first signal calculation module further includes:

[0017] The first capacitive coupler is connected to the output terminal of the first jitter signal generation submodule, the input position of the analog input signal, and the first input terminal of the target input buffer, respectively.

[0018] The second capacitive coupler is connected to the output terminal of the second jitter signal generation submodule, the input position of the analog input signal, and the second input terminal of the target input buffer.

[0019] In some embodiments of the present invention, the compensation module includes a harmonic compensation diode load connected to the target input buffer.

[0020] In some embodiments of the present invention, the harmonic coefficient generation module includes:

[0021] Multiple comparators, each with its input terminal connected to the output terminal of the second signal calculation module;

[0022] Multiple counters, each of which has its input terminal connected to the output terminal of its corresponding comparator;

[0023] Multiple accumulators, each with its input terminal connected to the output terminal of its corresponding counter;

[0024] The averager has its input terminals connected to the output terminals of each of the accumulators, and its output terminal connected to the input terminal of the compensation module.

[0025] In a second aspect, embodiments of the present invention provide a distortion calibration method for analog-to-digital conversion, based on the distortion calibration method for analog-to-digital conversion as described in any one of the first aspects, the method comprising:

[0026] The first signal calculation module adds the analog input signal and the jitter signal to obtain a first signal, and inputs the first signal into the target input buffer. The jitter signal is provided by the jitter signal generation module.

[0027] The target input buffer isolates the first signal and inputs it to the compensation module;

[0028] The compensation module performs harmonic compensation on the first signal according to the harmonic coefficient to obtain the second signal, and inputs the second signal into the analog-to-digital converter. The harmonic coefficient is generated by the harmonic coefficient generation module.

[0029] The analog-to-digital converter performs analog-to-digital conversion on the second signal to obtain the target digital signal;

[0030] The second signal calculation module subtracts the target digital signal from the jitter signal to obtain a third signal, and inputs the third signal into the harmonic coefficient generation module.

[0031] The harmonic coefficient generation module calculates the third signal and the jitter signal, and updates the harmonic coefficients based on the calculation results.

[0032] In some embodiments of the present invention, the harmonic coefficient generation module includes an accumulator, multiple comparators, multiple counters, and multiple accumulators. Each comparator is connected to each counter in a one-to-one correspondence, and each accumulator is connected to each counter in a one-to-one correspondence. The averager is connected to the accumulators and the averager is connected to the compensation module. Each comparator has a preset voltage threshold, and the voltage threshold in each comparator is different. The harmonic coefficient generation module calculates the harmonic coefficients of the third signal based on a preset harmonic coefficient generation algorithm, and inputs the harmonic coefficients to the compensation module, including:

[0033] The comparator compares the voltage threshold with the second signal to obtain a comparison result;

[0034] If the comparison result is less than the absolute value of the voltage threshold, then the third signal is assigned a value of 0;

[0035] If the comparison result is greater than the absolute value of the voltage threshold, then the third signal is assigned a value of 1;

[0036] The counter multiplies the third signal with the jitter signal to obtain the multiplication result;

[0037] The accumulator adds the multiplication results that have passed through the same comparator and counter to obtain the sum.

[0038] The averager averages the summation results output by each of the accumulators to obtain the harmonic coefficients.

[0039] In some embodiments of the present invention, the jitter signal generation module includes: a first jitter signal generation submodule for generating a first jitter sub-signal; a second jitter signal generation submodule for generating a second jitter sub-signal; the first signal calculation module further includes: a first capacitive coupler, the first capacitive coupler being connected to the output terminal of the first jitter signal generation submodule, the input position of the analog input signal, and the first input terminal of the target input buffer respectively; and a second capacitive coupler, the second capacitive coupler being connected to the output terminal of the second jitter signal generation submodule, the input position of the analog input signal, and the second input terminal of the target input buffer respectively.

[0040] The first signal calculation module adds the analog input signal and the jitter signal to obtain a first signal, and inputs the first signal into the target input buffer, including:

[0041] The first jitter signal generation submodule generates the first jitter sub-signal and inputs the first jitter sub-signal to the first capacitive coupler;

[0042] The first capacitive coupler couples the analog input signal with the first jitter sub-signal, and the coupled analog input signal is input to the target input buffer through the first input terminal of the target input buffer;

[0043] The second jitter signal generation submodule generates the second jitter sub-signal and inputs the second jitter sub-signal to the second capacitive coupler;

[0044] The second capacitive coupler couples the analog input signal with the second jitter sub-signal, and the coupled analog input signal is input to the target input buffer through the second input terminal of the target input buffer.

[0045] In some embodiments of the present invention, the compensation module includes a harmonic compensation diode load. The compensation module performs harmonic compensation on the first signal according to the harmonic coefficient to obtain a second signal, and inputs the second signal to the analog-to-digital converter, including:

[0046] The compensation module adjusts the load of the harmonic compensation diode according to the harmonic coefficient.

[0047] Thirdly, embodiments of the present invention provide an electronic device including a distortion calibration circuit for analog-to-digital conversion as described in the second aspect above.

[0048] Fourthly, embodiments of the present invention provide a computer-readable storage medium storing computer-executable instructions for performing the distortion calibration method for analog-to-digital conversion as described in the first aspect above.

[0049] The distortion calibration circuit for analog-to-digital conversion according to embodiments of the present invention has at least the following beneficial effects: a jitter signal generation module for generating a jitter signal; a first signal calculation module, wherein a first input terminal of the first signal calculation module is connected to an analog input signal, a second input terminal of the first signal calculation module is connected to the output terminal of the jitter signal generation module, and the first signal calculation module is used to add the analog input signal and the jitter signal; a target input buffer, wherein the input terminal of the target input buffer is connected to the output terminal of the first signal calculation module; and a compensation module, wherein the first input terminal of the compensation module is connected to the output terminal of the target input buffer. The system comprises the following modules: an output terminal connected to the input terminal; an analog-to-digital converter (ADC), whose input terminal is connected to the output terminal of the compensation module; a second signal calculation module, whose first input terminal is connected to the output terminal of the ADC, and whose second input terminal is connected to the output terminal of the jitter signal generation module, for subtracting the output signal of the jitter signal generation module from the output signal of the ADC; and a harmonic coefficient generation module, whose input terminal is connected to the output terminal of the second signal calculation module, and whose output terminal is connected to the second input terminal of the compensation module. By adding a random jitter signal to the input, and passing it through the nonlinear system of the target input buffer, the magnitude of this jitter signal becomes nonlinear due to the influence of the nonlinear system. Subtracting the previously added jitter signal from the output signal reveals the influence of the nonlinear system on the jitter signal. Adjusting the compensation module based on the harmonic coefficients generated by the jitter signal effectively improves the signal distortion caused by the nonlinearity of the target input buffer. Attached Figure Description

[0050] Figure 1This is a schematic diagram of the structure of a distortion calibration circuit for analog-to-digital conversion provided in one embodiment of the present invention;

[0051] Figure 2 This is a schematic diagram of the structure of the first signal calculation module, the target input buffer, and the compensation module provided in one embodiment of the present invention;

[0052] Figure 3 This is a flowchart of a distortion calibration method for analog-to-digital conversion provided in one embodiment of the present invention;

[0053] Figure 4 This is an embodiment of the present invention, which describes the sequential changes of adding and subtracting jitter signals in a linear system.

[0054] Figure 5 This is an embodiment of the present invention, which describes the sequential changes of adding and subtracting jitter signals in a nonlinear system.

[0055] Labels: Jitter signal generation module 100; First signal calculation module 200; Target input buffer 300; Compensation module 400; Analog-to-digital converter 500; Second signal calculation module 600; Harmonic coefficient generation module 700; First jitter signal generation submodule 121; Second jitter signal generation submodule 122; First reference voltage generation module 123; Second reference voltage generation module 124; Comparator 710; Counter 720; Accumulator 730; Averager 740. Detailed Implementation

[0056] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0057] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0058] In the description of this invention, "several" means one or more, "more than" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0059] In the description of this invention, unless otherwise explicitly defined, terms such as "set up," "install," and "connect" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.

[0060] The control method of the present invention will be further described below with reference to the accompanying drawings.

[0061] Reference Figure 1 , Figure 1 This is a schematic diagram of a distortion calibration circuit for analog-to-digital conversion provided in an embodiment of the present invention. The distortion calibration circuit for analog-to-digital conversion includes, but is not limited to:

[0062] Jitter signal generation module 100, used to generate jitter signals;

[0063] The first signal calculation module 200 has a first input terminal for connecting to an analog input signal and a second input terminal for connecting to the output terminal of the jitter signal generation module 100. The first signal calculation module 200 is used to add the analog input signal and the jitter signal.

[0064] The target input buffer 300 has its input terminal connected to the output terminal of the first signal calculation module 200.

[0065] The compensation module 400 has its first input terminal connected to the output terminal of the target input buffer 300.

[0066] Analog-to-digital converter 500, the input terminal of analog-to-digital converter 500 is connected to the output terminal of compensation module 400;

[0067] The second signal calculation module 600 has a first input terminal connected to the output terminal of the analog-to-digital converter 500 and a second input terminal connected to the output terminal of the jitter signal generation module 100. It is used to subtract the signal output by the analog-to-digital converter 500 from the output result of the jitter signal generation module 100.

[0068] The harmonic coefficient generation module 700 has its input terminal connected to the output terminal of the second signal calculation module 600, and its output terminal connected to the second input terminal of the compensation module 400.

[0069] It should be noted that the reference Figures 1-2 The jitter signal generated by the jitter signal generation module 100 has a constant magnitude but a random sign. The first signal calculation module 200 can be an adder to perform addition operations on the input signals. The summed signals are then input into the target input buffer 300. During this process, the jitter signal and the analog input signal undergo the same distortion process. The target input buffer 300 provides isolation. The first input terminal of the compensation module 400 is connected to the output terminal of the target input buffer 300, and the second input terminal is connected to the output terminal of the harmonic coefficient generation module 700. The analog-to-digital converter 500 converts the analog signal into a digital signal. The second calculation module can be a subtractor to perform subtraction operations on the signal output by the analog-to-digital converter 500 and the added random jitter signal, effectively subtracting the previously added random jitter signal. This reveals the influence of the nonlinear system, i.e., the target input buffer 300, on the jitter signal. The calculated signal is then input into the harmonic coefficient generation module 700 to generate harmonic coefficients, which is equivalent to converting the influence of the nonlinear system into harmonic coefficients, used to calibrate the signal distortion of the output of the target input buffer 300.

[0070] In another embodiment, the jitter signal generation module 100 includes:

[0071] The first jitter signal generation submodule 121 is used to generate the first jitter sub-signal;

[0072] The second jitter signal generation submodule 122 is used to generate a second jitter sub-signal;

[0073] The first signal calculation module 200 also includes:

[0074] The first capacitive coupler is connected to the output terminal of the first jitter signal generation submodule 121, the input position of the analog input signal, and the first input terminal of the target input buffer, respectively.

[0075] The second capacitive coupler is connected to the output terminal of the second jitter signal generation submodule 122, the input position of the analog input signal, and the second input terminal of the target input buffer.

[0076] It should be noted that the first jitter sub-signal output by the first jitter signal generation submodule 121 intersects with the analog input signal at the first capacitive coupler. Furthermore, a first reference voltage generation module 123 is also provided at the intersection point. The first reference voltage signal output by the first reference voltage generation module 123 is a DC voltage, used to DC bias the signal at the intersection point. The signal is then input into the target input buffer through the first input terminal of the target input buffer. Similarly, the second jitter sub-signal output by the second jitter signal generation submodule 122 intersects with the analog input signal at the second capacitive coupler. Furthermore, a second reference voltage generation module 124 is also provided at the intersection point. The second reference voltage signal output by the second reference voltage generation module 124 is a DC voltage, used to DC bias the signal at the intersection point. The signal is then input into the target input buffer through the second input terminal of the target input buffer.

[0077] In another embodiment, the compensation module 400 includes a harmonic compensation diode load connected to the target input buffer 300.

[0078] It should be noted that the compensation module 400 includes an adjustable harmonic compensation diode load, namely HC-DL, which is a diode-connected transistor. Its gate voltage is controlled by the distortion calibration circuit used for analog-to-digital conversion. Since the target input buffer 300 includes two MOSFETs, corresponding to the two sides of the input terminal respectively, it can be understood that, corresponding to the design of the MOSFETs, there are also two harmonic compensation diode loads. The source and drain of the MOSFETs are connected to the harmonic compensation diode loads respectively, that is, the target input buffer 300 and the harmonic compensation diode loads are connected in parallel.

[0079] In another embodiment, the harmonic coefficient generation module 700 includes:

[0080] Multiple comparators 710 are provided, and the input terminals of each comparator 710 are respectively connected to the output terminals of the second signal calculation module 600.

[0081] Multiple counters 720, each with its input terminal connected to the output terminal of its corresponding comparator 710;

[0082] Multiple accumulators 730, each with its input terminal connected to the output terminal of its corresponding counter 720;

[0083] The input terminals of the averager 740 and the accumulator 730 are connected to the output terminals of each accumulator 730, and the output terminal of the averager is connected to the input terminal of the compensation module 400.

[0084] It should be noted that the multiple comparators 710 in the harmonic coefficient generation module 700 are of the same type, the multiple counters 720 are also of the same type, and the multiple accumulators 730 are of the same type. This is to maintain the uniformity of the processing of the signal output by the second signal calculation module 600.

[0085] Reference Figure 3 , Figure 3 This invention provides a flowchart of a distortion calibration circuit for analog-to-digital conversion. Based on this circuit, the distortion calibration method for analog-to-digital conversion includes, but is not limited to:

[0086] In step S100, the first signal calculation module 200 adds the analog input signal and the jitter signal to obtain the first signal, and inputs the first signal into the target input buffer 300, wherein the jitter signal is provided by the jitter signal generation module 100.

[0087] In step S200, the target input buffer 300 isolates the first signal and inputs it to the compensation module 400;

[0088] In step S300, the compensation module 400 performs harmonic compensation on the first signal according to the harmonic coefficient to obtain the second signal, and inputs the second signal into the analog-to-digital converter 500. The harmonic coefficient is generated by the harmonic coefficient generation module 700.

[0089] In step S400, the analog-to-digital converter 500 performs analog-to-digital conversion on the second signal to obtain the target digital signal;

[0090] In step S500, the second signal calculation module 600 performs a subtraction calculation between the target digital signal and the jitter signal to obtain a third signal, and inputs the third signal into the harmonic coefficient generation module 700.

[0091] In step S600, the harmonic coefficient generation module 700 calculates the third signal and the jitter signal, and updates the harmonic coefficients based on the calculation results.

[0092] It should be noted that after the jitter signal generation module 100 generates a random jitter signal, it inputs the jitter signal into the first signal calculation module 200. The first signal calculation module 200 adds the jitter signal and the analog input signal to obtain the first signal. Then, the first signal is input into the first buffer, and after passing through the first buffer, it is input into the compensation module 400. The compensation module 400 performs harmonic compensation on the first signal to obtain the second signal. After being quantized by the analog-to-digital converter 500, the second signal calculation module 600 subtracts the previously added random jitter signal in the digital domain to obtain the third signal. The harmonic coefficient generation module 700 calculates the third signal to obtain the harmonic coefficient, which is then input into the compensation module 400 for adjustment. After that, the next cycle begins. The obtained harmonic coefficient is positively correlated with the harmonic magnitude of the uncalibrated output signal.

[0093] In another embodiment, the harmonic coefficient generation module 700 includes an accumulator 730, multiple comparators 710, multiple counters 720, and multiple accumulators 730. Each comparator 710 is connected to each counter 720 in a one-to-one correspondence, and each accumulator 730 is connected to each counter 720 in a one-to-one correspondence. An averager 740 is connected to the accumulators 730 and to the compensation module 400. Each comparator 710 has a preset voltage threshold, and the voltage threshold in each comparator 710 is different. The harmonic coefficient generation module 700 calculates the harmonic coefficients of the third signal based on a preset harmonic coefficient generation algorithm, and inputs the harmonic coefficients into the compensation module 400, including:

[0094] Comparator 710 compares the voltage threshold with the second signal to obtain the comparison result;

[0095] If the comparison result is less than the absolute value of the voltage threshold, the third signal is assigned a value of 0.

[0096] If the comparison result is greater than the absolute value of the voltage threshold, the third signal is assigned the value 1;

[0097] Counter 720 multiplies the third signal with the jitter signal to obtain the multiplication result;

[0098] The accumulator 730 adds the multiplication results passed through the same comparator 710 and counter 720 to obtain the sum.

[0099] The averager averages the sum of the outputs of each accumulator 730 to obtain the harmonic coefficients.

[0100] It should be noted that the second signal is compared sequentially with voltage thresholds in multiple comparators 710. For example, if the value of the second signal is within ±1, the voltage thresholds in different comparators 710 are set to -0.9, 0.8...0.1, 0.2...0.9 respectively. The second signal is sequentially input into different comparison values. If the absolute value of the second signal is less than the voltage threshold corresponding to the comparator 710 used for calculation, the third signal is assigned a value of 0; if the absolute value of the second signal is greater than the voltage threshold, the third signal is assigned a value of 1. Each comparator 710 is connected to a counter 720. The third signal output by the comparator 710 is input into the counter 720. The counter 720 multiplies the input third signal and the jitter signal to obtain the multiplication result. For example, if the third signal is 0, the multiplication result is 0; if the third signal is 1, the multiplication result is the magnitude of the jitter signal. Assuming the entire workflow repeats N times, and that there are M comparators 710, M counters 720, and M accumulators 730, the accumulator 730 will take the N inputs to the harmonic coefficient generation module 700, and sum the results after processing by the counters 720 and comparators 710. This sum is then input to the averager 740, which will have M summed results. These M averaged results are then averaged to obtain the harmonic coefficients. This ensures a stable and accurate acquisition of the relevant harmonic coefficients, allowing for more precise compensation of higher-order harmonics. Finally, the obtained harmonic coefficients are used to adjust the compensation circuit in the background.

[0101] In another embodiment, the jitter signal generation module includes: a first jitter signal generation submodule 121 for generating a first jitter sub-signal; and a second jitter signal generation submodule 122 for generating a second jitter sub-signal. The first signal calculation module further includes: a first capacitive coupler, which is connected to the output terminal of the first jitter signal generation submodule 121, the input position of the analog input signal, and the first input terminal of the target input buffer, respectively; and a second capacitive coupler, which is connected to the output terminal of the second jitter signal generation submodule 122, the input position of the analog input signal, and the second input terminal of the target input buffer, respectively.

[0102] The first signal calculation module adds the analog input signal and the jitter signal to obtain a first signal, and then inputs the first signal into the target input buffer, including:

[0103] The first jitter signal generation submodule 121 generates a first jitter sub-signal and inputs the first jitter sub-signal to the first capacitive coupler;

[0104] The first capacitive coupler couples the analog input signal with the first jitter sub-signal, and the coupled analog input signal is input to the target input buffer through the first input terminal of the target input buffer;

[0105] The second jitter signal generation submodule 122 generates a second jitter sub-signal and inputs the second jitter sub-signal to the second capacitive coupler;

[0106] The second capacitive coupler couples the analog input signal with the second jitter sub-signal, and the coupled analog input signal is input to the target input buffer through the second input terminal of the target input buffer.

[0107] It should be noted that the first jitter sub-signal output by the first jitter signal generation submodule 121 intersects with the analog input signal at the first capacitive coupler. Furthermore, a first reference voltage generation module 123 is also provided at the intersection point. The first reference voltage signal output by the first reference voltage generation module 123 is a DC voltage, used to DC bias the signal at the intersection point. The signal is then input into the target input buffer through the first input terminal of the target input buffer. Similarly, to ensure that the two input terminals of the target input buffer 300 are in phase, the second jitter sub-signal output by the second jitter signal generation submodule 122 intersects with the analog input signal at the second capacitive coupler. Furthermore, a second reference voltage generation module 124 is also provided at the intersection point. The second reference voltage signal output by the second reference voltage generation module 124 is a DC voltage, used to DC bias the signal at the intersection point. The signal is then input into the target input buffer through the second input terminal of the target input buffer. In other words, two sets of jitter signal generation submodules, capacitive couplers, and reference voltage modules are provided. The first jitter sub-signal and the second jitter sub-signal have the same magnitude.

[0108] In another embodiment, the compensation module 400 includes a harmonic compensation diode load. The compensation module 400 performs harmonic compensation on the first signal according to the harmonic coefficient to obtain a second signal, and inputs the second signal to the analog-to-digital converter 500, including:

[0109] The compensation module 400 adjusts the load of the harmonic compensation diode according to the harmonic coefficient.

[0110] It should be noted that after the harmonic coefficient generation module 700 inputs the harmonic coefficients into the compensation module 400, the signal distortion caused by the nonlinearity of the target input buffer 300 can be effectively improved by adjusting the load of the harmonic compensation diode in the compensation module 400 according to the harmonic coefficients.

[0111] The following are specific examples:

[0112] refer to Figure 4For example, consider a linear system where the x-axis represents the input and the y-axis represents the output. The thinnest line represents the normal input signal, while the thick dashed line represents the input signal with added random jitter. After adding the jitter, the output signal is increased by Vd. The thick solid line represents the output after subtracting the same random jitter. In a linear system, the thick solid line portion returns to the position of the thinnest line after subtracting the jitter.

[0113] refer to Figure 5 For a nonlinear system that requires calibration, such as Figure 5 The thinnest line represents the input-output curve of the signal, with the horizontal axis representing the input and the vertical axis representing the output. After adding random jitter, the output signal's thick dashed line does not directly shift, but rather exhibits a certain non-linear upward shift. The jitter signal directly subtracted from the output is unaffected by non-linearity, and the thick solid curve is directly shifted compared to the thick dashed curve. This process reveals that changing the sign of the jitter results in different thick and solid curves. For example, as shown in the figure, when the jitter Vd is positive, the reconstructed thick solid curve exhibits maximum non-linearity near VFS. It can be inferred that when the jitter Vd is negative, the reconstructed thick solid curve exhibits maximum non-linearity near 0. This property of random jitter can be used to evaluate the non-linear region under different conditions. By adding random jitter (constant magnitude, random sign) to the input, after passing through the input buffer—a non-linear system—the magnitude of this jitter becomes non-linear due to the influence of the non-linear system. Subtracting the previously added random jitter from the output signal then reveals the influence of the non-linear system on the random jitter.

[0114] This application also provides an electronic device, including a distortion calibration circuit for analog-to-digital conversion as described above.

[0115] This application also provides a storage medium, which is a computer-readable storage medium, storing a computer program that, when executed by a processor, implements the above-described distortion calibration method for analog-to-digital conversion.

[0116] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory may optionally include memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof. The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separate, and may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0117] It will be understood by those skilled in the art that all or some of the steps and systems in the methods disclosed above can be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, as is known to those skilled in the art, communication media typically include computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0118] The above provides a detailed description of the preferred embodiments of the present invention. However, the present invention is not limited to the above embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of the present invention.

Claims

1. A distortion calibration circuit for analog-to-digital conversion, characterized in that, include: Jitter signal generation module, used to generate jitter signals; A first signal calculation module, wherein a first input terminal of the first signal calculation module is used to connect to an analog input signal, and a second input terminal of the first signal calculation module is connected to the output terminal of the jitter signal generation module, and the first signal calculation module is used to add the analog input signal and the jitter signal; A target input buffer, wherein the input terminal of the target input buffer is connected to the output terminal of the first signal calculation module; A compensation module, wherein the first input terminal of the compensation module is connected to the output terminal of the target input buffer; An analog-to-digital converter, wherein the input terminal of the analog-to-digital converter is connected to the output terminal of the compensation module; The second signal calculation module has a first input terminal connected to the output terminal of the analog-to-digital converter and a second input terminal connected to the output terminal of the jitter signal generation module. It is used to subtract the signal output by the analog-to-digital converter from the output result of the jitter signal generation module. The harmonic coefficient generation module has its input terminal connected to the output terminal of the second signal calculation module, and its output terminal connected to the second input terminal of the compensation module.

2. The distortion calibration circuit for analog-to-digital conversion according to claim 1, characterized in that, The jitter signal generation module includes: The first jitter signal generation submodule is used to generate the first jitter sub-signal; The second jitter signal generation submodule is used to generate the second jitter sub-signal; The first signal calculation module further includes: The first capacitive coupler is connected to the output terminal of the first jitter signal generation submodule, the input position of the analog input signal, and the first input terminal of the target input buffer, respectively. The second capacitive coupler is connected to the output terminal of the second jitter signal generation submodule, the input position of the analog input signal, and the second input terminal of the target input buffer.

3. The distortion calibration circuit for analog-to-digital conversion according to claim 1, characterized in that, The compensation module includes a harmonic compensation diode load, which is connected to the target input buffer.

4. The distortion calibration circuit for analog-to-digital conversion according to claim 2, characterized in that, The harmonic coefficient generation module includes: Multiple comparators, each with its input terminal connected to the output terminal of the second signal calculation module; Multiple counters, each of which has its input terminal connected to the output terminal of its corresponding comparator; Multiple accumulators, each with its input terminal connected to the output terminal of its corresponding counter; The averager has its input terminals connected to the output terminals of each of the accumulators, and its output terminal connected to the input terminal of the compensation module.

5. A distortion calibration method for analog-to-digital conversion, characterized in that, Based on the distortion calibration circuit for analog-to-digital conversion as described in any one of claims 1 to 4, the method includes: The first signal calculation module adds the analog input signal and the jitter signal to obtain a first signal, and inputs the first signal into the target input buffer. The jitter signal is provided by the jitter signal generation module. The target input buffer isolates the first signal and inputs it to the compensation module; The compensation module performs harmonic compensation on the first signal according to the harmonic coefficient to obtain the second signal, and inputs the second signal into the analog-to-digital converter. The harmonic coefficient is generated by the harmonic coefficient generation module. The analog-to-digital converter performs analog-to-digital conversion on the second signal to obtain the target digital signal; The second signal calculation module subtracts the target digital signal from the jitter signal to obtain a third signal, and inputs the third signal into the harmonic coefficient generation module. The harmonic coefficient generation module calculates the third signal and the jitter signal, and updates the harmonic coefficients based on the calculation results.

6. The distortion calibration method for analog-to-digital conversion according to claim 5, characterized in that, The harmonic coefficient generation module includes multiple comparators, multiple counters, multiple accumulators, and multiple averagers. Each comparator is connected to a corresponding counter, each accumulator is connected to a corresponding counter, and each averager is connected to the accumulators and the compensation module. Each comparator has a preset voltage threshold, and the voltage threshold for each comparator is different. The harmonic coefficient generation module calculates the harmonic coefficients of the third signal based on a preset harmonic coefficient generation algorithm, and inputs the harmonic coefficients into the compensation module, including: The comparator compares the voltage threshold with the second signal to obtain a comparison result; If the comparison result is less than the absolute value of the voltage threshold, then the third signal is assigned a value of 0; If the comparison result is greater than the absolute value of the voltage threshold, then the third signal is assigned a value of 1; The counter multiplies the third signal with the jitter signal to obtain the multiplication result; The accumulator adds the multiplication results that have passed through the same comparator and counter to obtain the sum. The averager averages the summation results output by each of the accumulators to obtain the harmonic coefficients.

7. The distortion calibration method for analog-to-digital conversion according to claim 5, characterized in that, The jitter signal generation module includes: a first jitter signal generation submodule for generating a first jitter sub-signal; and a second jitter signal generation submodule for generating a second jitter sub-signal. The first signal calculation module further includes: a first capacitive coupler, which is connected to the output terminal of the first jitter signal generation submodule, the input position of the analog input signal, and the first input terminal of the target input buffer; and a second capacitive coupler, which is connected to the output terminal of the second jitter signal generation submodule, the input position of the analog input signal, and the second input terminal of the target input buffer. The first signal calculation module adds the analog input signal and the jitter signal to obtain a first signal, and inputs the first signal into the target input buffer, including: The first jitter signal generation submodule generates the first jitter sub-signal and inputs the first jitter sub-signal to the first capacitive coupler; The first capacitive coupler couples the analog input signal with the first jitter sub-signal, and the coupled analog input signal is input to the target input buffer through the first input terminal of the target input buffer; The second jitter signal generation submodule generates the second jitter sub-signal and inputs the second jitter sub-signal to the second capacitive coupler; The second capacitive coupler couples the analog input signal with the second jitter sub-signal, and the coupled analog input signal is input to the target input buffer through the second input terminal of the target input buffer.

8. The distortion calibration method for analog-to-digital conversion according to claim 5, characterized in that, The compensation module includes a harmonic compensation diode load. The compensation module performs harmonic compensation on the first signal according to the harmonic coefficient to obtain a second signal, and inputs the second signal to the analog-to-digital converter, including: The compensation module adjusts the load of the harmonic compensation diode according to the harmonic coefficient.

9. An electronic device, characterized in that, Includes the distortion calibration circuit for analog-to-digital conversion as described in any one of claims 1 to 4.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions for causing a computer to perform the distortion calibration method for analog-to-digital conversion as described in any one of claims 5 to 8.

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