Data processing method and device and communication system

Abstract

The invention provides a data processing method and device and a communication system, and belongs to the technical field of communication. The method comprises the steps that a data sequence is acquired, and the data sequence comprises a plurality of forward error correction (FEC) code words; performing FEC decoding on at least one FEC code word in the data sequence to obtain at least one decoded code word; and finding a preset sequence in the at least one decoded code word. The bit error rate of the decoded code word is low, so that the time consumed for searching the preset sequence in the at least one decoded code word of the data sequence is short, and the efficiency, precision and reliability of searching the preset sequence in the data sequence can be improved.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a method and device for processing data, and a communication system. Background Art

[0002] In the field of communications, when a transmitter in Ethernet sends data to a receiver, it periodically inserts a preset sequence into the data, and the transmitter sends a data sequence containing the preset sequence to the receiver. These periodic preset sequences may be used by the receiver to find the codeword boundary in the received data sequence, or may be used to fill the data sequence to a specific length, etc. After receiving the data sequence, the receiver finds the preset sequence in the data sequence, and then decodes the data sequence after deleting the preset sequence in the data sequence.

[0003] However, due to the influence of channel loss and noise, bit errors are inevitable in the process of transmitting the data sequence from the transmitter to the receiver. Bit errors are inevitable in the data sequence received by the receiver. These bit errors can easily increase the time spent by the receiver in searching for the preset sequence in the data sequence, or even cause the receiver to be unable to find the real preset sequence in the data sequence, thereby affecting the data processing at the receiver. Summary of the invention

[0004] The present application provides a method and device for processing data, and a communication system, which can shorten the time spent in searching for a preset sequence in a data sequence, and improve the efficiency, accuracy, and reliability of searching for a preset sequence in a data sequence. The technical solution of the present application is as follows.

[0005] In a first aspect, a method for processing data is provided, the method comprising: acquiring a data sequence, the data sequence comprising a plurality of forward error correction (FEC) codewords; performing FEC decoding on at least one FEC codeword in the data sequence to obtain at least one decoded codeword; and finding a preset sequence in the at least one decoded codeword.

[0006] The technical solution provided by the present application searches for a preset sequence based on decoded data. Since error detection and error correction can be performed on at least one FEC codeword in a data sequence during FEC decoding of the at least one FEC codeword, the bit error rate of at least one decoded codeword obtained by FEC decoding of the at least one FEC codeword is low or may even be error-free, so that the time spent in searching for the preset sequence in the at least one decoded codeword is short, and the efficiency, accuracy and reliability are all high, thereby ensuring the transmission efficiency and reliability of the communication system.

[0007] Optionally, the preset sequence is a sequence that appears periodically in the data sequence. The period in which the preset sequence appears in the data sequence may be a strict period or a non-strict period, different strict periods are strictly equal, different non-strict periods may be unequal, and the difference between different non-strict periods is less than a preset difference. Optionally, the period in which the preset sequence appears in the data sequence is a non-strict period, and the regularity of the appearance of the preset sequence in the data sequence is roughly periodic.

[0008] Optionally, the method includes: if a preset condition is met, deleting a padding sequence related to the preset sequence in the data sequence according to the position of the preset sequence found in the data sequence, the preset condition including that the number of the preset sequence included in n codewords in the at least one decoded codeword reaches a first threshold, n is a positive integer, and the interval between adjacent codewords in the n codewords is the period of the preset sequence appearing in the data sequence. The padding sequence related to the preset sequence may be a padding sequence including the preset sequence.

[0009] Optionally, the method includes: if a loss of lock condition is met, re-searching the FEC codeword boundary in the data sequence, the loss of lock condition including that the number of m codewords in the at least one decoded codeword that do not include the preset sequence reaches a second threshold, m is a positive integer, and the interval between adjacent codewords in the m codewords is the period in which the preset sequence appears in the data sequence.

[0010] The technical solution provided by the present application can, when the number of codewords that do not include a preset sequence in the m codewords in the at least one decoded codeword reaches a second threshold, determine that the locked FEC codeword boundary is incorrect and the locked FEC codeword boundary is unlocked, and therefore the FEC codeword boundary in the data sequence is searched again to facilitate FEC decoding of the data sequence according to the newly found FEC codeword boundary.

[0011] Optionally, performing FEC decoding on at least one FEC codeword in the data sequence to obtain at least one decoded codeword includes: performing FEC decoding on the multiple FEC codewords to obtain multiple decoded codewords; correspondingly, finding a preset sequence in the at least one decoded codeword includes: finding a preset sequence in the multiple decoded codewords. Optionally, searching for a preset sequence in the multiple decoded codewords in order of arrangement of the multiple decoded codewords until the first preset sequence is found; after finding the first preset sequence, searching for the preset sequence in the codeword after the codeword where the first preset sequence is located according to the period in which the preset sequence appears in the data sequence. That is, searching for the first preset sequence in the multiple decoded codewords codeword by codeword, after finding the first preset sequence, no longer searching for the preset sequence codeword by codeword, but searching for the preset sequence in the multiple decoded codewords according to the period in which the preset sequence appears in the data sequence.

[0012] The technical solution provided by the present application searches for the first preset sequence codeword by codeword. After finding the first preset sequence, the preset sequence is searched in the multiple decoded codewords according to the period at which the preset sequence appears in the data sequence, which can improve the efficiency of searching for the preset sequence.

[0013] Optionally, performing FEC decoding on at least one FEC codeword in the data sequence to obtain at least one decoded codeword, and finding a preset sequence in the at least one decoded codeword, includes: performing FEC decoding on the first FEC codeword in the data sequence to obtain the first decoded codeword; if the first decoded codeword does not include the preset sequence, continuing to perform FEC decoding on the FEC codewords after the first FEC codeword in the data sequence until the first preset sequence is found. For example, searching for the preset sequence in the decoded first codeword, if the preset sequence is not found in the decoded first codeword, performing FEC decoding on the FEC codewords after the first FEC codeword in the data sequence in sequence according to the arrangement order of the FEC codewords in the data sequence, and searching for the preset sequence in the decoded codewords until the first preset sequence is found. The first FEC codeword is a FEC codeword in the data sequence, for example, the first FEC codeword in the data sequence.

[0014] Optionally, performing FEC decoding on at least one FEC codeword in the data sequence to obtain at least one decoded codeword, and finding a preset sequence in the at least one decoded codeword, further includes: if the decoded first codeword includes the preset sequence, performing FEC decoding on the second FEC codeword after the first FEC codeword in the data sequence to obtain a decoded second codeword, wherein the interval between the second FEC codeword and the first FEC codeword is the period in which the preset sequence appears in the data sequence; and attempting to find the preset sequence in the decoded second codeword. That is, searching for the first preset sequence in the data sequence one by one FEC codeword, and after finding the first preset sequence, no longer searching for the preset sequence one by one FEC codeword, but searching for the preset sequence in the data sequence according to the period in which the preset sequence appears in the data sequence.

[0015] The technical solution provided by the present application attempts to find a preset sequence in the data sequence according to the period at which the preset sequence appears in the data sequence after the first preset sequence is found in the data sequence, which can improve the efficiency of finding the preset sequence.

[0016] Optionally, performing FEC decoding on at least one FEC codeword in the data sequence includes: performing FEC decoding on the first FEC codeword in the data sequence using a first decoding method; and performing FEC decoding on candidate FEC codewords after the first FEC codeword in the data sequence using a second decoding method. For example, during the process of locking the preset sequence, the first decoding method is used to perform FEC decoding on the FEC codewords in the data sequence (including the first FEC codeword and possibly the second FEC codeword), and after the preset sequence is locked, the second decoding method is used to perform FEC decoding on candidate FEC codewords after the first FEC codeword in the data sequence. The candidate FEC codewords include all undecoded FEC codewords in the data sequence after the preset sequence is locked.

[0017] In the technical solution provided by the present application, the first decoding method is different from the second decoding method, and the decoding method used in the preset sequence locking process is different from the decoding method used after the preset sequence is locked, which can increase the applicability of the present application.

[0018] Optionally, the first decoding method is soft-decision decoding (SDD), and the second decoding method is hard-decision decoding (HDD). Alternatively, the first decoding method is HDD, and the second decoding method is SDD. Optionally, SDD is used to perform FEC decoding on the FEC codewords in the data sequence during the preset sequence locking process, and HDD is used to perform FEC decoding on the FEC codewords in the data sequence after the preset sequence is locked. Alternatively, HDD is used to perform FEC decoding on the FEC codewords in the data sequence during the preset sequence locking process, and SDD is used to perform FEC decoding on the FEC codewords in the data sequence after the preset sequence is locked. The complexity of HDD decoding is low, and the decoding performance of SDD is better. After the preset sequence is locked, formal data processing is performed on the data sequence, and the formal data processing includes FEC decoding of the FEC codewords in the data sequence. That is, the process of performing FEC decoding on the FEC codewords in the data sequence after the preset sequence is locked belongs to the process of performing formal data processing on the data sequence.

[0019] The technical solution provided by the present application, when the first decoding mode is HDD and the second decoding mode is SDD, uses HDD to perform FEC decoding on the FEC codewords in the data sequence during the preset sequence locking process, and uses SDD to perform FEC decoding on the FEC codewords in the data sequence after the preset sequence is locked, which can reduce the complexity of locking the preset sequence and ensure the error performance of formal data processing. When the first decoding mode is SDD and the second decoding mode is HDD, uses SDD to perform FEC decoding on the FEC codewords in the data sequence during the preset sequence locking process, and uses HDD to perform FEC decoding on the FEC codewords in the data sequence after the preset sequence is locked, which can improve the reliability of locking the preset sequence and reduce the complexity of formal data processing.

[0020] Optionally, the first decoding method and the second decoding method are implemented using the same hardware logic, thereby reducing implementation complexity and cost.

[0021] Optionally, before performing FEC decoding on at least one FEC codeword in the data sequence, the method further includes: determining a boundary of an FEC codeword in the data sequence by means of self-synchronization.

[0022] The technical solution provided in the present application can achieve the technical effect of high-precision codeword synchronization by determining the FEC codeword boundary in the data sequence by means of self-synchronization, and the reliability of the FEC codeword boundary determined by self-synchronization is relatively high.

[0023] Optionally, the preset sequence is a frame sequence (FS) or the preset sequence is in an alignment marker (AM). Thus, the technical solution of the present application can interoperate with the Institute of Electrical and Electronics Engineers (IEEE) 802.3dj standard and the 200 / 400 Gigabyte Ethernet (GE) standard.

[0024] Optionally, the preset sequence is FS, the filling sequence associated with the preset sequence is the filling sequence in the IEEE802.3dj standard, the preset sequence is located at the beginning of the filling sequence associated with the preset sequence, and the length of the filling sequence is an integer multiple of the length of the FEC codeword in the data sequence.

[0025] Optionally, the method is performed by a host chip, an optical module or a chip in an optical module. The optical module may be a pluggable optical module.

[0026] Optionally, the data sequence is obtained based on an Ethernet signal received from an Ethernet interface.

[0027] Optionally, the Ethernet signal is a Terabit Ethernet (TbE) signal.

[0028] In a second aspect, a device for processing data is provided, wherein the device is used to execute the method provided by the first aspect or any optional implementation of the first aspect.

[0029] Optionally, the device includes an Ethernet interface. The Ethernet interface may be a Terabit Ethernet interface.

[0030] Optionally, the device is any one of the following: a forwarding device, a user terminal device or a server device, a host chip, an optical module or a chip in an optical module. The forwarding device may be a router or a switch.

[0031] In one implementation, the device includes at least one module, and the at least one module is used to execute the method provided in the first aspect or any optional aspect of the first aspect. The at least one module can be implemented based on software, hardware, or a combination of software and hardware, and the at least one module can be arbitrarily combined or divided based on the specific implementation.

[0032] Optionally, the device comprises:

[0033] An acquisition module, used for acquiring a data sequence, wherein the data sequence includes a plurality of forward error correction FEC code words;

[0034] A decoding module, configured to perform FEC decoding on at least one FEC codeword in the data sequence to obtain at least one decoded codeword;

[0035] The searching module is used to find a preset sequence in the at least one decoded code word.

[0036] Optionally, the preset sequence is a sequence that appears periodically in the data sequence.

[0037] Optionally, the device also includes: a deletion module, used to delete a padding sequence related to the preset sequence in the data sequence according to the position of the preset sequence found in the data sequence if a preset condition is met, and the preset condition includes that the number of the preset sequences included in n codewords in the at least one decoded codeword reaches a first threshold, n is a positive integer, and the interval between adjacent codewords in the n codewords is the period of appearance of the preset sequence in the data sequence.

[0038] Optionally, the device also includes: a synchronization module, used to re-search the FEC codeword boundary in the data sequence if the loss of lock condition is met, and the loss of lock condition includes that the number of m codewords in the at least one decoded codeword that do not include the preset sequence reaches a second threshold, m is a positive integer, and the interval between adjacent codewords in the m codewords is the period in which the preset sequence appears in the data sequence.

[0039] Optionally, the decoding module is used to perform FEC decoding on the multiple FEC codewords to obtain multiple decoded codewords;

[0040] Correspondingly, the searching module is used to find a preset sequence in the multiple decoded code words.

[0041] Optionally, the decoding module is used to:

[0042] Performing FEC decoding on a first FEC codeword in the data sequence to obtain a decoded first codeword;

[0043] If the decoded first codeword does not include the preset sequence, FEC decoding is continued on the FEC codewords after the first FEC codeword in the data sequence until a first preset sequence is found.

[0044] Optionally, the decoding module is further configured to: if the decoded first codeword includes the preset sequence, perform FEC decoding on a second FEC codeword following the first FEC codeword in the data sequence to obtain a decoded second codeword, wherein an interval between the second FEC codeword and the first FEC codeword is a period in which the preset sequence appears in the data sequence;

[0045] Correspondingly, the searching module is used to try to find the preset sequence in the decoded second codeword.

[0046] Optionally, the decoding module is used to: perform FEC decoding on the first FEC codeword in the data sequence using a first decoding method; and perform FEC decoding on candidate FEC codewords following the first FEC codeword in the data sequence using a second decoding method.

[0047] Optional; the first decoding mode is soft decision decoding, and the second decoding mode is hard decision decoding; or,

[0048] The first decoding mode is hard decision decoding, and the second decoding mode is soft decision decoding.

[0049] Optionally, the device further includes: a synchronization module, configured to determine the FEC codeword boundary in the data sequence by self-synchronization.

[0050] Optionally, the preset sequence is a frame sequence FS or the preset sequence is in an alignment mark AM.

[0051] Optionally, the data sequence is obtained based on an Ethernet signal received from an Ethernet interface.

[0052] Optionally, the Ethernet signal is a Terabit Ethernet signal.

[0053] In another implementation, the device includes: a memory, a processor, and a communication interface, wherein the communication interface includes an Ethernet interface;

[0054] The memory is used to store a computer program; the processor is used to execute the computer program stored in the memory so that the device performs relevant steps in the method provided in the above-mentioned first aspect or any optional manner of the first aspect.

[0055] Optionally, the processor is used to execute a computer program stored in the memory so that the device performs: finding a preset sequence in at least one decoded codeword, wherein the at least one decoded codeword is obtained by FEC decoding at least one forward error correction (FEC) codeword in a data sequence, and the data sequence includes multiple FEC codewords.

[0056] Optionally, the processor is used to execute the computer program stored in the memory and further causes the device to execute: if a preset condition is met, deleting a padding sequence related to the preset sequence in the data sequence according to the position of the preset sequence found in the data sequence, and the preset condition includes that the number of the preset sequences included in n codewords in the at least one decoded codeword reaches a first threshold, n is a positive integer, and the interval between adjacent codewords in the n codewords is the period of appearance of the preset sequence in the data sequence.

[0057] In a third aspect, a chip is provided for executing the method provided in the first aspect or any optional manner of the first aspect.

[0058] Optionally, the chip is a main chip or a chip in an optical module, and the chip includes a programmable logic circuit and / or program instructions.

[0059] In a fourth aspect, a computer-readable storage medium is provided, wherein a computer program is stored in the computer-readable storage medium, and when the computer program is executed, it is implemented: finding a preset sequence in at least one decoded codeword, wherein the at least one decoded codeword is obtained by FEC decoding at least one forward error correction (FEC) codeword in a data sequence, and the data sequence includes multiple FEC codewords.

[0060] Optionally, when the computer program is executed, it also implements: if a preset condition is met, deleting a padding sequence related to the preset sequence in the data sequence according to the position of the preset sequence found in the data sequence, and the preset condition includes that the number of the preset sequences included in n codewords in the at least one decoded codeword reaches a first threshold, n is a positive integer, and the interval between adjacent codewords in the n codewords is the period of appearance of the preset sequence in the data sequence.

[0061] In a fifth aspect, a computer program product is provided, comprising a program or code, which, when executed, implements: finding a preset sequence in at least one decoded codeword, wherein the at least one decoded codeword is obtained by performing FEC decoding on at least one forward error correction (FEC) codeword in a data sequence, and the data sequence comprises multiple FEC codewords.

[0062] Optionally, when the program or code is executed, it also implements: if a preset condition is met, deleting a padding sequence related to the preset sequence in the data sequence according to the position of the preset sequence found in the data sequence, and the preset condition includes that the number of the preset sequences included in n codewords in the at least one decoded codeword reaches a first threshold, n is a positive integer, and the interval between adjacent codewords in the n codewords is the period of appearance of the preset sequence in the data sequence.

[0063] In a sixth aspect, a communication system is provided, comprising an optical module and a host, wherein the optical module is communicatively connected to the host, for example, the optical module is plugged into the host, and the optical module is used to execute the method provided in the first aspect or any optional manner of the first aspect.

[0064] Optionally, the host is a forwarding device, a user terminal device or a server device. The forwarding device is a router or a switch.

[0065] The technical solution provided by the present application is that since the optical module is used to execute the method provided by the first aspect or any optional method of the first aspect mentioned above, the optical module executing the above method can improve the efficiency, accuracy and reliability of finding a preset sequence in a data sequence, thereby enabling the host connected to the optical module to obtain corresponding benefits, such as improving the host's processing efficiency and reliability of the data sequence.

[0066] The technical effects not described in the above-mentioned second to sixth aspects can refer to the technical effects of the first aspect and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] Figure 1 It is a schematic diagram of sending data at the physical layer;

[0068] Figure 2 It is a schematic diagram of an application scenario provided by an embodiment of the present application;

[0069] Figure 3 is a schematic diagram of a data sequence provided in an embodiment of the present application;

[0070] Figure 4 is a schematic diagram of another data sequence provided in an embodiment of the present application;

[0071] Figure 5 is a schematic diagram of another data sequence provided in an embodiment of the present application;

[0072] Figure 6 is a schematic diagram of another data sequence provided in an embodiment of the present application;

[0073] Figure 7is a schematic diagram of another application scenario provided by an embodiment of the present application;

[0074] Figure 8 is a schematic diagram of another application scenario provided by an embodiment of the present application;

[0075] Fig. 9 is a schematic diagram of another application scenario provided by an embodiment of the present application;

[0076] Fig.10 is a schematic diagram of another application scenario provided by an embodiment of the present application;

[0077] Fig.11 is a flow chart of a method for processing data provided by an embodiment of the present application;

[0078] Fig.12 is a flow chart of another method for processing data provided by an embodiment of the present application;

[0079] Fig.13 is a schematic diagram of a method for processing data provided in an embodiment of the present application;

[0080] Fig.14 is a state diagram of a preset sequence locking process provided by an embodiment of the present application;

[0081] Fig.15 is a state diagram of a preset sequence monitoring process provided by an embodiment of the present application;

[0082] Fig.16 is a schematic diagram of a device for processing data provided by an embodiment of the present application;

[0083] Fig.17 is a schematic diagram of another device for processing data provided in an embodiment of the present application;

[0084] Fig.18 It is a schematic diagram of another device for processing data provided in an embodiment of the present application. DETAILED DESCRIPTION

[0085] The implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0086] Synchronization technology is an important technology in the field of communications, and there are many scenarios where synchronization technology is used. Based on different goals, synchronization can be divided into multiple types such as clock synchronization, carrier synchronization, bit synchronization, and frame synchronization. Clock synchronization is to ensure the time consistency between different devices. Carrier synchronization refers to the process in which the receiver obtains a coherent carrier from the received signal in coherent optical transmission. Bit synchronization refers to the process in which the receiver extracts a clock signal from the received signal to make correct sampling decisions for information code elements. Frame synchronization refers to the process in which the receiver identifies the beginning or end of a specific data block from a received data sequence (or data stream). For example, the data sequence received by the receiver includes multiple codewords (codeword, CW), and frame synchronization refers to the process in which the receiver identifies the beginning or end of a codeword from the data sequence. The beginning and end of a codeword are also called codeword boundaries, so frame synchronization refers to the process in which the receiver identifies the codeword boundary from the received data sequence. Optionally, the data sequence received by the receiving end is a data sequence encoded by forward error correction (FEC), the codeword in the data sequence is an FEC codeword, and frame synchronization refers to the process of the receiving end identifying the FEC codeword boundary from the data sequence. The FEC codeword boundary is also the codeword boundary of the FEC codeword, also known as the boundary of the FEC codeword. In some implementation scenarios, frame synchronization is also called codeword synchronization (codeword synchronization), and the codeword boundary in the data sequence is also called synchronization position (synchronization position).

[0087] In the field of communications, when a transmitter in Ethernet sends data to a receiver, it periodically inserts a preset sequence into the data, and the transmitter sends a data sequence containing the preset sequence to the receiver. These periodic preset sequences may be used by the receiver to find the codeword boundary in the received data sequence, or may be used to fill the data sequence to a specific length, etc. After receiving the data sequence, the receiver finds the preset sequence in the data sequence, and then decodes the data sequence after deleting the preset sequence in the data sequence. Figure 1 This is a schematic diagram of the physical layer data transmission adopted by the Institute of Electrical and Electronics Engineers (IEEE) 802.3dj standard project. Figure 1As shown, the transmitting end includes a host chip and an optical module, and the host chip and the optical module are connected through an attachment unit interface (AUI). When the transmitting end sends a data sequence A0, the host chip first performs a first FEC encoding on the data sequence A0 to obtain a data sequence A1, and the host chip sends the data sequence A1 to the optical module through the AUI. The optical module performs a second FEC encoding on the data sequence A1 and periodically inserts a pad or padding sequence into the data sequence A1 to obtain a data sequence A2, and the optical module sends the data sequence A2 to the receiving end. Among them, the data sequence A2 includes a plurality of codewords (codewords, CW) and a plurality of padding sequences, and each CW of the plurality of CWs is an FEC codeword obtained by the second FEC encoding. Optionally, the optical module also interleaves the FEC codewords obtained by the second FEC encoding. In this case, each CW in the data sequence A2 is an interleaved codeword block obtained after the FEC codewords are interleaved (that is, an equal-length data block obtained after the FEC codewords are interleaved). The optical module may not interleave the FEC codewords obtained through the second FEC encoding, and this is not limited in the embodiments of the present application. The multiple filling sequences appear periodically in the data sequence A2, and each of the multiple filling sequences includes a preset sequence known to both the transmitter and the receiver. For example, the preset sequence is called a frame sequence (FS) in the IEEE802.3dj standard discussion. The preset sequence in each filling sequence is located at the beginning of the filling sequence, and the starting position of the preset sequence in each filling sequence is the same as the starting position of the filling sequence. The filling sequence has also undergone the second FEC encoding and possible interleaving, and the length of each filling sequence is an integer multiple of the length of the CW ( Figure 1 Take k times as an example, k is a positive integer, such as k = 2), so it can be considered that each padding sequence includes an integer number of padding CWs (padding CWs), which can also be called virtual CWs or simulated CWs. This integer number of padding CWs is additionally inserted by the transmitter in the data sequence to be sent. For example, CW is an FEC codeword obtained by the second FEC encoding, and the optical module inserts 3 padding codewords at intervals of 3264 FEC codewords (the padding codeword is also an FEC codeword, that is, the length of the padding sequence is 3 times the length of the FEC codeword), or inserts 8 padding codewords at intervals of 8704 FEC codewords (the padding codeword is also an FEC codeword, that is, the length of the padding sequence is 8 times the length of the FEC codeword).

[0088] After receiving the data sequence A2, in order to perform the second FEC decoding (i.e., the FEC decoding corresponding to the second FEC encoding) on ​​the data sequence A2, the receiving end needs to find the codeword boundary in the data sequence A2. For example, when the CW in the data sequence A2 is the FEC codeword obtained by the second FEC encoding, the codeword boundary is Figure 1 The boundary of the CW in the data sequence A2 is the FEC codeword boundary; in the case where the CW in the data sequence A2 is an interleaved codeword block obtained after interleaving the FEC codeword obtained by the second FEC encoding, the receiving end first deinterleaves the data sequence A2, and then finds the codeword boundary in the data sequence A2. Since the padding sequence is an additionally inserted non-media access control (MAC) data, the receiving end also needs to find the padding sequence in the data sequence A2 to delete it. The receiving end can find the padding sequence including the preset sequence in the data sequence A2 by finding the preset sequence known to the receiving end in the data sequence A2. The receiving end can find the codeword boundary in the data sequence A2 by performing codeword synchronization on the data sequence A2. Here, the CW in the data sequence A2 is an FEC codeword obtained by the second FEC encoding but not interleaved as an example. After the receiving end finds the codeword boundary in the data sequence A2, the receiving end determines the CW in the data sequence A2 according to the codeword boundary in the data sequence A2 and performs the second FEC decoding on the CW in the data sequence A2. Optionally, the receiving end performs the second FEC decoding on the data sequence A2 to obtain the data sequence A1, and the receiving end also performs the first FEC decoding (i.e., the FEC decoding corresponding to the first FEC encoding) on ​​the data sequence A1 to obtain the data sequence A0. It should be noted that the first FEC encoding, the second FEC encoding, the first FEC decoding, and the second FEC decoding are described as examples here. In some implementation scenarios or manuscripts, the first FEC encoding here is also described as outer FEC encoding or outer code encoding, the second FEC encoding here is also described as inner FEC encoding or inner code encoding, the first FEC decoding here is also described as outer FEC decoding or outer code decoding, and the second FEC decoding here is also described as inner FEC decoding or inner code decoding, and the embodiments of the present application do not limit this.

[0089] A codeword synchronization scheme is mentioned in the discussion of the IEEE802.3dj standard. The following is an example of the receiving end using the codeword synchronization scheme to find the codeword boundary in the data sequence A2, and an example of the CW in the data sequence A2 being the FEC codeword obtained through the second FEC encoding without interleaving. In the introduction, the preset sequence in the data sequence A2 is described as FS. The receiving end first searches for FS in the data sequence A2 based on the FS known to the receiving end, and then determines the codeword boundary in the data sequence A2 based on the FS found in the data sequence A2. The process of the receiving end searching for FS in the data sequence A2 based on the FS known to the receiving end includes a FS locking process and a FS monitoring process. Specifically, the FS locking process includes: the receiving end compares the FS known to the receiving end with the data sequence A2 bit by bit to find the FS in the data sequence A2. After the receiving end finds the first FS in the data sequence A2, the receiving end searches for the FS in the data sequence A2 based on the first FS and the period in which the FS appears in the data sequence A2. If the number of FSs found by the receiving end in succession in the data sequence A2 reaches a specified number (for example, 3), the receiving end considers that the first FS found is the real FS, and the receiving end locks the first FS. The FS monitoring process includes: after the receiving end locks the first FS, the receiving end determines the potential FS position in the data sequence A2 based on the target FS found in the FS locking process (for example, the target FS is the last FS found in the FS locking process) and the period in which the FS appears in the data sequence A2. The receiving end verifies whether the data content of the potential FS position matches the content of the FS known to the receiving end; if the data content of a potential FS position matches the content of the known FS, the receiving end determines that the data content of the potential FS position is FS (that is, the receiving end finds a FS), and the receiving end successfully verifies the potential FS position. If the receiving end fails to verify multiple potential FS positions that appear consecutively, the receiving end determines that the first locked FS is unlocked, and the receiving end re-locks the data sequence A2 (that is, re-executes the FS locking process), and performs FS monitoring on the data sequence A2 based on the re-locked FS (that is, re-executes the FS monitoring process), thus forming a closed-loop process of FS locking-FS monitoring-FS locking. After the receiving end locks the FS in the data sequence A2, the receiving end determines the codeword boundary in the data sequence A2 based on the locked FS in the data sequence A2. Among them, the potential FS position is the position where the FS may appear. The potential FS position is the area in the data sequence A2 whose length is equal to the FS length.For example, if the target FS is in bits a1 to (a1+48), and the period of FS appearance is (3264*128+3*128) bits, then the potential FS positions are bits [a1+(3264*128+3*128)] to [(a1+48)+(3264*128+3*128)], bits [a1+2*(3264*128+3*128)] to [(a1+48)+2*(3264*128+3*128)], ..., 3264*128 bits is the period of the filling sequence appearing in the data sequence A2, and 3*128 is the length of the filling sequence. For another example, the period of FS occurrence is (8704*128+8*128) bits, then the potential FS positions are [a1+(8704*128+8*128)]th to [(a1+48)+(8704*128+8*128)]th bits, [a1+2*(8704*128+8*128)]th to (a1+48)+2*(8704*128+8*128)]th bits, ..., 8704*128 bits are the interval of the filling sequence, and 8*128 is the length of the filling sequence.

[0090] The 200 / 400 Gigabyte Ethernet (GE) standard defined by the IEEE802.3bs project also mentions a codeword synchronization scheme, which differs from the above codeword synchronization scheme mentioned in the IEEE802.3dj standard discussion in that the padding sequence is replaced with an alignment marker (AM). Specifically, when the transmitting end sends a data sequence B0, the transmitting end performs FEC encoding on the data sequence B0 and periodically inserts AM into the data sequence B0 to obtain a data sequence B1, and the transmitting end sends the data sequence B1 to the receiving end. Among them, the data sequence B1 includes multiple CWs and multiple AMs, and each CW in the multiple CWs is an FEC codeword obtained by the FEC encoding. Optionally, the transmitting end also interleaves the FEC codewords obtained by the FEC encoding, in which case each CW in the data sequence B1 is an interleaved codeword block obtained after the FEC codewords are interleaved. The transmitting end may also not interleave the FEC codewords obtained by the FEC encoding, and the embodiments of the present application do not limit this. The multiple AMs appear periodically in the data sequence B1, and each of the multiple AMs includes a preset sequence known to both the transmitting end and the receiving end, and the AM has also been FEC encoded and possibly interleaved. Take the example that the CW in the data sequence B1 is an FEC codeword obtained through FEC encoding but not interleaved. After the receiving end receives the data sequence B1, the receiving end searches for the AM in the data sequence B1 according to the preset sequence known to the receiving end. For example, the receiving end searches for the preset sequence in the data sequence B1 according to the preset sequence known to the receiving end. The receiving end finds the AM including the preset sequence based on the preset sequence found, and the receiving end determines the codeword boundary in the data sequence B1 based on the AM found in the data sequence B1. The process of the receiving end searching for the AM in the data sequence A2 according to the preset sequence known to the receiving end includes an AM locking process and an AM monitoring process. Specifically, the AM locking process includes: the receiving end compares the preset sequence known to the receiving end and the data sequence B1 bit by bit to find AM in the data sequence B1. After the receiving end finds the first AM in the data sequence B1, the receiving end searches for AM in the data sequence B1 based on the first AM and the period at which AM appears in the data sequence B1. If the number of AMs found continuously by the receiving end in the data sequence B1 reaches a specified number (for example, 3), the receiving end considers that the first AM found is the real AM, and the receiving end locks the first AM.The AM monitoring process includes: after the receiving end locks the first AM, the receiving end determines the potential AM position in the data sequence B1 based on the target AM found in the AM locking process (for example, the target AM is the last AM found in the AM locking process) and the period of the AM appearing in the data sequence B1, and the receiving end verifies whether the data content of the potential AM position matches the content of the preset sequence known to the receiving end; if the data content of a potential AM position matches the content of the known preset sequence, the receiving end determines that the data content of the potential AM position is AM (that is, the receiving end has found an AM in the data sequence B1), and the receiving end successfully verifies the potential AM position. If the receiving end fails to verify multiple potential AM positions that appear in succession, the receiving end determines that the first locked AM is unlocked, the receiving end re-AM locks the data sequence B1 (that is, re-executes the AM locking process), and the receiving end performs AM monitoring on the data sequence B1 based on the re-locked AM (that is, re-executes the AM monitoring process), thus forming a closed-loop process of AM locking-AM monitoring-AM locking. After the receiving end locks the AM in the data sequence B1, the receiving end determines the codeword boundary in the data sequence B1 according to the AM locked in the data sequence B1. Among them, the potential AM position is the position where the AM may appear. The potential AM position is the area in the data sequence B1 whose length is equal to the length of the AM. For example, if the target AM is in the b1th to (b1+1028)th bits, and the period of AM appearance is 4096*5440 bits, then the potential AM position is the (b1+4096*5440)th to [(b1+1028)+4096*5440]th bit, the (b1+2*4096*5440)th to [(b1+1028)+2*4096*5440]th bit, ..., 1028 is the length of the AM. For another example, if the target AM is in bits b1 to (b1+1028), and the period of AM occurrence is 2*4096*5440 bits, then the potential AM positions are bits (b1+2*4096*5440) to [(b1+1028)+2*4096*5440], bits (b1+2*2*4096*5440) to [(b1+1028)+2*2*4096*5440], ... After the receiving end finds the codeword boundary in the data sequence B1, the receiving end determines the codeword in the data sequence B1 (e.g., the above-mentioned CW) according to the codeword boundary in the data sequence B1 and performs FEC decoding on the codeword in the data sequence B1.In the codeword synchronization scheme mentioned in the 200 / 400GE standard defined in the IEEE802.3bs project, the receiving end continuously monitors the data sequence B1 for uncorrectable codewords during the process of FEC decoding the data sequence B1. If the number of uncorrectable codewords (i.e., uncorrectable codewords) that appear continuously in the data sequence B1 reaches a preset number, or the proportion of uncorrectable codewords that appear continuously in the data sequence B1 reaches a preset ratio, the receiving end considers that the currently locked AM is out of lock, and the receiving end re-AM-locks the data sequence B1, the receiving end performs AM monitoring on the data sequence B1 based on the re-locked AM, and the receiving end re-determines the codeword boundary in the data sequence B1 based on the re-locked AM, and performs FEC decoding on the data sequence B1 based on the re-determined codeword boundary.

[0091] According to the above description, whether it is the above codeword synchronization scheme mentioned in the IEEE802.3dj standard discussion or the above codeword synchronization scheme mentioned in the 200 / 400GE standard defined by the IEEE802.3bs project, it is necessary to use the additional data inserted in the data sequence (such as FS in the IEEE802.3dj standard discussion, AM in the 200 / 400GE standard defined by the IEEE802.3bs project) to find the codeword boundary in the data sequence. According to the above description, the process of the receiving end finding (or identifying) the codeword boundary in the data sequence is called codeword synchronization (or frame synchronization). In the embodiment of the present application, the synchronization scheme that uses additional data such as FS, AM, etc. inserted in the data sequence to find or identify the codeword boundary in the data sequence is called a non-self-synchronization scheme. Therefore, the above codeword synchronization scheme mentioned in the IEEE802.3dj standard discussion and the above codeword synchronization scheme mentioned in the 200 / 400GE standard defined by the IEEE802.3bs project are both non-self-synchronization schemes. Since the non-self-synchronization scheme needs to use additional data inserted in the data sequence to find the codeword boundary in the data sequence, the accuracy of finding the codeword boundary in the data sequence is low, the time consumption is long, the efficiency is low, and the reliability is low.

[0092] Specifically, in the above codeword synchronization scheme mentioned in the discussion of the IEEE802.3dj standard, FS locking and FS monitoring are both performed based on the data sequence before decoding, that is, the receiving end searches for FS in the data sequence before decoding, and then searches for the codeword boundary based on the found FS. Since code errors are inevitable in the process of transmitting the data sequence from the transmitting end to the receiving end, code errors are inevitable in the data sequence before decoding, and the code error rate of the data sequence before decoding may be high, for example, the bit error rate (bit error ratio, BER) of the data sequence before decoding is high, which easily leads to an increase in the time spent by the receiving end to find FS, and even causes the receiving end to be unable to find the real FS, thereby causing the efficiency, stability and reliability of the receiving end to find the codeword boundary to be low. For example, code errors in the FS in the data sequence A2 easily lead to the receiving end being unable to find the real FS during the FS locking process, thereby missing the real FS, resulting in a longer time spent in the FS locking process and an increased probability of the receiving end locking the FS incorrectly. For another example, the bit error in the FS in the data sequence A2 can easily cause the receiving end to fail to verify the originally correct FS position during the FS monitoring process, which in turn requires re-locking and re-monitoring the FS. The bit error in the data sequence A2 can easily cause the receiving end to repeatedly perform FS locking and FS monitoring on the data sequence A2, affecting the receiving end's search for codeword boundaries, and further affecting the receiving end's subsequent processing of the data sequence, as well as affecting the transmission efficiency of the communication system.

[0093] Specifically, in the codeword synchronization scheme mentioned in the 200 / 400GE standard defined in the IEEE802.3bs project, AM locking and AM monitoring are both performed based on the data sequence before decoding, that is, the receiving end searches for AM in the data sequence before decoding, and then searches for the codeword boundary based on the found AM. Since there are inevitably bit errors in the data sequence before decoding, and the bit error rate of the data sequence before decoding may be high, this increases the time spent by the receiving end in searching for AM, and even causes the receiving end to be unable to find the real AM, which in turn results in low efficiency, stability, and reliability in searching for codeword boundaries. In addition, the codeword synchronization scheme mentioned in the 200 / 400GE standard requires the addition of additional verification logic (such as additional hardware circuits) for non-error-correctable codeword monitoring, which makes the implementation process complex and the implementation cost high.

[0094] In addition to the above two codeword synchronization schemes, a self-synchronization (self-sync) scheme can also be used to find the codeword boundary in the data sequence. The receiving end finds a preset sequence (such as FS) in the data sequence based on the codeword boundary found in the data sequence using the self-synchronization scheme, thereby finding a filling sequence including the preset sequence and deleting the filling sequence. And, the receiving end determines the codeword in the data sequence based on the codeword boundary found in the data sequence, and then performs codeword decoding on the data sequence.

[0095] Among them, self-synchronization refers to the process in which the receiving end searches for or identifies the codeword boundary in the data sequence according to the intrinsic feature or characteristic of the data sequence. In the self-synchronization scheme, the receiving end does not need to use additional data such as FS, AM, etc. inserted in the data sequence to search for or identify the codeword boundary in the data sequence. In one embodiment, after the receiving end receives the data sequence, the receiving end attempts to divide the data sequence according to the length of the codeword in the data sequence known to the receiving end (for example, 128 bits), and decodes the test data block obtained by the division, wherein the length of the test data block is the length of the codeword, and the receiving end determines whether the division position of the data sequence is a codeword boundary according to the decoding result of the test data block. It should be noted that, since the receiving end attempts to divide the data sequence to obtain a test data block whose length is equal to the length of the codeword, the test data block obtained by the receiving end may be a real codeword or not. For example, when the division position is exactly the codeword boundary, the test data block obtained by the division is a real codeword, and when the division position is not the codeword boundary, the test data block obtained by the division is not a real codeword. Since the length of the test data block obtained by the division is equal to the length of the codeword, for simplicity, the test data block obtained by the division is described as a "codeword" here. For example, the receiving end divides the data sequence into multiple codewords according to the codeword length known to the receiving end (that is, the length of the codeword in the data sequence), and the receiving end decodes the multiple codewords; the receiving end determines the number of uncorrectable codewords in the multiple codewords according to the decoding result; if the number of uncorrectable codewords in the multiple codewords does not reach a preset number, or the proportion of the number of uncorrectable codewords in the multiple codewords (for example, the ratio of the number of uncorrectable codewords in the multiple codewords to the number of the multiple codewords) does not reach a preset ratio, the receiving end determines that the codeword division of the data sequence is The division position is a codeword boundary, that is, the receiving end has found a codeword boundary in the data sequence; if the number of uncorrectable codewords in the multiple codewords reaches a preset number, or the proportion of the number of uncorrectable codewords in the multiple codewords reaches a preset ratio, the receiving end determines that the division position for codeword division of the data sequence is not a codeword boundary, and the receiving end re-codes the data sequence according to the codeword length known to the receiving end, decodes the re-divided codewords, and determines whether the division position for re-codeword division of the data sequence is a codeword boundary according to the decoding result. Repeat this process until a codeword boundary is found.In addition, the self-synchronization scheme is only described here as an example. For the specific implementation of the self-synchronization scheme, please refer to the patent application document "Codeword Synchronization Method, Receiver, Network Device and Network System" with publication number CN113517949A, and the reference standard document "InnerCodeword Self-sync Proposal" (address: https: / / www.ieee802.org / 3 / dj / public / 23_07 / he_3dj_03b_2307.pdf). The entire contents of them are incorporated herein by reference, as if all statements are made. This article does not go into details about the self-synchronization scheme.

[0096] Specifically, in the self-synchronization scheme, after receiving the data sequence, the receiving end uses a self-synchronization method to find the codeword boundary in the data sequence. After finding the codeword boundary in the data sequence, the receiving end locks the codeword boundary in the data sequence. The receiving end searches for a preset sequence (such as FS) in the data sequence based on the locked codeword boundary. Specifically, the receiving end first performs a preset sequence lock on the data sequence based on the locked codeword boundary, and then performs a preset sequence monitoring on the data sequence based on the locked codeword boundary and the locked preset sequence. The receiving end can find the preset sequence that appears periodically in the data sequence by performing preset sequence locking and preset sequence monitoring on the data sequence, and the receiving end can delete the padding sequence including these preset sequences in the data sequence. The receiving end also determines the codeword in the data sequence based on the locked codeword boundary in the data sequence, and decodes the codeword in the data sequence. After the receiving end locks the codeword boundary in the data sequence, it also monitors the codeword boundary of the data sequence to determine whether the locked codeword boundary is unlocked. In the case that the locked codeword boundary is unlocked, the receiving end uses a self-synchronization method to re-search for the codeword boundary in the data sequence, and re-searches for the preset sequence in the data sequence based on the re-found codeword boundary, and so on.

[0097] Based on the description of the above self-synchronization scheme, it can be known that the self-synchronization scheme can find the codeword boundary in the data sequence without the help of additional data inserted in the data sequence. Therefore, the process of finding the codeword boundary will not be affected by these additional data, and the accuracy of finding the codeword boundary is high, the time consumption is short, the efficiency is high, and the reliability is high. However, if the receiving end still searches for the preset sequence in the data sequence before decoding, the error in the data sequence before decoding is likely to increase the time consumption of the receiving end to find the preset sequence, thereby affecting the subsequent processing process of the receiving end on the data sequence. For example, the preset sequence is FS, and the error in the FS in the data sequence before decoding is likely to cause the receiving end to be unable to find the real FS, and increase the probability of finding a non-real FS, and the reliability of the FS found by the receiving end is greatly reduced. For another example, the error in the FS in the data sequence before decoding is likely to cause the receiving end to fail to verify the originally correct FS position during the FS monitoring process, which increases the time consumption of the receiving end to find the real FS and reduces the efficiency of finding the FS in the data sequence.

[0098] The embodiment of the present application provides a method and device for processing data, and a communication system. These methods, devices, and communication systems are based on the same inventive concept. In the method, after the receiving end obtains a data sequence including multiple FEC codewords, the receiving end performs FEC decoding on at least one FEC codeword in the data sequence to obtain at least one decoded codeword, and the receiving end finds a preset sequence in the at least one decoded codeword, for example, the preset sequence is the FS mentioned in the discussion of the IEEE802.3dj standard, or the preset sequence is in the AM mentioned in the 200 / 400GE standard defined in the IEEE802.3bs project. In the process of performing FEC decoding on the at least one FEC codeword in the data sequence, the receiving end can perform error detection and error correction on the at least one FEC codeword, and most of the errors are corrected during the FEC decoding process. Therefore, the error rate of the at least one decoded codeword obtained by FEC decoding is low or even there may be no error, which can reduce the efficiency of the receiving end in finding the preset sequence due to the error, and the time consumption of the receiving end in finding the preset sequence in the at least one decoded codeword is short, and the efficiency, accuracy, and reliability are all high, which can ensure the transmission efficiency and reliability of the communication system. Since most of the bit errors are corrected during the FEC decoding process, the mean time to lock (MTTL) of the preset sequence (such as FS) can be greatly reduced, and the mean time to false-unlock (MTTFU) of the preset sequence (such as FS) can be greatly improved. MTTL is the average duration of the preset sequence locking process, and MTTL is the duration determined based on the locking probability. For example, a preset sequence locking process is performed p times (p is a positive integer) on a certain data sequence, and the duration of most of the locking processes in these p locking processes is the first duration (for example, the number of locking processes with a duration of the first duration in these p locking processes is greater than the first number), then the MTTL of the data sequence is the first duration. MTTFU is the average duration of the preset sequence being unlocked during the preset sequence monitoring process (that is, the duration from the start of the preset sequence monitoring to the determination that the preset sequence is unlocked). MTTFU is a duration determined based on the locking probability. For example, a preset sequence monitoring process is performed q times (q is a positive integer) on a certain data sequence. During most of the locking processes during these q monitoring processes, the duration of the preset sequence being unlocked is the second duration (for example, the number of monitoring processes during which the duration of the lock loss during these q monitoring processes is greater than the second number), then the MTTFU of the data sequence is the second duration. In addition, compared to the codeword synchronization scheme mentioned in the 200 / 400GE standard defined in the IEEE802.3bs project, the technical solution of the embodiment of the present application can shorten the time taken by the receiving end to search for the preset sequence without adding additional verification logic (such as additional hardware circuits), thereby improving the efficiency, accuracy and reliability of the receiving end in searching for the preset sequence. The implementation process of the embodiment of the present application is simple and the implementation cost is low.

[0099] In an embodiment of the present application, the receiving end includes a host chip and an optical module, the optical module includes a chip, and the method of the embodiment of the present application is performed by the host chip in the receiving end, the optical module in the receiving end, or the chip in the optical module in the receiving end. The receiving end obtains a data sequence including a plurality of FEC codewords, the receiving end performs FEC decoding on at least one FEC codeword in the data sequence to obtain at least one decoded codeword, and the receiving end searches for a preset sequence in the at least one decoded codeword. The receiving end may be a forwarding device, a user terminal device, or a server device, and the receiving end may include an Ethernet interface. The data sequence is obtained by the receiving end according to an Ethernet signal received from the Ethernet interface of the receiving end, and the Ethernet signal is sent by the transmitting end to the receiving end, the transmitting end may be a forwarding device, a user terminal device, or a server device, and the transmitting end may also include an Ethernet interface. The forwarding device may be a router or a switch. The Ethernet signal may be a Terabit Ethernet (TbE) signal. Terabit Ethernet is a high-speed Ethernet. Terabit Ethernet refers to Ethernet with a speed exceeding 100 Gbits per second (100Gbit / s). The speed of Terabit Ethernet can reach or even exceed 200Gbit / s or 400Gbit / s, so Terabit Ethernet can achieve high-speed data transmission.

[0100] The technical solution of the embodiment of the present application can be applied to cascade FEC coding scenarios and non-cascade FEC coding scenarios. In the cascade FEC coding scenario, the sending end performs at least two levels of FEC coding on the data to be sent and then sends it to the receiving end, and the receiving end performs at least two levels of FEC decoding on the received data to obtain the original data. For example, the sending end performs the first FEC coding and the second FEC coding on the data to be sent in sequence, and the receiving end performs the second FEC decoding and the first FEC decoding on the received data in sequence, the second FEC decoding corresponds to the second FEC coding, and the first FEC decoding corresponds to the first FEC coding. The first FEC coding and the second FEC coding are respectively a first-level (or a layer) FEC coding, and the first FEC decoding and the second FEC decoding are respectively a first-level FEC decoding. In some embodiments or technical manuscripts, the first FEC coding is also described as an outer layer FEC coding or an outer code coding, the second FEC coding is also described as an inner layer FEC coding or an inner code coding, the second FEC decoding is also described as an inner layer FEC decoding or an inner code decoding, and the first FEC decoding is also described as an outer layer FEC decoding or an outer code decoding. In a non-cascaded FEC encoding scenario, the sender performs a first-level (or called a layer) FEC encoding on the data to be sent and then sends it to the receiver, and the receiver performs a first-level FEC encoding on the received data to obtain the original data. Non-cascaded FEC encoding is also called single-level FEC encoding, single-layer FEC encoding, first-level FEC encoding or a layer of FEC encoding. Among them, the FEC code used by the receiver to perform the corresponding FEC decoding on the received data is the same as the FEC code used by the sender to perform FEC encoding on the data. For example, in a cascaded FEC encoding scenario, the FEC code used by the receiver to perform the first FEC decoding on the received data is the same as the FEC code used by the sender to perform the first FEC encoding on the data, and the FEC code used by the receiver to perform the second FEC decoding on the received data is the same as the FEC code used by the sender to perform the second FEC encoding on the data. In an embodiment of the present application, the FEC code may be a Reed-Solomon code (RS code), a Bose-Chaudhuri-Hocquenghem code (BCH code), an extended BCH code, a low-density parity-check code (LDPC code), a Hamming code, an extended Hamming code, a Golay code, a Reed-Muller code, a staircase code, a turbo code or a turbo product code (TPC), etc.For example, the transmitting end first uses the RS (544, 514) code to perform the first FEC encoding on the data to be sent, and then uses the Hamming (128, 120) code or the Hamming (68, 60) code to perform the second FEC encoding on the data, and then the transmitting end sends the data sequence obtained by the first FEC encoding and the second FEC encoding to the receiving end; after the receiving end receives the data sequence, the receiving end first uses the Hamming (128, 120) code or the Hamming (68, 60) code to perform the second FEC decoding on the data sequence, and then uses the RS (544, 514) code to perform the first FEC decoding on the data sequence. In the embodiment of the present application, when the transmitting end inserts a preset sequence into the data, the receiving end also needs to find the preset sequence in the received data sequence and delete the padding sequence including the preset sequence. Before deleting the padding sequence, the receiving end can also extract the information carried by the padding sequence for use by the physical layer. Among them, the filling sequence is the filling sequence in the IEEE802.3dj standard, and the preset sequence is the FS mentioned in the discussion of the IEEE802.3dj standard; or, the filling sequence is the AM in the 200 / 400GE standard defined by the IEEE802.3bs project, and the preset sequence is in the AM, for example, the preset sequence is the AM or a fixed part in the AM, and the embodiment of the present application does not limit this.

[0101] The following describes the application scenarios of the technical solutions provided by the embodiments of the present application in conjunction with the accompanying drawings.

[0102] The application scenario of the embodiment of the present application includes a transmitting end and a receiving end, and the transmitting end is connected to the receiving end in communication, for example, the transmitting end and the receiving end are connected via an optical fiber. Specifically, the transmitting end and the receiving end may both include an Ethernet interface, and the Ethernet interface of the transmitting end is connected to the Ethernet interface of the receiving end via an optical fiber. Among them, the transmitting end includes a host chip and / or an optical module, and the receiving end includes a host chip and / or an optical module. For example, the transmitting end and the receiving end both include a host chip and an optical module, and in the transmitting end and / or the receiving end, the host chip and the optical module can be connected via an interface such as AUI. For ease of description, the host chip in the transmitting end is referred to as host chip 1, the optical module in the transmitting end is referred to as optical module 1, the host chip in the receiving end is referred to as host chip 2, and the optical module in the receiving end is referred to as optical module 2.

[0103] Please refer to Figure 2, which shows a schematic diagram of an application scenario provided by an embodiment of the present application. The application scenario is a non-cascaded FEC encoding scenario, in which the transmitting end includes a main chip 1 and / or an optical module 1, and the receiving end includes a main chip 2 and / or an optical module 2. When the transmitting end sends a data sequence C0 to the receiving end, the main chip 1 or the optical module 1 performs FEC encoding on the data sequence C0 and periodically inserts a filling sequence including a preset sequence into the data sequence C0 to obtain a data sequence C1, and the data sequence C1 includes multiple FEC codewords obtained through FEC encoding (the filling sequence has also been FEC encoded, and the filling sequence may include at least one FEC codeword obtained through FEC encoding, and the FEC codewords in the filling sequence may be called filling codewords), and the transmitting end sends the data sequence C1 to the receiving end. For example, Figure 3 A schematic diagram of a data sequence C1 is shown. Figure 3 Taking the preset sequence FS as an example, the data sequence C1 includes multiple FEC codewords and periodically appearing filling sequences, each filling sequence includes FS, the length of the filling sequence is 3 times the length of the FEC codeword, the length of FS is 48 bits, the filling sequence appears in the data sequence C1 for a period of 3264 FEC codewords (3264*128 bits), and the FS appears in the data sequence C1 for a period of 3264+3=3267 FEC codewords (3267*128 bits). For another example, Figure 4 A schematic diagram of another data sequence C1 is shown. Figure 4 Taking the preset sequence FS as an example, the data sequence C1 includes multiple FEC codewords and periodically appearing filling sequences, each filling sequence includes FS, the length of the filling sequence is 8 times the length of the FEC codeword, the length of FS is 48 bits, the filling sequence appears in the data sequence C1 for a period of 8704 FEC codewords (8704*128 bits), and the FS appears in the data sequence C1 for a period of 8704+8=8712 FEC codewords (8712*128 bits). For another example, Figure 5 A schematic diagram of another data sequence C1 is shown. Figure 5 Taking the filling sequence as AM as an example, the data sequence C1 includes multiple RS code words and periodically appearing AMs, each AM includes a preset sequence, the length of AM is 1028 bits, and the period of AM appearing in the data sequence C1 is 4096 RS code words (4096*5440 bits). Figure 6 A schematic diagram of yet another data sequence C1 is shown. Figure 6 Taking the filling sequence as AM as an example, the data sequence C1 includes multiple RS code words and periodically appearing AMs, each AM includes a preset sequence, the length of AM is 2056 bits, and the period of AM appearing in the data sequence C1 is 8192 RS code words (8192*5440 bits). Figure 5 and Figure 6 The data sequence C1 shown is a data sequence obtained by RS encoding. RS encoding is also a kind of FEC encoding. Therefore Figure 5 and Figure 6 The RS codeword in the data sequence C1 shown is also a FEC codeword. After the receiving end receives the data sequence C1, the main chip 2 or the optical module 2 performs codeword synchronization on the data sequence C1 (for example, performs codeword synchronization on the data sequence C1 in a self-synchronization manner) to determine the FEC codeword boundary in the data sequence C1. The main chip 2 or the optical module 2 determines the FEC codeword in the data sequence C1 according to the FEC codeword boundary in the data sequence C1 (for Figure 5 and Figure 6 In the data sequence C1 shown, the FEC codeword boundary is the RS codeword boundary, and the FEC codeword is the RS codeword), the main chip 2 or the optical module 2 performs FEC decoding on at least one FEC codeword in the data sequence C1 to obtain at least one decoded codeword, the main chip 2 or the optical module 2 searches for a preset sequence in the at least one decoded codeword, and the main chip 2 or the optical module 2 deletes the padding sequence including the preset sequence in the data sequence C1. The main chip 2 or the optical module 2 performs FEC decoding on all FEC codewords in the data sequence C1 and deletes the padding sequence in the data sequence C1 to obtain the data sequence C0.

[0104] Please refer to Figure 7 , which shows a schematic diagram of another application scenario provided by an embodiment of the present application. The application scenario is a cascade FEC encoding scenario, in which the transmitting end includes a main chip 1 and an optical module 1, and the receiving end includes a main chip 2 and an optical module 2. When the transmitting end sends the data sequence D0 to the receiving end, the main chip 1 performs the first FEC encoding on the data sequence D0 to obtain the data sequence D1, and the data sequence D1 includes multiple FEC codewords obtained through the first FEC encoding (for the convenience of description, the FEC codeword obtained through the first FEC encoding is referred to as FEC codeword 1). The main chip 1 sends the data sequence D1 to the optical module 1, and the optical module 1 performs the second FEC encoding on the data sequence D1 and periodically inserts a padding sequence including a preset sequence into the data sequence D1 to obtain the data sequence D2, and the data sequence D2 includes multiple FEC codewords obtained through the second FEC encoding (for the convenience of description, the FEC codeword obtained through the second FEC encoding is referred to as FEC codeword 2, and the padding sequence in the data sequence D2 has also been subjected to the second FEC encoding, and the padding sequence may include at least one FEC codeword 2 obtained through the second FEC encoding). The distribution of the FEC codewords and padding sequences in the data sequence D2 can be referred to. Figures 3 to 6The data sequence C1 shown, the transmitting end sends the data sequence D2 to the receiving end. After the receiving end receives the data sequence D2, the optical module 2 performs a second codeword synchronization on the data sequence D2 (for example, performs a second codeword synchronization on the data sequence D2 in a self-synchronization manner) to determine the FEC codeword boundary in the data sequence D2, the optical module 2 determines multiple FEC codewords 2 in the data sequence D2 according to the FEC codeword boundary in the data sequence D2, the optical module 2 performs a second FEC decoding on at least one FEC codeword 2 in the data sequence D2 to obtain at least one decoded codeword, the optical module 2 searches for a preset sequence in the at least one decoded codeword, and the optical module 2 deletes the padding sequence in the data sequence D2 including the preset sequence found. The optical module 2 performs a second FEC decoding on all FEC codewords 2 in the data sequence D2 and deletes the padding sequence in the data sequence D2 to obtain the data sequence D1. The optical module 2 sends the data sequence D1 to the main chip 2, and the main chip 2 performs a first codeword synchronization on the data sequence D1 (for example, the first codeword synchronization is performed by self-synchronization) to determine the FEC codeword boundary in the data sequence D1. The main chip 2 determines multiple FEC codewords 1 in the data sequence D1 according to the FEC codeword boundary in the data sequence D1, and the main chip 2 performs a first FEC decoding on the multiple FEC codewords 1 to obtain multiple decoded codewords, and the multiple decoded codewords constitute the data sequence D0.

[0105] Please refer to Figure 8 , which shows a schematic diagram of another application scenario provided by an embodiment of the present application. The application scenario is a cascade FEC encoding scenario, in which the transmitting end includes a main chip 1 and an optical module 1, and the receiving end includes a main chip 2 and an optical module 2. When the transmitting end sends a data sequence E0 to the receiving end, the main chip 1 performs a first FEC encoding on the data sequence E0 and periodically inserts a padding sequence including a preset sequence into the data sequence E0 to obtain a data sequence E1, and the data sequence E1 includes multiple FEC codewords obtained through the first FEC encoding (for ease of description, the FEC codeword obtained through the first FEC encoding is referred to as FEC codeword 1, the padding sequence inserted by the main chip 1 into the data sequence E0 is referred to as padding sequence 1, the preset sequence included in the padding sequence 1 is referred to as preset sequence 1, the padding sequence 1 has also undergone the first FEC encoding, and the padding sequence 1 may include at least one FEC codeword 1 obtained through the first FEC encoding), and the distribution of the FEC codewords and padding sequences in the data sequence E1 can be referred to. Figures 3 to 6The data sequence C1 shown, the main chip 1 sends the data sequence E1 to the optical module 1. The optical module 1 performs the second FEC encoding on the data sequence E1 and periodically inserts a filling sequence including a preset sequence into the data sequence E1 to obtain a data sequence E2, and the data sequence E2 includes a plurality of FEC codewords obtained through the second FEC encoding (for the convenience of description, the FEC codeword obtained through the second FEC encoding is referred to as FEC codeword 2, the filling sequence inserted by the optical module 1 into the data sequence E1 is referred to as filling sequence 2, the preset sequence included in the filling sequence 2 is referred to as preset sequence 2, the filling sequence 2 is also subjected to the second FEC encoding, and the filling sequence 2 may include at least one FEC codeword 2 obtained through the second FEC encoding), and the distribution of the FEC codewords and the filling sequence in the data sequence E2 can be referred to. Figures 3 to 6 As shown in the data sequence C1, the transmitting end sends the data sequence E2 to the receiving end. After the receiving end receives the data sequence E2, the optical module 2 performs a second codeword synchronization on the data sequence E2 (for example, performs a second codeword synchronization on the data sequence E2 in a self-synchronization manner) to determine the FEC codeword boundary in the data sequence E2, and the optical module 2 determines multiple FEC codewords 2 in the data sequence E2 according to the FEC codeword boundary in the data sequence E2. The optical module 2 performs a second FEC decoding on at least one FEC codeword 2 in the data sequence E2 to obtain at least one decoded codeword, and the optical module 2 searches for a preset sequence 2 in the at least one decoded codeword and deletes the padding sequence 2 in the data sequence E2 including the preset sequence 2. The optical module 2 performs a second FEC decoding on all FEC codewords 2 in the data sequence E2 and deletes the padding sequence 2 in the data sequence E2 to obtain the data sequence E1. The optical module 2 sends the data sequence E1 to the main chip 2, and the main chip 2 performs the first codeword synchronization on the data sequence E1 (for example, performs the first codeword synchronization on the data sequence E1 in a self-synchronization manner) to determine the FEC codeword boundary in the data sequence E1. The main chip 2 determines multiple FEC codewords 1 in the data sequence E1 according to the FEC codeword boundary in the data sequence E1. The main chip 2 performs the first FEC decoding on at least one FEC codeword 1 in the data sequence E1 to obtain at least one decoded codeword. The main chip 2 searches for the preset sequence 1 in the at least one decoded codeword and deletes the padding sequence 1 in the data sequence E1 including the preset sequence 1. The main chip 2 performs the first FEC decoding on all FEC codewords 1 in the data sequence E1 and deletes the padding sequence 1 in the data sequence E1 to obtain the data sequence E0.

[0106] Please refer to Fig. 9, which shows a schematic diagram of another application scenario provided by an embodiment of the present application. The application scenario is a cascade FEC encoding scenario, in which the transmitting end includes a main chip 1 and an optical module 1, and the receiving end includes a main chip 2 and an optical module 2. When the transmitting end sends a data sequence F0 to the receiving end, the main chip 1 performs a first FEC encoding on the data sequence F0 and periodically inserts a padding sequence including a preset sequence into the data sequence F0 to obtain a data sequence F1, and the data sequence F1 includes multiple FEC codewords obtained through the first FEC encoding (for ease of description, the FEC codeword obtained through the first FEC encoding is referred to as FEC codeword 1, and the padding sequence in the data sequence F1 has also undergone the first FEC encoding, and the padding sequence may include at least one FEC codeword 1 obtained through the first FEC encoding). The distribution of FEC codewords and padding sequences in the data sequence F1 can be referred to. Figures 3 to 6 As shown in the data sequence C1, the main chip 1 sends the data sequence F1 to the optical module 1. The optical module 1 performs the second FEC encoding on the data sequence F1 to obtain the data sequence F2, and the data sequence F2 includes multiple FEC codewords obtained through the second FEC encoding (for the convenience of description, the FEC codewords obtained through the second FEC encoding are referred to as FEC codewords 2), and the transmitting end sends the data sequence F2 to the receiving end. After the receiving end receives the data sequence F2, the optical module 2 performs the second codeword synchronization on the data sequence F2 (for example, the second codeword synchronization is performed on the data sequence F2 in a self-synchronization manner) to determine the FEC codeword boundary in the data sequence F2, and the optical module 2 determines the multiple FEC codewords 2 in the data sequence F2 according to the FEC codeword boundary in the data sequence F2, and the optical module 2 performs the second FEC decoding on the multiple FEC codewords 2 to obtain multiple decoded codewords, and the multiple decoded codewords constitute the data sequence F1. The optical module 2 sends the data sequence F1 to the main chip 2, the main chip 2 performs the first codeword synchronization on the data sequence F1 (for example, performs the first codeword synchronization on the data sequence F1 in a self-synchronization manner) to determine the FEC codeword boundary in the data sequence F1, the main chip 2 determines multiple FEC codewords 1 in the data sequence F1 according to the FEC codeword boundary in the data sequence F1, the main chip 2 performs the first FEC decoding on at least one FEC codeword 1 in the data sequence F1 to obtain at least one decoded codeword, the main chip 2 searches for a preset sequence in the at least one decoded codeword, and the main chip 2 deletes the padding sequence including the preset sequence in the data sequence F1. The main chip 2 performs the first FEC decoding on all FEC codewords 1 in the data sequence F1 and deletes the padding sequence in the data sequence F1 to obtain the data sequence F0.

[0107] Please refer to Fig.10, which shows a schematic diagram of another application scenario provided by an embodiment of the present application. The application scenario is a cascade FEC encoding scenario, in which the transmitting end includes a main chip 1 and / or an optical module 1, and the receiving end includes a main chip 2 and / or an optical module 2. When the transmitting end sends a data sequence G0 to the receiving end, first, the main chip 1 or the optical module 1 performs a first FEC encoding on the data sequence G0 to obtain a data sequence G1, and the data sequence G1 includes a plurality of FEC codewords obtained through the first FEC encoding (for ease of description, the FEC codeword obtained through the first FEC encoding is referred to as FEC codeword 1). Then, the main chip 1 or the optical module 1 performs a second FEC encoding on the data sequence G1 and periodically inserts a filling sequence including a preset sequence into the data sequence G1 to obtain a data sequence G2, wherein the data sequence G2 includes a plurality of FEC codewords obtained through the second FEC encoding (for ease of description, the FEC codeword obtained through the second FEC encoding is referred to as FEC codeword 2, and the filling sequence in the data sequence G2 is also subjected to the second FEC encoding, and the filling sequence may include at least one FEC codeword 2 obtained through the second FEC encoding). The distribution of the FEC codewords and the filling sequence in the data sequence G2 can be referred to. Figures 3 to 6 The data sequence C1 shown. Finally, the transmitting end sends the data sequence G2 to the receiving end. After the receiving end receives the data sequence G2, the main chip 2 or the optical module 2 performs a second codeword synchronization on the data sequence G2 (for example, the data sequence G2 is synchronized with the second codeword in a self-synchronization manner) to determine the FEC codeword boundary in the data sequence G2, the main chip 2 or the optical module 2 determines multiple FEC codewords 2 in the data sequence G2 according to the FEC codeword boundary in the data sequence G2, the main chip 2 or the optical module 2 performs a second FEC decoding on at least one FEC codeword 2 in the data sequence G2 to obtain at least one decoded codeword, the main chip 2 or the optical module 2 searches for a preset sequence in the at least one decoded codeword and deletes the padding sequence in the data sequence G2 including the preset sequence. The main chip 2 or the optical module 2 performs a second FEC decoding on all FEC codewords 2 in the data sequence G2 and deletes the padding sequence in the data sequence G2 to obtain the data sequence G1. The main chip 2 or optical module 2 performs a first codeword synchronization on the data sequence G1 (for example, a self-synchronization method is used to perform the first codeword synchronization) to determine the FEC codeword boundary in the data sequence G1. The main chip 2 or optical module 2 determines multiple FEC codewords 1 in the data sequence G1 according to the FEC codeword boundary in the data sequence G1. The main chip 2 or optical module 2 performs a first FEC decoding on the multiple FEC codewords 1 to obtain multiple decoded codewords, and the multiple decoded codewords constitute the data sequence G0.

[0108] It should be noted that Figure 2 , Figures 7 to 10The filling sequence involved in the application scenario introduction shown may be a filling sequence in the IEEE802.3dj standard, and the preset sequence may be the FS mentioned in the discussion of the IEEE802.3dj standard. Alternatively, the filling sequence is the AM in the 200 / 400GE standard defined in the IEEE802.3bs project, and the preset sequence is in the AM, for example, the preset sequence is the AM or a fixed part in the AM. In addition, the above-mentioned FEC encoding can be Reed-Solomon (RS) encoding, Bose-Chaudhuri-Hocquenghem (BCH) encoding, low-density parity-check (LDPC) encoding, Hamming encoding, Golay encoding, Reed-Muller encoding, staircase encoding, turbo encoding or turbo product code (TPC) encoding, and correspondingly, the above-mentioned FEC decoding can be Reed-Solomon (RS) decoding, Bose-Chaudhuri-Hocquenghem (BCH) decoding, low-density parity-check (LDPC) encoding, Hamming encoding, Golay encoding, Reed-Muller encoding, staircase encoding, turbo encoding or turbo product code (TPC) encoding. parity-check, LDPC) decoding, Hamming decoding, Golay decoding, Reed-Muller decoding, staircase decoding, turbo decoding or turbo product code (TPC) decoding. The FEC code used for FEC decoding is the same as the FEC code used for the corresponding FEC encoding. For example, for Figures 7 to 10 In the application scenario shown, the FEC code used in the first FEC encoding is the same as the FEC code used in the first FEC decoding, and the FEC code used in the second FEC encoding is the same as the FEC code used in the second FEC decoding. For example, the FEC code used in the first FEC encoding and the FEC code used in the first FEC decoding are both RS (544, 514) codes, and the FEC code used in the second FEC encoding and the FEC code used in the second FEC decoding are both Hamming (128, 120) codes or Hamming (68, 60) codes. Figure 2 In the application scenario shown, the FEC code used in FEC encoding and the FEC code used in FEC decoding are the same, for example, the FEC code used in FEC encoding and the FEC code used in FEC decoding are both RS (544, 514) code, Hamming (128, 120) code or Hamming (68, 60) code.

[0109] In addition, for a data sequence that needs to be FEC encoded and a padding sequence inserted at the transmitting end, the embodiment of the present application does not limit the order in which the transmitting end performs FEC encoding on the data sequence and inserts the padding sequence into the data sequence. For a data sequence that needs to be FEC decoded and a padding sequence deleted at the receiving end, the embodiment of the present application does not limit the order in which the receiving end performs FEC decoding on the data sequence and deletes the padding sequence from the data sequence, and the process of the receiving end performing FEC decoding on the data sequence and the process of the receiving end deleting the padding sequence from the data sequence can be performed alternately. For example, refer to Figure 2 And its related description, the embodiment of the present application does not limit the order in which the main chip 1 or optical module 1 performs FEC encoding on the data sequence C0 and inserts the filling sequence into the data sequence C0. The main chip 1 or optical module 1 can first perform FEC encoding on the data sequence C0 and then insert the filling sequence into the data sequence C0, or can first insert the filling sequence into the data sequence C0 and then perform FEC encoding on the data sequence C0. In an optional implementation, the main chip 1 or optical module 1 first inserts the filling sequence into the data sequence C0 and then performs FEC encoding on the data sequence C0, so that the filling sequence is also FEC encoded. In an optional implementation, the main chip 1 or optical module 1 first performs FEC encoding on the data sequence C0 and then inserts the filling sequence into the data sequence C0. The main chip 1 or optical module 1 can also perform FEC encoding on the inserted filling sequence. Continue to refer to Figure 2 And the related description, the embodiment of the present application does not limit the main chip 2 or optical module 2 to perform FEC decoding on the data sequence C1 and delete the filling sequence of the preset sequence in the data sequence C1. The main chip 2 or optical module 2 can first perform FEC decoding on all FEC codewords in the data sequence C1, and then delete the filling sequence including the preset sequence in the data sequence C1, or perform FEC decoding on the FEC codewords in the data sequence C1 while deleting the filling sequence in the data sequence C1. For example, the main chip 2 or optical module 2 first performs FEC decoding on a part of the FEC codewords in the data sequence C1, and then deletes the filling sequence in this part of the FEC codewords, and then the main chip 2 or optical module 2 first performs FEC decoding on another part of the FEC codewords in the data sequence C1, and deletes the filling sequence in this other part of the FEC codewords, and so on.

[0110] The above description of the sender and the receiver is only exemplary. In some embodiments, the sender is also referred to as a sender device and the receiver is also referred to as a receiver device. Both the sender and the receiver can be forwarding devices, user terminal devices or server devices.

[0111] The above is an introduction to the application scenarios of the embodiments of the present application. The following is an introduction to the method embodiments of the present application.

[0112] Please refer to Fig.11 , which shows a flow chart of a method for processing data provided by an embodiment of the present application. The method is executed by a main chip in the receiving end, an optical module in the receiving end, or a chip in an optical module in the receiving end. For ease of description, the following description takes the method being executed by the receiving end as an example. It can be understood that the method is specifically executed by a main chip in the receiving end, an optical module in the receiving end, or a chip in an optical module in the receiving end. Fig.11 As shown, the method includes the following steps S1101 to S1103.

[0113] S1101. Obtain a data sequence X, where the data sequence X includes multiple FEC codewords.

[0114] The data sequence X is obtained according to an Ethernet signal received from an Ethernet interface of the receiving end. The Ethernet interface may be a Terabit Ethernet interface, and the Ethernet signal may be a Terabit Ethernet signal.

[0115] In one embodiment, the receiving end receives an Ethernet signal sent by the transmitting end through an Ethernet interface, the Ethernet signal carries a data sequence X, and the receiving end extracts the data sequence X from the Ethernet signal. In another embodiment, the Ethernet signal carries an interleaved sequence of the data sequence X, the receiving end extracts the interleaved sequence from the Ethernet signal, and the receiving end deinterleaves the interleaved sequence to obtain the data sequence X.

[0116] The data sequence X is obtained by the transmitter performing target FEC encoding on the initial data sequence, and the FEC codeword included in the data sequence X is the FEC codeword obtained by the target FEC encoding. The lengths of the multiple FEC codewords are equal, and the length of any FEC codeword in the multiple FEC codewords depends on the FEC code used by the transmitter to perform the target FEC encoding. For example, the lengths of the multiple FEC codewords are all 128 bits.

[0117] Among them, the data sequence X includes a preset sequence Z, the preset sequence Z appears periodically in the data sequence X, and the preset sequence Z is periodically inserted by the transmitter in the initial data sequence. For example, the data sequence X includes a filling sequence that appears periodically, and each filling sequence includes the preset sequence Z. Optionally, the filling sequence inserted periodically by the transmitter in the initial data sequence includes the preset sequence Z. The filling sequence described in the embodiment of the present application can be a filling sequence in the IEEE802.3dj standard or an AM in the 200 / 400GE standard defined by the IEEE802.3bs project. The preset sequence Z can be the FS mentioned in the discussion of the IEEE802.3dj standard, or the preset sequence Z in the AM in the 200 / 400GE standard defined by the IEEE802.3bs project. The preset sequence Z in the AM can be understood as the preset sequence Z is all or part of the AM, for example, the preset sequence Z is the AM, or the preset sequence Z is a fixed part of the AM known to both the transmitter and the receiver. The filling sequence in the data sequence X is also encoded by the target FEC. Optionally, the padding sequence is a padding sequence in the IEEE802.3dj standard, the length of the padding sequence is an integer multiple of the length of the FEC codeword in the data sequence X, and the padding sequence includes an integer number of the FEC codewords. In an embodiment of the present application, the periodic appearance of the preset sequence Z in the data sequence X may be that the preset sequence Z appears in the data sequence X according to a strict period, that is, the period at which the preset sequence Z appears in the data sequence X is a strict period, and different periods of the preset sequence Z are strictly equal. Alternatively, the periodic appearance of the preset sequence Z in the data sequence X may be that the preset sequence Z appears in the data sequence X according to a non-strict period, that is, the period at which the preset sequence Z appears in the data sequence X is a non-strict period, different non-strict periods of the preset sequence Z may not be equal, the difference between different non-strict periods is less than the preset difference, and the regularity of the appearance of the preset sequence Z is roughly periodic. The embodiment of the present application does not limit this.

[0118] Among them, the initial data sequence is the data sequence before the sender performs the target FEC encoding. In other words, the initial data sequence is the object of the sender to perform the target FEC encoding. The sender may first insert a padding sequence including a preset sequence Z into the initial data sequence, and then perform the target FEC encoding on the initial data sequence, or may first perform the target FEC encoding on the initial data sequence, and then insert the padding sequence including the preset sequence Z into the initial data sequence. The embodiment of the present application does not limit the order in which the sender performs the target FEC encoding on the initial data sequence and inserts the padding sequence into the initial data sequence. If the sender first inserts the padding sequence into the initial data sequence, the sender may perform the target FEC encoding on the padding sequence during the process of performing the target FEC encoding on the initial data sequence. If the sender first performs the target FEC encoding on the initial data sequence, the sender may also perform the target FEC encoding on the inserted padding sequence after inserting the padding sequence into the initial data sequence. In the embodiment of the present application, the initial data sequence may not be FEC encoded, or may be other FEC encoded, and the initial data sequence may be inserted with a padding sequence, or may not be inserted with a padding sequence. For example, in a non-concatenated FEC encoding scenario, the initial data sequence is not FEC encoded, and in a concatenated FEC encoding scenario, the initial data sequence may be FEC encoded in other ways, or may be inserted with a padding sequence. Figure 2 and its related description, Figure 2 The example shown is a non-concatenated FEC encoding scenario, where the initial data sequence is data sequence C0, data sequence X is data sequence C1, and the initial data sequence is not FEC encoded and no padding sequence is inserted. Figure 7 and its related description, Figure 7 The example shown is a cascade FEC encoding scenario, the initial data sequence is data sequence D1, data sequence X is data sequence D2, the initial data sequence has been encoded by the first FEC, the initial data sequence has no padding sequence inserted, and the target FEC encoding is the second FEC encoding. Figure 8 and its related description, Figure 8 The diagram shows a cascade FEC coding scenario, where the initial data sequence is data sequence E0, data sequence X is data sequence E1, the initial data sequence has not been FEC coded, and no padding sequence is inserted, and the target FEC coding is the first FEC coding; or, the initial data sequence is data sequence E1, data sequence X is data sequence E2, the initial data sequence has been FEC coded and padding sequence 1 is inserted, and the target FEC coding is the second FEC coding. In another example, referring to Fig. 9 and its related description, Fig. 9The example shown is a cascade FEC encoding scenario, the initial data sequence is the data sequence F0, the data sequence X is the data sequence F1, the initial data sequence is not FEC encoded, and no padding sequence is inserted, and the target FEC encoding is the first FEC encoding. Fig.10 and its related description, Fig.10 The diagram shows a cascade FEC coding scenario, where the initial data sequence is data sequence G1, data sequence X is data sequence G2, the initial data sequence has been subjected to the first FEC coding, no padding sequence is inserted into the initial data sequence, and the target FEC coding is the second FEC coding.

[0119] S1102. Perform FEC decoding on at least one FEC codeword in the data sequence X to obtain at least one decoded codeword Y.

[0120] This step and the FEC decoding of the FEC codewords in the data sequence X described later all refer to target FEC decoding of the FEC codewords in the data sequence X. The target FEC decoding is the FEC decoding corresponding to the target FEC encoding described in S1101. The FEC code used in the target FEC decoding is the same as the FEC code used in the target FEC encoding.

[0121] The at least one FEC codeword in the data sequence X may be all the FEC codewords in the data sequence X, or may be part of the FEC codewords in the data sequence X. The at least one decoded codeword Y corresponds one-to-one to the at least one FEC codeword. The at least one decoded codeword Y may be a decoded codeword obtained by performing target FEC decoding on all the FEC codewords in the data sequence X, or may be a decoded codeword obtained by performing target FEC decoding on part of the FEC codewords in the data sequence X. This embodiment of the present application does not limit this.

[0122] This article only describes the target FEC decoding of the FEC codewords in the data sequence X by the receiving end, and does not elaborate on the detailed decoding process. The implementation process of the target FEC decoding of any FEC codeword in the data sequence X by the receiving end can refer to the relevant technical documents of FEC decoding.

[0123] S1103. Find a preset sequence Z in the at least one decoded codeword Y.

[0124] The receiving end searches for the preset sequence Z in the at least one decoded codeword Y according to the preset sequence Z known to the receiving end, and the receiving end can find the preset sequence Z in the at least one decoded codeword Y. Optionally, the receiving end compares the preset sequence Z known to the receiving end with the at least one decoded codeword Y (for example, bit by bit comparison) to find the preset sequence Z in the at least one decoded codeword Y.

[0125] In one embodiment, the preset sequence Z includes multiple nibbles, that is, the length of each nibble is 4 bits. In the process of comparing the preset sequence Z known to the receiving end with any codeword Y in the at least one decoded codeword Y, if the number of nibbles in the any codeword Y that matches the multiple nibbles in the preset sequence Z reaches a set number, the receiving end determines that the any codeword Y matches the preset sequence Z, and the receiving end determines that the preset sequence Z is found in the any codeword Y. In an example, the length of the preset sequence Z is 48 bits, the preset sequence Z includes 12 nibbles, and the set number is 9, that is, if the number of nibbles in any codeword Y that matches the multiple nibbles in the preset sequence Z reaches 9, it is considered that the any codeword Y matches the preset sequence Z, and the receiving end determines that the preset sequence Z is found in the any codeword Y.

[0126] The at least one decoded codeword Y may be a decoded codeword obtained by the receiving end performing target FEC decoding on all FEC codewords in the data sequence X, or may be a decoded codeword obtained by the receiving end performing target FEC decoding on part of the FEC codewords in the data sequence X. Therefore, in combination with S1102 and S1103, it can be known that the receiving end may first perform target FEC decoding on all FEC codewords in the data sequence X, and then search for the preset sequence Z in all the decoded codewords Y; or the receiving end may perform target FEC decoding on the FEC codewords in the data sequence X while searching for the preset sequence Z in the decoded codewords Y. For example, the receiving end first performs target FEC decoding on part of the FEC codewords in the data sequence X and searches for the preset sequence Z in the decoded codewords of this part; then, the receiving end performs target FEC decoding on another part of the FEC codewords in the data sequence X and searches for the preset sequence Z in the decoded codewords of this part, and so on. Optionally, the receiving end groups the FEC codewords in the data sequence X to obtain multiple codeword groups, each of the multiple codeword groups includes at least one FEC codeword in the data sequence X, and the FEC codewords in any two of the multiple codeword groups do not overlap. The receiving end performs target FEC decoding on the FEC codewords in the data sequence X group by group. The receiving end can obtain a group of decoded codewords after decoding each FEC codeword in a codeword group. The receiving end searches for a preset sequence Z in the group of decoded codewords. This embodiment of the present application is not limited to this.

[0127] The implementation process of S1102 and S1103 is introduced in two embodiments below.

[0128] First embodiment: The receiving end performs target FEC decoding on all FEC codewords in the data sequence X, and the receiving end searches for a preset sequence Z in all decoded codewords Y. Optionally, the receiving end performs FEC decoding (i.e., target FEC decoding) on ​​the multiple FEC codewords (i.e., all FEC codewords) in the data sequence X to obtain multiple decoded codewords Y, and the multiple decoded codewords Y may correspond one-to-one to the multiple FEC codewords; the receiving end searches for the preset sequence Z in the multiple decoded codewords Y, and the receiving end may find the preset sequence Z in the multiple decoded codewords Y. For example, the receiving end may find multiple preset sequences Z in the multiple decoded codewords Y.

[0129] In a specific embodiment, the arrangement order of the multiple decoded codewords Y is the same as the arrangement order of the multiple FEC codewords, and the receiving end searches for the preset sequence Z in the multiple decoded codewords Y in sequence according to the arrangement order of the multiple decoded codewords Y until the first preset sequence Z is found. For example, the multiple decoded codewords Y are codeword Y1, codeword Y2, codeword Y3, etc., and codeword Y1, codeword Y2, codeword Y3, etc. are arranged in sequence. The receiving end first searches for the preset sequence Z in codeword Y1. If the receiving end finds the preset sequence Z in codeword Y1, the receiving end has found the first preset sequence Z. If the receiving end does not find the preset sequence Z in codeword Y1, the receiving end continues to search for the preset sequence Z in codeword Y2; if the receiving end finds the preset sequence Z in codeword Y2, the receiving end has found the first preset sequence Z. If the receiving end does not find the preset sequence Z in codeword Y2, the receiving end continues to search for the preset sequence Z in codeword Y3, and so on, until the first preset sequence Z is found. After the receiving end finds the first preset sequence Z in the multiple decoded code words Y, for example, the receiving end finds the first preset sequence Z in code word Y1, the receiving end determines at least one code word in the code words after code word Y1 in the multiple decoded code words Y according to the period in which the preset sequence Z appears in the data sequence X (for the convenience of description, the period in which the preset sequence Z appears in the data sequence X is called the target period), the interval between adjacent code words in the at least one code word is the target period, and the interval between the first code word in the at least one code word and code word Y1 is the target period, and the receiving end searches for the preset sequence Z in the at least one code word until the at least one code word is found. That is, the receiving end searches for the first preset sequence Z in the multiple decoded code words Y code word by code word, and after finding the first preset sequence Z in the multiple decoded code words Y, the receiving end no longer searches for the preset sequence Z code word by code word, but searches for the preset sequence Z in the multiple decoded code words Y according to the target period, thereby improving the efficiency of searching for the preset sequence Z.

[0130] Optionally, after the receiving end finds the first preset sequence Z in the multiple decoded code words Y, the receiving end searches for the preset sequence Z in the multiple decoded code words Y according to the target period. If the number of preset sequences Z found by the receiving end in succession in the multiple decoded code words Y reaches a specified number (for example, the specified number is 3, and the interval between the preset sequence Z adjacent to the first preset sequence Z in the specified number of preset sequences Z and the first preset sequence Z is the target period, or the specified number of preset sequences Z include the first preset sequence Z), the receiving end locks the first preset sequence Z found. The process from the receiving end starting to search for the first preset sequence Z to locking the first preset sequence Z found can be called a preset sequence locking process. After the receiving end locks the first preset sequence Z, the receiving end performs a preset sequence monitoring process. Specifically, the receiving end continues to search for the preset sequence Z in the multiple decoded codewords Y according to the target period based on the target preset sequence found in the preset sequence locking process (for example, the target preset sequence is the last preset sequence found in the preset sequence locking process), until the codewords Y distributed according to the target period in the multiple decoded codewords Y are found, or until the locked preset sequence is lost (the preset sequence monitoring process fails). For example, the preset sequence is the FS mentioned in the IEEE802.3dj standard discussion, the preset sequence locking process can be called the FS locking process, and the preset sequence monitoring process can be called the FS monitoring process. For another example, the preset sequence is in the AM mentioned in the 200 / 400GE standard, the preset sequence locking process can be called the AM locking process, and the preset sequence monitoring process can be called the AM monitoring process. Since the receiving end performs preset sequence locking and preset sequence monitoring based on the decoded codewords of the data sequence X, and the bit error rate of the decoded codewords is low, the probability of the preset sequence losing lock by mistake can be reduced. Among them, the preset sequence false lock means that the preset sequence is locked correctly but the preset sequence monitoring process fails. For example, during the preset sequence monitoring process, the preset sequence Z is not found in multiple consecutive target cycles, or the proportion of cycles in which the data sequence X is not found in multiple consecutive target cycles reaches the preset proportion, and the preset sequence monitoring process is considered to have failed.

[0131] Second embodiment: The receiving end performs target FEC decoding on the FEC codewords in the data sequence X while searching for the preset sequence Z in the decoded codeword Y. In one implementation, the receiving end performs FEC decoding (i.e., target FEC decoding) on ​​the first FEC codeword in the data sequence X to obtain the decoded first codeword, and the receiving end searches for the preset sequence Z in the decoded first codeword. If the decoded first codeword does not include the preset sequence Z, that is, the receiving end does not find the preset sequence Z in the decoded first codeword, the receiving end continues to perform FEC decoding (i.e., target FEC decoding) on ​​the FEC codewords after the first FEC codeword in the data sequence X and searches for the preset sequence Z in the decoded codewords until the first preset sequence Z is found. If the decoded first codeword includes the preset sequence Z, that is, the receiving end finds the preset sequence Z in the decoded first codeword, the receiving end performs FEC decoding (i.e., target FEC decoding) on ​​the second FEC codeword after the first FEC codeword in the data sequence X to obtain the decoded second codeword, and the receiving end attempts to find the preset sequence Z in the decoded second codeword. The first FEC codeword is an FEC codeword in the data sequence X, for example, the first FEC codeword is the first FEC codeword in the data sequence X, and the interval between the second FEC codeword and the first FEC codeword is the period during which the preset sequence Z appears in the data sequence X.

[0132] In a specific embodiment, if the receiving end finds the preset sequence Z in the decoded first codeword, the receiving end determines the second FEC codeword after the first FEC codeword in the data sequence X, the interval between the second FEC codeword and the first FEC codeword is the target period (that is, the period in which the preset sequence Z appears in the data sequence X), the receiving end performs target FEC decoding on the second FEC codeword to obtain the decoded second codeword, and the receiving end attempts to find the preset sequence Z in the decoded second codeword. Also, the receiving end determines the third FEC codeword after the second FEC codeword in the data sequence X, the interval between the third FEC codeword and the second FEC codeword is the target period, the receiving end performs target FEC decoding on the third FEC codeword to obtain the decoded third codeword, and the receiving end attempts to find the preset sequence Z in the decoded third codeword. And, the receiving end determines the fourth FEC codeword after the third FEC codeword in the data sequence X, the interval between the fourth FEC codeword and the third FEC codeword is the target period, the receiving end performs target FEC decoding on the fourth FEC codeword to obtain the decoded fourth codeword, and the receiving end attempts to find the preset sequence Z in the decoded fourth codeword. And so on. That is, if the receiving end finds the preset sequence Z in the first decoded codeword, the receiving end traverses the FEC codewords after the first FEC codeword in the data sequence X according to the target period (the interval between two adjacent FEC codewords traversed according to the target period is the target period), the receiving end performs target FEC decoding on the traversed FEC codewords, and attempts to find the preset sequence Z in the decoded codewords. In other words, if the receiving end finds the preset sequence Z in the first decoded codeword, the receiving end attempts to find the preset sequence Z in the FEC codewords after the first FEC codeword in the data sequence X according to the target period. Optionally, the preset sequence Z found by the receiving end in the first decoded codeword is the first preset sequence Z found by the receiving end. After the receiving end finds the first preset sequence Z, the receiving end traverses the FEC codewords after the first FEC codeword in the data sequence X according to the target period, the receiving end performs target FEC decoding on the traversed FEC codewords, and attempts to find the preset sequence Z in the decoded codewords. If the number of preset sequences Z found by the receiving end in the data sequence X reaches a specified number (for example, the specified number is 3, and the interval between the preset sequence Z adjacent to the first preset sequence Z in the specified number of preset sequences Z and the first preset sequence Z is the target period, or the specified number of preset sequences Z include the first preset sequence Z), the receiving end locks the first preset sequence Z found. The process from the beginning of searching for the first preset sequence Z to locking the first preset sequence Z found by the receiving end can be called a preset sequence locking process. After the receiving end locks the first preset sequence Z, the receiving end performs a preset sequence monitoring process.Specifically, the receiving end continues to traverse the FEC codewords of data sequence X according to the target period based on the position of the target preset sequence found in the preset sequence locking process (for example, the target preset sequence is the last preset sequence found in the preset sequence locking process) in the data sequence X, and the receiving end performs target FEC decoding on the traversed FEC codewords, and searches for the preset sequence Z in the decoded codewords until all FEC codewords distributed according to the target period in the data sequence X are found, or until the locked preset sequence loses lock (the preset sequence monitoring process fails). Since the receiving end performs preset sequence locking and preset sequence monitoring on the data sequence X based on the decoded codewords of the data sequence X, and the bit error rate of the decoded codewords is low, the probability of the preset sequence losing lock by mistake can be reduced.

[0133] In a specific embodiment, if the receiving end does not find the preset sequence Z in the first decoded codeword, the receiving end sequentially performs target FEC decoding on multiple FEC codewords after the first FEC codeword in the data sequence X according to the arrangement order of the FEC codewords in the data sequence X, and sequentially searches for the preset sequence Z in the decoded codewords. Specifically, each time the receiving end obtains a decoded codeword, the receiving end searches for the preset sequence Z in the decoded codeword. If the preset sequence Z is not found in the decoded codeword, the receiving end performs target FEC decoding on the next FEC codeword, and searches for the preset sequence Z in the next decoded codeword, and so on, until the first preset sequence Z is found. The codeword boundaries of any two adjacent FEC codewords in the multiple FEC codewords after the first FEC codeword are adjacent, and the codeword boundary of the FEC codeword adjacent to the first FEC codeword in the multiple FEC codewords is adjacent to the codeword boundary of the first FEC codeword. The adjacent codeword boundaries of the two FEC codewords mentioned here refer to: in the two FEC codewords, the end of the previous FEC codeword (for example, the last bit in the previous FEC codeword) is adjacent to the beginning of the next FEC codeword (for example, the first bit in the next FEC codeword), there are no other bits between the end of the previous FEC codeword and the beginning of the next FEC codeword, and the next bit of the last bit in the previous FEC codeword is the first bit in the next FEC codeword. Optionally, after the receiving end finds the first preset sequence Z, for example, the receiving end finds the first preset sequence Z in the decoded codeword of the target FEC codeword in the data sequence X, the receiving end traverses the FEC codewords after the target FEC codeword in the data sequence X according to the target period (that is, the period in which the preset sequence Z appears in the data sequence X), the receiving end performs target FEC decoding on the traversed FEC codewords, and searches for the preset sequence Z in the decoded codewords. That is, before the receiving end finds the first preset sequence Z, the receiving end searches for the preset sequence Z in the data sequence X in sequence according to the arrangement order of the FEC codewords in the data sequence X (that is, searches for the preset sequence Z one by one FEC codeword), and after the receiving end finds the first preset sequence Z, the receiving end no longer searches for the preset sequence Z one by one FEC codeword, but searches for the preset sequence Z in the data sequence X according to the target period, thereby improving the efficiency of searching for the preset sequence Z.

[0134] Optionally, after the receiving end finds the first preset sequence Z in the data sequence X, the receiving end searches for the preset sequence Z in the data sequence X according to the target period. If the number of preset sequences Z found by the receiving end in a plurality of FEC codewords reaches a specified number (for example, the specified number is 3, and the interval between the preset sequence Z adjacent to the first preset sequence Z in the specified number of preset sequences Z and the first preset sequence Z is the target period, or the specified number of preset sequences Z includes the first preset sequence Z), the receiving end locks the first preset sequence Z found. The process from the beginning of searching for the first preset sequence Z to locking the first preset sequence Z found by the receiving end can be called a preset sequence locking process. After the receiving end locks the first preset sequence Z, the receiving end performs a preset sequence monitoring process. Specifically, the receiving end continues to search for the preset sequence Z in the data sequence X according to the target period based on the position of the target preset sequence found in the preset sequence locking process (for example, the target preset sequence is the last preset sequence found in the preset sequence locking process) in the data sequence X, until all FEC codewords distributed according to the target period in the data sequence X are found, or until the locked preset sequence loses lock (the preset sequence monitoring process fails). Since the receiving end performs preset sequence locking and preset sequence monitoring on the data sequence X based on the decoded codeword of the data sequence X, and the bit error rate of the decoded codeword is low, the probability of false loss of preset sequence lock can be reduced.

[0135] In an optional embodiment, the receiving end uses a first decoding method to perform FEC decoding on the first FEC codeword in the data sequence X (that is, target FEC decoding), and the receiving end uses a second decoding method to perform FEC decoding on the candidate FEC codeword after the first FEC codeword in the data sequence X (that is, target FEC decoding). The receiving end may also use the first decoding method to perform FEC decoding on the second FEC codeword in the data sequence X (that is, target FEC decoding). One of the first decoding method and the second decoding method is soft-decision decoding (SDD), and the other is hard-decision decoding (HDD). That is, the first decoding method is SDD and the second decoding method is HDD; or, the first decoding method is HDD and the second decoding method is SDD. The candidate FEC codewords described here may include all FEC codewords that have not been decoded in the data sequence X after the receiving end locks the preset sequence. In one embodiment, the receiving end uses a first decoding method to perform target FEC decoding on the FEC codewords in the data sequence X during the preset sequence locking process, and the receiving end uses a second decoding method to perform target FEC decoding on the FEC codewords in the data sequence X after the preset sequence is locked. The receiving end performs formal data processing on the data sequence X after the preset sequence is locked, and the formal data processing includes performing target FEC decoding on the FEC codewords in the data sequence X. In one example, the first decoding method is HDD and the second decoding method is SDD. Since the decoding complexity of HDD is low and the decoding performance of SDD is good (for example, there are fewer bit errors in the decoded codewords), the receiving end uses the first decoding method (that is, HDD) to perform target FEC decoding on the FEC codewords in the data sequence X during the preset sequence locking process, which can reduce the complexity of the receiving end locking the preset sequence, and the receiving end uses the second decoding method (that is, SDD) to perform target FEC decoding on the FEC codewords in the data sequence X after the preset sequence is locked, which can ensure the bit error performance of the formal data processing of the receiving end. In another example, the first decoding method is SDD, and the second decoding method is HDD. The receiving end uses the first decoding method (that is, SDD) to perform target FEC decoding on the FEC codewords in the data sequence X during the preset sequence locking process, which can improve the reliability of the receiving end locking the preset sequence. After the preset sequence is locked, the receiving end uses the second decoding method (that is, HDD) to perform target FEC decoding on the FEC codewords in the data sequence X, which can reduce the complexity of the formal data processing of the receiving end. In an embodiment of the present application, the first decoding method and the second decoding method are implemented using the same hardware logic, that is, SDD and HDD are implemented using the same hardware logic. For example, SDD is implemented by a specific hardware circuit, and HDD is implemented by a part of the specific hardware circuit, thereby reducing the implementation complexity and implementation cost of the technical solution of the present application.

[0136] In summary, the technical solution provided by the embodiment of the present application is that after the receiving end obtains a data sequence including multiple FEC codewords, the receiving end performs FEC decoding on at least one FEC codeword in the data sequence to obtain at least one decoded codeword, and the receiving end finds a preset sequence in the at least one decoded codeword. Since the receiving end can perform error detection and error correction on the at least one FEC codeword during the FEC decoding of the at least one FEC codeword, the bit error rate of the at least one decoded codeword is low or may even be free of bit errors, which can reduce the effect of bit errors on the efficiency of the receiving end in finding the preset sequence. The time taken by the receiving end to find the preset sequence in the at least one decoded codeword is short, and the efficiency, accuracy and reliability are all high, which ensures the transmission efficiency and reliability of the communication system. Especially when the bit error rate of the data sequence obtained by the receiving end is high, the technical solution of the embodiment of the present application can obtain greater benefits. In addition, the FEC decoding process performed by the receiving end on the data sequence during the preset sequence locking process and the FEC decoding process performed by the receiving end on the data sequence during the formal data processing process are implemented using the same hardware logic, and the time taken by the receiving end to search for the preset sequence can be shortened without adding additional verification logic, thereby improving the efficiency, accuracy and reliability of the receiving end in searching for the preset sequence. The implementation process of the embodiment of the present application is simple, the implementation cost is low, and the applicability is wide.

[0137] For optional embodiments, please refer to Fig.12 , which shows a flow chart of another method for processing data provided by an embodiment of the present application. Before S1102, the method for processing data further includes the following step S1104.

[0138] S1104. Determine the FEC codeword boundary in the data sequence X by self-synchronization.

[0139] The method of determining the FEC codeword boundary in the data sequence X by self-synchronization can refer to the patent application document "Codeword Synchronization Method, Receiver, Network Device and Network System" with publication number CN113517949A, and the reference standard document "Inner Codeword Self-sync Proposal" (address: https: / / www.ieee802.org / 3 / dj / public / 23_07 / he_3dj_03b_2307.pdf), all of which are incorporated herein by reference, as if all were stated, and will not be repeated here.

[0140] After the receiving end determines the FEC codeword boundary in the data sequence X, the receiving end locks the FEC codeword boundary in the data sequence X. Also, after the receiving end determines the FEC codeword boundary in the data sequence X (for example, after the receiving end locks the FEC codeword boundary in the data sequence X), the receiving end determines multiple FEC codewords included in the data sequence X according to the FEC codeword boundary in the data sequence X, and then performs FEC decoding on at least one FEC codeword among the multiple FEC codewords and searches for the preset sequence Z in the decoded codewords, that is, executes S1102 to S1103.

[0141] For optional embodiments, please refer to Fig.12 , after S1103, the method for processing data further includes the following step S1105.

[0142] S1105. If the preset condition is met, the padding sequence related to the preset sequence Z in the data sequence X is deleted according to the position of the preset sequence Z found in the data sequence X, and the preset condition includes that the number of the preset sequence Z included in the n codewords in the at least one decoded codeword Y reaches a first threshold, n is a positive integer, and the interval between adjacent codewords in the n codewords is the period of the preset sequence Z appearing in the data sequence X.

[0143] The number of preset sequences Z included in the n codewords reaching the first threshold may be that the number of preset sequences Z included in the n codewords is greater than the first threshold, or the number of preset sequences Z included in the n codewords is greater than or equal to the first threshold. The interval between adjacent codewords in the n codewords is the period in which the preset sequence Z appears in the data sequence X, and the n codewords are continuous, that is, the n codewords are continuous according to the period in which the preset sequence Z appears in the data sequence X. All or part of the n codewords include the preset sequence Z, one codeword usually includes one preset sequence Z, and some codewords may not include the preset sequence Z. The value of n and the first threshold can be set according to actual conditions, for example, n=3, and the first threshold is 3.

[0144] Among them, the padding sequence related to the preset sequence Z in the data sequence X is the padding sequence that includes the preset sequence Z in the data sequence X. For example, if a certain padding sequence includes the preset sequence Z, then the certain padding sequence is related to the preset sequence Z, and the certain padding sequence is the padding sequence related to the preset sequence Z. In one embodiment, the preset sequence Z is the FS mentioned in the discussion of the IEEE802.3dj standard, and the padding sequence related to the preset sequence Z is the padding sequence that includes the FS in the IEEE802.3dj standard. In another embodiment, the preset sequence Z is in the AM defined in the 200 / 400GE standard defined by the IEEE802.3bs project, and the padding sequence related to the preset sequence Z is AM.

[0145] In the process of searching for the preset sequence Z in the at least one decoded codeword Y by the receiving end, for example, in the process of locking the preset sequence, the receiving end monitors whether the preset condition is met, for example, the receiving end detects in real time or periodically whether the preset condition is met. If the receiving end determines that the preset condition is met, the receiving end obtains the preset sequence Z that the receiving end has found in the at least one decoded codeword Y when the preset condition is met, and for each preset sequence Z that the receiving end has found in the at least one decoded codeword Y when the preset condition is met, the receiving end determines the padding sequence related to each preset sequence Z in the data sequence X according to the position of each preset sequence Z in the data sequence X, and the receiving end deletes the padding sequence related to each preset sequence Z in the data sequence X. Optionally, the receiving end monitors whether the preset condition is met in the process of locking the preset sequence, and if the receiving end determines that the preset condition is met, the receiving end locks the first preset sequence Z found, and then the receiving end performs the preset sequence detection process. Specifically, the receiving end continues to search for the preset sequence Z in the at least one decoded codeword Y based on the position of the target preset sequence found in the preset sequence locking process (for example, the target preset sequence is the last preset sequence found in the preset sequence locking process) in the data sequence X, and deletes the padding sequence related to the preset sequence Z in the data sequence X according to the position of the preset sequence Z found in the data sequence X, until all FEC codewords distributed according to the target period in the data sequence X are found, or until the locked preset sequence loses lock (the preset sequence monitoring process fails). The preset condition includes that the number of preset sequences Z included in the n codewords in the at least one decoded codeword Y reaches a first threshold, and the interval between adjacent codewords in the n codewords is the period of the preset sequence Z appearing in the data sequence X (that is, the target period mentioned above). The fact that the number of preset sequences Z included in the n codewords reaches the first threshold value indicates that the number of preset sequences Z included in the n codewords is relatively large, further indicating that there is no problem with the preset sequence that the receiving end has found (for example, the preset sequence that has been found is a true preset sequence). Therefore, when the number of preset sequences Z included in the n codewords reaches the first threshold value, the receiving end deletes the padding sequence related to the preset sequence Z in the data sequence X according to the position of the found preset sequence Z in the data sequence X.

[0146] In one embodiment, the receiving end performs target FEC decoding on the multiple FEC codewords (that is, all FEC codewords) in the data sequence X to obtain multiple decoded codewords Y, and the receiving end searches for a preset sequence Z in the multiple decoded codewords Y. The receiving end monitors whether a preset condition is met during the process of searching for the preset sequence Z in the multiple decoded codewords Y. If the receiving end determines that the preset condition is met, the receiving end locks the first preset sequence Z found, and then the receiving end continues to search for the preset sequence Z in the codewords after the currently searched codeword in the multiple decoded codewords Y according to the target period based on the target preset sequence found in the preset sequence locking process (for example, the target preset sequence is the last preset sequence found in the preset sequence locking process), and deletes the padding sequence related to the preset sequence Z in the data sequence X according to the position of the found preset sequence Z in the data sequence X.

[0147] In another embodiment, the receiving end performs target FEC decoding on the FEC codewords in the data sequence X while searching for the preset sequence Z in the decoded codewords Y. The receiving end monitors whether the preset condition is met in the process of searching for the preset sequence Z in the data sequence X. If the receiving end determines that the preset condition is met, the receiving end locks the first preset sequence Z found, and then the receiving end continues to search for the preset sequence Z in the FEC codewords after the currently searched FEC codewords in the data sequence X according to the target period based on the target preset sequence found in the preset sequence locking process (for example, the target preset sequence is the last preset sequence found in the preset sequence locking process), and deletes the padding sequence related to the preset sequence Z in the data sequence X according to the position of the found preset sequence Z in the data sequence X. Optionally, after the receiving end determines that the preset conditions are met, the receiving end traverses the FEC codewords after the currently decoded FEC codeword in the data sequence X according to the target period, the receiving end performs target FEC decoding on the traversed FEC codewords, and searches for the preset sequence Z in the decoded codewords until the FEC codewords distributed according to the target period after the currently decoded FEC codeword are traversed.

[0148] For optional embodiments, please continue to refer to Fig.12 , after S1103, the method for processing data further includes the following step S1106.

[0149] S1106. If the lock-loss condition is met, the FEC codeword boundary in the data sequence X is searched again, and the lock-loss condition includes that the number of m codewords in the at least one decoded codeword Y that does not include the preset sequence Z reaches a second threshold, m is a positive integer, and the interval between adjacent codewords in the m codewords is the period of the preset sequence Z appearing in the data sequence X.

[0150] Among them, the number of codewords that do not include the preset sequence Z in the m codewords reaches the second threshold value, which may be that the number of codewords that do not include the preset sequence Z in the m codewords is greater than the second threshold value, or the number of codewords that do not include the preset sequence Z in the m codewords is greater than or equal to the second threshold value. The interval between adjacent codewords in the m codewords is the period in which the preset sequence Z appears in the data sequence X. Optionally, the m codewords are continuous, that is, the m codewords are continuous according to the period in which the preset sequence Z appears in the data sequence X. All or part of the m codewords include the preset sequence Z, and one codeword usually includes one preset sequence Z, and some codewords may not include the preset sequence Z. The value of m and the second threshold value are both set according to actual conditions, for example, m=12, and the second threshold value is 12. The lock-out condition described here can also be described as "the number of codewords that include the wrong (bad) preset sequence Z in the m codewords in the at least one decoded codeword Y reaches the second threshold value", and the wrong (bad) preset sequence is also called a bad preset sequence, an incorrect preset sequence, an invalid preset sequence, etc.

[0151] In the embodiment of the present application, after the receiving end locks the FEC codeword boundary in the data sequence X, the receiving end determines multiple FEC codewords included in the data sequence X according to the FEC codeword boundary in the data sequence X, and then performs FEC decoding on at least one FEC codeword among the multiple FEC codewords to obtain the at least one decoded codeword Y. In the process of the receiving end searching for the preset sequence Z in the at least one decoded codeword Y, for example, in the process of monitoring the preset sequence, the receiving end monitors whether the loss-of-lock condition is met, for example, the receiving end detects in real time or periodically whether the loss-of-lock condition is met. If the receiving end determines that the unlocking condition is met, the receiving end determines that the locked FEC codeword boundary is incorrect, the locked FEC codeword boundary is unlocked (or called data sequence X is unlocked), and the receiving end re-searches the FEC codeword boundary in the data sequence X. For example, the receiving end re-searches the FEC codeword boundary in the data sequence X by self-synchronization (or called re-determining the FEC codeword boundary in the data sequence X). The receiving end re-determines the multiple FEC codewords included in the data sequence X according to the re-found FEC codeword boundary, and then performs FEC decoding on at least one FEC codeword among the re-determined multiple FEC codewords and searches for the preset sequence Z. For example, the receiving end executes the above S1102, S1103 and S1105 according to the re-found FEC codeword boundary. Optionally, if the receiving end determines that the lock-out condition is not met, the receiving end determines that the locked FEC codeword is not locked (or the data sequence X is not locked), and the receiving end continues to search for the preset sequence Z in the original at least one decoded codeword Y, and continues to monitor whether the lock-out condition is met until the lock-out condition is met or until the at least one decoded codeword Y is completely found. The lock-out condition includes that the number of codewords that do not include the preset sequence Z in the m codewords in the at least one decoded codeword Y reaches a second threshold, and the interval between adjacent codewords in the m codewords is a target period. The number of codewords that do not include the preset sequence Z in the m codewords reaches the second threshold, indicating that the number of preset sequences Z included in the m codewords is small, further indicating that the FEC codeword boundary locked by the receiving end is incorrect, so when the number of codewords that include the preset sequence Z in the m codewords reaches the second threshold, the receiving end searches for the FEC codeword boundary in the data sequence X again.

[0152] In one embodiment, in S1102, the receiving end performs target FEC decoding on the multiple FEC codewords (that is, all FEC codewords) in the data sequence X to obtain multiple decoded codewords Y, and in S1103, the receiving end searches for a preset sequence Z in the multiple decoded codewords Y. If the loss of lock condition is not met, the receiving end continues to search for the preset sequence in the codewords after the currently searched codeword in the multiple decoded codewords Y according to the target period, and continues to monitor whether the loss of lock condition is met until the loss of lock condition is met or until the multiple decoded codewords Y are searched for according to the target period. For example, the receiving end continues to traverse the codewords after the currently searched codeword in the multiple decoded codewords Y according to the target period, and the interval between two adjacent codewords traversed by the receiving end according to the target period is the target period.

[0153] In another embodiment, in S1102 and S1103, the receiving end performs target FEC decoding on the FEC codewords in the data sequence X while searching for the preset sequence Z in the decoded codewords Y. If the loss of lock condition is not met, the receiving end continues to search for the preset sequence Z in the FEC codewords after the currently searched FEC codewords in the data sequence X according to the target period, and continues to monitor whether the loss of lock condition is met until the loss of lock condition is met or until the FEC codewords in the data sequence X are searched for according to the target period. Optionally, if the loss of lock condition is not met, the receiving end traverses the FEC codewords after the currently decoded FEC codeword in the data sequence X according to the target period, performs target FEC decoding on the traversed FEC codewords, and searches for the preset sequence Z in the decoded codewords.

[0154] In the embodiment of the present application, the lock-loss condition includes that the number of codewords that do not include the preset sequence Z in the m codewords in the at least one decoded codeword Y reaches a second threshold value. That is, the number of preset sequences Z found by the receiving end from the decoded codeword Y is used as the judgment condition of whether the lock is lost. The lock-loss condition may also include other conditions. In an optional embodiment, after the receiving end locks the FEC codeword boundary in the data sequence X, the codeword boundary of the data sequence X is monitored to determine whether the lock-loss condition is met. In this embodiment, the lock-loss condition may include that the number of uncorrectable codewords that appear continuously in the data sequence X reaches a preset number, the proportion of uncorrectable codewords that appear continuously in the data sequence X reaches a preset ratio, etc. In these cases, the receiving end considers that the locked FEC codeword boundary is incorrect, and the receiving end searches for the FEC codeword boundary in the data sequence X again. Among them, the preset number and the preset ratio can be set according to actual conditions. The continuously appearing uncorrectable codewords are the uncorrectable codewords that appear continuously in multiple FEC codewords that the receiving end continuously performs target FEC decoding. The multiple FEC codewords can be continuous or discontinuous (for example, there may be some FEC codewords in the multiple FEC codewords with the interval between them being the target period). Optionally, the data sequence X includes FEC codeword X1, FEC codeword X2, FEC codeword X3...FEC codeword Xh, and the receiving end continuously performs target FEC decoding on FEC codeword X1, FEC codeword X4, and FEC codeword X7. Then, FEC codeword X1, FEC codeword X4, and FEC codeword X7 are multiple FEC codewords on which the receiving end continuously performs target FEC decoding. The continuously appearing uncorrectable codewords are the continuously appearing uncorrectable codewords in FEC codeword X1, FEC codeword X4, and FEC codeword X7. For example, the receiving end determines through target FEC decoding that FEC codeword X1 and FEC codeword X4 are both uncorrectable codewords. Then, FEC codeword X1 and FEC codeword X4 are the “continuously appearing uncorrectable codewords” described in the embodiments of the present application. Among them, the proportion of uncorrectable codewords appearing continuously in the data sequence X is the proportion of uncorrectable codewords appearing continuously in multiple FEC codewords that the receiving end continuously performs target FEC decoding, specifically, the ratio of the number of uncorrectable codewords appearing continuously in the multiple FEC codewords to the number of the multiple FEC codewords. For example, the receiving end continuously performs target FEC decoding on FEC codeword X1, FEC codeword X4, and FEC codeword X7 to determine that FEC codeword X1 and FEC codeword X4 are both uncorrectable codewords, then the receiving end determines that the proportion of uncorrectable codewords appearing continuously is 0.5.In a specific embodiment, during the process of the receiving end monitoring the codeword boundary of the data sequence X, the receiving end performs target FEC decoding on the FEC codeword in the data sequence X according to the locked FEC codeword boundary, and the receiving end determines whether the FEC codeword is an uncorrectable codeword according to the decoding result to perform uncorrectable codeword monitoring. If the receiving end determines during the monitoring process that the number of uncorrectable codewords that appear continuously reaches a preset number or the proportion of uncorrectable codewords that appear continuously reaches a preset ratio, the receiving end determines that the lock-out condition is met, the locked FEC codeword boundary is locked, and the FEC codeword boundary in the data sequence X is searched again. It can be seen that there may be multiple lock-out conditions in the embodiment of the present application, and setting multiple lock-out conditions to monitor whether the locked FEC codeword boundary is locked can improve the reliability of the lock-out monitoring performed by the receiving end.

[0155] As previously mentioned, in an embodiment of the present application, the receiving end determines the FEC codeword boundary in the data sequence X by means of self-synchronization. After the receiving end determines the FEC codeword boundary in the data sequence X, it locks the FEC codeword boundary in the data sequence X. After the receiving end locks the FEC codeword boundary in the data sequence X, it also monitors the FEC codeword boundary of the data sequence X to determine whether the locked FEC codeword boundary is unlocked. Since the receiving end determines the FEC codeword boundary in the data sequence X and locks the FEC codeword boundary in the data sequence X by means of self-synchronization, the process of the receiving end locking the FEC codeword boundary (the process from the receiving end starting to look for the FEC codeword boundary in the data sequence X to the receiving end locking the FEC codeword boundary in the data sequence X) can be called a self-synchronization locking process or a codeword boundary locking process, and the process of the receiving end monitoring the FEC codeword boundary of the data sequence X can be called a self-synchronization monitoring process or a codeword boundary monitoring process. In an optional embodiment, Fig.13 Schematic diagram of a method for processing data provided by an embodiment of the present application. Fig.13As shown, the receiving end first performs a self-synchronization locking process to lock the FEC codeword boundary of the data sequence X, and then performs a self-synchronization monitoring process based on the locked FEC codeword boundary to monitor the FEC codeword boundary of the data sequence X. Specifically, the receiving end performs target FEC decoding on the FEC codeword in the data sequence X according to the locked FEC codeword boundary, and the receiving end performs uncorrectable codeword monitoring on the data sequence X according to the decoding result. During the self-synchronization monitoring process performed by the receiving end, if the receiving end determines that the self-synchronization monitoring fails (for example, the number of uncorrectable codewords that appear continuously in the data sequence X reaches a preset number, the proportion of uncorrectable codewords that appear continuously in the data sequence X reaches a preset ratio, etc.), the receiving end determines that the locked FEC codeword boundary is unlocked, and the receiving end re-executes the self-synchronization locking process to lock the FEC codeword boundary of the data sequence X. The receiving end performs a self-synchronization monitoring process based on the re-locked FEC codeword boundary, thus forming a closed-loop process of self-synchronization locking-self-synchronization monitoring-self-synchronization locking.

[0156] like Fig.13 As shown, after locking the FEC codeword boundary in the data sequence X, the receiving end also performs a preset sequence locking process based on the locked FEC codeword boundary to lock the preset sequence Z in the data sequence X, and the receiving end performs a preset sequence monitoring process based on the locked preset sequence Z. Specifically, the receiving end performs target FEC decoding on at least one FEC codeword in the data sequence X based on the locked FEC codeword boundary to obtain at least one decoded codeword Y, and the receiving end searches for the preset sequence Z in the at least one decoded codeword Y. If the number of preset sequences Z found continuously by the receiving end in the at least one decoded codeword Y reaches a first threshold (for example, 3), for example, if the receiving end determines that the preset condition described in S1105 is satisfied, the receiving end locks the first preset sequence Z found. Specifically, during the preset sequence monitoring process, the receiving end searches for the preset sequence Z in the at least one decoded codeword Y according to the target period based on the position of the target preset sequence found in the preset sequence locking process (for example, the target preset sequence is the last preset sequence found in the preset sequence locking process) in the data sequence X, until it is determined that the number of codewords that do not include the preset sequence Z in the at least one decoded codeword Y reaches a second threshold (that is, until the loss of lock condition described in S1106 is met), and the receiving end determines that the preset sequence monitoring process has failed, or until the receiving end has found the at least one decoded codeword Y according to the target period. If the receiving end determines that the preset sequence monitoring has failed, the receiving end determines that the locked preset sequence has lost lock. Since the locked preset sequence is locked based on the locked FEC codeword boundary, when the locked preset sequence loses lock, it can be considered that the locked FEC codeword boundary has lost lock. Therefore, if Fig.13As shown, if the receiving end determines that the preset sequence monitoring fails, the receiving end re-executes the self-synchronization locking process to lock the FEC codeword boundary of the data sequence X, the receiving end performs the self-synchronization monitoring process based on the re-locked FEC codeword boundary, the receiving end performs target decoding on the FEC codeword in the data sequence X based on the re-locked FEC codeword boundary and performs the preset sequence locking process, and performs the preset sequence monitoring process based on the re-locked preset sequence Z, thus forming a closed-loop process of self-synchronization locking-preset sequence locking-preset sequence monitoring-self-synchronization locking. Optionally, if the receiving end determines that the preset sequence monitoring fails, the receiving end can also skip the self-synchronization locking process and directly re-execute the preset sequence locking process, thus forming a closed-loop process of preset sequence locking-preset sequence monitoring-preset sequence locking, which is not limited in the embodiments of the present application.

[0157] The following takes the preset sequence Z as an example to introduce the preset sequence locking process and the preset sequence monitoring process. Fig.14 and Fig.15 As shown, Fig.14 is a state diagram of a preset sequence locking process provided by an embodiment of the present application, Fig.15 It is a state diagram of a preset sequence monitoring process provided in an embodiment of the present application. Fig.14 Take the case where the number of FSs found by the receiving end in at least one decoded codeword Y reaches a first threshold and locks the FS in the data sequence X as an example, that is, the case where the receiving end locks the FS in the data sequence X when the preset condition described in S1105 is met as an example, and Fig.14 For example, the first threshold is 3. Fig.15 The unlocking condition is that the number of codewords not including FS in the m codewords in at least one decoded codeword of the data sequence X reaches the second threshold value as an example, and Fig.15 Take the second threshold value of 12 as an example. For example, the lock-out condition is that the number of bad FS in the m codewords of at least one decoded codeword of the data sequence X reaches 12. Fig.14 and Fig.15 In the diagram, a large rectangular box formed by two small rectangular boxes overlapped represents the state of the state machine. In each large rectangular box, the small rectangular box located on the top records the state name, and the small rectangular box located on the bottom records the operation performed by the state machine in the corresponding state. For example, Fig.14In the example, "FS_LOCK_INIT" is the state name, and "test_fs<=false" in the small rectangular box below the small rectangular box where "FS_LOCK_INIT" is located indicates that the operation performed by the state machine in the "FS_LOCK_INIT" state is to assign "false" to the variable "test_fs". In the arrows connected to each large rectangular box used to represent the state, the arrow connected to the large rectangular box at the end records the transition condition for the state machine to enter the state represented by the large rectangular box, and the arrow connected to the large rectangular box at the head records the transition condition for the state machine to exit the state represented by the large rectangular box. For example, in Fig.14 In the example, the transition condition for the state machine to enter the state "FS_LOCK_INIT" is all_locked* and! fs_lock, and the transition condition for the state machine to exit the state "FS_LOCK_INIT" is UCT, which is an unconditional transition. That is, the state machine can exit the state "FS_LOCK_INIT" without any condition, and so on. Fig.14 It can be seen that during the FS locking process, the receiving end continuously searches for FS, and the receiving end locks the FS when the number of FSs found continuously reaches 3. Fig.15 It can be seen that after the receiving end locks the FS, it enters the FS monitoring process. In the FS monitoring process, the receiving end determines that the FS is unlocked when the number of bad FS found continuously reaches 12, so the receiving end searches for the FEC codeword boundary in the data sequence X again.

[0158] The method for processing data provided in the embodiment of the present application can be executed entirely by hardware, or by software and hardware. For example, the steps of performing FEC decoding on the FEC codewords in the data sequence X and the steps before decoding can be performed by hardware, and the steps after decoding the FEC codewords in the data sequence X can be performed by software. Optionally, the receiving end includes an acquisition module, a synchronization module, a decoding module, a search module and a deletion module, the acquisition module, the synchronization module and the decoding module are all hardware modules, the search module and the deletion module are all software modules, for example, the acquisition module is also called an acquisition circuit, the synchronization module is also called a synchronization circuit, and the decoding module is also called a decoding circuit (or called an FEC decoding circuit, an FEC decoder, etc.), the acquisition module extracts the data sequence X from the Ethernet signal received by the receiving end, the synchronization module searches for the FEC codeword boundary in the data sequence X, the decoding module performs FEC decoding on the FEC codewords in the data sequence X, the search module finds the preset sequence Y in the decoded codewords, and the deletion module monitors whether the preset conditions are met, and deletes the padding sequence related to the preset sequence Z in the data sequence X when the preset conditions are met. In an optional embodiment, the decoding module may send all decoded codewords to the search module, and the search module searches for a preset sequence in all decoded codewords; or, the decoding module may send part of the decoded codewords to the search module, and the search module searches for a preset sequence in the decoded part of the codewords. For example, the decoding module screens the decoding results, and the decoding module sends the screened part of the codewords to the search module. Optionally, the decoding module screens the decoding results according to the target period (that is, the period in which the preset sequence Z appears in the data sequence X), and sends the screened part of the codewords to the search module, which is not limited in the embodiment of the present application.

[0159] The length and content of the preset sequence described in the embodiments of the present application are fixed. In some technical documents, the preset sequence is also referred to as a fixed sequence or a similar name.

[0160] The above embodiments are described by taking the application of the present application to Ethernet as an example. The application scenarios of the embodiments of the present application are not limited to Ethernet. The embodiments of the present application can also be applied to optical transport networks (OTN), secret private networks (SPN), fiber channels, infinite bandwidth (infiniband) and other network systems.

[0161] The above is an introduction to the method embodiment of the present application. The following is an introduction to the device embodiment of the present application. The device of the present application can be used to execute the method of the present application. For details not disclosed in the device embodiment of the present application, please refer to the method embodiment.

[0162] The present application provides a device for processing data, which is used to perform the following steps: Fig.10 or Fig.11 The method embodiment shown.

[0163] Optionally, the device includes an Ethernet interface, which may be a Terabit Ethernet interface.

[0164] Optionally, the device is any one of the following: forwarding equipment, user terminal equipment or server equipment, main chip, optical module or chip in the optical module. The forwarding equipment may be a router or a switch.

[0165] In one implementation, the device includes at least one module, the at least one module being configured to execute: Fig.10 or Fig.11 The at least one module can be implemented based on software, hardware, or a combination of software and hardware, and can be arbitrarily combined or divided based on specific implementations.

[0166] Optional, please refer to Fig.16 , which shows a schematic diagram of a device 1600 for processing data provided in an embodiment of the present application, wherein the device 1600 includes: an acquisition module 1610, a decoding module 1620 and a search module 1630.

[0167] The acquisition module 1610 is used to acquire a data sequence, which includes multiple FEC codewords; the decoding module 1620 is used to perform FEC decoding on at least one FEC codeword in the data sequence to obtain at least one decoded codeword; the search module 1630 is used to find a preset sequence in the at least one decoded codeword. For the functional implementation of the acquisition module 1610, please refer to the relevant description in S1101. For the functional implementation of the decoding module 1620, please refer to the relevant description in S1102, and for the functional implementation of the search module 1630, please refer to the relevant description in S1103.

[0168] Optionally, the preset sequence is a sequence that appears periodically in the data sequence.

[0169] Optional, please continue to refer to Fig.16 The device 1600 further includes: a deletion module 1640, which is used to delete a padding sequence related to the preset sequence in the data sequence according to the position of the preset sequence found in the data sequence if a preset condition is met, wherein the preset condition includes that the number of preset sequences included in n codewords in the at least one decoded codeword reaches a first threshold, n is a positive integer, and the interval between adjacent codewords in the n codewords is the period in which the preset sequence appears in the data sequence. Please refer to the description in S1105 for the functional implementation of the deletion module 1640.

[0170] Optional, please continue to refer to Fig.16 The device 1600 further includes: a synchronization module 1650, which is used to re-search the FEC codeword boundary in the data sequence if the loss of lock condition is met, and the loss of lock condition includes that the number of codewords that do not include the preset sequence in the m codewords of the at least one decoded codeword reaches a second threshold, m is a positive integer, and the interval between adjacent codewords in the m codewords is the period of the preset sequence appearing in the data sequence. Please refer to the relevant description in S1106 for the functional implementation of the synchronization module 1650.

[0171] Optionally, the decoding module 1620 is used to perform FEC decoding on the multiple FEC codewords to obtain multiple decoded codewords; correspondingly, the searching module 1630 is used to find a preset sequence in the multiple decoded codewords.

[0172] Optionally, the decoding module 1620 is used to: perform FEC decoding on the first FEC codeword in the data sequence to obtain a decoded first codeword; if the decoded first codeword does not include a preset sequence, continue to perform FEC decoding on the FEC codewords after the first FEC codeword in the data sequence until the first preset sequence is found.

[0173] Optionally, the decoding module 1620 is further configured to: if the decoded first codeword includes a preset sequence, perform FEC decoding on a second FEC codeword following the first FEC codeword in the data sequence to obtain a decoded second codeword, wherein an interval between the second FEC codeword and the first FEC codeword is a period in which the preset sequence appears in the data sequence;

[0174] The searching module 1630 is further configured to attempt to search for a preset sequence in the decoded second codeword.

[0175] Optionally, the decoding module 1620 is used to: perform FEC decoding on a first FEC codeword in the data sequence using a first decoding method; and perform FEC decoding on a candidate FEC codeword following the first FEC codeword in the data sequence using a second decoding method.

[0176] Optional; the first decoding method is soft decision decoding, and the second decoding method is hard decision decoding; or, the first decoding method is hard decision decoding, and the second decoding method is soft decision decoding.

[0177] Optionally, the apparatus 1600 further includes a synchronization module 1650, configured to determine the FEC codeword boundary in the data sequence by self-synchronization.

[0178] Optionally, the preset sequence is FS or the preset sequence is in AM.

[0179] Optionally, the data sequence is obtained based on an Ethernet signal received from an Ethernet interface.

[0180] Optionally, the Ethernet signal is a Terabit Ethernet signal.

[0181] The device 1600 for processing data provided in the embodiment of the present application can also be implemented by an application-specific integrated circuit (ASIC) or a programmable logic device (PLD), and the above-mentioned PLD can be a complex programmable logical device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof. Some steps of the method for processing data provided in the above-mentioned method embodiment can also be implemented by software. When some steps of the method for processing data provided in the above-mentioned method embodiment are implemented by software, some modules in the device 1600 for processing data are software modules. Optionally, the acquisition module 1610, the decoding module 1620 and the synchronization module 1650 are all hardware modules, and the search module 1630 and the deletion module 1640 are all software modules.

[0182] In another implementation, the device includes: a memory, a processor, and a communication interface. The communication interface includes an Ethernet interface; the memory is used to store a computer program; the processor is used to execute the computer program stored in the memory so that the device performs the following steps: Fig.11 or Fig.12 The relevant steps in the method embodiment shown, for example, enable the device to execute steps S1103, S1105, etc.

[0183] In one embodiment, please refer to Fig.17 , which shows a schematic diagram of another apparatus 1700 for processing data provided in an embodiment of the present application. The apparatus 1700 may be a forwarding device, a user terminal device, or a server device. The apparatus 1700 includes at least one processor 1701 ( Fig.17 Taking two processors 1701 as an example), a communication bus 1702, a memory 1703, and at least one communication interface 1704, the at least one processor 1701, the memory 1703, and the at least one communication interface 1704 are connected via the communication bus 1702. The at least one processor 1701, the memory 1703, and the at least one communication interface 1704 may also be connected in other connection modes besides the communication bus 1702.

[0184] The memory 1703 is used to store the computer program for executing the technical solution of the present application and is controlled to be executed by the processor 1701. The computer program stored in the memory 1703 includes but is not limited to program code, program instructions, data, etc. The memory 1703 may be a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a random access memory (RAM) or other types of dynamic storage devices that can store information and instructions, or may be a non-volatile random access memory (NVRAM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, an optical disc storage (including a compressed optical disc, a laser disc, an optical disc, a digital versatile disc, a Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited to these. The memory 1703 may exist independently and be connected to the processor 1701 via the communication bus 1702. The memory 1703 may also be integrated with the processor 1701, which is not limited in the embodiment of the present application.

[0185] Processor 1701 can be a general-purpose processor or a special-purpose processor. A general-purpose processor is a processor that performs specific steps and / or operations by reading and executing a computer program stored in a memory (e.g., memory 1703). The general-purpose processor may use a computer program stored in a memory (e.g., memory 1703) in the process of performing the above steps and / or operations. The stored computer program can be executed to implement the related functions of the aforementioned search module 1630, deletion module 1650, etc. A general-purpose processor is, for example, but not limited to, a central processing unit (CPU). A special-purpose processor is a processor specially designed to perform specific steps and / or operations, and a special-purpose processor is, for example, but not limited to, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. Processor 1701 can implement or execute various logic blocks, modules, and circuits described in conjunction with the disclosure of the embodiments of the present application. Processor 1701 can also be a combination that implements a computing function, for example, including a combination of one or more microprocessors, a combination of a DSP and a microprocessor, and the like. The processor can be used to: find a preset sequence in at least one decoded codeword, where the at least one decoded codeword is obtained by performing FEC decoding on at least one FEC codeword in a data sequence, where the data sequence includes multiple FEC codewords; and, if a preset condition is met, delete a padding sequence related to the preset sequence in the data sequence according to the position of the found preset sequence in the data sequence, where the preset condition includes that the number of the preset sequence included in n codewords in the at least one decoded codeword reaches a first threshold, n is a positive integer, and the interval between adjacent codewords in the n codewords is the period during which the preset sequence appears in the data sequence.

[0186] The communication bus 1702 is used to transmit information between the processor 1701, the communication interface 1704 and the memory 1703. The communication bus 1702 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus. The communication bus 1702 can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Fig.17 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0187] The communication interface 1704 includes an input / output (I / O) interface, a physical interface, and a logical interface, etc., which are used to realize the interconnection of devices inside the device 1700, and an interface for realizing the interconnection of the device 1700 with other communication devices. The physical interface can be an Ethernet interface, a fast Ethernet (FE) interface, a gigabit Ethernet (GE) interface, a terabit Ethernet (TbE) interface, a 400G Ethernet interface, an asynchronous transfer mode (ATM) interface, etc., which are used to realize the interconnection of the device 1700 with other devices. The logical interface is an interface inside the device 1700, which is used to realize the interconnection of devices inside the device 1700. It is easy to understand that the communication interface 1704 is used for the device 1700 to communicate with other devices, for example, the communication interface 1704 is used for sending and receiving Ethernet signals between the device 1700 and other devices or communication networks. The communication interface 1704 may be a device using any transceiver, and the communication network may be Ethernet, optical transport network (OTN), secret private network (SPN), fiber channel, infiniband, etc.

[0188] In a specific implementation, as an embodiment, the apparatus 1700 includes multiple processors 1701, each of which may be a single-CPU processor or a multi-CPU processor. The processor here may refer to one or more devices, circuits and / or processing cores for processing data (e.g., computer program instructions).

[0189] In a specific embodiment, the communication interface 1704 in the device 1700 is used to receive an Ethernet signal carrying a data sequence, and the processor 1701 is used to: obtain the data sequence in the Ethernet signal, perform FEC decoding on at least one FEC codeword in the data sequence to obtain at least one decoded codeword, and search for a preset sequence in the at least one decoded codeword. Please refer to the above for the detailed processing process of the processor 1701 Fig.11 and Fig.12 The relevant description in the illustrated method embodiment will not be repeated here.

[0190] In another embodiment, please refer to Fig.18, which shows a schematic diagram of another apparatus 1800 for processing data provided in an embodiment of the present application. The apparatus 1800 may be a forwarding device, such as a switch or a router. Fig.18 As shown, the device 1800 includes a main control board and one or more interface boards, and the main control board is connected to the interface board in communication. The main control board is also called a main processing unit (MPU) or a route processing card. The main control board is responsible for the control and management of each component in the device 1800, including routing calculation, equipment management and maintenance functions. The interface board is also called a line processing unit (LPU) or a line card. The interface board is used to forward data. In some embodiments, the device 1800 may also include a switching fabric board, which is connected to the main control board and the interface board in communication. The switching fabric board is used to forward data between the interface boards. The switching fabric board may also be called a switch fabric unit (SFU). The interface board includes a central processing unit, a memory, a forwarding chip and a physical interface card (PIC). The central processing unit is connected to the memory, the forwarding chip and the physical interface card in communication. The memory is used to store a forwarding table. The forwarding chip is used to forward the received data frame based on the forwarding table stored in the memory. If the destination address of the data frame is the address of the device 1800, the data frame is sent to the CPU for processing; if the destination address of the data frame is not the address of the device 1800, the next hop and the output interface corresponding to the destination address are found in the forwarding table according to the destination address, and the data frame is forwarded to the output interface corresponding to the destination address. The forwarding chip can be a network processor (NP). The PIC is also called a daughter card, which can be installed on the interface board and is responsible for converting the photoelectric signal into a data frame and forwarding the data frame to the forwarding chip for processing after checking the legitimacy of the data frame. In some embodiments, the central processing unit can also perform the functions of the forwarding chip, such as implementing software forwarding based on a general-purpose CPU, so that the forwarding chip is not required in the interface board. The communication connection between the main control board, the interface board, and the switching network board can be realized through a bus. The forwarding chip can be implemented by ASIC or FPGA.

[0191] Logically, the device 1800 includes a control plane and a forwarding plane. The control plane includes a main control board and a central processing unit, and the forwarding plane includes various components for performing forwarding, such as a memory, a PIC, and an NP. The control plane performs functions such as generating a forwarding table for the router, processing signaling and protocol messages, and configuring and maintaining the status. The control plane sends the generated forwarding table to the forwarding plane. On the forwarding plane, the NP forwards the message received by the PIC of the device 1800 based on the forwarding table sent by the control plane. The forwarding table sent by the control plane can be stored in the memory. In some embodiments, the control plane and the forwarding plane can be completely separated and not on the same device.

[0192] In a specific embodiment, the interface board is used to receive an Ethernet signal, obtain a data sequence from the Ethernet signal, the data sequence includes multiple FEC codewords, and perform FEC decoding on at least one FEC codeword in the data sequence to obtain at least one decoded codeword. For the specific process, please refer to the description in S1101 to S1102 above. The main control board is used to search for a preset sequence in the at least one decoded codeword. For the specific process, please refer to the description in S1103 above, which will not be repeated here.

[0193] In a possible implementation, an inter-process communication (IPC) channel is established between the main control board and the interface board, and the main control board and the interface board communicate through the IPC channel.

[0194] Based on the same inventive concept, the present application embodiment provides a chip for executing Fig.11 or Fig.12 The method provided by the illustrated embodiment.

[0195] Optionally, the chip is a main chip or a chip in an optical module. The chip includes a programmable logic circuit and / or program instructions.

[0196] Optionally, the chip can be used in cascade FEC encoding scenarios and non-cascade FEC encoding scenarios. Specifically, cascade FEC encoding includes outer FEC encoding and inner FEC encoding, and the corresponding FEC decoding includes inner FEC decoding and outer FEC decoding. The chip provided in the embodiment of the present application is used for inner FEC decoding and / or outer FEC decoding. The non-cascade FEC encoding scenario includes a layer of FEC encoding, and the corresponding FEC decoding includes a layer of FEC decoding. The chip provided in the embodiment of the present application is used for the layer of FEC decoding.

[0197] Based on the same inventive concept, an embodiment of the present application provides a computer-readable storage medium, in which a computer program is stored, and when the computer program is executed (for example, by a forwarding device, a user terminal device, a server device, a main chip, an optical module or a chip in an optical module, etc.), the following is implemented: Fig.11 and Fig.12 The steps of the method embodiment shown are, for example, steps S1103 and S1105.

[0198] Based on the same inventive concept, an embodiment of the present application provides a computer program product, which includes a program or code, and when the program or code is executed (for example, by a forwarding device, a user terminal device, a server device, a main chip, an optical module or a chip in an optical module, etc.), the following is implemented: Fig.11 and Fig.12 The steps of the method embodiment shown are, for example, steps S1103 and S1105.

[0199] Based on the same inventive concept, an embodiment of the present application provides a communication system, which includes an optical module and a host, wherein the optical module is communicatively connected to the host, for example, the optical module is plugged into the host, and the optical module is used to perform the following steps: Fig.11 and Fig.12 The method embodiment is shown.

[0200] Optionally, the host is a forwarding device, a user terminal device or a server device. The forwarding device is a router or a switch.

[0201] Optionally, the communication system is a network system such as Ethernet, optical transport network (OTN), secret private network (SPN), fiber channel, or infinite bandwidth (infiniband).

[0202] The technical solution provided in the embodiment of the present application is that the optical module is used to perform the following Fig.11 and Fig.12 In the method embodiment shown, the optical module performs the following steps: Fig.11 and Fig.12 The method embodiment shown can improve the efficiency, accuracy and reliability of searching for a preset sequence in a data sequence, thereby enabling a host connected to the optical module to obtain corresponding benefits, such as improving the host's processing efficiency and reliability of the data sequence.

[0203] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product, and the computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website site, a computer, a server or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server, a data center, etc. that contains one or more available media integrated. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium, or a semiconductor medium (e.g., a solid-state hard disk), etc.

[0204] It should be understood that the term "at least one" in this application refers to one or more, and "plurality" refers to two or more. In this application, unless otherwise specified, the symbol " / " generally means or, for example, A / B can represent A or B. The term "and / or" in this application is merely a description of the association relationship of associated objects, indicating that three relationships may exist, for example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. For the sake of clarity, in this application, words such as "first", "second", and "third" are used to distinguish between identical or similar items with substantially the same functions and effects. Those skilled in the art will understand that words such as "first", "second", and "third" do not limit the quantity and execution order.

[0205] The different types of embodiments such as the method embodiments and device embodiments provided in the embodiments of the present application can refer to each other, and the embodiments of the present application are not limited thereto. The sequence of operations of the method embodiments provided in the embodiments of the present application can be appropriately adjusted, and the operations can also be increased or decreased in response to the situation. Any technician familiar with the technical field can easily think of the changed methods within the technical scope disclosed in the present application, and they should be included in the protection scope of the present application, so they will not be repeated.

[0206] In the corresponding embodiments provided in the present application, it should be understood that the disclosed devices and the like can be implemented by other configuration methods. For example, the device embodiments described above are only schematic, for example, the division of units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, and the indirect coupling or communication connection of devices or units can be electrical or other forms.

[0207] The units described as separate components may or may not be physically separated, and the components described as units may or may not be physical units, and may be located in one place or distributed on multiple network nodes. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0208] The above is only an exemplary embodiment of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A method for processing data, characterized in that: The method comprises: Acquire a data sequence, wherein the data sequence includes a plurality of forward error correction (FEC) code words; Performing FEC decoding on at least one FEC codeword in the data sequence to obtain at least one decoded codeword; A preset sequence is found in the at least one decoded codeword.

2. The method according to claim 1, characterized in that The preset sequence is a sequence that appears periodically in the data sequence.

3. The method according to claim 2, characterized in that The method comprises: If a preset condition is met, a padding sequence related to the preset sequence in the data sequence is deleted according to the position of the preset sequence found in the data sequence, wherein the preset condition includes that the number of the preset sequences included in n codewords of the at least one decoded codeword reaches a first threshold, n is a positive integer, and the interval between adjacent codewords in the n codewords is the period of appearance of the preset sequence in the data sequence.

4. The method according to claim 2 or 3, characterized in that: The method comprises: If the lock-loss condition is met, the FEC codeword boundary in the data sequence is searched again, and the lock-loss condition includes that the number of m codewords in the at least one decoded codeword that do not include the preset sequence reaches a second threshold, m is a positive integer, and the interval between adjacent codewords in the m codewords is the period of the preset sequence appearing in the data sequence.

5. The method according to any one of claims 2 to 4, characterized in that: The performing FEC decoding on at least one FEC codeword in the data sequence to obtain at least one decoded codeword comprises: performing FEC decoding on the multiple FEC codewords to obtain multiple decoded codewords; The finding a preset sequence in the at least one decoded codeword includes: finding a preset sequence in the multiple decoded codewords.

6. The method according to any one of claims 2 to 4, characterized in that: The performing FEC decoding on at least one FEC codeword in the data sequence to obtain at least one decoded codeword, and finding a preset sequence in the at least one decoded codeword, comprises: Performing FEC decoding on a first FEC codeword in the data sequence to obtain a decoded first codeword; If the decoded first codeword does not include the preset sequence, FEC decoding is continued on the FEC codewords after the first FEC codeword in the data sequence until a first preset sequence is found.

7. The method according to claim 6, characterized in that The performing FEC decoding on at least one FEC codeword in the data sequence to obtain at least one decoded codeword, and finding a preset sequence in the at least one decoded codeword, further comprises: If the decoded first codeword includes the preset sequence, FEC decoding is performed on a second FEC codeword following the first FEC codeword in the data sequence to obtain a decoded second codeword, wherein an interval between the second FEC codeword and the first FEC codeword is a period during which the preset sequence appears in the data sequence; Try to find the preset sequence in the decoded second codeword.

8. The method according to claim 6 or 7, characterized in that: The performing FEC decoding on at least one FEC codeword in the data sequence comprises: Performing FEC decoding on the first FEC codeword in the data sequence using a first decoding method; The candidate FEC codewords following the first FEC codeword in the data sequence are FEC decoded using a second decoding method.

9. The method according to claim 8, It is characterized by: The first decoding mode is soft decision decoding, and the second decoding mode is hard decision decoding; or, The first decoding mode is hard decision decoding, and the second decoding mode is soft decision decoding.

10. The method according to any one of claims 1 to 9, characterized in that: Before performing FEC decoding on at least one FEC codeword in the data sequence, the method further includes: determining a FEC codeword boundary in the data sequence by self-synchronization.

11. The method according to any one of claims 1 to 10, characterized in that: The preset sequence is a frame sequence FS or the preset sequence is in an alignment mark AM.

12. The method according to any one of claims 1 to 11, characterized in that: The method is executed by a main chip, an optical module or a chip in an optical module.

13. The method according to any one of claims 1 to 12, characterized in that: The data sequence is obtained according to an Ethernet signal received from an Ethernet interface.

14. The method according to claim 13, characterized in that The Ethernet signal is a Terabit Ethernet signal.

15. A device for processing data, characterized in that: Used to perform the method according to any one of claims 1 to 14.

16. The device according to claim 15, characterized in that The device comprises an Ethernet interface.

17. The device according to claim 15 or 16, characterized in that The device is any one of the following: a forwarding device, a user terminal device or a server device, a main chip, an optical module or a chip in an optical module.

18. A chip, characterized in that: Used to perform the method according to any one of claims 1 to 14.

19. The chip according to claim 18, characterized in that: The chip is a main chip or a chip in an optical module.

20. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, which, when executed, implements: finding a preset sequence in a decoded codeword; wherein the decoded codeword is obtained by performing FEC decoding on a forward error correction (FEC) codeword in a data sequence, and the data sequence includes multiple FEC codewords.

21. A communication system, characterized in that: It comprises an optical module and a host, and the optical module is used to execute the method according to any one of claims 1 to 14.

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