Calibration system and calibration method for frequency offset of serial communication interface

Abstract

The invention provides a serial communication interface frequency offset calibration system and calibration method, and relates to the technical field of serial communication, the calibration system comprises an analog front end module used for receiving a data signal sent by a host, extracting corresponding data edge information, and sending the data edge information to the analog front end module; the data edge information represents a time point of a rising edge or a falling edge of the data signal; the signal comparison module is used for comparing an internal clock signal of the equipment with the data edge information to generate frequency offset information; the frequency offset coefficient generation module is used for calculating and processing the frequency offset information based on a preset modulation coefficient to generate a frequency offset modulation coefficient; and the phase-locked loop module is used for performing frequency adjustment on the internal clock signal according to the frequency offset modulation coefficient. According to the invention, the clock signal in the equipment can follow the frequency offset of the clock signal of the host in real time, the hardware overhead is saved, and the equipment compatibility is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of serial communication, and in particular to a calibration system and method for a frequency deviation of a serial communication interface. Background Art

[0002] PCIe (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard that is now widely used. In PCIe communication, the device usually uses the 100MHz SSC (Spread Spectrum Clocking) signal provided by the host as the reference input of the device's PLL (Phase-Locked Loop). Since the triangular wave spread spectrum frequency of the SSC clock signal is relatively slow, it can be approximately considered that the device's clock frequency is consistent with the host. Then, the 100MHz reference clock stability information transmitted by the host through the PERST signal is used to ensure clock synchronization.

[0003] However, the above-mentioned homologous reference clock solution strongly relies on the 100MHz differential clock and PERST signal, which adds additional hardware cost and complexity. In addition, when the SSC clock signal is used between the host and the device, compatibility issues are usually encountered because the time points from the activation of the PERST signal to the stable output of the 100MHz reference clock are inconsistent for different hosts. Therefore, there is room for improvement. Summary of the invention

[0004] The object of the present invention is to provide a serial communication interface frequency deviation calibration system and calibration method, which are used to solve the technical problems in the prior art that the same-source reference clock solution has poor compatibility and increases additional hardware cost and complexity.

[0005] In order to solve the above technical problems, the present invention is achieved through the following technical solutions:

[0006] The present invention provides a calibration system for a serial communication interface frequency deviation, which is applied to a device connected to a host in serial communication, and comprises:

[0007] An analog front-end module, used to receive a data signal sent by a host and extract corresponding data edge information, wherein the data edge information represents a time point of a rising edge or a falling edge of the data signal;

[0008] A signal comparison module, used to compare the internal clock signal of the device with the data edge information to generate frequency deviation information;

[0009] A frequency deviation coefficient generating module, used to calculate and process the frequency deviation information based on a preset modulation coefficient to generate a frequency deviation modulation coefficient;

[0010] A phase-locked loop module is used to adjust the frequency of the internal clock signal according to the frequency deviation modulation coefficient.

[0011] In one embodiment of the present invention, the phase-locked loop module is provided with a voltage-controlled oscillator, and the voltage-controlled oscillator is used to generate the internal clock signal.

[0012] In one embodiment of the present invention, the signal comparison module includes:

[0013] A phase detector, used to compare the phase error between the internal clock signal of the device and the data edge information to generate phase error information;

[0014] The second-order low-pass filter is used to perform integration processing on the phase error information to generate frequency deviation information.

[0015] In one embodiment of the present invention, the signal comparison module further includes a phase interpolator, and the phase interpolator is used to adjust the phase of the internal clock signal.

[0016] In one embodiment of the present invention, the second-order low-pass filter is also used to generate phase adjustment information based on the phase error information, and the phase interpolator is also used to perform phase adjustment on the internal clock signal based on the phase adjustment information, and send the adjusted internal clock signal to the phase detector.

[0017] In one embodiment of the present invention, the second-order low-pass filter is provided with a proportional path and an integral path, wherein the proportional path is used to generate phase adjustment information according to the amplitude of the phase error information, and the integral path is used to generate frequency deviation information according to the integration of the phase error information over time.

[0018] In one embodiment of the present invention, the integration path is a 16-bit integration path accumulator.

[0019] In one embodiment of the present invention, the frequency deviation modulation coefficient is expressed as:

[0020]

[0021] Among them, f vco represents the frequency of the internal clock signal, f ref represents the clock frequency of the data signal, 2 23 is the scaling factor, the floor() function is used to round down, and the dec2hex() function is used to convert the calculation result into hexadecimal representation. represents the proportional value of the frequency deviation information, and k represents the preset modulation coefficient.

[0022] The present invention also provides a method for calibrating a frequency deviation of a serial communication interface, comprising:

[0023] Receive a data signal sent by a host, and extract corresponding data edge information, wherein the data edge information represents a time point of a rising edge or a falling edge of the data signal;

[0024] Compare and process the internal clock signal of the device with the data edge information to generate frequency deviation information;

[0025] Based on a preset modulation coefficient, the frequency deviation information is calculated and processed to generate a frequency deviation modulation coefficient;

[0026] The frequency of the internal clock signal is adjusted according to the frequency deviation modulation coefficient.

[0027] In one embodiment of the present invention, the step of comparing the internal clock signal of the device with the data edge information to generate the frequency deviation information includes:

[0028] Comparing a phase error between an internal clock signal of a device and the data edge information to generate phase error information;

[0029] generating phase adjustment information and frequency deviation information according to the phase error information;

[0030] The internal clock signal is phase adjusted according to the phase adjustment information.

[0031] As described above, the present invention provides a calibration system and method for the frequency deviation of a serial communication interface, which has the following beneficial effects: the present invention can realize that the internal clock signal of the device follows the frequency deviation of the SSC clock signal of the host in real time, solves the dependence on the host 100MHz reference clock in PCIe communication, saves hardware overhead, and improves device compatibility.

[0032] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0034] Figure 1 The figure is a schematic diagram of the structure of a system for calibrating the frequency deviation of a serial communication interface in one embodiment of the present invention.

[0035] Figure 2 FIG. 4 is a schematic diagram of the structure of a signal comparison module in an embodiment of the present invention.

[0036] Figure 3 It is a schematic diagram of an internal clock signal of a device following a host clock signal in one embodiment of the present invention.

[0037] Figure 4 Schematic diagram of the frequency difference between the internal clock signal of the device and the clock signal of the host in one embodiment of the present invention.

[0038] Figure 5 The figure is a flow chart of a method for calibrating a frequency deviation of a serial communication interface according to an embodiment of the present invention.

[0039] In the figure:

[0040] 100. Equipment; 110. Analog front-end module; 120. Signal comparison module; 121. Phase detector; 122. Second-order low-pass filter; 123. Phase interpolator; 130. Frequency deviation coefficient generation module; 140. Phase-locked loop module.

[0041] 200 hosts;

[0042] 301, first frequency curve; 302, second frequency curve. DETAILED DESCRIPTION

[0043] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0044] First of all, it should be noted that PCIe (Peripheral Component Interconnect Express) high-speed interface communication is a high-speed serial bus standard widely used in modern computer systems. It is used to connect various components inside the computer, such as graphics cards, storage devices, network adapters, etc. The PCIe specification supports two reference clock architectures: common reference clock architecture and independent reference clock architecture. In the independent reference clock architecture, the transmitter and receiver each have an independent 100MHz local reference clock. In PCIe communication, frequency deviation (Jitter) refers to the change or fluctuation of the clock signal relative to its ideal position. Frequency deviation can be divided into many types, including random frequency deviation, periodic frequency deviation, and deterministic frequency deviation. Frequency deviation directly affects the quality of the signal and the performance of the system. When there is a frequency deviation difference between the 100MHz local clocks at both ends, the clock after multiplication by the internal PLL (Phase-Locked Loop) will also have a frequency deviation difference.

[0045] In the prior art homologous reference clock solution, the device uses the 100MHz SSC (Spread Spectrum Clocking) signal provided by the host as the reference clock input of the PLL (Phase-Locked Loop) to achieve clock synchronization between the device and the host. However, this method increases hardware overhead and may cause compatibility issues between different hosts.

[0046] In SSC (Spread Spectrum Clocking) communication, the data clock is modulated by a low frequency (such as a 30kHz-33kHz triangle wave) to reduce electromagnetic interference (EMI). This modulation causes the frequency and phase of the clock signal to change continuously, so a mechanism is needed to ensure that the receiving end (device) can accurately follow these changes.

[0047] The present invention provides a calibration system and method for the frequency deviation of a serial communication interface, which relates to the field of serial communication technology and can be specifically applied to solve the technical problems of poor compatibility of a homologous reference clock solution, as well as additional hardware cost and complexity. The present invention uses CDR (Clock Data Recovery) to detect SSC frequency deviation and calculate the PLL frequency modulation coefficient, which can effectively synchronize the clock signal of a device with a host, while reducing hardware overhead and improving compatibility. The following is a detailed description through specific embodiments.

[0048] See also Figure 1In one embodiment of the present invention, a calibration system for a serial communication interface frequency deviation of the present invention may include an analog front-end module 110, a signal comparison module 120, a frequency deviation coefficient generation module 130, and a phase-locked loop module 140. The calibration system may be applied to a device 100 that is connected to a host 200 for communication. The analog front-end module 110 is electrically connected to the host 200, and may be used to receive a data signal transmitted by the host 200, and extract corresponding data center information and data edge information from the data signal. The signal comparison module 120 is electrically connected to the analog front-end module 110, and may be used to compare and process an internal clock signal of the device 100 with the data edge information, generate phase adjustment information and frequency deviation information, and may perform phase adjustment on the internal clock signal according to the phase adjustment information. The frequency deviation coefficient generation module 130 is electrically connected to the signal comparison module 120, and may be used to calculate and process the frequency deviation information based on a preset modulation coefficient, and generate a frequency deviation modulation coefficient. The phase-locked loop module 140 is electrically connected between the signal comparison module 120 and the frequency deviation coefficient generation module 130, and can be used to adjust the frequency of the internal clock signal of the device according to the phase adjustment information and the frequency deviation modulation coefficient.

[0049] In one embodiment of the present invention, in a signal processing or communication system, the analog front-end module 110 may be responsible for capturing analog signals from various sensors, devices or other signal sources, and an analog-to-digital converter (ADC) is integrated in the analog front-end module 110, which can convert the collected analog signals into digital signals, or pre-process the analog signals for subsequent digital processing. In this embodiment, the data signal output by the host 200 is an analog signal. The analog front-end module 110 is the starting point for processing the data signal sent by the host 200. It first performs analog-to-digital conversion on the data signal sent by the host 200, and then extracts the corresponding data center information and data edge information from the converted data signal. Among them, the data center information refers to the effective value of the data, that is, the actual value of the data bit (0 or 1). The data edge information refers to the time point of the rising edge or falling edge of the data signal. The data edge information is crucial for recovering the clock signal, which provides the moment when the data changes.

[0050] In one embodiment of the present invention, the signal comparison module 120 performs a phase comparison between the internal clock signal of the device 100 and the data edge information to generate phase adjustment information and frequency deviation information. The phase adjustment information is to measure the phase difference between the data edge information and the internal clock signal to determine whether the internal clock signal needs to be adjusted to better align with the data signal. The frequency deviation information is to estimate the average frequency deviation between the clock signal of the data signal and the internal clock signal through statistical analysis of the phase difference over a period of time. This deviation can be represented by a coefficient for subsequent frequency adjustment.

[0051] See also Figure 2 In one embodiment of the present invention, the signal comparison module 120 may include a phase detector 121, a second-order low-pass filter 122, and a phase interpolator 123. The phase detector 121 is electrically connected to the analog front-end module 110. The second-order low-pass filter 122 is electrically connected to the phase detector 121. The phase interpolator 123 is electrically connected between the second-order low-pass filter 122 and the phase detector 121. The phase detector 121 can be used to detect the phase difference between two signals. Specifically, the phase detector 121 is used to detect the phase difference between the clock signal (i.e., data edge information) in the data signal sent by the host 200 (host) and the clock signal output by the phase interpolator 123, thereby generating error information. The second-order low-pass filter 122 is an electronic filter that allows signals below the cutoff frequency to pass, while signals above the cutoff frequency are weakened or blocked. In signal processing, the second-order low-pass filter 122 can be used to remove noise, smooth signals, etc. In this embodiment, the second-order low-pass filter 122 receives the error information from the phase detector 121 and generates the phase adjustment information and the frequency deviation information according to the error information. The phase interpolator 123 can be used to adjust the phase of the internal clock signal according to the phase adjustment information and transmit the adjusted internal clock signal to the phase detector 121.

[0052] In one embodiment of the present invention, a voltage-controlled oscillator (VCO) is provided in the phase-locked loop module 140. A voltage-controlled oscillator is an oscillation circuit whose output frequency corresponds to an input control voltage. Its working state or the component parameters of the oscillation circuit are controlled by the input control voltage, thereby changing the output frequency. The voltage-controlled oscillator is used to generate an internal clock signal of the device 100. In this embodiment, the phase interpolator 123 is also electrically connected to the voltage-controlled oscillator. The phase interpolator 123 obtains the internal clock signal of the device 100 from the voltage-controlled oscillator, and aligns the clock edge of the internal clock signal with the center point of the clock signal in the data signal according to the phase adjustment information.

[0053] In one embodiment of the present invention, a proportional path and an integral path are provided in the second-order low-pass filter 122. Among them, the proportional path can be used to process the phase information of the signal, and it can generate phase adjustment information according to the amplitude of the phase error information. In this embodiment, the proportional path directly amplifies the input error signal, quickly responds to the phase change, and ensures that the sampling clock can quickly follow the phase change of the data center. The integral path can be used to process the frequency deviation, and it can generate the frequency deviation information according to the accumulation of the phase error information over time. In this embodiment, when there is a frequency mismatch between the host 200 and the device, the integral path gradually adjusts the clock frequency of the device by accumulating the error signal to achieve long-term stable synchronization. The processing mechanism of the integral path ensures that even if there is a slight frequency deviation, it can be compensated by time accumulation.

[0054] In one embodiment of the present invention, when the integration path uses a 16-bit integration path accumulator, the frequency deviation information outputted by the integration path can be expressed as tlf i (15:0). Further, the output of the integral path is converted into a proportional value between 0 and 1. The proportional value can be expressed as:

[0055]

[0056] In one embodiment of the present invention, the frequency deviation coefficient generation module 130 is used to generate a frequency deviation modulation coefficient according to the frequency deviation coefficient. The frequency deviation modulation coefficient is used to indicate how the phase-locked loop module 140 adjusts its output frequency to compensate for the detected frequency deviation. The frequency deviation modulation coefficient can be expressed as:

[0057]

[0058] Among them, f vco represents the output frequency of the voltage-controlled oscillator (VCO), i.e. the target frequency, f ref Indicates the reference clock frequency, 2 23 is the scaling factor in the frequency division or multiplication calculation, the floor() function is used to round down, and the dec2hex() function is used to convert the calculation result into hexadecimal representation. In this embodiment, Represents the ratio of the frequency deviation of the integration path. The integration path accumulator is 16 bits. K represents the modulation coefficient, which represents the deviation ratio between the clock frequency of the device at this time and the SSC signal frequency of the host 200.

[0059] In one embodiment of the present invention, the phase-locked loop module 140 is used to adjust the internal clock signal of the device 100 according to the frequency deviation modulation coefficient. Specifically, the phase-locked loop module 140 controls the frequency offset of the output signal of the voltage-controlled oscillator according to the frequency deviation modulation coefficient. By adjusting the frequency deviation modulation coefficient, the frequency of the clock signal can be accurately controlled.

[0060] Furthermore, in one embodiment of the present invention, the phase-locked loop module 140 can also accurately control the phase of the voltage-controlled oscillator (VCO) output signal according to the phase adjustment information, so that it is synchronized with the phase of the reference signal or changes in a predetermined manner. This helps to reduce the phase error of the clock signal and improve the stability and synchronization of the system.

[0061] See also Figure 3 In one embodiment of the present invention, the serial communication interface frequency deviation calibration system of the present invention is applied on the device side, the first frequency curve 301 is the triangular wave SSC frequency output by the simulated host, the center frequency is 2.5GHz, the spread spectrum range is ±6.25MHz, and the second frequency curve 302 is the device modulation frequency. Figure 3 As shown, the frequency output by the phase-locked loop module 140 of the device can always follow the triangle wave SSC frequency modulation of the host.

[0062] See also Figure 4 , the maximum frequency difference between the second frequency curve 302 and the first frequency curve 301 is -666.6kHz and 491kHz, and the frequency difference is converted into frequency deviation, which is -266ppm and 196ppm. It can be seen that there is no need to rely on the 100M clock sent by the host as a reference clock to achieve very good frequency following, saving hardware overhead. Furthermore, for the M.2 protocol, the complex power-on sequence can be omitted. As long as the host powers on the device, the device can be powered on and lock the phase-locked loop module, saving initialization time and avoiding compatibility issues between different hosts.

[0063] In one embodiment of the present invention, if in the datasheet of the relevant interface product, it is not clearly stated to use a 100 MHz host reference clock, or when a 100 MHz reference clock is used, by capturing the online transmission (TX) waveform it is found that the TX signal appears before the reset signal (PERST), then it can be roughly determined that the product adopts the technical solution of the present invention.

[0064] See also Figure 5 The present invention further provides a method for calibrating a frequency deviation of a serial communication interface, which is applied to a system for calibrating a frequency deviation of a serial communication interface in any of the above embodiments and may include the following steps:

[0065] Step S100, receiving a data signal sent by a host, and extracting corresponding data edge information, where the data edge information represents the time point of a rising edge or a falling edge of the data signal;

[0066] Step S200: Compare the internal clock signal of the device with the data edge information to generate frequency deviation information;

[0067] Step S300: Based on a preset modulation coefficient, the frequency deviation information is calculated and processed to generate a frequency deviation modulation coefficient;

[0068] Step S400: adjusting the frequency of the internal clock signal according to the frequency deviation modulation coefficient.

[0069] In one embodiment of the present invention, when step S100 is executed, the data signal sent by the host is received, and the corresponding data edge information is extracted, and the data edge information represents the time point of the rising edge or falling edge of the data signal. Specifically, the data signal sent by the host 200 is first converted into a digital analog, and then the corresponding data center information and data edge information are extracted from the converted data signal. Among them, the data center information refers to the effective value of the data, that is, the actual value of the data bit (0 or 1). The data edge information refers to the time point of the rising edge or falling edge of the data signal.

[0070] In one embodiment of the present invention, when executing step S200, the internal clock signal of the device is compared with the data edge information to generate frequency deviation information. Specifically, the following steps may be included:

[0071] Step S210, comparing the phase error between the internal clock signal of the device and the data edge information to generate phase error information;

[0072] Step S220, generating phase adjustment information and frequency deviation information according to the phase error information;

[0073] Step S230: perform phase adjustment on the internal clock signal according to the phase adjustment information.

[0074] In one embodiment of the present invention, when step S210 is executed, the phase error between the internal clock signal of the device and the data edge information is compared to generate phase error information. Specifically, the phase difference between the clock signal (i.e., data edge information) in the data signal sent by the host 200 (host) and the clock signal output by the phase interpolator 123 is compared to generate error information.

[0075] In one embodiment of the present invention, when step S220 is executed, phase adjustment information and frequency offset information are generated according to the phase error information. Specifically, the following steps may be included:

[0076] Step S221, generating phase adjustment information according to the amplitude of the phase error information;

[0077] Step S222: Generate frequency deviation information according to the accumulation of phase error information over time.

[0078] In one embodiment of the present invention, when executing step S221 to step S222, specifically, a proportional path and an integral path are provided in the second-order low-pass filter 122. Among them, the proportional path can be used to process the phase information of the signal, and it can generate phase adjustment information according to the amplitude of the phase error information. In this embodiment, the proportional path directly amplifies the input error signal, quickly responds to the phase change, and ensures that the sampling clock can quickly follow the phase change of the data center. The integral path can be used to process the frequency deviation, and it can generate the frequency deviation information according to the accumulation of the phase error information over time. In this embodiment, when there is a frequency mismatch between the host 200 and the device, the integral path gradually adjusts the clock frequency of the device by accumulating the error signal to achieve long-term stable synchronization. The processing mechanism of the integral path ensures that even if there is a slight frequency deviation, it can be compensated by time accumulation.

[0079] In one embodiment of the present invention, when step S230 is executed, the internal clock signal is phase-adjusted according to the phase adjustment information. Specifically, the internal clock signal is phase-adjusted according to the phase adjustment information, and the adjusted internal clock signal is transmitted to the phase detector 121 .

[0080] In one embodiment of the present invention, when executing step S300, the frequency deviation information is calculated and processed based on the preset modulation coefficient to generate the frequency deviation modulation coefficient. Specifically, when the integral path uses a 16-bit integral path accumulator, the frequency deviation information outputted by it can be expressed as tlf i (15:0). The output of the integral path is converted into a proportional value between 0 and 1. The proportional value can be expressed as:

[0081]

[0082] In this embodiment, based on the preset modulation coefficient, the frequency deviation information is calculated and processed to generate the frequency deviation modulation coefficient. The frequency deviation modulation coefficient is used to indicate how to adjust its output frequency to compensate for the detected frequency deviation. The frequency deviation modulation coefficient can be expressed as:

[0083]

[0084] Among them, f vco represents the output frequency of the voltage-controlled oscillator (VCO), i.e. the target frequency, fref Indicates the reference clock frequency, that is, the clock signal contained in the data signal output by the host. 23 is the scaling factor, the floor() function is used to round down, and the dec2hex() function is used to convert the calculation result into hexadecimal representation. In this embodiment, represents the ratio of the frequency deviation of the integration path, k represents the preset modulation coefficient, and represents the deviation ratio between the clock frequency of the device at this time and the SSC signal frequency of the host 200.

[0085] In one embodiment of the present invention, when step S400 is executed, the frequency of the internal clock signal is adjusted according to the frequency deviation modulation coefficient. Specifically, the frequency offset of the output signal of the voltage-controlled oscillator (VCO) is controlled according to the frequency deviation modulation coefficient. By adjusting the frequency deviation modulation coefficient, the frequency of the clock signal can be accurately controlled.

[0086] Furthermore, in one embodiment of the present invention, the phase of the voltage-controlled oscillator output signal can also be precisely controlled according to the phase adjustment information so that it is synchronized with the phase of the reference signal or changes in a predetermined manner. This helps to reduce the phase error of the clock signal and improve the stability and synchronization of the system.

[0087] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architecture, functions and operations of the systems, methods and application structures according to various embodiments of the present invention. Among them, each box in the flowchart or block diagram can represent a module, a program segment, or a part of a code, and the above-mentioned module, program segment, or a part of the code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, and the combination of boxes in the block diagram or flowchart, can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0088] The modules involved in the embodiments of the present invention may be implemented by software or hardware, and the modules described may also be arranged in a processor. The names of these modules do not, in some cases, limit the modules themselves.

[0089] In summary, the present invention provides a calibration system and method for the frequency deviation of a serial communication interface, which can solve the technical problems that the homologous reference clock scheme in the prior art has poor compatibility and adds additional hardware cost and complexity. The present invention generates a frequency modulation coefficient by calculating the output of the integral path channel in the signal comparison module, and modulates the frequency of the phase-locked loop module accordingly, so that the internal clock signal of the device follows the frequency deviation of the SSC clock signal of the host in real time, solves the dependence on the host 100MHz reference clock in PCIe communication, saves hardware overhead, and improves device compatibility.

[0090] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A calibration system for a serial communication interface frequency deviation, characterized in that: Applicable to devices connected to the host serial communication, including: An analog front-end module, used to receive a data signal sent by a host and extract corresponding data edge information, wherein the data edge information represents a time point of a rising edge or a falling edge of the data signal; A signal comparison module, used to compare the internal clock signal of the device with the data edge information to generate frequency deviation information; A frequency deviation coefficient generating module, used to calculate and process the frequency deviation information based on a preset modulation coefficient to generate a frequency deviation modulation coefficient; A phase-locked loop module is used to adjust the frequency of the internal clock signal according to the frequency deviation modulation coefficient.

2. The serial communication interface frequency deviation calibration system according to claim 1, characterized in that: The phase-locked loop module is provided with a voltage-controlled oscillator, and the voltage-controlled oscillator is used to generate the internal clock signal.

3. The serial communication interface frequency deviation calibration system according to claim 1, characterized in that: The signal comparison module comprises: A phase detector, used to compare the phase error between the internal clock signal of the device and the data edge information to generate phase error information; The second-order low-pass filter is used to perform integration processing on the phase error information to generate frequency deviation information.

4. The serial communication interface frequency deviation calibration system according to claim 3, characterized in that: The signal comparison module further includes a phase interpolator, and the phase interpolator is used to adjust the phase of the internal clock signal.

5. The serial communication interface frequency deviation calibration system according to claim 4, characterized in that: The second-order low-pass filter is also used to generate phase adjustment information according to the phase error information, and the phase interpolator is also used to perform phase adjustment on the internal clock signal according to the phase adjustment information, and send the adjusted internal clock signal to the phase detector.

6. The serial communication interface frequency deviation calibration system according to claim 2, characterized in that: The second-order low-pass filter is provided with a proportional path and an integral path, wherein the proportional path is used to generate phase adjustment information according to the amplitude of the phase error information, and the integral path is used to generate frequency deviation information according to the integration of the phase error information over time.

7. The serial communication interface frequency deviation calibration system according to claim 6, characterized in that: The integration path is a 16-bit integration path accumulator.

8. The serial communication interface frequency deviation calibration system according to claim 7, characterized in that: The frequency deviation modulation coefficient is expressed as: Among them, f vco represents the frequency of the internal clock signal, f ref represents the clock frequency of the data signal, 2 23 is the scaling factor, the floor() function is used to round down, and the dec2hex() function is used to convert the calculation result into hexadecimal representation. represents the proportional value of the frequency deviation information, and k represents the preset modulation coefficient.

9. A method for calibrating a frequency deviation of a serial communication interface, characterized in that: include: Receive a data signal sent by a host, and extract corresponding data edge information, wherein the data edge information represents a time point of a rising edge or a falling edge of the data signal; Compare and process the internal clock signal of the device with the data edge information to generate frequency deviation information; Based on a preset modulation coefficient, the frequency deviation information is calculated and processed to generate a frequency deviation modulation coefficient; The frequency of the internal clock signal is adjusted according to the frequency deviation modulation coefficient.

10. The method for calibrating the frequency deviation of a serial communication interface according to claim 9, characterized in that: The step of comparing the internal clock signal of the device with the data edge information to generate frequency deviation information comprises: Comparing a phase error between an internal clock signal of a device and the data edge information to generate phase error information; generating phase adjustment information and frequency deviation information according to the phase error information; The internal clock signal is phase adjusted according to the phase adjustment information.

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