High-voltage-withstanding Ga2O3 vertical power diode with composite terminal and preparation method of high-voltage-withstanding Ga2O3 vertical power diode
By introducing a composite terminal structure of the ion implantation region and dielectric layer into the gallium oxide power diode, and deposition of nickel oxide thin films in combination with the ICP-CVD process, the problems of heat dissipation difference and reverse leakage of the gallium oxide power diode are solved, and the effects of high withstand voltage and low leakage are achieved, which are suitable for high power and high voltage fields.
Patent Information
- Application Number
- CN202411673974.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-21
- Publication Date
- 2025-03-04
AI Technical Summary
The existing gallium oxide power diodes have problems such as heat dissipation and large reverse leakage, which leads to their withstand voltage and reliability that do not meet the application requirements in the field of high power.
A high-voltage Ga2O3 vertical power diode structure with composite terminals is adopted, and an ion implantation region and a dielectric layer are introduced at the top of the n-Ga2O3 epitaxial layer to form an edge terminal of the ring structure, and a high-quality nickel oxide film is deposited in conjunction with the ICP-CVD process.
It significantly reduces the reverse leakage of the device, improves the breakdown voltage, enhances the withstand voltage and reliability of the diode, and is suitable for high-power and high-voltage fields.
Smart Images
Figure CN119562531A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of semiconductor devices, and mainly relates to high-performance gallium oxide devices, specifically a high-voltage Ga2O3 vertical power diode with a composite terminal and a preparation method, which can be used to prepare high-voltage and low-leakage current gallium oxide devices. The diode in the present invention can be used in the field of high power and high voltage. Background Art
[0002] Gallium oxide is divided into five crystal forms: α, β, γ, δ and ε. Among them, monoclinic β-Ga2O3 has the best thermal stability and is easy to produce, so it has been widely studied. The band gap of β-Ga2O3 is 4.6eV-4.9eV, and the critical breakdown field strength is about 8MV / cm, which is more than 20 times that of Si and more than twice that of SiC and GaN. The electron mobility is 250-300cm at 300k. 2 / Vs, the saturation electron rate is 2×10 7 cm / s. Due to the above superior properties, the Baliga figure of merit of β-Ga2O3 has reached over 3000, far exceeding the third-generation semiconductors 4H-SiC and GaN. Power semiconductor devices based on β-Ga2O3 have great potential in high-frequency, high-voltage, and high-power applications.
[0003] Ga2O3 materials currently on the market usually use Sn as the n-type doping element, and Sn can regulate the carriers of n-Ga2O3 crystals over a large range. In β-Ga2O3, p-type doping is difficult to achieve due to the self-compensation of Ga and O vacancies, the deep acceptor energy levels formed by various impurity doping, and the low solubility of dopants. NiO has a wide bandgap of 3.8-4.2eV and a large critical breakdown electric field of about 5MV / cm. Since NiO is also an oxide semiconductor, it can avoid the interface oxidation effect when forming a heterojunction with n-Ga2O3, making it the preferred material for forming a heterojunction with n-Ga2O3. The heterojunction diode formed by n-Ga2O3 and p-NiO has a large breakdown voltage.
[0004] In the field of power devices, heat generation under high-power environments is also an important issue. As the operating temperature of the device increases, the electron mobility will decrease, causing the device on-resistance to increase. Since the thermal conductivity of Ga2O3 material is only 0.2W / cm·K, which is 8 times lower than GaN and 30 times lower than SiC, gallium oxide-based devices have worse heat dissipation efficiency than wide bandgap semiconductor devices made of other materials. This is a serious disadvantage of Ga2O3 materials. As the temperature and breakdown voltage of high-voltage power devices made of Ga2O3 materials increase, their reverse leakage current will also increase significantly, increasing device energy loss and causing device performance to decline.
[0005] In existing research, p-NiO material is usually used as a substitute for p-type gallium oxide material. However, since the peak electric field at the anode edge of the heterojunction diode made of p-NiO / n-Ga2O3 is difficult to suppress, its reverse leakage is more obvious, and it is difficult to have a significant breakthrough in the breakdown voltage. The withstand voltage has not yet reached the theoretical limit of gallium oxide materials.
[0006] In summary, in the existing research on gallium oxide power diodes, there are still problems with poor heat dissipation and large reverse leakage of the device, which makes the voltage resistance and reliability of this gallium oxide power device still not meet its large-scale application in the high-power field. Summary of the invention
[0007] The purpose of the present invention is to address the problems and shortcomings of the prior art and to propose a high-voltage Ga2O3 vertical power diode with a composite terminal that reduces leakage current and a preparation method thereof.
[0008] The invention discloses a high withstand voltage Ga2O3 vertical power diode with a composite terminal. The diode is provided with, from bottom to top, a cathode, a substrate, an epitaxial layer, an ion implantation region, a dielectric layer, a p-type NiO thin film layer covering a passivation layer, and an anode metal layer covering a device surface. The diode is characterized in that the epitaxial layer is an n-Ga2O3 gallium oxide material epitaxial layer, the top of the epitaxial layer is provided with an ion implantation region, a p-type NiO thin film layer is provided above the dielectric layer, and from a top view, the ion implantation region, the dielectric layer and the NiO thin film layer are all annular structures, the inner diameter of the dielectric layer is slightly larger than the ion implantation region, the inner diameter of the NiO thin film layer is the same as the inner diameter of the dielectric layer, the dielectric layer and the ion implantation region on the top of the n-Ga2O3 epitaxial layer serve as two edge terminals, and the whole diode constitutes a high withstand voltage, low leakage and low power consumption Ga2O3 vertical power diode.
[0009] The present invention is also a method for preparing a high-voltage Ga2O3 vertical power diode with a composite terminal, which realizes the preparation of any high-voltage Ga2O3 vertical power diode with a composite terminal described in claims 1-4, characterized in that a dielectric layer of 20nm-100nm is deposited on the outer side of the upper surface of the n-Ga2O3 epitaxial layer by atomic layer deposition, and a p-type NiO film with a thickness of 200nm-400nm is deposited on the upper surface of the dielectric layer by low temperature deposition, and the ion implantation area on the top of the dielectric layer and the n-Ga2O3 epitaxial layer serves as an edge terminal of a high resistivity region to withstand a higher electric field, and includes the following steps:
[0010] 1) Select and pre-treat the substrate: select a doping concentration of 1e18cm -3 -3e18 cm -3The n-type β-Ga2O3 single crystal substrate has a thickness ranging from 300 nm to 500 nm, and is ultrasonically cleaned in acetone solution, anhydrous ethanol, and deionized water for 5 min each, and then dried with nitrogen to obtain a pretreated substrate;
[0011] 2) Making cathode: depositing metal Ti / Au with a thickness of 60nm / 120nm on the back area of the substrate by electron beam evaporation E-Beam system to form a cathode;
[0012] 3) Cleaning the epitaxial wafer: Select a homoepitaxial gallium oxide epitaxial wafer with a thickness of 5 μm-10 μm and clean it, that is, put the gallium oxide epitaxial wafer into an acetone solution and an anhydrous ethanol solution in turn, ultrasonically clean it for 5 min-10 min each, then rinse it with a large amount of deionized water, and then blow dry it with nitrogen to obtain the cleaned epitaxial wafer, that is, the epitaxial layer of the device;
[0013] 4) Photolithography to form the area to be ion implanted: Photolithography is performed on the cleaned epitaxial wafer, that is, firstly, photoresist is coated on the upper surface of the n-Ga2O3 epitaxial wafer, and then pre-baking, alignment and exposure, post-baking, development, hardening and pattern detection are performed to obtain a photoresist-protected area with a width of 30μm-100μm on the upper surface of the epitaxial wafer;
[0014] 5) Ion implantation: Ion implantation is performed on the area to be implanted after photolithography is completed to form a doping concentration of 5e19cm -3 , a high-doped region with a depth of 300-800nm, and then annealing the epitaxial wafer after ion implantation. In a N2 environment, the furnace annealing temperature is set to 800℃-950℃, and the annealing time is 20min-40min to activate the implanted ions;
[0015] 6) Deposition of dielectric layer: The dielectric layer is deposited by atomic layer deposition (ALD) process, using trimethylaluminum (TMA) and water (H2O) as precursors to deposit a dielectric layer with a thickness of 20nm-100nm on the surface.
[0016] 7) Wet etching of dielectric layer: first, photolithography is performed on the surface of the dielectric layer to obtain a photoresist-protected area with a ring width of 4 μm-20 μm on the upper surface of the epitaxial wafer, and finally, the epitaxial wafer with photoresist is immersed in BOE solution for 3-10 seconds to obtain a dielectric layer with a thickness of 20nm-100nm in the shape of a ring in top view;
[0017] 8) Deposition of p-type NiO layer: first, photolithography is performed on the upper surface of the device so that the photoresist covers the upper surface of the n-Ga2O3 epitaxial layer not covered by the dielectric layer, and then an inductively coupled plasma chemical device, i.e., a low-temperature deposition device ICP-CVD is used to deposit a p-type NiO film, specifically, a p-type NiO film with a thickness of 200nm-400nm is deposited in the area not covered by the photoresist, and the photoresist is washed off;
[0018] 9) Deposition of anode metal layer: Ni / Au with a thickness of 50nm / 200nm-60nm / 300nm is deposited on the top of the device through the electron beam evaporation E-Beam system to form an anode metal layer, and form ohmic contacts with the p-type NiO film and n-Ga2O3 epitaxial layer respectively to complete the high-voltage Ga2O3 vertical power diode with composite terminal.
[0019] The present invention solves the reverse leakage problem caused by the low thermal conductivity of β-Ga2O3 materials in the prior art. The present invention takes a different approach and introduces an ion implantation region and a dielectric layer between n-Ga2O3 and p-NiO as the ion implantation terminal and dielectric edge terminal of the device. The present invention also obtains a high-quality dielectric layer pattern through a wet etching process, and uses an ICP-CVD process to quickly deposit a high-quality nickel oxide film with good uniformity and high density under low temperature and low pressure conditions, which significantly reduces the reverse leakage of the device and increases the breakdown voltage.
[0020] The present invention has the following advantages:
[0021] The present invention can effectively reduce reverse leakage current and improve the breakdown voltage of the device: the present invention adopts a vertical diode structure, which is conducive to heat dissipation and reducing the conduction voltage drop, and introduces ion injection terminals and dielectric edge terminals. The ion injection terminal can effectively regulate the carrier concentration at the top of the epitaxial layer, forming a high resistivity area at the top of the epitaxial layer, effectively improving the withstand voltage; the dielectric edge terminal plays an isolation role, isolating the ion injection area and the p-type NiO layer, effectively reducing the reverse leakage of the device, and the dielectric layer can also be used as the field plate structure of the device, effectively alleviating the electric field concentration effect, and further improving the withstand voltage. The present invention also introduces a variety of terminal structures, so that the device has a significant improvement in withstand voltage and reliability.
[0022] The prepared nickel oxide film has better uniformity and higher density: When depositing the NiO film, the present invention applies the inductively coupled plasma chemical vapor deposition ICP-CVD process to form a large-area, high-uniformity and high-electron-density plasma under low temperature and low pressure conditions, which can quickly deposit a high-quality nickel oxide film with good uniformity and high density. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Figure 1This is a schematic diagram of the structure of a high-voltage Ga2O3 vertical power diode with a composite terminal according to the present invention;
[0024] Figure 2 A schematic diagram of the process flow of a high-voltage Ga2O3 vertical power diode with a composite terminal according to the present invention;
[0025] Figure 3 The present invention is a flowchart of the steps for preparing a high-voltage Ga2O3 vertical power diode with a composite terminal. DETAILED DESCRIPTION
[0026] Example 1
[0027] In the preparation of p-NiO / n-Ga2O3 heterojunction, the peak electric field at the edge of the anode is difficult to suppress, resulting in a relatively obvious reverse leakage current in such devices, and the breakdown voltage is therefore limited. Different edge terminals need to be introduced according to the bandgap width, the degree of lattice matching, and various effects generated when different materials are in contact to suppress the peak electric field at the edge of the anode. The present invention conducts research on this and proposes a high-voltage Ga2O3 vertical power diode with a composite terminal.
[0028] The present invention is a high-voltage Ga2O3 vertical power diode with a composite terminal, which is provided with, from bottom to top: a cathode 1, a substrate 2, an epitaxial layer 3, an ion implantation region 4, a dielectric layer 5, a p-type NiO thin film layer 6 covering the dielectric layer, and an anode metal layer 7 covering the surface of the device, see Figure 1 . Figure 1 The schematic diagram of the structure of the Ga2O3 vertical power diode with high withstand voltage and low leakage of the present invention is shown in the figure. The epitaxial layer 3 of the present invention is epitaxial of n-Ga2O3 material, and an ion implantation area 4 is provided on the top of the epitaxial layer 3. A p-type NiO film layer 6 is provided above the dielectric layer 5. From a top view, the ion implantation area 4, the dielectric layer 5 and the NiO film layer 6 are all annular structures. The inner diameter of the dielectric layer 5 is slightly larger than the ion implantation area 4. Different types of ion implantation and different dielectric materials can be selected according to different device sizes. The inner diameter of the NiO film layer 6 is the same as that of the dielectric layer 5. The dielectric layer 5 and the ion implantation area 4 on the top of the n-Ga2O3 epitaxial layer 3 serve as two edge terminals, and the whole constitutes a Ga2O3 vertical power diode with high withstand voltage, low leakage and low power consumption.
[0029] The present invention aims at the problem of reverse leakage of Ga2O3 power diodes, introduces ion implantation edge terminals and dielectric edge terminals during the research process, and forms a novel gallium oxide vertical power diode solution.
[0030] The present invention is an overall technical solution, which introduces an ion implantation edge terminal to effectively reduce the carrier concentration on the outside of the top of the epitaxial layer, so that the ion implantation area is subjected to a higher electric field, and then introduces a dielectric edge terminal to further share the electric field, and serves as a field plate terminal to alleviate the electric field concentration effect at the edge of the device. The two edge terminals constitute a composite terminal structure as a whole, which effectively reduces the reverse leakage of the device and improves the breakdown voltage of the device.
[0031] The present invention improves the heat dissipation capability and reduces the conduction voltage drop by using a vertical diode structure, and introduces ion implantation terminals and dielectric edge terminals to form a high resistivity region at the edge of the device, effectively regulating the carrier concentration of the epitaxial layer, transferring the peak electric field when the device breaks down to the edge terminal, and alleviating the electric field concentration effect at the edge of the device, thereby effectively improving the breakdown voltage and realizing a new gallium oxide vertical power diode with good performance and high reliability.
[0032] Example 2
[0033] The structure of the high-voltage Ga2O3 vertical power diode with a composite terminal is the same as that of Example 1. In the present invention, the total thickness of the n-Ga2O3 epitaxial layer 3 is 5μm-10μm, the depth of the ion implantation area 4 on the top of the epitaxial layer 3 is 300nm-800nm, and the top view shape is a circular ring with a ring width of 3μm-18μm. The type of ion implantation can be N, P ion implantation or Mg ion implantation. The dielectric material of the dielectric layer 5 on the top of the ion implantation area 4 can be SiO2 or Al2O3, with a thickness of 20nm-100nm, and the top view shape is a circular ring with a ring width of 4μm-20μm. The NiO thin film layer 6 on the top of the dielectric layer 5 has a thickness of 200nm-400nm, and the top view shape is the same as that of the dielectric layer 5.
[0034] This example provides three specific combinations of epitaxial layer thickness, ion implantation area size and implantation type, dielectric layer size and dielectric material type, and NiO film layer thickness and size. The specific parameter combinations are as follows:
[0035] 1. Select an epitaxial layer with a thickness of 10μm, ion implantation is N and P ion implantation, the depth is 800nm, the ring width is 18μm, the dielectric layer material is SiO2, the thickness is 100nm, and the ring width is 20μm. This allows the terminal area to withstand a larger peak electric field, alleviate the current edge effect to a greater extent, and make the device have lower leakage and better breakdown characteristics. In this example, a 400nm thick NiO film is selected to allow enough p-region holes to enter the n-region, thereby triggering a hole superinjection effect and reducing the on-resistance.
[0036] 2. Select an epitaxial layer with a thickness of 5μm, ion implantation is N and P ion implantation, the depth is 300nm, the ring width is 3μm, the dielectric layer material is Al2O3, the thickness is 20nm, the ring width is 4μm, and the NiO film thickness can be set to 200nm. This can make the device have a smaller size, lower preparation cost, higher integration of the manufactured circuit, and minimize the impact of parasitic capacitance and surface defects of the epitaxial layer.
[0037] 3. Select an epitaxial layer with a thickness of 7μm, Mg ion implantation, a depth of 500nm, a ring width of 10μm, a dielectric layer material of SiO2, a thickness of 50nm, a ring width of 12μm, and a NiO film thickness of 300nm. This allows the device to achieve a better balance between size, cost, breakdown voltage, and parasitic capacitance.
[0038] This example gives three specific combinations of the thickness of the epitaxial layer of the present invention, the size and injection type of the ion implantation area, the size and material type of the dielectric layer, and the thickness and size of the NiO thin film layer. In addition to the three combinations given in this embodiment, there can be more combinations within the scope given in this example, and it cannot be determined that the specific implementation of the present invention is limited to these three combinations.
[0039] Example 3
[0040] The structure of the high-voltage Ga2O3 vertical power diode with a composite terminal is the same as that of Example 1-2. The cathode 1 of the present invention adopts a Ti / Au material with a thickness of 60nm / 200nm, and the anode metal layer 7 adopts a Ni / Au material with a thickness of 50nm / 200nm-60nm / 300nm.
[0041] Selecting Ti / Au metal as the cathode material of the device makes the device more suitable for use in high temperature environments, and protects the device to a certain extent, reducing the DC power consumption of the device. Selecting Ni / Au metal as the anode of the device can make the device have good ohmic contact, and the conductivity of the anode will be improved. When the anode thickness is set to 50nm / 200nm, the overall size of the device can be optimized and the manufacturing cost is lower; when the anode thickness is set to 60nm / 300nm, the device can have better ohmic contact; when the anode thickness is set to 55nm / 250nm, the cost and efficiency of device preparation can be well balanced. The thickness of the gate metal layer is not limited to the three thicknesses given above, and any thickness between 50nm / 200nm-60nm / 300nm can be used as a reasonable anode metal layer thickness.
[0042] Example 4
[0043] The structure of the high-voltage Ga2O3 vertical power diode with composite termination is the same as that of Examples 1-3. The substrate 2 in the present invention is a Ga2O3 substrate with a thickness of 300nm-500nm.
[0044] In the present invention, a Ga2O3 substrate is selected to ensure that the device has a high reverse breakdown voltage and a low preparation cost, and the substrate thickness is selected to be between 300nm and 500nm, so that the device has better current characteristics. When the substrate thickness is set to 300nm, the device size is reduced and the forward conduction resistance is reduced; when the substrate thickness is set to 500nm, the overall withstand voltage of the device can be improved; when the substrate thickness is set to 400nm, the device has a high withstand voltage characteristic while having a lower forward conduction resistance. The substrate layer thickness is not limited to the three thicknesses given above, and a reasonable substrate thickness can be between 300nm and 500nm.
[0045] Example 5
[0046] The present invention is also a method for preparing a high-voltage Ga2O3 vertical power diode with a composite terminal. For the preparation of any of the above-mentioned high-voltage and low-leakage Ga2O3 vertical power diodes, the structure of the high-voltage and low-leakage Ga2O3 vertical power diode is the same as that of Embodiments 1-4, see Figure 3 , Figure 3 The present invention is a flowchart of the preparation process of the Ga2O3 vertical power diode with high withstand voltage and low leakage. The outer side of the upper surface of the n-Ga2O3 epitaxial layer 3 of the present invention is deposited with a dielectric layer 5 of 20nm-100nm by atomic layer deposition, and the upper surface of the dielectric layer 5 is deposited with a p-type NiO film 6 of 200nm-400nm thickness by low temperature deposition. The dielectric layer 5 and the ion implantation area 4 on the top of the n-Ga2O3 epitaxial layer 3 serve as edge terminals of the high resistivity region, and the steps are as follows:
[0047] 1) Select and pre-treat the substrate: select a doping concentration of 1e18cm -3 -3e18 cm -3 The n-type β-Ga2O3 single crystal substrate with a thickness ranging from 300nm to 500nm is ultrasonically cleaned in acetone solution, anhydrous ethanol, and deionized water for 5 minutes respectively, and then dried with nitrogen to obtain a pretreated substrate.
[0048] 2) Fabrication of cathode: Metal Ti / Au is deposited on the back area of the substrate by electron beam evaporation E-Beam system with a thickness of 60nm / 120nm to form a cathode.
[0049] 3) Cleaning the epitaxial wafer: Select a homoepitaxial gallium oxide epitaxial wafer with a thickness of 5μm-10μm and clean it, that is, put the gallium oxide epitaxial wafer into acetone solution and anhydrous ethanol solution in turn, ultrasonically clean it for 5min-10min each, then rinse it with a large amount of deionized water, and then blow it dry with nitrogen to obtain the cleaned epitaxial wafer, that is, the epitaxial layer of the device.
[0050] 4) Photolithography to form the area to be ion implanted: Photolithography is performed on the cleaned epitaxial wafer, that is, firstly, photoresist is coated on the upper surface of the n-Ga2O3 epitaxial wafer, and then through pre-baking, alignment and exposure, post-baking, development, hardening and pattern detection, a photoresist-protected area with a width of 30μm-100μm on the upper surface of the epitaxial wafer is obtained.
[0051] 5) Ion implantation to obtain a high resistivity ion implantation area: Ion implantation is performed on the area to be implanted after photolithography is completed to form a doping concentration of 5e19cm -3 , a highly doped area with a depth of 300-800nm. After that, the epitaxial wafer after ion implantation is annealed. In a N2 environment, the annealing temperature in the furnace is set to 800℃-950℃, and the annealing time is 20min-40min to activate the implanted ions, and finally a high resistivity ion implantation area at the top of the epitaxial layer is obtained.
[0052] 6) Deposition of dielectric layer: The dielectric layer is deposited by atomic layer deposition (ALD) process, using trimethylaluminum (TMA) and water (H2O) as precursors to deposit a dielectric layer with a thickness of 20 nm to 100 nm on the surface.
[0053] 7) Wet etching of dielectric layer: First, the dielectric layer surface is subjected to a photolithography process to obtain a photoresist-protected area with a ring width of 4μm-20μm on the upper surface of the epitaxial wafer. Finally, the epitaxial wafer with the photoresist is immersed in a BOE solution for 3-10 seconds. Through the isotropy of the F ions in the BOE solution on the dielectric layer material, a high-quality circular dielectric layer with a thickness of 20nm-100nm is obtained.
[0054] 8) Deposition of p-type NiO layer: First, the upper surface of the device is subjected to a photolithography process so that the photoresist covers the upper surface of the n-Ga2O3 epitaxial layer not covered by the dielectric layer, and then an inductively coupled plasma chemical equipment, i.e., a low-temperature deposition equipment ICP-CVD is used to deposit a p-type NiO film. Specifically, a p-type NiO film with a thickness of 200nm-400nm is deposited in the area not covered by the photoresist, and the photoresist is washed off.
[0055] 9) Deposition of anode metal layer: Ni / Au with a thickness of 50nm / 200nm-60nm / 300nm is deposited on the top of the device through the electron beam evaporation E-Beam system to form an anode metal layer, and form ohmic contacts with the p-type NiO film and n-Ga2O3 epitaxial layer respectively to complete the high-voltage Ga2O3 vertical power diode with composite terminal.
[0056] The present invention is an overall technical solution, which effectively regulates the carrier concentration on the surface of the epitaxial layer through an ion implantation process, obtains a high-quality dielectric layer pattern through a wet etching process, and completes a high-voltage Ga2O3 vertical power diode with a composite terminal.
[0057] The present invention solves the reverse leakage problem caused by the low thermal conductivity of β-Ga2O3 materials in the prior art. The present invention adopts a vertical structure, which is conducive to heat dissipation and reducing the on-state voltage drop. At the same time, ion implantation terminals and dielectric edge terminals are introduced to form a high resistivity area at the edge of the device, effectively reducing the carrier concentration of the epitaxial layer, and transferring the peak electric field when the device breaks down to the edge terminal, which significantly reduces the reverse leakage of the device and improves the breakdown voltage.
[0058] Example 6
[0059] The high-voltage Ga2O3 vertical power diode with composite terminal and the preparation method thereof are the same as in Examples 1-5. In step 2) of the present invention, an electron beam evaporation E-Beam system is used to deposit cathode metal Ti / Au on the back area of the substrate, and the process conditions are as follows:
[0060] Evaporation rate: 0.1-20A / s
[0061] Pre-evaporation power: 5-45
[0062] Evaporation power: 0-60
[0063] Working vacuum: 5e-4Pa
[0064] Working temperature: 20℃-200℃.
[0065] The present invention adopts an electron beam evaporation E-Beam system to deposit high-quality and high-density cathode metal Ti / Au on the back area of the substrate to form a device cathode and form a good ohmic contact with the back of the substrate.
[0066] Example 7
[0067] The high withstand voltage Ga2O3 vertical power diode with composite terminal and the preparation method thereof are the same as in Examples 1-6. In step 6) of the present invention, the dielectric layer is deposited by atomic layer deposition ALD process, and the process conditions are as follows:
[0068] Reaction chamber pressure: 880Pa
[0069] Reaction chamber gas: high purity nitrogen
[0070] Reaction chamber gas flow rate: 300sccm
[0071] Al2O3 growth rate: 0.5nm / min
[0072] Al2O3 growth time: 40min-100min.
[0073] The present invention adopts the atomic layer deposition ALD process to deposit the dielectric layer, thereby obtaining a dielectric layer with high density and smooth surface. The obtained dielectric layer has high resistivity and good quality.
[0074] Example 8
[0075] The high withstand voltage Ga2O3 vertical power diode with composite terminal and the preparation method thereof are the same as in Examples 1-7. In step 7) of the present invention, a low temperature deposition device ICP-CVD is used to deposit a p-type NiO film, and the process conditions are as follows:
[0076] Reaction chamber pressure: 10mTorr
[0077] Ionization voltage: 1.8-4.5KV
[0078] Plasma ionization electrode: Ni
[0079] Reaction chamber gases: O2, N2, Ar.
[0080] The present invention uses an inductively coupled plasma chemical vapor deposition (ICP-CVD) process to form a large-area, high-uniformity, and high-electron-density plasma under low temperature and low pressure conditions, thereby generating a NiO film with a low impurity content. Under this ionization voltage, a NiO film with a thickness of 300 nm and a smooth surface can be generated.
[0081] Example 9
[0082] The high-voltage Ga2O3 vertical power diode with a composite terminal and the preparation method thereof are the same as in Examples 1-8. The high-voltage Ga2O3 vertical power diode with a composite terminal and the preparation process of the present invention are further described in detail below in conjunction with the accompanying drawings.
[0083] The present invention introduces ion implantation terminals and dielectric edge terminals, forms a high resistivity region at the edge of the device, effectively regulates the carrier concentration of the epitaxial layer, transfers the peak electric field when the device breaks down to the edge terminal, and alleviates the electric field concentration effect at the edge of the device, thereby effectively increasing the breakdown voltage, enhancing the performance of the diode, and improving its reliability.
[0084] Reference Figure 1The high-voltage Ga2O3 vertical power diode with composite terminal of the present invention comprises: a cathode 1, a substrate 2, an epitaxial layer 3, an ion implantation region 4, a dielectric layer 5, a p-type NiO thin film layer 6 covering the dielectric layer, and an anode metal layer 7 covering the surface of the device, see Figure 1 , Figure 1 This is a schematic diagram of the structure of a Ga2O3 vertical power diode with high withstand voltage and low leakage of the present invention. The epitaxial layer 3 of the present invention is an epitaxial growth of n-Ga2O3 material, and the top of the epitaxial layer 3 is provided with an ion implantation area 4. A p-type NiO thin film layer 6 is provided above the dielectric layer 5. From a top-down perspective, the ion implantation area 4, the dielectric layer 5 and the NiO thin film layer 6 are all annular structures, the inner diameter of the dielectric layer 5 is slightly larger than the ion implantation area 4, the inner diameter of the NiO thin film layer 6 is the same as the inner diameter of the dielectric layer 5, the dielectric layer 5 and the ion implantation area 4 on the top of the n-Ga2O3 epitaxial layer serve as two edge terminals, and the whole constitutes a Ga2O3 vertical power diode with high withstand voltage, low leakage and low power consumption.
[0085] Reference Figure 2 , Figure 2 The present invention is a schematic diagram of the process flow of a high-voltage Ga2O3 vertical power diode with a composite terminal. The present invention provides the following three more detailed implementation instructions for preparing a high-voltage Ga2O3 vertical power diode with a composite terminal:
[0086] 1. On a 300nm thick gallium oxide substrate and a 5μm thick n-type gallium oxide homoepitaxial wafer, N and P ion implantation with a ring width of 3μm and a depth of 300nm is performed, and an Al2O3 dielectric layer with a thickness of 20nm and a ring width of 4μm is deposited. The NiO film thickness is 200nm, and the anode metal is Ni / Au with a thickness of 50nm / 200nm.
[0087] Step 1, cleaning the epitaxial wafer, such as Figure 2 (a) Figure 2 (a) shows the pre-processed substrate and epitaxial wafer.
[0088] A homoepitaxial gallium oxide epitaxial wafer with a thickness of 5 μm is selected and cleaned, that is, the gallium oxide epitaxial wafer is sequentially placed in an acetone solution and an anhydrous ethanol solution for ultrasonic cleaning for 5 minutes each, then rinsed with a large amount of deionized water, and then dried with nitrogen to obtain the cleaned epitaxial wafer;
[0089] Step 2, make the cathode, such as Figure 2 (b), 2(b) A cathode is deposited on the back side of the substrate.
[0090] Ti / Au with a thickness of 60nm / 200nm is deposited on the back area of the substrate by an electron beam evaporation E-Beam system to form a cathode;
[0091] Step 3, photolithography forms the area to be ion implanted, such as Figure 2 (c) Figure 2 (c) Photoresist covers the surface of the epitaxial layer.
[0092] Performing photolithography on the cleaned epitaxial wafer, that is, first coating the upper surface of the n-Ga2O3 epitaxial wafer with photoresist, and then performing pre-baking, alignment and exposure, post-baking, development, hardening and pattern detection to obtain a photoresist-protected area with a width of 30 μm on the upper surface of the epitaxial wafer;
[0093] Step 4, ion implantation, such as Figure 2 (d) Figure 2 (d) is the ion implantation area.
[0094] N and P ions are implanted into the area to be implanted after photolithography to form a doping concentration of 5e19cm -3 , a high-doped region with a depth of 300nm, and then annealing the epitaxial wafer after ion implantation. In a N2 environment, the furnace annealing temperature is set to 800℃ and the annealing time is 20min to activate the implanted ions;
[0095] Step 5, depositing a dielectric layer, such as Figure 2 (e) Deposit a full dielectric layer over the epitaxial layer and ion implantation areas.
[0096] Through the atomic layer deposition ALD process, trimethylaluminum TMA and water H2O are used as precursors to deposit a 20nm thick Al2O3 dielectric layer on the surface;
[0097] Step 6, wet etching the dielectric layer, such as Figure 2 (f) Figure 2 (f) is a dielectric layer that is annular in top view.
[0098] First, the surface of the dielectric layer is subjected to a photolithography process to obtain a photoresist-protected area with a ring width of 4 μm on the upper surface of the epitaxial wafer, and then the epitaxial wafer with the photoresist is immersed in a BOE solution for 3 seconds to obtain a 20 nm thick Al2O3 dielectric layer in the shape of a ring in a top view;
[0099] Step 7, depositing a NiO layer, such as Figure 2 (g) Figure 2 (g) shows a ring-shaped p-type NiO thin film layer.
[0100] First, the upper surface of the device is subjected to a photolithography process so that the photoresist covers the upper surface of the n-Ga2O3 epitaxial layer not covered by the dielectric layer, and then a p-type NiO film with a thickness of 200 nm is deposited in the area not covered by the photoresist using inductively coupled plasma chemical vapor deposition (ICP-CVD), and the photoresist is washed away;
[0101] Step 8, depositing an anode metal layer, such as Figure 2 (h), Figure 2 (h) Depositing a high-quality anode metal layer on the device surface.
[0102] Ni / Au with a thickness of 50nm / 200nm is deposited on the top of the device through the electron beam evaporation E-Beam system to form an anode metal layer, and form ohmic contacts with the p-type NiO film and n-Ga2O3 epitaxial layer respectively to complete a high-voltage Ga2O3 vertical power diode with a composite terminal.
[0103] 2. On a 400nm thick gallium oxide substrate and a 7μm thick n-type gallium oxide homoepitaxial wafer, Mg ion implantation with a ring width of 10μm and a depth of 500nm is performed, and a SiO2 dielectric layer with a thickness of 50nm and a ring width of 12μm is deposited. The NiO film thickness is 300nm, and the anode metal is Ni / Au with a thickness of 55nm / 250nm.
[0104] Step 1: Clean the sample, such as Figure 2 (a).
[0105] 1.1) transferring a 7 μm thick n-Ga2O3 epitaxial wafer onto a 400 nm thick n-Ga2O3 substrate;
[0106] 1.2) The transferred samples were placed in acetone solution and anhydrous ethanol solution for ultrasonic cleaning for 8 minutes each, then rinsed with a large amount of deionized water and then dried with nitrogen.
[0107] Step 2: Make a cathode, such as Figure 2 (b).
[0108] 2.1) Deposit the drain electrode on the back of the substrate by using an electron beam evaporation E-Beam system to deposit Ti / Au with a thickness of 60nm / 200nm on the substrate;
[0109] 2.2) Place the sample in an annealing furnace, set the annealing temperature in the furnace to 500°C and the annealing time to 1 min in a N2 environment to form a cathode of good quality.
[0110] Step 3: Photolithography to form the area to be ion implanted, such as Figure 2 (c).
[0111] Photolithography is performed on the upper surface of the cleaned n-Ga2O3 epitaxial wafer, that is, firstly, photoresist is coated on the upper surface of the n-Ga2O3 epitaxial wafer, and then pre-baking, alignment and exposure, post-baking, development, hardening and pattern detection are performed to obtain an area to be ion-implanted with a width of 50 μm on the upper surface of the epitaxial wafer that is not protected by the photoresist;
[0112] Step 4: ion implantation, such as Figure 2 (d).
[0113] Mg ions are implanted into the area to be implanted after photolithography to form a doping concentration of 5e19 cm -3 , a highly doped region with a depth of 500nm;
[0114] Step 5: deposit a dielectric layer, such as Figure 2 (e).
[0115] A 50nm thick SiO2 dielectric layer was deposited on the surface by atomic layer deposition (ALD) process using trimethylaluminum (TMA) and water (H2O) as precursors.
[0116] Step 6: wet-etch the dielectric layer, such as Figure 2 (f).
[0117] First, the surface of the dielectric layer is subjected to a photolithography process to obtain a photoresist-protected area with a ring width of 4 μm on the upper surface of the epitaxial wafer, and then the epitaxial wafer with the photoresist is immersed in a BOE solution for 3 seconds to obtain a 20 nm thick Al2O3 dielectric layer in the shape of a ring in a top view;
[0118] Step 7: deposit a p-type NiO film, such as Figure 2 (g).
[0119] 6.1) Photolithography is performed on the portion of the epitaxial layer that is not covered by the SiO2 dielectric layer, i.e., a p-NiO region to be deposited is formed through a series of processes including photoresist coating, pre-baking, alignment and exposure, post-baking, development, hardening and pattern detection;
[0120] 6.2) Then, inductively coupled plasma chemical vapor deposition (ICP-CVD) is applied to deposit a NiO film with a thickness of 400 nm in the region where p-type NiO is to be deposited above the SiO2 dielectric layer.
[0121] Step eight, depositing an anode metal layer, such as Figure 2 (h).
[0122] Ni / Au with a thickness of 55nm / 250nm is deposited on the top of the device through the electron beam evaporation E-Beam system to form an anode metal layer, and form ohmic contacts with the p-type NiO film and n-Ga2O3 epitaxial layer respectively to complete a high-voltage Ga2O3 vertical power diode with a composite terminal.
[0123] 3. On a 500nm thick gallium oxide substrate and a 10μm thick n-type gallium oxide homoepitaxial wafer, N and P ion implantation with a ring width of 18μm and a depth of 800nm is performed, and a SiO2 dielectric layer with a thickness of 100nm and a ring width of 20μm is deposited. The NiO film thickness is 400nm, and the anode metal is Ni / Au with a thickness of 60nm / 300nm.
[0124] Cleaning samples:
[0125] First, a 10 μm thick n-Ga2O3 epitaxial wafer is transferred to a 500 nm thick n-Ga2O3 substrate.
[0126] Then, the transferred samples were placed in acetone solution and anhydrous ethanol solution for ultrasonic cleaning for 8 minutes each, then rinsed with a large amount of deionized water and dried with nitrogen. Figure 2 (a).
[0127] Make the cathode:
[0128] First, the drain electrode is deposited on the back side of the substrate, and Ti / Au with a thickness of 60nm / 200nm is deposited on the substrate by an electron beam evaporation E-Beam system.
[0129] Then place the sample in an annealing furnace, set the annealing temperature in the furnace to 500℃, and the annealing time to 1min in a N2 environment to form a cathode of good quality, such as Figure 2 (b).
[0130] Photolithography forms the area to be ion implanted:
[0131] Photolithography is performed on the upper surface of the cleaned n-Ga2O3 epitaxial wafer, that is, firstly, photoresist is coated on the upper surface of the n-Ga2O3 epitaxial wafer, and then pre-baking, alignment and exposure, post-baking, development, hardening and pattern detection are performed to obtain an ion implantation area with a width of 100 μm on the upper surface of the epitaxial wafer that is not protected by the photoresist, such as Figure 2 (c).
[0132] Ion implantation:
[0133] N and P ions are implanted into the area to be implanted after photolithography to form a doping concentration of 5e19cm -3 , a highly doped region with a depth of 800nm, such as Figure 2 (d).
[0134] Deposition of dielectric layer:
[0135] By using the atomic layer deposition (ALD) process, trimethylaluminum (TMA) and water (H2O) are used as precursors to deposit a 100nm thick SiO2 dielectric layer on the surface. Figure 2(e).
[0136] Wet etching of dielectric layer:
[0137] First, the surface of the dielectric layer is subjected to a photolithography process to obtain a photoresist-protected area with a ring width of 4 μm on the upper surface of the epitaxial wafer. Then, the epitaxial wafer with the photoresist is immersed in a BOE solution for 3 seconds to obtain a 20 nm thick Al2O3 dielectric layer in the shape of a ring in top view, as shown in FIG. Figure 2 (f).
[0138] Deposition of p-type NiO thin film:
[0139] First, photolithography is performed on the portion of the epitaxial layer that is not covered by the SiO2 dielectric layer, that is, a p-NiO region to be deposited is formed through a series of processes including photoresist coating, pre-baking, alignment and exposure, post-baking, development, hardening and pattern detection;
[0140] Then, inductively coupled plasma chemical vapor deposition (ICP-CVD) is used to deposit a NiO film with a thickness of 500 nm in the p-type NiO region to be deposited above the SiO2 dielectric layer. Figure 2 (g).
[0141] Deposition of anode metal layer:
[0142] Ni / Au with a thickness of 60nm / 300nm is deposited on the top of the device by electron beam evaporation E-Beam system to form an anode metal layer, and form ohmic contacts with the p-type NiO film and n-Ga2O3 epitaxial layer respectively. Figure 2 (h) This completes the high-voltage Ga2O3 vertical power diode with composite termination.
[0143] In summary, the present invention provides a high-voltage Ga2O3 vertical power diode with a composite terminal and a preparation method thereof, which solves the problem of excessive reverse leakage current caused by current edge effect and electric field concentration effect in existing gallium oxide power diodes, and introduces two edge terminal structures to significantly reduce reverse leakage and improve breakdown voltage. The vertical power diode structure of the present invention includes from bottom to top: cathode, substrate, epitaxial layer, ion implantation area, dielectric layer, p-type NiO thin film layer covering on the dielectric layer, and anode metal layer covering on the surface of the device. The epitaxial layer is epitaxial of n-Ga2O3 gallium oxide material, and the top of the epitaxial layer has an ion implantation area, which can effectively regulate the carrier concentration at the top of the epitaxial layer. A dielectric layer is provided between the ion implantation area and the p-type NiO thin film layer, which can be used as dielectric isolation to effectively improve the device withstand voltage, and can also be used as a field plate structure to effectively alleviate the peak electric field at the edge of the device. From a top view, the ion implantation area, the dielectric layer and the NiO thin film layer are all annular structures, the inner diameter of the dielectric layer is slightly larger than the ion implantation area, and the inner diameter of the NiO thin film layer is the same as the inner diameter of the dielectric layer, so that the contact area between the NiO thin film and the dielectric layer is maximized, effectively improving the device performance. The dielectric layer and the ion implantation area on the top of the n-Ga2O3 epitaxial layer serve as two edge terminals, and the whole constitutes a Ga2O3 vertical power diode with high withstand voltage, low leakage and low power consumption.
[0144] The preparation steps of the vertical power diode in the present invention include the following steps: cleaning the epitaxial wafer, making a cathode, photolithography to form an area to be ion-implanted, ion implantation, deposition of a dielectric layer, wet etching of the dielectric layer, deposition of a p-type NiO film, and deposition of an anode metal layer. The present invention obtains a high-quality dielectric layer pattern through a wet etching process and the isotropic principle of F ions etching dielectric materials in a BOE solution; and uses an ICP-CVD process to quickly deposit a high-quality nickel oxide film with good uniformity and high compactness under low temperature and low pressure conditions; the present invention forms a high-resistivity region at the edge of the device by introducing an ion implantation terminal and a dielectric edge terminal, effectively regulating the carrier concentration of the epitaxial layer, transferring the peak electric field when the device is broken down to the edge terminal, and alleviating the electric field concentration effect at the edge of the device, thereby effectively reducing the reverse leakage of the device, increasing the breakdown voltage, and improving the performance and reliability of the diode.
[0145] The above are only some embodiments of the present invention, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. Obviously, for professionals in this field, after understanding the content and principles of the present invention, it is possible to make various modifications and changes in form and details without departing from the principles and structures of the present invention, but these modifications and changes based on the ideas of the present invention are still within the scope of protection of the claims of the present invention.
Claims
1. A high-voltage Ga2O3 vertical power diode with a composite terminal, which is provided with, from bottom to top: a cathode, a substrate, an epitaxial layer, a p-type NiO thin film layer, and an anode metal layer covering the surface of the device, characterized in that: The epitaxial layer is an n-Ga2O3 material epitaxial layer, and a ring-shaped ion implantation area extending inward along the periphery is provided at the top of the epitaxial layer. A dielectric layer with the same area as the p-type NiO thin film layer is provided between the ion implantation area and the p-type NiO thin film layer. From a top-down perspective, the ion implantation area, the dielectric layer and the NiO thin film layer are all concentric ring structures, the inner diameter of the dielectric layer is slightly smaller than that of the ion implantation area, and the inner diameter of the p-type NiO thin film layer is the same as that of the dielectric layer. The dielectric layer and the ion implantation area at the top of the n-Ga2O3 epitaxial layer serve as two edge terminals of the device, and the whole constitutes a Ga2O3 vertical power diode with high withstand voltage, low leakage and low power consumption.
2. The high withstand voltage Ga2O3 vertical power diode with composite termination according to claim 1, characterized in that: The thickness of the n-Ga2O3 epitaxial layer is 5μm-10μm; the depth of the ion implantation zone at the top of the epitaxial layer is 300nm-800nm, and the shape when viewed from above is a circular ring with a ring width of 3μm-18μm; the type of ion implantation is either N, P ion implantation, or Mg ion implantation; the material of the dielectric layer at the top of the ion implantation zone is either SiO2 or Al2O3, with a thickness of 20nm-100nm, and the shape when viewed from above is a circular ring with a ring width of 4μm-20μm; the thickness of the NiO thin film layer on the top of the dielectric layer is 200nm-400nm, and the shape when viewed from above is the same as that of the dielectric layer.
3. The high withstand voltage Ga2O3 vertical power diode with composite termination according to claim 1, characterized in that: The cathode is made of Ti / Au material with a thickness of 60nm / 200nm, and the anode metal layer is made of Ni / Au material with a thickness of 50nm / 200nm-60nm / 300nm.
4. The high withstand voltage Ga2O3 vertical power diode with composite termination according to claim 1, characterized in that: The substrate is a Ga2O3 substrate with a thickness of 300-500nm.
5. A method for preparing a high-voltage Ga2O3 vertical power diode with a composite terminal, characterized in that: The n-Ga2O3 epitaxial layer has an ion implantation region on the top, and a dielectric layer is deposited on the top of the ion implantation region to form two composite edge terminal structures, including the following steps: 1) Select and pre-treat the substrate: select a doping concentration of 1e18cm -3 -3e18cm -3 The n-type β-Ga2O3 single crystal substrate with a thickness ranging from 300nm to 500nm is ultrasonically cleaned in acetone solution, anhydrous ethanol, and deionized water for 5 minutes respectively, and then dried with nitrogen to obtain a pretreated substrate. 2) Fabrication of cathode: Metal Ti / Au is deposited on the back area of the substrate by electron beam evaporation E-Beam system with a thickness of 60nm / 120nm to form a cathode. 3) Cleaning the epitaxial wafer: Select a homoepitaxial gallium oxide epitaxial wafer with a thickness of 5μm-10μm and clean it, that is, put the gallium oxide epitaxial wafer into acetone solution and anhydrous ethanol solution in turn, ultrasonically clean it for 5min-10min each, then rinse it with a large amount of deionized water, and then blow it dry with nitrogen to obtain the cleaned epitaxial wafer, that is, the epitaxial layer of the device. 4) Photolithography to form the area to be ion implanted: Photolithography is performed on the cleaned epitaxial wafer, that is, firstly, photoresist is coated on the upper surface of the n-Ga2O3 epitaxial wafer, and then through pre-baking, alignment and exposure, post-baking, development, hardening and pattern detection, a photoresist-protected area with a width of 30μm-100μm on the upper surface of the epitaxial wafer is obtained. 5) Ion implantation: Ion implantation is performed on the area to be implanted after photolithography is completed to form a doping concentration of 5e19cm -3 , a highly doped area with a depth of 300-800nm. After that, the epitaxial wafer after ion implantation is annealed. In a N2 environment, the annealing temperature in the furnace is set to 800℃-950℃, and the annealing time is 20min-40min to activate the implanted ions, and finally a high resistivity ion implantation area at the top of the epitaxial layer is obtained. 6) Deposition of dielectric layer: The dielectric layer is deposited by atomic layer deposition (ALD) process, using trimethylaluminum (TMA) and water (H2O) as precursors to deposit a dielectric layer with a thickness of 20 nm to 100 nm on the surface. 7) Wet etching of dielectric layer: First, the dielectric layer surface is subjected to a photolithography process to obtain a photoresist-protected area with a ring width of 4μm-20μm on the upper surface of the epitaxial wafer. Finally, the epitaxial wafer with the photoresist is immersed in a BOE solution for 3-10 seconds. Through the isotropy of the F ions in the BOE solution on the dielectric layer material, a high-quality circular dielectric layer with a thickness of 20nm-100nm is obtained. 8) Deposition of p-type NiO layer: First, the upper surface of the device is subjected to a photolithography process so that the photoresist covers the upper surface of the n-Ga2O3 epitaxial layer not covered by the dielectric layer, and then an inductively coupled plasma chemical equipment, i.e., a low-temperature deposition equipment ICP-CVD is used to deposit a p-type NiO film. Specifically, a p-type NiO film with a thickness of 200nm-400nm is deposited in the area not covered by the photoresist, and the photoresist is washed off. 9) Deposition of anode metal layer: Ni / Au with a thickness of 50nm / 200nm-60nm / 300nm is deposited on the top of the device through the electron beam evaporation E-Beam system to form an anode metal layer, and form ohmic contacts with the p-type NiO film and n-Ga2O3 epitaxial layer respectively to complete the high-voltage Ga2O3 vertical power diode with composite terminal.
6. The method for preparing a high-voltage Ga2O3 vertical power diode with a composite terminal according to claim 5, characterized in that: In step 2, cathode metal Ti / Au is deposited on the back area of the substrate using an electron beam evaporation E-Beam system, and the process conditions are as follows: Evaporation rate: 0.1-20A / s Pre-evaporation power: 5-45 Evaporation power: 0-60 Working vacuum: 5e-4Pa Working temperature: 20℃-200℃.
7. The method for preparing a high-voltage Ga2O3 vertical power diode with a composite terminal according to claim 5, characterized in that: In step 6, the dielectric layer is deposited using an atomic layer deposition (ALD) process, and the process conditions are as follows: Reaction chamber pressure: 880Pa Reaction chamber gas: high purity nitrogen Reaction chamber gas flow rate: 300sccm Al2O3 growth rate: 0.5nm / min Al2O3 growth time: 40min-100min.
8. The method for preparing a high-voltage Ga2O3 vertical power diode with a composite terminal according to claim 5, characterized in that: In step 8, a p-type NiO film is deposited by using a low temperature deposition device ICP-CVD, and the process conditions are as follows: Reaction chamber pressure: 10mTorr Ionization voltage: 1.8-4.5KV Plasma ionization electrode: Ni Reaction chamber gases: O2, N2, Ar.