Field effect transistor with asymmetric defect region

Abstract

The invention relates to a field effect transistor with an asymmetric defect region. A structure for a field effect transistor and a method of forming a structure for a field effect transistor are provided. The structure includes one or more semiconductor layers, a gate on the one or more semiconductor layers, a source / drain region including a first portion in the one or more semiconductor layers and a second portion in the one or more semiconductor layers, and a defect region in the one or more semiconductor layers. The defect region is disposed adjacent to the first portion of the source / drain region.

Description

Technical Field

[0001] The present invention relates to integrated circuit and semiconductor device manufacturing, and more particularly to a structure for a field effect transistor and a method for forming the structure for a field effect transistor. Background Art

[0002] A field effect transistor generally includes a source, a drain, a body forming a channel region between the source and the drain, and a gate electrode overlapping the channel region. When a control voltage exceeding a characteristic threshold voltage is applied to the gate electrode, carrier flow occurs in the channel region of the body between the source and the drain to generate a device output current.

[0003] A silicon-on-insulator substrate includes a bulk substrate, a device layer, and an electrical insulator layer disposed between the device layer and the bulk substrate. The advantage of using a silicon-on-insulator substrate to form a field effect transistor is that parasitic capacitance is reduced due to the electrical isolation of the device layer from the bulk substrate. During operation, the depletion region of the field effect transistor may only partially extend through the device layer. Partially depleted field effect transistors are affected by the floating body effect, in which a body located in the device layer forms a capacitor relative to the insulating bulk substrate, and charge accumulates on the capacitor. The accumulated charge can have a negative impact on device performance.

[0004] What is needed are structures for field effect transistors and methods of forming structures for field effect transistors. Summary of the invention

[0005] In one embodiment of the present invention, a structure for a field effect transistor is provided. The structure includes one or more semiconductor layers, a gate located on the one or more semiconductor layers, a source / drain region including a first portion located in the one or more semiconductor layers and a second portion located in the one or more semiconductor layers, and a defect region located in the one or more semiconductor layers. The defect region is disposed adjacent to the first portion of the source / drain region.

[0006] In one embodiment of the present invention, a method for forming a structure for a field effect transistor is provided. The method includes forming a defect region in a first semiconductor layer, forming a second semiconductor layer on the first semiconductor layer, forming a gate on the second semiconductor layer, and forming a source / drain region, the source / drain region including a first portion located in the first semiconductor layer and a second portion located in the second semiconductor layer. The defect region is disposed adjacent to the first portion of the source / drain region. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings, which are included in and constitute a part of this specification, illustrate various embodiments of the present invention and, together with the general description of the present invention made above and the detailed description of the embodiments made below, are used to explain the embodiments of the present invention. In the accompanying drawings, like reference numerals represent similar features in different views.

[0008] Figure 1 A cross-sectional view of a structure is shown at an initial manufacturing stage of a processing method in accordance with an embodiment of the present invention.

[0009] Figure 2 Display in Figure 1 A cross-sectional view of the structure following a manufacturing stage of the process.

[0010] Figure 3 Display in Figure 2 A cross-sectional view of the structure following a manufacturing stage of the process.

[0011] Figure 4 Display in Figure 3 A cross-sectional view of the structure following a manufacturing stage of the process. DETAILED DESCRIPTION

[0012] Please refer to Figure 1 According to an embodiment of the present invention, a device structure 10 for a transistor can be fabricated using a silicon-on-insulator substrate, which includes a semiconductor layer 12, a substrate 16, and a dielectric layer 14 disposed between the semiconductor layer 12 and the substrate 16. The semiconductor layer 12 can be composed of a semiconductor material, such as single crystal silicon. The dielectric layer 14 can be composed of a dielectric material (e.g., silicon dioxide), which is an electrical insulator. The substrate 16 can be composed of a semiconductor material, such as single crystal silicon. The semiconductor layer 12 and the dielectric layer 14 are adjacent along an interface 18. In one embodiment, the semiconductor layer 12 can have a thickness in a range of about 50 nanometers to about 200 nanometers.

[0013] The damaged region 20 may be formed in the semiconductor layer 12 by, for example, ion implantation under a given set of implantation conditions. A patterned implantation mask 22 may be formed on the top surface 11 of the semiconductor layer 12 to define a selected area exposed for the ion implantation (as indicated by a single arrow). The implantation mask 22 may include a photoresist layer that is applied and patterned to form an opening that exposes the selected area and at least partially determines the location and horizontal size of the damaged region 20. The implantation mask 22 has a thickness and a stop power sufficient to prevent ions from being implanted in the masked area. The implantation mask 22 may be stripped after the damaged region 20 is formed.

[0014] The implantation conditions (e.g., ion species, dose, kinetic energy, tilt angle) may be selected to adjust the physical characteristics of the damaged region 20 located in the semiconductor layer 12, such as depth and damage level. In one embodiment, the implanted ion species may be electrically inactive in the semiconductor material of the semiconductor layer 12. In one embodiment, the damaged region 20 may be formed by implanting ions of germanium or carbon. In one embodiment, the damaged region 20 may be formed by co-implanting germanium ions and carbon ions. In one embodiment, the damaged region 20 may be formed by implanting ions generated from an inert gas (e.g., argon or xenon).

[0015] The kinetic energy and dose of the implanted ion species required to produce the damaged region 20 may depend on, among other factors, the thickness of the semiconductor layer 12. In one embodiment, the damaged region 20 may be formed by implanting germanium ions at a kinetic energy of 30 keV to 45 keV. In one embodiment, the damaged region 20 may be formed by implanting argon ions at a kinetic energy of 50 keV to 70 keV. In one embodiment, the damaged region 20 may be formed by implanting xenon ions at a kinetic energy of 40 keV to 60 keV. In one embodiment, the ion dose of the germanium ions or xenon ions may be in the range of 3x10 14 ions / cm2 to 1x10 15 ions / cm2.

[0016] The implantation process produces a damage distribution in the damage region 20, which may exhibit a maximum damage level near the projected range of the implanted ions. The ion implantation process that forms the damage region 20 introduces high-energy ions, and the ion trajectories travel along a path within the semiconductor layer 12. The high-energy ions lose energy along their paths through stochastic scattering events with atomic nuclei and electrons in the semiconductor material of the semiconductor layer 12 passing through, and eventually stop in the semiconductor layer 12 after their energy dissipates. The energy lost in the nuclear collision causes the target atoms of the semiconductor layer 12 to deviate from their original lattice positions, thereby damaging the lattice structure. Compared with the undamaged semiconductor material in the area of ​​the semiconductor layer 12 masked by the implantation mask 22 and the area of ​​the semiconductor layer 12 located below the damage layer 20, the lattice structure of the semiconductor layer 12 is highly disordered in the damage region 20 (especially near the projected range). In one embodiment, the lattice structure of the semiconductor layer 12 may be amorphized in the damage region 20.

[0017] In one embodiment, damaged region 20 may extend from top surface 11 of semiconductor layer 12 to a depth that is less than the thickness of semiconductor layer 12. Areas of semiconductor layer 12 adjacent damaged region 20 are protected by the implantation mask from being damaged by the ion implantation, as are portions of semiconductor layer 12 between damaged region 20 and dielectric layer 14.

[0018] Please refer to Figure 2 , wherein similar reference numerals denote Figure 1 In the next manufacturing stage of the processing method, the defect region 28 can be formed from the damaged region 20 by performing an annealing process. In one embodiment, the annealing process can heat the silicon-on-insulator substrate to a peak temperature greater than or equal to 850° C. In one embodiment, the annealing process can be a rapid thermal annealing. In one embodiment, the annealing process can be a furnace annealing.

[0019] The crystal structure of the semiconductor layer 12 in the damaged region 20 between the damaged region 20 and the top surface 11 of the semiconductor layer 12 may be recrystallized by the annealing process. The recrystallized semiconductor material may have a crystallinity and a crystal structure that are substantially the same as the original crystallinity and crystal structure of the semiconductor layer 12. The crystal structure of the semiconductor layer 12 located in the defect region 28 may include a distribution of defects, such as dislocations. Dislocations may be linear crystal defects or irregularities within the crystal structure of the semiconductor layer 12, which include a sudden change in the arrangement of atoms. In one embodiment, the defects in the defect region 28 may coincide with the end-of-range of the implantation process that formed the damaged region 20. The defect region 28 is completely located between the top surface 11 of the semiconductor layer 12 and the interface 18 (located between the semiconductor layer 12 and the dielectric layer 14).

[0020] Please refer to Figure 3 , wherein similar reference numerals denote Figure 2 1 and 12. In the next manufacturing stage of the process method, a semiconductor layer 30 may be formed on the top surface 11 of the semiconductor layer 12. In one embodiment, the semiconductor layer 30 may be formed by an epitaxial growth process and may include a single crystalline semiconductor material, such as single crystalline silicon. The single crystalline semiconductor material of the semiconductor layer 12 has a crystal structure that acts as a crystal template during the epitaxial growth of the crystal structure of the single crystalline semiconductor material of the semiconductor layer 30. In one embodiment, the semiconductor layer 30 may be a homoepitaxial layer composed of the same semiconductor material as the semiconductor layer 12.

[0021] Semiconductor layer 30 is adjacent to semiconductor layer 12 along an interface coextensive with top surface 11 of semiconductor layer 12. Defect region 28 is disposed entirely in semiconductor layer 12 between semiconductor layer 30 and dielectric layer 14. Defect region 28 does not extend into semiconductor layer 30 because defect region 28 is formed before semiconductor layer 30 is formed, and the defect does not propagate into semiconductor layer 30 during epitaxial growth. Therefore, semiconductor layer 30 may not have defects, such as dislocations.

[0022] A trench isolation region 32 may be formed extending through the semiconductor layer 30 and the semiconductor layer 12 to the dielectric layer 14. The trench isolation region 32 surrounds an active region including a portion of the semiconductor layer 12 and a portion of the semiconductor layer 30. The surrounded portion of the semiconductor layer 12 located in the active region includes the defect region 28. The trench isolation region 32 may be formed by a shallow trench isolation technique, which utilizes photolithography and etching processes to pattern trenches in the semiconductor layers 12, 30, deposits dielectric material to fill the trenches, and utilizes chemical mechanical polishing and / or etch back to planarize the dielectric material. The dielectric material included in the trench isolation region 32 may be composed of a dielectric material (e.g., silicon dioxide), which is an electrical insulator.

[0023] Please refer to Figure 4 , wherein similar reference numerals denote Figure 3 In the active region, a field effect transistor 34 may be formed in the next manufacturing stage of the process method. In one embodiment, the field effect transistor 34 may be deployed in a low noise amplifier found in a radio frequency circuit. In one embodiment, the field effect transistor 34 may be deployed in a power amplifier found in a radio frequency circuit.

[0024] Field effect transistor 34 may include gate 36, source / drain region 38, and source / drain region 40. Gate 36 may include gate electrode 42 and gate dielectric layer 44 disposed between gate electrode 42 and semiconductor layer 30. Gate electrode 42 is composed of a conductor, such as doped polysilicon and / or work function metal. Gate dielectric layer 44 is composed of a dielectric material (such as silicon dioxide or hafnium oxide), which is an electrical insulator. Gate electrode 42 and gate dielectric layer 44 may be formed by patterning their respective material layers using photolithography and etching processes. Gate 36 is disposed between source / drain region 38 and source / drain region 40 in a lateral direction. Gate 36 may be arranged so that defect region 28 and source / drain region 38 are adjacent to the same sidewall of gate 36. Semiconductor layer 30 is completely disposed between defect region 28 and gate 36, and between semiconductor layer 12 and gate 36.

[0025] The source / drain region 38 and the source / drain region 40 (formed by Figure 4 The source / drain region 38 has an upper portion located in the semiconductor layer 30 and a lower portion located in the semiconductor layer 12. The source / drain region 40 also has an upper portion located in the semiconductor layer 30 and a lower portion located in the semiconductor layer 12.

[0026] The source / drain regions 38 and the source / drain regions 40 may be formed by self-aligned ion implantation of dopants into the semiconductor layers 12, 30 under a given set of implantation conditions. The implantation conditions (e.g., ion species, dose, kinetic energy, and tilt angle) may be selected to adjust the electrical and physical properties of the source / drain regions 38 and the source / drain regions 40. In one embodiment, the source / drain regions 38 and the source / drain regions 40 may include semiconductor materials doped with n-type dopants (e.g., phosphorus and / or arsenic) to provide n-type conductivity. The term "source / drain region" as used herein refers to a doped region of a semiconductor material that may serve as a source or drain of the field effect transistor 34. In one embodiment, the source / drain region 38 may define a source region of the field effect transistor 34, and the source / drain region 40 may define a drain region of the field effect transistor 34.

[0027] Prior to forming the source / drain regions 38 and the source / drain regions 40, a well may be formed in the semiconductor layers 12, 30 by ion implantation of dopants having a conductivity type opposite to that of the source / drain regions 38 and the source / drain regions 40. The portion of the well in the semiconductor layers 12, 30 between the source / drain regions 38 and the source / drain regions 40 may constitute a body or channel region 46 of the field effect transistor 34. The source / drain regions 38 are adjacent to the channel region 46 along the junction 26, and the conductivity type of the semiconductor material changes across the junction 26. The channel region 46 is disposed below the gate 36 in a vertical direction. The field effect transistor 34 may include side spacers 45 disposed on the sidewalls of the gate 36. In one embodiment, the side spacers 45 may be composed of a dielectric material, such as a combination of silicon dioxide and silicon nitride layers. The field effect transistor 34 may also include other features, such as a ring region and a lightly doped drain extension region.

[0028] The defect region 28 is disposed adjacent to the lower portion of the source / drain region 38. The channel region 46 is disposed between the defect region 28 and the source / drain region 40 in a lateral direction, and the defect region 28 is disposed between the channel region 46 and the source / drain region 38 in a lateral direction. The defect region 28 may surround the lower portion of the source / drain region 38 and the lower portion of the junction 26 between the source / drain region 38 and the channel region 46. In one embodiment, the defect region 28 may overlap the lower portion of the junction 26. The defect region 28 does not extend into the channel region 46 of the field effect transistor 34. The source / drain region 40 of the field effect transistor 34 does not have a defect region similar to the defect region 28, thereby creating an asymmetry in the device layout.

[0029] The defects in defect region 28 can effectively change the source junction current and the floating body to eliminate the floating body effect associated with the partially depleted field effect transistor 34. In this regard, the defects (e.g., dislocations) in the defect region 28 can create recombination centers that mitigate the floating body effect during operation of the field effect transistor 34. Mitigating the floating body effect by the defect region 28 can improve the bulk time constant of the field effect transistor 34 without degrading the baseline device performance (manifested by factors such as drain-induced barrier lowering). The channel region 46 of the field effect transistor 34 and the source / drain region 40 of the field effect transistor 34 do not have defects caused by the amorphization and recrystallization that form the defect region 28.

[0030] The method described above is used for the manufacture of integrated circuit chips. The manufacturer can distribute the resulting integrated circuit chips in raw wafer form (e.g., as a single wafer with multiple unpackaged chips), as a bare die, or in a packaged form. The chip can be integrated with other chips, discrete circuit elements and / or other signal processing devices as part of an intermediate product or a final product. The final product can be any product that includes an integrated circuit chip, such as a computer product or a smart phone with a central processing unit.

[0031] Terms modified by approximate language such as "about," "approximately," and "substantially" cited herein are not limited to the exact value specified. The approximate language may correspond to the precision of the instrument used to measure the value, and may represent + / -10% of the value unless otherwise dependent on the precision of the instrument.

[0032] Terms such as "vertical", "horizontal", etc. are cited herein as examples to establish a reference frame and are not limiting. The term "horizontal" as used herein is defined as a plane parallel to the conventional plane of the semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms "vertical" and "orthogonal" refer to directions perpendicular to the horizontal plane as just defined. The term "lateral" refers to a direction within the horizontal plane.

[0033] A feature that is "connected" or "coupled" to another feature may be directly connected or coupled to the other feature, or one or more intermediate features may be present. A feature may be "directly connected" or "directly coupled" to another feature if there are no intermediate features. A feature may be "indirectly connected" or "indirectly coupled" to another feature if there is at least one intermediate feature. A feature that is "on" or "in contact with" another feature may be directly on or in direct contact with the other feature, or one or more intermediate features may be present. A feature may be directly "on" or "in direct contact with" another feature if there are no intermediate features. A feature may not be "directly" "on" or "not directly in contact with" another feature if there is at least one intermediate feature. Different features "overlap" if one feature extends over and covers a portion of another feature.

[0034] The description of various embodiments of the present invention is for illustrative purposes and is not intended to be exhaustive or limited to the described embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements over commercially known technologies, or to enable those of ordinary skill in the art to understand the embodiments described herein.

Claims

1. A structure for a field effect transistor, characterized in that: The structure includes: one or more semiconductor layers; a gate disposed on the one or more semiconductor layers; a first source / drain region including a first portion located in the one or more semiconductor layers and a second portion located in the one or more semiconductor layers; and A defect region is located in the one or more semiconductor layers, and the defect region is adjacent to the first portion of the first source / drain region.

2. The structure according to claim 1, characterized in that The one or more semiconductor layers include a first semiconductor layer and a second semiconductor layer located on the first semiconductor layer, and the second semiconductor layer is completely disposed between the defective region and the gate.

3. The structure according to claim 2, characterized in that The first portion of the first source / drain region is disposed in the first semiconductor layer, and the second portion of the first drain / source region is disposed in the second semiconductor layer.

4. The structure according to claim 3, characterized in that The first semiconductor layer is adjacent to the second semiconductor layer along an interface. The gate is arranged on the second semiconductor layer, and the interface is arranged between the defective region and the second portion of the first source / drain region.

5. The structure according to claim 2, characterized in that Also includes: substrate; as well as a dielectric layer, disposed on the substrate, The first semiconductor layer is adjacent to the second semiconductor layer along an interface, and the defect region is completely disposed between the second semiconductor layer and the dielectric layer.

6. The structure according to claim 5, characterized in that Also includes: The silicon-on-insulator substrate comprises the first semiconductor layer, the dielectric layer, and the substrate.

7. The structure according to claim 2, characterized in that The second semiconductor layer is a homoepitaxial layer including the same semiconductor material as the first semiconductor layer.

8. The structure according to claim 1, characterized in that The defect region surrounds the first portion of the first source / drain region.

9. The structure according to claim 1, characterized in that The first source / drain region is a source region of the field effect transistor.

10. The structure according to claim 1, characterized in that Also includes: a second source / drain region located in the one or more semiconductor layers; as well as A channel region is located in the one or more semiconductor layers, and the channel region is disposed below the gate between the first source / drain region and the second source / drain region. The channel region is located between the defect region and the second source / drain region.

11. The structure according to claim 10, characterized in that The channel region is adjacent to the defect region.

12. The structure according to claim 11, characterized in that The channel region has no defects.

13. The structure according to claim 10, characterized in that The first source / drain region is a source region of the field effect transistor, and the second source / drain region is a drain region of the field effect transistor.

14. The structure according to claim 10, characterized in that The defective region is disposed between the channel region and the first source / drain region.

15. The structure according to claim 10, characterized in that The second source / drain region has no defects.

16. The structure according to claim 1, characterized in that The defective region includes a dislocation.

17. A method of forming a structure for a field effect transistor, characterized in that The method includes: forming a defect region in the first semiconductor layer; forming a second semiconductor layer on the first semiconductor layer; forming a gate on the second semiconductor layer; and forming a source / drain region, the source / drain region including a first portion located in the first semiconductor layer and a second portion located in the second semiconductor layer, The defective region is adjacent to the first portion of the source / drain region.

18. The method according to claim 17, characterized in that After forming the defect region in the first semiconductor layer, the second semiconductor layer is formed.

19. The method according to claim 17, characterized in that Forming the defect region in the first semiconductor layer includes: disordering a crystal structure of a portion of the first semiconductor layer; and The portion of the first semiconductor layer is converted into a recrystallized semiconductor material and the defect region.

20. The method of claim 18, wherein: The source / drain region is formed in a portion of the second semiconductor layer and in the recrystallized semiconductor material of the first semiconductor layer.

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