Semiconductor device and preparation method

Abstract

The invention relates to a semiconductor device and a preparation method, and relates to the technical field of semiconductors, in the semiconductor device and the preparation method, a dielectric layer with a first groove is arranged on a substrate, then a grid electrode is formed in the first groove, and in the direction perpendicular to the substrate, the height of the grid electrode is larger than that of the first groove; and forming a conductive structure on the side wall of the grid electrode. As the conductive structure can be conductive, electric field lines in the region, close to the conductive structure, of the grid can be guided and dispersed by the conductive structure, electric fields are prevented from being concentrated on the lower side of the grid, and the breakdown voltage of the device is increased. Meanwhile, the conductive structure widens the conduction path of the current, increases the current intensity, and further reduces the specific on-resistance. At the moment, the thickness of the dielectric layer on the lower side of the conductive structure is larger than that of the dielectric layer on the lower side of the gate, and the voltage-resistant performance of the device can be further improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a preparation method thereof. Background Art

[0002] In the current traditional semiconductor device structure, the peak electric field is concentrated below the gate. The concentration of the electric field at this location will cause the device to break down prematurely, resulting in device breakdown and damage.

[0003] Based on this, how to regulate the device electric field and increase the avalanche breakdown voltage on the device surface, thereby significantly improving the device's voltage resistance and reducing the specific on-resistance has become a technical problem that technical personnel in this field urgently need to solve. Summary of the invention

[0004] Based on this, it is necessary to provide a semiconductor device and a preparation method for improving the breakdown voltage of the semiconductor device and reducing the specific on-resistance.

[0005] In order to achieve the above object, on the one hand, the present invention provides a semiconductor device, comprising:

[0006] substrate;

[0007] A dielectric layer, located on one side of the substrate, wherein the dielectric layer has a first groove;

[0008] a gate, located in the first groove, wherein a height of the gate is greater than a height of the first groove in a direction perpendicular to the substrate;

[0009] The conductive structure covers the gate sidewall and is located on both sides of the first groove.

[0010] In one of the embodiments, in a direction perpendicular to the substrate, the height of the conductive structure is 1 / 2-3 / 4 of the height of the gate.

[0011] In one embodiment, the dielectric layer comprises:

[0012] A first sub-dielectric layer and a second sub-dielectric layer;

[0013] The first sub-dielectric layer is located at one side of the substrate, and the first sub-dielectric layer has a second groove;

[0014] The second sub-dielectric layer covers the first sub-dielectric layer and the second groove, and an orthographic projection of the first groove on the substrate overlaps with an orthographic projection of the second groove on the substrate.

[0015] In one embodiment, the first sub-dielectric layer and the second sub-dielectric layer are made of the same material.

[0016] In one embodiment, the conductive structure is a first sidewall of the gate. In one embodiment, the semiconductor device further includes:

[0017] A second spacer is located at a side of the conductive structure away from the gate.

[0018] In one embodiment, the material of the second sidewall spacer includes insulating material.

[0019] On the other hand, a method for preparing a semiconductor device is also provided, comprising:

[0020] providing a substrate;

[0021] forming a dielectric layer on the substrate, wherein the dielectric layer has a first groove;

[0022] forming a gate in the first groove, wherein the height of the gate is greater than the height of the first groove in a direction perpendicular to the substrate;

[0023] A conductive structure covering the gate sidewall is formed on both sides of the first groove.

[0024] In one embodiment, the dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer, and forming the dielectric layer on the substrate includes:

[0025] forming a first sub-dielectric material layer on one side of the substrate;

[0026] forming a first photoresist on the surface of the first sub-dielectric material layer;

[0027] etching the first sub-dielectric material layer based on the first photoresist to form a second groove, so as to obtain the first sub-dielectric layer;

[0028] removing the first photoresist;

[0029] The second sub-dielectric layer having the first groove is formed on the surface of the first sub-dielectric layer and in the second groove.

[0030] In one embodiment, after forming the conductive structure on both sides of the gate, the method further comprises:

[0031] A second spacer is formed on a side of the conductive structure away from the gate.

[0032] Compared with the prior art, the above technical solution has the following advantages:

[0033] In the semiconductor device and preparation method, a dielectric layer having a first groove is provided on a substrate, and then a gate is formed in the first groove. In a direction perpendicular to the substrate, the height of the gate is greater than the height of the first groove, and then a conductive structure is formed on the sidewall of the gate. Since the conductive structure can conduct electricity, the electric field lines in the area where the gate is close to the conductive structure will be guided and dispersed by the conductive structure, thereby avoiding the electric field from being concentrated on the lower side of the gate and increasing the breakdown voltage of the device. At the same time, the conductive structure widens the conduction path of the current, increases the current intensity, and further reduces the specific on-resistance. At this time, the thickness of the dielectric layer on the lower side of the conductive structure is greater than the thickness of the dielectric layer on the lower side of the gate, which can further increase the voltage resistance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0035] Figure 1-Figure 11 A schematic diagram of a partial cross-sectional structure of a semiconductor device is provided for an embodiment of the present application;

[0036] Fig.12 A schematic diagram of a process for preparing a semiconductor device provided in an embodiment of the present application;

[0037] Fig.13 It is a schematic diagram of a simulation image of a traditional structure;

[0038] Fig.14 A schematic diagram of a simulation image of the structure of an embodiment of the present application;

[0039] Fig.15 Schematic diagram comparing the peak value of the surface electric field in the breakdown state between the structure of the embodiment of the present application and the traditional structure.

[0040] Explanation of the reference numerals: 01-substrate; 02-dielectric layer; 0211-first sub-dielectric material layer; 021-first sub-dielectric layer; 022-second sub-dielectric layer; 02a-first groove; 021a-second groove; 03-first photoresist; 04-gate; 041-gate material layer; 05-second photoresist; 06-conductive structure; 07-second sidewall; 08-source region; 09-drain region; 10-interlayer dielectric layer; 11-contact hole. DETAILED DESCRIPTION

[0041] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0043] It should be understood that when a layer is referred to as being "on," "adjacent to," or "connected to" another layer, it can be directly on, adjacent to, or connected to the other layer, or intervening layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," or "directly connected to" another layer, there are no intervening layers.

[0044] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" etc. specify the presence of stated features, wholes, steps, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof.

[0045] In order to make the purpose, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0046] refer to Figure 1-Figure 11 , Figure 1-Figure 11 A schematic diagram of a partial cross-sectional structure of a semiconductor device is provided for an embodiment of the present application; the semiconductor device includes:

[0047] Substrate 01;

[0048] The dielectric layer 02 is located on one side of the substrate 01, and the dielectric layer 02 has a first groove 02a (such as Figure 5 shown);

[0049] The gate 04 is located in the first groove 02a. In the direction perpendicular to the substrate 01, the height of the gate 04 is greater than the height of the first groove 02a (eg Figure 7 shown);

[0050] The conductive structure 06 covers the sidewalls of the gate 04 and is located on both sides of the first groove 02a (eg Figure 8 as shown).

[0051] Specifically, the substrate 01 may be a silicon substrate 01. The material of the dielectric layer 02 may be silicon dioxide or silicon nitride. The dielectric layer 02 located on one side of the substrate 01 may serve as an insulating layer to prevent the device from short-circuiting. The gate 04 is located in the first groove 02a of the dielectric layer 02, that is, part of the sidewall of the gate 04 is wrapped by the dielectric layer 02. At this time, the thickness of the dielectric layer 02 on the lower side of the gate 04 is less than the thickness of the dielectric layer 02 in other areas. The design of the dielectric layer 02 on the lower side of the gate 04 to be thinner can shorten the distance between the gate 04 and the conductive channel, improve the switching speed of the semiconductor device, and enhance the gate 04's ability to control the conductive channel.

[0052] When the gate 04 is pressurized, the peak electric field tends to gather at the lower side of the gate 04. At this time, the conductive structure 06 is arranged on both sides of the gate 04 to share part of the electric field and increase the breakdown voltage of the device. The conductive structure 06 is arranged at a thicker position of the dielectric layer 02, and the thicker dielectric layer 02 can also increase the voltage resistance performance of the device.

[0053] In this embodiment, since the conductive structure 06 is conductive, the electric field lines in the area of ​​the gate 04 close to the conductive structure 06 will be guided and dispersed by the conductive structure 06, avoiding the electric field concentration on the lower side of the gate 04, thereby increasing the breakdown voltage of the device. At the same time, the conductive structure 06 widens the conduction path of the current, increases the current intensity, and further reduces the specific on-resistance. At this time, the thickness of the dielectric layer 02 on the lower side of the conductive structure 06 is greater than the thickness of the dielectric layer 02 on the lower side of the gate 04, which can further increase the withstand voltage performance of the device.

[0054] In another embodiment of the present application, in a direction perpendicular to the substrate 01 , the height of the conductive structure 06 is 1 / 2-3 / 4 of the height of the gate 04 .

[0055] Specifically, in the direction perpendicular to the substrate 01, the height of the conductive structure 06 can be set to 1 / 2-3 / 4 of the height of the gate 04, including endpoint values. For example, the height of the conductive structure 06 can be 1 / 2, 2 / 3, 3 / 4, etc. of the height of the gate 04, and there is no specific limitation.

[0056] It should be noted that if the conductive structure 06 is set relatively low, that is, the thickness of the dielectric layer 02 is relatively thick, the effect of sharing the electric field is not obvious; if the conductive structure 06 is set relatively high, that is, the thickness of the dielectric layer 02 is relatively thin, the breakdown voltage will be low. Therefore, in this embodiment, the height of the conductive structure 06 is set to 1 / 2-3 / 4 of the height of the gate 04. At this time, while the breakdown voltage is increased, the conductive structure 06 has a better effect of sharing the electric field.

[0057] In another embodiment of the present application, the dielectric layer 02 includes:

[0058] The first sub-dielectric layer 021 and the second sub-dielectric layer 022 (such as Figure 4 shown);

[0059] The first sub-dielectric layer 021 is located on one side of the substrate 01 and has a second groove 021a. The second sub-dielectric layer 022 covers the first sub-dielectric layer 021 and the second groove 021a. The orthographic projection of the first groove 02a on the substrate 01 overlaps with the orthographic projection of the second groove 021a on the substrate 01.

[0060] Specifically, the dielectric layer 02 may include a first sub-dielectric layer 021 and a second sub-dielectric layer 022. It should be noted that the material of the first sub-dielectric layer 021 and the material of the second sub-dielectric layer 022 may both be materials with a relatively large dielectric constant, such as silicon nitride material or silicon dioxide material. In one embodiment, the material of the first sub-dielectric layer 021 and the material of the second sub-dielectric layer 022 may be different, for example, the material of the first sub-dielectric layer 021 may be silicon dioxide material, and the material of the second sub-dielectric layer 022 may be silicon nitride material, without specific limitation.

[0061] In order to make the dielectric layer 02 have the first groove 02a, a second groove 021a can be formed first when forming the first sub-dielectric layer 021, and then the second sub-dielectric layer 022 is formed on the first sub-dielectric layer 021. Due to the existence of the second groove 021a, the finally formed dielectric layer 02 has the first groove 02a, wherein the orthographic projection of the first groove 02a on the substrate 01 is located within the orthographic projection of the second groove on the substrate 01.

[0062] After the gate 04 is set on the dielectric layer 02, since the gate 04 is located in the first groove 02a, the thickness of the dielectric layer 02 under the gate 04 is thinner than other areas, which can shorten the distance between the gate 04 and the conductive channel, improve the switching speed of the semiconductor device, and enhance the control ability of the gate 04 over the conductive channel.

[0063] The dielectric layer 02 on the lower side of the conductive structure 06 includes a first sub-dielectric layer 021 and a second sub-dielectric layer 022. The two sub-dielectric layers not only increase the thickness of the dielectric layer 02 on the lower side of the conductive structure 06 and increase the voltage resistance, but also can adjust the direction of the guided electric field through the characteristics of different sub-dielectric layers.

[0064] In this embodiment, the first sub-dielectric layer 021 and the second sub-dielectric layer 022 are provided to better adjust the electric field and improve the breakdown voltage.

[0065] In another embodiment of the present application, the first sub-dielectric layer 021 and the second sub-dielectric layer 022 are made of the same material.

[0066] Specifically, in this embodiment, the materials of the first sub-dielectric layer 021 and the second sub-dielectric layer 022 are set to be the same, which can reduce the preparation steps, increase the speed of device preparation, and reduce the preparation cost.

[0067] In another embodiment of the present application, the material of the conductive structure 06 includes polysilicon material or conductive metal material.

[0068] Specifically, in this embodiment, the material of the conductive structure 06 can be polysilicon material or conductive metal material to achieve the purpose of widening the conduction path of the current. When the conductive structure 06 is polysilicon material, the gate 04 and the conductive structure 06 can be an integrated structure, which simplifies the process, reduces the additional preparation process caused by different materials, and improves the compatibility of the process.

[0069] In another embodiment of the present application, the conductive structure 06 is a first spacer of the gate 04 .

[0070] In this embodiment, the conductive structure 06 is used as the first sidewall of the gate 04, which does not change the length of the conductive trench, and can flexibly adjust the distribution of the electric field to reduce the phenomenon of electric field concentration, thereby reducing resistance loss, increasing the current flow path, and improving the flow uniformity of the current.

[0071] In another embodiment of the present application, the semiconductor device further includes:

[0072] The second spacer 07 is located on a side of the conductive structure 06 away from the gate 04 .

[0073] Specifically, a second spacer 07 is formed on one side of the principle gate 04 of the conductive structure 06 , and the second spacer 07 can protect the internal structure and enhance the stability of the device structure.

[0074] In another embodiment of the present application, the material of the second spacer includes insulating material.

[0075] Specifically, the second sidewall spacer 07 may be an oxide layer or a nitride layer, and is not specifically limited. The insulating material may isolate the active area from other surrounding structures to prevent leakage and interference.

[0076] Based on the above semiconductor device, the present application also provides a method for preparing a semiconductor device, which is used to prepare the above semiconductor device. Fig.12 , Fig.12 A schematic flow chart of a method for preparing a semiconductor device provided in an embodiment of the present application; the method for preparing the semiconductor device comprises:

[0077] Step S101: providing a substrate 01.

[0078] In this step, the substrate 01 may be a silicon substrate 01 .

[0079] Step S102: forming a dielectric layer 02 on the substrate 01, wherein the dielectric layer 02 has a first groove 02a (such as Figure 5 as shown).

[0080] In this step, the dielectric layer 02 may be formed on the substrate 01 by deposition. The dielectric layer 02 may be used as an insulating layer to prevent the device from short-circuiting.

[0081] Step S103: forming a gate 04 in the first groove 02a. In a direction perpendicular to the substrate 01, the height of the gate 04 is greater than the height of the first groove 02a (eg Figure 7 shown);

[0082] In this step, the gate 04 can be formed by deposition. The gate 04 is formed in the first groove 02a. Since the thickness of the dielectric layer 02 in the first groove 02a is less than the thickness of the dielectric layer 02 in other areas, the switching speed of the device is improved. In the direction perpendicular to the substrate 01, the height of the gate 04 is greater than the height of the first groove 02a, and the height of the first groove 02a can be 1 / 4-1 / 2 of the height of the gate 04.

[0083] Step S104: forming a conductive structure 06 (such as a conductive structure 06) covering the sidewalls of the gate 04 on both sides of the first groove 02a. Figure 8 as shown).

[0084] In this step, the conductive structure 06 is disposed on both sides of the gate 04 to increase the flow path of the current.

[0085] In this preparation method, since the conductive structure 06 is conductive, the electric field lines in the area of ​​the gate 04 close to the conductive structure 06 will be guided and dispersed by the conductive structure 06, avoiding the electric field concentration on the lower side of the gate 04, thereby increasing the breakdown voltage of the device. At the same time, the conductive structure 06 widens the conduction path of the current, increases the current intensity, and further reduces the specific on-resistance. At this time, the thickness of the dielectric layer 02 on the lower side of the conductive structure 06 is greater than the thickness of the dielectric layer 02 on the lower side of the gate 04, which can further increase the withstand voltage performance of the device.

[0086] In another embodiment of the present application, the dielectric layer 02 includes a first sub-dielectric layer 021 and a second sub-dielectric layer 022, and step S101 includes:

[0087] Step S1011: forming a first sub-dielectric material layer 0211 (such as Figure 1 as shown).

[0088] The first sub-dielectric material layer 0211 may be formed by deposition, and the material of the first sub-dielectric material layer 0211 may be silicon dioxide material.

[0089] Step S1012: forming a first photoresist 03 (such as Figure 2 as shown).

[0090] Step S1013: etching the first sub-dielectric material layer 0211 based on the first photoresist 03 to form a second groove 021a, so as to obtain the first sub-dielectric layer 021 (such as Figure 3 as shown).

[0091] Step S1014: Remove the first photoresist 03 (such as Figure 3 as shown).

[0092] The first sub-dielectric material layer 0211 is photolithographically processed based on the first photoresist 03 to etch a second groove 021a, which penetrates the first sub-dielectric material layer 0211 to expose the substrate 01. The first photoresist 03 may be removed by wet removal, etc., without specific limitation.

[0093] Step S1015: forming a second sub-dielectric layer 022 having a first groove 02a on the surface of the first sub-dielectric layer 021 and in the second groove 021a (eg Figure 4 as shown).

[0094] In this embodiment, the materials of the first sub-dielectric layer 021 and the second sub-dielectric layer 022 can be different materials or the same material, and there is no specific limitation.

[0095] In one embodiment, when the first sub-dielectric layer 021 and the second sub-dielectric layer 022 are made of the same material, a dielectric material layer of sufficient thickness may be first formed on one side of the substrate 01 (not shown in the figure), and then a dielectric layer 02 having a first groove 02a is formed on the dielectric material layer by etching (e.g. Figure 5 This method can reduce the preparation process.

[0096] In another embodiment of the present application, step S103 includes:

[0097] Step S1031: forming a gate material layer 041 (eg, Figure 6 as shown).

[0098] It should be noted that the gate material layer 041 can be formed by deposition.

[0099] Step S1032: forming a second photoresist 05 (such as Figure 6 as shown).

[0100] Step S1033: etching the gate material layer 041 based on the second photoresist 05, and the remaining gate material layer 041 is the gate 04 (such as Figure 7 as shown).

[0101] Step S1034: Remove the second photoresist 05 (such as Figure 7 as shown).

[0102] A second photoresist 05 is formed on the surface of the gate material layer 041 , and the gate material layer 041 is photolithographically processed based on the second photoresist 05 to remove the other gate material layer 041 except the first groove 02 a , and the final required gate 04 is retained in the first groove 02 a .

[0103] In another embodiment of the present application, step S104 includes:

[0104] A second spacer 07 (eg, Fig. 9 as shown).

[0105] Specifically, after the conductive structure 06 is formed, in order to prevent leakage and interference, a second spacer 07 is formed on the side of the conductive structure 06 away from the gate 04. The second spacer 07 can be formed by first depositing and then etching. It should be noted that the material of the second spacer 07 can be silicon dioxide or silicon nitride.

[0106] The semiconductor device may be any one of LDMOS, NMOS, and PMOS. When the semiconductor device is LDMOS, after providing a substrate 01, a drift region and a channel region may be formed in the substrate 01. Then, after forming the second sidewall 07, ion implantation is performed on the substrate 01 to form a source region 08 and a drain region 09 (such as Fig. 9 As shown). It should be noted that the source region 08 and the body region are located in the channel region, and the drain region 09 is located in the drift region. Then, an interlayer dielectric layer 10 (as shown) is formed on the surface of the substrate 01, the gate 04, the conductive structure 06 and the second spacer 07. Fig.10 As shown in FIG. 1 , the interlayer dielectric layer 10 protects the devices on the lower side and realizes surface flatness. Then, a contact hole 11 is formed in the interlayer dielectric layer 10 (as shown in FIG. 1 ). Fig.11 As shown in FIG. 1 , the contact hole 11 exposes part of the gate 04, the source region 08 and the drain region 09, providing a prerequisite for subsequent electrical connection. It should be noted that the method of forming the source region 08, the drain region 09, the interlayer dielectric layer 10 and the contact hole 11 is the same as the conventional method, and will not be repeated here.

[0107] Based on the above semiconductor device and preparation method, in order to more intuitively reflect the above effects of the present application, the present application also takes NLDMOS as an example and provides a simulation data table of the device, as shown in Table 1 below:

[0108]

[0109] Table 1

[0110] It can be seen that when the vertical threshold voltage VTL, drain circuit density IDL and source current RSP are basically the same, the breakdown voltage BV of the traditional structure is smaller than the breakdown voltage BV of the present application, and the quality factor FOM of the traditional structure is smaller than the quality factor FOM of the present application.

[0111] This application also provides simulation diagrams, refer to Fig.13 , Fig.13 This is a simulation image diagram of a traditional structure; Fig.14 , Fig.14 This is a schematic diagram of a simulation image of the structure of the embodiment of the present application; Fig.15 , Fig.15 Schematic diagram comparing the peak value of the surface electric field in the breakdown state between the structure of the embodiment of the present application and the traditional structure.

[0112] Fig.13 and Fig.14 It can be seen from the comparison that the region of the conductive structure 06 of the present application shares part of the electric field, and compared with the traditional structure, the breakdown voltage is increased and the specific on-resistance is reduced.

[0113] Fig.15 It can be seen that the peak value of the surface electric field of the present application is lower than that of the traditional one, which increases the breakdown voltage and the conduction speed of the semiconductor device.

[0114] Based on the simulation comparison, it is obvious that in this application, since the conductive structure 06 can conduct electricity, the electric field lines in the area of ​​the gate 04 close to the conductive structure 06 will be guided and dispersed by the conductive structure 06, avoiding the electric field concentration on the lower side of the gate 04, and increasing the breakdown voltage of the device. At the same time, the conductive structure 06 widens the conduction path of the current, increases the current intensity, and further reduces the specific on-resistance. At this time, the thickness of the dielectric layer 02 on the lower side of the conductive structure 06 is greater than the thickness of the dielectric layer 02 on the lower side of the gate 04, which can further increase the withstand voltage performance of the device.

[0115] In the description of this specification, the description with reference to the terms "some embodiments", "another embodiment", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.

[0116] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0117] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A semiconductor device, characterized in that: include: substrate; A dielectric layer, located on one side of the substrate, wherein the dielectric layer has a first groove; A gate is located in the first groove, and in a direction perpendicular to the substrate, a height of the gate is greater than a height of the first groove; The conductive structure covers the gate sidewall and is located on both sides of the first groove.

2. The semiconductor device according to claim 1, wherein: In a direction perpendicular to the substrate, the height of the conductive structure is 1 / 2-3 / 4 of the height of the gate.

3. The semiconductor device according to claim 1, wherein: The dielectric layer comprises: A first sub-dielectric layer and a second sub-dielectric layer; The first sub-dielectric layer is located at one side of the substrate, and the first sub-dielectric layer has a second groove; The second sub-dielectric layer covers the first sub-dielectric layer and the second groove, and an orthographic projection of the first groove on the substrate overlaps with an orthographic projection of the second groove on the substrate.

4. The semiconductor device according to claim 3, characterized in that The first sub-dielectric layer and the second sub-dielectric layer are made of the same material.

5. The semiconductor device according to claim 1, wherein: The conductive structure is a first spacer of the gate.

6. The semiconductor device according to claim 1 or 5, characterized in that: The semiconductor device further comprises: A second spacer is located at a side of the conductive structure away from the gate.

7. The semiconductor device according to claim 6, characterized in that The material of the second sidewall includes insulating material.

8. A method for preparing a semiconductor device, characterized in that: include: providing a substrate; forming a dielectric layer on the substrate, wherein the dielectric layer has a first groove; forming a gate in the first groove, wherein the height of the gate is greater than the height of the first groove in a direction perpendicular to the substrate; A conductive structure covering the gate sidewall is formed on both sides of the first groove.

9. The method for preparing a semiconductor device according to claim 8, characterized in that: The dielectric layer includes a first sub-dielectric layer and a second sub-dielectric layer, and the dielectric layer is formed on the substrate, including: forming a first sub-dielectric material layer on one side of the substrate; forming a first photoresist on the surface of the first sub-dielectric material layer; etching the first sub-dielectric material layer based on the first photoresist to form a second groove, so as to obtain the first sub-dielectric layer; removing the first photoresist; The second sub-dielectric layer having the first groove is formed on the surface of the first sub-dielectric layer and in the second groove.

10. The method for preparing a semiconductor device according to claim 8, characterized in that: After forming the conductive structure on both sides of the gate, the method includes: A second spacer is formed on a side of the conductive structure away from the gate.

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