Active optical chip adapter plate and preparation method thereof

Abstract

The invention relates to the technical field of adapter plates, and discloses an active optical chip adapter plate and a preparation method thereof. The preparation method of the active optical chip adapter plate comprises the following steps: providing an active optical chip with a connection point and an exposed optical port, and forming a protection layer covering the optical port and the connection point on the active optical chip; forming a through-silicon-via structure penetrating through the protective layer and extending to the active optical chip, wherein the through-silicon-via structure comprises conductive metal and is staggered with the optical port and the connection point; removing the protection layer on the connection point to expose the connection point, and forming a first wiring layer electrically communicating the conductive metal and the connection point on the protection layer; and removing the first wiring layer and the protective layer on the optical port to expose the optical port. According to the invention, before the active optical chip is subjected to the silicon through hole process, the protective layer is formed on the surface of the active optical chip, so that pollution to an optical port by a subsequent process and damage to a connection point by a wet process liquid medicine are reduced, and the performance of the optical chip active adapter plate is ensured.

Description

Technical Field

[0001] The present invention relates to the technical field of adapter plates, and in particular to an active optical chip adapter plate and a preparation method thereof. Background Art

[0002] In order to achieve higher bandwidth, higher speed and lower energy consumption information transmission, optical chips are no longer satisfied with simple wire bonding (WB) packaging process, but began to try various packaging processes such as bump process and through-hole process on optical chips, so as to achieve 2.5D / 3D packaging and meet more and higher application requirements. For example, the chip-on-wafer-on-substrate (CoWoS) is a 2.5D packaging technology that packages the chip onto the wafer and uses the high-density wiring on the wafer for interconnection, and further connects to the packaging substrate; CoWoS-S (including Silicon Interposer) is a type of CoWoS. CoWoS-S is a wafer substrate packaging technology that uses a silicon interposer (i.e., a silicon interposer) as the main connection medium. The silicon interposer has a precise manufacturing process and superior electrical performance. Therefore, this structure usually has a high-density I / O interconnection to meet the needs of high-performance computing and large-scale integrated circuits.

[0003] In the related technology, optical chips can be used to make active adapter boards to replace the silicon adapter boards in the CoWoS-S process to achieve multi-chip interconnect packaging, which is one of the most promising solutions for achieving 2.5D / 3D optoelectronic packaging. However, in the process of making optical chips into active adapter boards, it is usually necessary to use through silicon via (TSV) technology to form interconnect channels on silicon wafers. However, the process of processing TSV is easy to contaminate the exposed optical ports on the silicon wafer, which leads to the problem of reduced performance or even failure of the adapter board. Summary of the invention

[0004] In view of this, the present invention provides an active optical chip adapter plate and a preparation method thereof to solve the problem that the optical port is easily contaminated during the through silicon via manufacturing process of the active optical chip, resulting in failure or even reduction of the performance of the adapter plate.

[0005] In a first aspect, the present invention provides a method for preparing an active optical chip adapter plate, comprising:

[0006] Providing an active optical chip, the active optical chip having a connection point and an exposed optical port;

[0007] forming a protective layer on the active optical chip, wherein the protective layer covers the optical port and the connection point;

[0008] Forming a through silicon via structure penetrating the protective layer and extending to the active optical chip, wherein the through silicon via structure includes a conductive metal and is staggered with the optical port and the connection point;

[0009] Removing a protective layer located on the connection point to expose the connection point;

[0010] forming a first wiring layer on the protective layer, the first wiring layer electrically connecting the conductive metal and the connection point;

[0011] The first wiring layer and the protection layer located on the optical port are removed to expose the optical port.

[0012] Beneficial effects: The preparation method of the active optical chip adapter board of the present invention first forms a protective layer on the surface of the active optical chip before performing the through silicon via process on the active optical chip, so as to protect the optical port and metal connection points on the surface of the active optical chip, and minimize the contamination of the optical port by materials such as photoresist and physical vapor deposition in subsequent processes, as well as the damage of the surface metal connection points by wet chemical solutions; in addition, the through silicon via structure is formed on the protective layer and the active optical chip at one time, avoiding defects such as nail heads on different structural layers due to factors such as overlay, simplifying the process flow, and ensuring the performance of the optical chip active adapter board.

[0013] In an optional embodiment, the active optical chip includes an optical chip body and an active functional layer located on a surface of one side of the optical chip body, and the optical port and the connection point are arranged on a side of the active functional layer relatively far from the optical chip body.

[0014] Beneficial effects: The active functional layer integrates power supply, on-chip network communication and other functions, and the optical chip body provides matrix support. The connection points of the active functional layer are used for electrical connection of the active optical chip, and the dielectric layer is coated with the metal layer to achieve protection function.

[0015] In an optional embodiment, forming a through silicon via structure penetrating the protective layer and extending to the active optical chip includes:

[0016] forming a vertical hole penetrating the protective layer, the active functional layer and extending to a portion of the optical chip body;

[0017] Forming a first insulating layer on one side of the protective layer, the first insulating layer covering a surface of the protective layer facing away from the active optical chip and an inner wall surface of the vertical hole;

[0018] A conductive metal is filled in the vertical hole having the first insulating layer to form a through silicon via structure.

[0019] Beneficial effect: To form a through silicon via structure, firstly, a vertical hole is opened on the active optical chip, avoiding the connection point and the optical port. The vertical hole penetrates the protective layer and the active functional layer, and extends to part of the optical chip body, that is, the bottom of the vertical hole is located at a certain distance from the bottom of the optical chip body, so as to form a complete first insulating layer; the filled conductive metal and the first insulating layer on its surrounding side constitute a through silicon via structure, which is convenient for efficient electrical connection in the direction perpendicular to the chip surface, avoiding leakage problems that may be caused by metal ion migration.

[0020] In an optional embodiment, forming a vertical hole penetrating the protective layer and the active functional layer and extending to a portion of the optical chip body includes:

[0021] forming a mask layer having a hollow region on the protective layer, wherein the hollow region is suitable for exposing a portion of the protective layer;

[0022] The protective layer, active functional layer and part of the optical chip body exposed in the hollowed-out area are removed at one time, so as to form a vertical hole penetrating the protective layer and part of the active optical chip;

[0023] The mask layer is removed.

[0024] Beneficial effects: The present invention prepares and utilizes a mask layer once to continuously complete the opening of the protective layer and the etching of the active optical chip, avoiding nail head defects caused by multiple overlays of different mask layers on different structural layers, improving the quality of the active optical chip adapter board, and simplifying the process flow, thereby having the effect of reducing costs and increasing efficiency.

[0025] In an optional embodiment, the first wiring layer includes: a first metal layer, a first dielectric material layer and a second metal layer, the first metal layer connects the connection point and the conductive metal; the first dielectric material layer covers the first metal layer; the second metal layer is suitable for passing through the first dielectric material layer to electrically connect the first metal layer and the external structure.

[0026] Beneficial effects: The first wiring layer includes a first metal layer and a second metal layer. The bottom first metal layer is used to fill the first opening on the connection point and extend to the conductive metal of the through-silicon via structure to achieve precise electrical conduction between the through-silicon via structure and the connection point. The second metal layer is connected to the first metal layer in the vertical direction, and the exposed upper end of the second metal layer can also be used as a "pad" electrically connected to the external structure; at the same time, the first dielectric material layer fills other areas between the first metal layer and the second metal layer to achieve insulation protection.

[0027] In an optional implementation manner, after removing the first wiring layer and the protective layer on the optical port to expose the optical port, the method further includes:

[0028] Thin the side of the active optical chip facing away from the first wiring layer to expose the conductive metal:

[0029] A second insulating layer is provided on a side of the active optical chip away from the first wiring layer, and the second insulating layer is connected to the first insulating layer;

[0030] A second wiring layer is formed on one side of the second insulating layer to connect the conductive metal on the side of the active optical chip away from the first wiring layer.

[0031] Beneficial effects: A second wiring layer is formed on the other side of the active optical chip opposite to the first wiring layer, the metal material in the second wiring layer serves as an interconnect metal to realize the electrical derivation of the conductive metal of the through silicon via structure, and has a lateral extension on the surface of the second insulating layer to realize the reasonable arrangement of the electrical derivation position and size; the dielectric material in the second wiring layer surrounds the coated metal material to realize insulation protection.

[0032] In an optional embodiment, after the step of forming a second wiring layer on one side of the second insulating layer to connect the conductive metal on the side of the active optical chip away from the first wiring layer, the method further includes:

[0033] A solder ball is arranged on a side of the second wiring layer away from the active optical chip to be electrically connected to the second wiring layer.

[0034] Beneficial effect: Solder balls are arranged on the back side of the active optical chip adapter board for connecting to the substrate, thereby achieving efficient electrical connection.

[0035] In an optional embodiment, after removing the first wiring layer and the protective layer on the optical port to expose the optical port, and before thinning the side of the active optical chip away from the first wiring layer to expose the conductive metal, the method further includes: providing a release adhesive layer on the first wiring layer, the release adhesive layer covering the optical port; providing a temporary bonding layer on the release adhesive layer;

[0036] After the solder balls are arranged on the side of the second wiring layer away from the active optical chip, the method further includes: removing the peeling glue layer and the temporary bonding layer.

[0037] Beneficial effect: After completing the structural preparation on the front side, a temporary auxiliary peeling adhesive layer and a temporary bonding layer are set on the front side. The peeling adhesive layer has a certain stickiness but can be torn off. It can not only protect the light port, but also fix the temporary bonding layer, which is helpful to form structures such as the second wiring layer on the back side of the active optical chip; and it is convenient to remove the temporary bonding layer on the peeling adhesive layer when removing it.

[0038] In the second aspect, the present invention also provides an active optical chip adapter board, which is prepared by the above-mentioned active optical chip adapter board preparation method, including: an active optical chip, a protective layer, a silicon through hole structure and a first wiring layer, one side surface of the active optical chip has a connection point and an exposed optical port; the protective layer is arranged on the side of the active optical chip with the optical port, and the protective layer has openings on the optical port and the connection point to expose the optical port and the connection point; the silicon through hole structure includes a conductive metal that penetrates the protective layer and the active optical chip; the silicon through hole structure is staggered with the optical port and the connection point; the first wiring layer is arranged on the side of the protective layer away from the active optical chip, the first wiring layer is electrically connected to the conductive metal and the connection point, and is suitable for conducting electricity to an external structure, and the protective layer and the first wiring layer expose the optical port.

[0039] Beneficial effects: For the active optical chip adapter board of the present invention, a protective layer is first used to protect the optical port and the connection point before the through silicon via structure is formed, so as to avoid damage to the optical port and the connection point, and ensure that the connection point can efficiently realize circuit connectivity and the optical port can smoothly receive the optical signal; when other semiconductor structure layers are stacked on the active optical chip, the through silicon via structure and the first wiring layer ensure the connectivity of the lines in the vertical direction, and finally the active optical chip adapter board can realize the power supply, on-chip network communication and other performances of the semiconductor device of the multi-layer chip integrated package.

[0040] In an optional implementation, the active optical chip adapter board further includes:

[0041] A first insulating layer is provided on a surface of the protective layer facing away from the active optical chip and on an outer side of the through silicon via structure;

[0042] A second insulating layer is disposed on a surface of the active optical chip on a side away from the first wiring layer, and the second insulating layer has an opening on the through silicon via structure;

[0043] A second wiring layer is arranged on a side of the active optical chip away from the first wiring layer, and the second wiring layer is suitable for connecting to the conductive metal through the opening of the second insulating layer;

[0044] The solder ball is disposed on the second wiring layer, and the solder ball is electrically connected to the second wiring layer.

[0045] Beneficial effects: The first insulating layer and the second insulating layer form an insulating isolation for the conductive metal and other structural layers, ensuring that the conductive metal can accurately realize the electrical connection with the connection point and the first wiring layer and the second wiring layer, thereby ensuring the communication between the active optical chip and the structures on the upper and lower sides; the second wiring layer and solder balls arranged on the back side of the active optical chip help to realize the connection between the active optical chip and structures such as the substrate, and ultimately enable the active optical chip adapter board to provide vertical line electrical connection and internal communication and other performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0047] Figure 1 It is a schematic flow chart of a method for preparing an active optical chip adapter board according to an embodiment of the present invention;

[0048] Figure 2 is a schematic structural diagram of an active optical chip according to an embodiment of the present invention;

[0049] Figure 3 is a schematic structural diagram of forming a protective layer on an active optical chip according to an embodiment of the present invention;

[0050] Figure 4 is a schematic structural diagram of forming vertical holes on a protective layer and an active optical chip according to an embodiment of the present invention;

[0051] Figure 5 is a schematic structural diagram of forming a through silicon via structure according to an embodiment of the present invention;

[0052] Figure 6 is a structural schematic diagram of a connection point in an embodiment of the present invention in which a first opening is formed on the connection point to expose the connection point;

[0053] Figure 7 is a schematic structural diagram of forming a first wiring layer on the front side of an active optical chip according to an embodiment of the present invention;

[0054] Figure 8 is a structural schematic diagram of forming a second opening above the light port to expose the light port in an embodiment of the present invention;

[0055] Fig. 9 It is a schematic structural diagram of a stripping adhesive layer and a temporary bonding layer provided on the front side of an active optical chip according to an embodiment of the present invention;

[0056] Fig.10 It is a schematic structural diagram of an active optical chip adapter board according to an embodiment of the present invention.

[0057] Description of reference numerals:

[0058] 1. Optical chip body; 2. Active functional layer; 201. Connection point; 202. Optical port; 3. Protective layer; 4. Through silicon via structure; 401. Vertical hole; 402. Conductive metal; 5. First insulating layer; 6. First wiring layer; 601. First metal layer; 602. First dielectric material layer; 603. Second metal layer; 7. Second insulating layer; 8. Second wiring layer; 801. Third metal layer; 802. Second dielectric material layer; 9. Solder ball; 10. First opening; 11. Second opening;

[0059] 100, peeling adhesive layer; 200, temporary bonding layer. DETAILED DESCRIPTION

[0060] The present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It is understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only some structures related to the present invention are shown in the accompanying drawings, rather than all structures. In the following description, the description of known structures and technologies is omitted to avoid unnecessary confusion of the concept of the present invention. Various structural schematic diagrams according to embodiments of the present invention are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified for the purpose of clear expression, and some details may be omitted. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships between them are only exemplary, and may be deviated due to manufacturing tolerances or technical limitations in practice, and those skilled in the art may additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs. In the context of the present invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. In addition, if one layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0061] refer to Figures 1 to 10 This embodiment provides a method for preparing an active optical chip adapter plate. Figure 1 is a schematic flow diagram of the preparation method, which comprises:

[0062] Step S101 : providing an active optical chip, wherein the active optical chip has a connection point 201 and an exposed optical port 202 .

[0063] refer to Figure 2The active optical chip of this embodiment is provided with an exposed connection point 201 and an optical port 202 on the upper surface. The connection point 201 may be a metal pad, for example. The connection point 201 is used to interconnect with subsequent circuits, and the optical port 202 is used to receive subsequent optical signals, thereby laying the foundation for the optical chip active adapter board to realize functions such as power supply and intra-chip network communication; Figure 2 The structure shown may be an incoming wafer structure of an optical chip, and an active functional layer 2 is provided on one side surface of the optical chip body 1 , and the connection point 201 and the optical port 202 are exposed on the active functional layer 2 .

[0064] Step S102 , forming a protection layer 3 on the active optical chip, wherein the protection layer 3 covers the optical port 202 and the connection point 201 .

[0065] For example, reference Figure 3 The protective layer 3 of this embodiment is an inorganic dielectric layer formed of silicon oxide or silicon nitride. The protective layer 3 is used to protect the optical port 202 and the connection point 201, and to minimize the contamination of the optical port 202 by the photoresist and deposition materials in the subsequent process, and to avoid the damage of the metal connection point 201 on the surface by the wet process liquid. Figure 2 As shown, in this embodiment, a protective layer 3 can be formed on the surface of the active functional layer 2 away from the optical chip body 1 through a deposition process. The thickness of the protective layer 3 can be set according to specific preparation requirements, which is not limited in this embodiment.

[0066] Step S103 , forming a through silicon via structure 4 penetrating the protective layer 3 and the active optical chip. The through silicon via structure 4 includes a conductive metal 402 and is staggered with the optical port 202 and the connection point 201 .

[0067] refer to Figure 4 and Figure 5 , forming a through silicon via structure 4 that sequentially penetrates the protective layer 3 and the active functional layer 2 and extends into the optical chip body 1. Optionally, after the through silicon via structure 4 penetrates the protective layer 3 and the active functional layer 2, it can also penetrate the optical chip body 1. In this embodiment, after the through silicon via structure 4 is formed, a metal material layer can be formed in the through silicon via structure 4 and on the protective layer 3 by depositing a metal material, and the metal material layer on the surface of the protective layer 3 can be removed by a process such as planarization, and the metal material layer in the through silicon via structure 4 is retained to obtain a conductive metal 402.

[0068] The through silicon via structure 4 (TSV structure for short) vertically penetrates the protective layer 3 and extends to the active optical chip. The conductive metal 402 in the through silicon via structure 4 can be used to accurately connect the stacked structures on both sides of the overall structure formed by the protective layer 3 and the active optical chip, thereby realizing high-speed communication of the structure within the chip or vertical line conduction of the stacked chips, thereby achieving technical purposes such as improving the interconnection performance of the integrated circuit and assisting in improving the performance of the active optical chip.

[0069] Step S104 , removing the protection layer 3 on the connection point 201 to expose the connection point 201 .

[0070] refer to Figure 6 For example, the protective layer 3 located above the connection point 201 can be precisely removed by photolithography, that is, a first opening 10 is formed above the connection point 201 to expose the connection point 201, and the exposed connection point 201 facilitates subsequent circuit connection.

[0071] Specifically, in this embodiment, a photolithography mask may be disposed above the protective layer 3, and the mask has a pattern matching the connection point 201, so that part of the protective layer 3 and part of the active functional layer 2 may be removed by photolithography to expose the connection point 201. Alternatively, the connection point 201 may also be exposed by etching.

[0072] Step S105 , forming a first wiring layer 6 on the protection layer 3 , wherein the first wiring layer 6 electrically connects the conductive metal 402 and the connection point 201 .

[0073] refer to Figure 7 The process of forming the first wiring layer 6 on the protective layer 3 may include a process of forming a non-metallic part and a process of forming a metal part. The metal part of the first wiring layer 6 is filled into the first opening 10 and extends to the conductive metal 402 of the through silicon via structure 4 above the protective layer 3 to achieve electrical connection between the connection point 201 and the conductive metal 402. At the same time, when other chips are stacked on the upper surface of the active optical chip adapter board of this embodiment, the first wiring layer 6 can also be used as an intermediate layer for electrical connection. The first wiring layer 6 can be used to achieve electrical connection between different structures and improve the positional relationship of the electrical connection.

[0074] Step S106 , removing the first wiring layer 6 and the protection layer 3 located on the optical port 202 to expose the optical port 202 .

[0075] refer to Figure 8 The purpose of this step is to expose the optical port 202 to achieve the reception of optical signals. Therefore, it is necessary to remove the structural layer covering the optical port 202 to form a second opening 11 exposing the optical port 202, which specifically includes a small portion of the first wiring layer 6 and the protective layer 3 corresponding to the optical port 202. Of course, in some embodiments, if the first wiring layer 6 is not covered above the optical port 202 in the aforementioned step, it is only necessary to remove the protective layer 3.

[0076] The preparation method of the active optical chip adapter board of this embodiment is as follows: before performing the through silicon via process on the active optical chip, a protective layer 3 is first formed on the surface of the active optical chip to protect the optical port 202 and the metal connection point 201 on the surface of the active optical chip, so as to minimize the contamination of the optical port 202 by materials such as photoresist and physical vapor deposition materials in subsequent processes, and the damage of the surface metal connection point 201 by wet chemical solution; in addition, the through silicon via structure 4 is formed on the protective layer 3 and the active optical chip at one time, so as to avoid defects such as nail heads on different structural layers due to factors such as overlay, simplify the process flow, and ensure the performance of the optical chip active adapter board.

[0077] like Figures 2 to 10 As described above, the active optical chip comprises an optical chip body 1 and an active functional layer 2 located on a surface of one side of the optical chip body 1 , and the optical port 202 and the connection point 201 are arranged on a side of the active functional layer 2 relatively far from the optical chip body 1 .

[0078] Specifically, the active functional layer 2 integrates functions such as power supply and on-chip network communication, and the optical chip body 1 provides substrate support. The active functional layer 2 includes a dielectric layer and a metal layer with a connection point 201. The metal layer includes multiple layers of metal interconnects. The metal material involved in each embodiment of the present invention can be copper, aluminum, silver, gold and other metal materials, generally formed by a Damascus inlay process, and the dielectric layer can be silicon oxide or silicon nitride; the connection point 201 is used for the electrical connection of the active optical chip, and the connection point 201 can be exposed or covered by the dielectric layer. In this embodiment, the connection point 201 of the active optical chip is exposed.

[0079] In one embodiment, the step S103, forming a through silicon via structure 4 penetrating the protective layer 3 and the active optical chip, includes:

[0080] Step S1031 , forming a vertical hole 401 penetrating the protective layer 3 and the active functional layer 2 and extending to a portion of the optical chip body 1 .

[0081] refer to Figure 4 In the process of forming the through silicon via structure 4, firstly, a vertical hole 401 is opened on the active optical chip at a position avoiding the connection point 201 and the optical port 202. The vertical hole 401 penetrates the protective layer 3 and the active functional layer 2, and extends to part of the optical chip body 1, that is, the bottom of the vertical hole 401 is located at a certain distance from the bottom of the optical chip body 1. The distance between the bottom of the vertical hole 401 and the bottom of the optical chip body 1 is specifically the sum of the thickness of the part to be removed in the optical chip body 1 described later and the thickness of the first insulating layer 5 described later.

[0082] Step S1032 : forming a first insulating layer 5 on one side of the protective layer 3 , wherein the first insulating layer 5 covers a surface of the protective layer 3 facing away from the active optical chip and an inner wall surface of the vertical hole 401 .

[0083] refer to Figure 5 The first insulating layer 5 covers the surface on the side where the protective layer 3 is located, specifically including the upper surface of the protective layer 3 and the side wall and bottom surface of the vertical hole 401, so that the structure subsequently formed above the vertical hole 401 and the protective layer 3 is relatively insulated from the surface of the active optical chip that does not need to be electrically connected, preventing metal ions from migrating and causing defects such as leakage; wherein the material forming the first insulating layer 5 can be, for example, silicon oxide or silicon nitride, etc., a material that can be used to achieve an insulating function.

[0084] Step S1033 , filling the vertical hole 401 having the first insulating layer 5 with a conductive metal 402 to form a through silicon via structure 4 .

[0085] refer to Figure 5 In this embodiment, a metal material layer can be deposited and ensured to fill the vertical hole 401. Then, the metal material layer on the surface of the protective layer 3 can be removed by CMP (Chemical Mechanical Planarization) or other methods, so that the remaining metal material layer is used as a conductive metal 402. The upper surface of the conductive metal 402 is flush with the upper surface of the insulating layer to strictly ensure the electrical connection performance of the silicon through hole structure 4. The filled conductive metal 402 and the first insulating layer 5 on its surrounding side constitute the silicon through hole structure 4, which is convenient for efficient electrical connection in a direction perpendicular to the chip surface, avoiding leakage problems that may be caused by metal ion migration.

[0086] In one embodiment, the step S1031 above, forming a vertical hole 401 penetrating the protective layer 3 and the active functional layer 2 and extending to a portion of the optical chip body 1, includes:

[0087] Step S1031a: forming a mask layer having a hollow area on the protective layer 3, wherein the hollow area is suitable for exposing a portion of the protective layer 3.

[0088] Specifically, a layer of photoresist is first deposited on the protective layer 3 as an initial mask layer, and then hollowed out on the photoresist corresponding to the area where holes need to be opened on the protective layer 3 through a photolithography method of exposure and development, so as to obtain a mask layer with partially hollowed-out areas, which serves as a shielding layer for subsequent selective area opening.

[0089] Step S1031b, removing the protective layer 3, the active functional layer 2 and part of the optical chip body 1 exposed in the hollowed-out area at one time, forming a vertical hole 401 penetrating the protective layer 3 and part of the active optical chip.

[0090] For example, KOH wet etching, laser drilling, deep reactive ion etching and light-assisted electrochemical etching can be used to remove the protective layer 3, active functional layer 2 and part of the optical chip body 1 exposed in the hollow area to form a vertical hole 401 whose bottom is a certain distance from the bottom of the optical chip body 1.

[0091] Step S1031c, removing the mask layer.

[0092] Exemplarily, the mask layer after the opening is removed by chemical solution.

[0093] In the present embodiment, the window opening of the protective layer 3 and the etching of the active optical chip are completed in a continuous operation through the preparation and utilization of a single mask layer, thereby avoiding nail head defects caused by multiple overlays of different mask layers on different structural layers, improving the quality of the active optical chip adapter board, simplifying the process flow, and having the effect of reducing costs and increasing efficiency.

[0094] Figure 6 In the above step S104 shown, in the step of removing the protection layer 3 on the connection point 201, the first insulating layer 5 above the protection layer 3 can be removed simultaneously; in this way, the process steps can be reduced and the process flow can be simplified.

[0095] See also Figure 7 The first wiring layer 6 of this embodiment includes: a first metal layer 601, a first dielectric material layer 602 and a second metal layer 603, the first metal layer 601 connects the connection point 201 and the conductive metal 402; the first dielectric material layer 602 covers the first metal layer 601; the second metal layer 603 is suitable for passing through the first dielectric material layer 602 to electrically connect the first metal layer 601 and the external structure.

[0096] The side where the active functional layer 2 of the active optical chip is located is used as the front side, and the other side surface opposite to the front side is used as the back side; a first wiring layer 6 is formed on the front side, and the first wiring layer 6 includes a first metal layer 601 and a second metal layer 603 made of the same metal material. The first metal layer 601 of the bottom layer is used to fill the first opening 10 on the connection point 201 and the conductive metal 402 extending to the silicon through hole structure 4, so as to achieve precise electrical conduction between the silicon through hole structure 4 and the connection point 201. The second metal layer 603 is connected with the first metal layer 601 in the vertical direction. The exposed upper end of the second metal layer 603 can also be used as a "pad" electrically connected to an external circuit structure, and the external structure can be a chip with micro-bumps; at the same time, the first dielectric material layer 602 fills other areas between the first metal layer 601 and the second metal layer 603. The material of the first dielectric material layer 602 can be an insulating material such as silicon nitride to achieve insulation protection. The specific process for forming the first wiring layer 6 in this embodiment can be selected from the relevant technology, subject to the ability to form the first wiring layer 6 on the protective layer 3, and this embodiment does not limit this.

[0097] Figure 8 In step S106 shown, while removing the first wiring layer 6 and the protective layer 3 on the optical port 202 to expose the optical port 202 , the first insulating layer 5 corresponding to the position of the optical port 202 on the protective layer 3 is removed simultaneously.

[0098] In one embodiment, reference Fig. 9 and Fig.10 In the above step S106, after removing the first wiring layer 6 and the protective layer 3 located on the optical port 202 to expose the optical port 202, the preparation method of this embodiment further includes:

[0099] Step S107 , thinning a side of the active optical chip away from the first wiring layer 6 to expose the conductive metal 402 .

[0100] Exemplarily, the back side of the active optical chip can be thinned by cutting, grinding, etc., so that the conductive metal 402 originally located at the bottom of the vertical hole 401 and at a certain distance from the back side of the active optical chip can be exposed from the back side of the active optical chip.

[0101] It should be known that the thinning in this step will simultaneously remove the first insulating layer 5 located at the bottom of the vertical hole 401, thereby ensuring that the conductive metal 402 can be exposed from the back side of the active optical chip and making the first insulating layer 5 a discontinuous structure, that is, there is no first insulating layer 5 on the lower end surface of the conductive metal 402.

[0102] Step S108 , disposing a second insulating layer 7 on a side of the active optical chip away from the first wiring layer 6 , wherein the second insulating layer 7 is connected to the first insulating layer 5 .

[0103] On the basis of the above, a second insulating layer 7 is deposited on the back side of the active optical chip, and the conductive metal 402 is exposed from the back side of the active optical chip by partially removing a portion of the second insulating layer 7 corresponding to the position of the conductive metal 402. In this embodiment, the method of removing a portion of the second insulating layer 7 corresponding to the position of the conductive metal 402 can be implemented by using a photolithography or etching process, and the specific details of the photolithography or etching process are not described in detail.

[0104] Step S109 , forming a second wiring layer 8 on one side of the second insulating layer 7 to connect the conductive metal 402 on the side of the active optical chip away from the first wiring layer 6 .

[0105] In this embodiment, the second wiring layer 8 has a similar structure to the first wiring layer 6 and can be manufactured using the same processing technology. Specifically, the second wiring layer 8 has a third metal layer 801 and a second dielectric material layer 802. The third metal layer 801 is used as an interconnecting metal to realize the electrical extraction of the conductive metal 402 of the through silicon via structure 4. The third metal layer 801 has a lateral extension on the surface of the second insulating layer 7 and the optical chip body 1 to realize the reasonable arrangement of the electrical extraction position and size, and can improve the stability of the connection between the solder ball 9 and the substrate described later; the second dielectric material layer 802 is made of the same material as the first dielectric material layer 602, and surrounds the third metal layer 801 to achieve insulation protection.

[0106] See also Fig.10 In one embodiment, after step S109 of forming a second wiring layer 8 on one side of the second insulating layer 7 to connect the conductive metal 402 on the side of the active optical chip away from the first wiring layer 6, the method further includes:

[0107] Step S1010 : disposing solder balls 9 on a side of the second wiring layer 8 away from the active optical chip to be electrically connected to the second wiring layer 8 .

[0108] In this embodiment, the back side of the active optical chip adapter board is used to connect to the substrate, and solder balls 9 with larger spacing are set to achieve connection with the substrate. Since the first wiring layer 6 on the front side is usually used for chip stacking, this embodiment realizes the function of the active optical chip with micro-bumps, so there is no need to set an additional solder ball 9 structure on the first wiring layer 6.

[0109] In one embodiment, after step S106 of removing the first wiring layer 6 and the protective layer 3 located on the optical port 202 to expose the optical port 202, and before step S107 of thinning the side of the active optical chip away from the first wiring layer 6 to expose the conductive metal 402, it also includes: setting a release adhesive layer 100 on the first wiring layer 6, the release adhesive layer 100 covering the optical port 202; and setting a temporary bonding layer 200 on the release adhesive layer 100.

[0110] That is, after completing the structural preparation on the front side, a temporary auxiliary release adhesive layer 100 and a temporary bonding layer 200 are set on the front side. The temporary bonding layer 200 can be used to ensure the stable implementation of the preparation process of the second wiring layer 8. The release adhesive layer 100 has a certain viscosity but can be torn off. It can not only protect the optical port 202, but also fix the temporary bonding layer 200, so as to help to make the second wiring layer 8 and other structures on the back of the active optical chip.

[0111] On this basis, after step S1010 of arranging solder balls 9 on the side of the second wiring layer 8 away from the active optical chip, the method further includes: removing the release adhesive layer 100 and the temporary bonding layer 200 .

[0112] Specifically, the adhesive layer 100 can be peeled off by tearing or removing with a cleaning solution to remove the adhesive layer 100 , and the temporary bonding layer 200 thereon will also fall off.

[0113] The present embodiment also provides an active optical chip adapter board, which is manufactured by the preparation method of the active optical chip adapter board in one or more embodiments of the present invention, and includes: an active optical chip, a protective layer 3, a silicon through hole structure 4 and a first wiring layer 6, wherein one side surface of the active optical chip has a connection point 201 and an exposed optical port 202; the protective layer 3 is arranged on the side of the active optical chip having the optical port 202, and the protective layer 3 has openings on the optical port 202 and the connection point 201 to expose the optical port 202 and the connection point 201; the silicon through hole structure 4 includes a conductive metal 402 that penetrates the protective layer 3 and the active optical chip; the silicon through hole structure 4 is staggered with the optical port 202 and the connection point 201, and is insulated from the protective layer 3 and the active optical chip; the first wiring layer 6 is arranged on the side of the protective layer 3 away from the active optical chip, the first wiring layer 6 is electrically connected to the conductive metal 402 and the connection point 201, and is suitable for conducting electricity to an external structure, and the protective layer 3 and the first wiring layer 6 expose the optical port 202.

[0114] In the active optical chip adapter board of this embodiment, before the silicon through via structure 4 is formed, the protective layer 3 is first used to protect the optical port 202 and the connection point 201, so as to avoid damage to the optical port 202 and the connection point 201, thereby ensuring that the connection point 201 efficiently realizes circuit connectivity and the optical port 202 smoothly receives the optical signal; when other semiconductor structure layers are stacked on the active optical chip, the silicon through via structure 4 and the first wiring layer 6 ensure the connectivity of the lines in the vertical direction, thereby finally enabling the active optical chip adapter board to realize the power supply, on-chip network communication and other performances of the semiconductor device with multi-layer chip integrated packaging.

[0115] In one embodiment, the above-mentioned active optical chip adapter board also includes: a first insulating layer 5, a second insulating layer 7, a second wiring layer 8 and a solder ball 9, the first insulating layer 5 is arranged on the side surface of the protective layer 3 away from the active optical chip and on the outside of the silicon through hole structure 4; the second insulating layer 7 is arranged on the side surface of the active optical chip away from the first wiring layer 6, and the second insulating layer 7 has an opening on the silicon through hole structure 4; the second wiring layer 8 is arranged on the side of the active optical chip away from the first wiring layer 6, and the second wiring layer 8 is suitable for connecting with the conductive metal 402 through the opening of the second insulating layer 7; the solder ball 9 is arranged on the second wiring layer 8, and the solder ball 9 is electrically connected to the second wiring layer 8.

[0116] The first insulating layer 5 and the second insulating layer 7 mentioned above form an insulating isolation for the conductive metal 402 and other structural layers to ensure that the conductive metal 402 accurately realizes electrical connection with the connection point 201 and the first wiring layer 6 and the second wiring layer 8, and ensures the communication between the internal circuit of the active optical chip and the structures on the upper and lower sides; the second wiring layer 8 and the solder ball 9 arranged on the back side of the active optical chip help to realize the connection between the active optical chip and the substrate and other structures, and finally enable the active optical chip adapter board to provide line electrical connection and internal communication in the direction perpendicular to the chip surface.

[0117] The further functional description and structural layout embodiments of the above-mentioned structures are the same as the corresponding embodiments in the above-mentioned method for preparing the active optical chip adapter board, and will not be repeated here.

[0118] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

[0119] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A method for preparing an active optical chip adapter plate, characterized in that: include: Providing an active optical chip, wherein the active optical chip has a connection point and an exposed optical port; forming a protective layer on the active optical chip, wherein the protective layer covers the optical port and the connection point; Forming a through silicon via structure penetrating the protective layer and extending into the active optical chip, wherein the through silicon via structure comprises a conductive metal, is staggered with the optical port and the connection point, and is insulated from the protective layer and the active optical chip; removing the protective layer on the connection point to expose the connection point; forming a first wiring layer on the protective layer, wherein the first wiring layer electrically connects the conductive metal and the connection point; The first wiring layer and the protection layer located on the optical port are removed to expose the optical port.

2. The method for preparing the active optical chip adapter plate according to claim 1, characterized in that: The active optical chip comprises an optical chip body and an active functional layer located on a surface of one side of the optical chip body, and the optical port and the connection point are arranged on a side of the active functional layer relatively far away from the optical chip body.

3. The method for preparing the active optical chip adapter plate according to claim 2, characterized in that: The forming of a through silicon via structure penetrating the protective layer and the active optical chip comprises: forming a vertical hole penetrating the protective layer, the active functional layer and extending to a portion of the optical chip body; forming a first insulating layer on one side of the protective layer, wherein the first insulating layer covers a surface of the protective layer facing away from the active optical chip and an inner wall surface of the vertical hole; A conductive metal is filled in the vertical hole having the first insulating layer to form a through silicon via structure.

4. The method for preparing the active optical chip adapter plate according to claim 3, characterized in that: The forming of a vertical hole penetrating the protective layer and the active functional layer and extending to a portion of the optical chip body comprises: forming a mask layer having a hollow region on the protective layer, wherein the hollow region is suitable for exposing a portion of the protective layer; Removing the protective layer, the active functional layer and part of the optical chip body exposed in the hollow area at one time to form a vertical hole penetrating the protective layer and part of the active optical chip; The mask layer is removed.

5. The method for preparing the active optical chip adapter plate according to claim 1, characterized in that: The first wiring layer includes: a first metal layer, a first dielectric material layer and a second metal layer, the first metal layer connects the connection point and the conductive metal; the first dielectric material layer covers the first metal layer; the second metal layer is suitable for passing through the first dielectric material layer to electrically connect the first metal layer and the external structure.

6. The method for preparing the active optical chip adapter plate according to claim 3, characterized in that: After removing the first wiring layer and the protective layer on the optical port to expose the optical port, the method further includes: Thinning a side of the active optical chip away from the first wiring layer to expose the conductive metal: Disposing a second insulating layer on a side of the active optical chip away from the first wiring layer, wherein the second insulating layer is connected to the first insulating layer; A second wiring layer is formed on one side of the second insulating layer to connect the conductive metal on the side of the active optical chip away from the first wiring layer.

7. The method for preparing the active optical chip adapter plate according to claim 6, characterized in that: After the step of forming a second wiring layer on one side of the second insulating layer to connect the conductive metal on the side of the active optical chip away from the first wiring layer, the method further includes: A solder ball is disposed on a side of the second wiring layer away from the active optical chip to be electrically connected to the second wiring layer.

8. The method for preparing the active optical chip adapter plate according to claim 7, characterized in that: After the step of removing the first wiring layer and the protective layer on the optical port to expose the optical port, and before the step of thinning the side of the active optical chip away from the first wiring layer to expose the conductive metal, the method further includes: providing a release adhesive layer on the first wiring layer, the release adhesive layer covering the optical port; and providing a temporary bonding layer on the release adhesive layer; After solder balls are arranged on a side of the second wiring layer away from the active optical chip, the method further includes: removing the release adhesive layer and the temporary bonding layer.

9. An active optical chip adapter board, made by the method for making an active optical chip adapter board according to any one of claims 1 to 8, characterized in that: include: An active optical chip, wherein one side surface of the active optical chip has a connection point and an exposed optical port; A protective layer, wherein the protective layer is disposed on a side of the active optical chip having the optical port, and the protective layer has openings on the optical port and the connection point to expose the optical port and the connection point; A through silicon via structure, wherein the through silicon via structure includes a conductive metal penetrating the protective layer and the active optical chip; The through silicon via structure is staggered with the optical port and the connection point; A first wiring layer, wherein the first wiring layer is arranged on a side of the protective layer away from the active optical chip, the first wiring layer electrically connects the conductive metal and the connection point and is suitable for conducting electricity to an external structure, and the protective layer and the first wiring layer expose the optical port.

10. The active optical chip adapter board according to claim 9, characterized in that: Also includes: A first insulating layer is disposed on a surface of the protective layer facing away from the active optical chip and on an outer side of the through silicon via structure; A second insulating layer is disposed on a surface of the active optical chip on a side away from the first wiring layer, and the second insulating layer has an opening on the through silicon via structure; A second wiring layer is arranged on a side of the active optical chip away from the first wiring layer, and the second wiring layer is suitable for connecting to the conductive metal through the opening of the second insulating layer; A solder ball is disposed on the second wiring layer, and the solder ball is electrically connected to the second wiring layer.

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