Touch and display driver integrated circuit

Abstract

The invention provides a TDDI circuit. The TDDI circuit comprises first to sixth pins, first to second low dropout regulator (LDO) and first to seventh switches. The fourth pin is coupled to the first pin through a first external capacitor and provides a first driving voltage. The fourth pin is coupled to a first lower limit voltage. The fifth pin is coupled to the second pin through a second external capacitor and provides a second driving voltage. The sixth pin is coupled to the third pin through a third external capacitor and provides a substrate voltage. The sixth pin is coupled to a second lower limit voltage and a ground voltage. The first LDO provides a specific voltage. The second LDO provides an output signal. The first switch, the fifth switch and the seventh switch are controlled by a first control signal. The second switch and the sixth switch are controlled by a second control signal. The third switch and the fourth switch are respectively controlled by the third control signal and the fourth control signal.

Description

Technical Field

[0001] The present invention relates to a display, and in particular to a touch and display driver integration (TDDI) circuit. Background Art

[0002] Please refer to Figures 1 to 3 , Figure 1 is a schematic diagram of a traditional TDDI circuit; Figure 2 The timing diagram of the traditional TDDI circuit driving the amorphous silicon (a-Si) panel to operate in the display time and touch time; Figure 3 The timing diagram of the traditional TDDI circuit driving the low-temperature polysilicon (LTPS) panel to operate in the display time and touch time.

[0003] In the application of TDDI circuit IC, the display driver circuit and the touch circuit are operated in time-sharing mode, that is, the display time DT of the display driver circuit and the touch time TT of the touch circuit are separated from each other. Figure 2 and Figure 3 During the touch time TT, the first driving voltage VGH and the second driving voltage VGL for controlling the thin film transistor switch on the liquid crystal display panel are in a floating state, and the first pin VGH_CAP_REF and the second pin VGL_CAP_REF of the TDDI circuit IC are coupled to the touch driving voltage for driving, so that the first driving voltage VGH and the second driving voltage VGL together serve as the touch driving voltage to eliminate the parasitic capacitance on the panel.

[0004] In general semiconductor processes, the withstand voltage of transistor components is usually limited to less than or equal to 32 volts (V). If the touch circuit of the TDDI circuit IC is a negative voltage circuit, the TDDI circuit IC needs to generate a minimum voltage as the substrate voltage VPSUB of the TDDI circuit IC during operation. However, this substrate voltage VPSUB will increase the cross-voltage of the component, resulting in the voltage difference between the first driving voltage VGH and the second driving voltage VGL being limited and unable to reach the limit value of 32 volts, and the voltage amplitude of the touch sensing signal whose voltage difference from the first driving voltage VGH to the substrate voltage VPSUB is less than or equal to 32 volts is also limited, which needs further improvement.

[0005] by Figure 2Taking the conventional TDDI circuit IC driving an amorphous silicon (a-Si) panel as an example, when the voltage difference between the first driving voltage VGH and the second driving voltage VGL is too large, in order to make the voltage difference from the first driving voltage VGH to the substrate voltage VPSUB less than or equal to 32 volts, the amplitude of the touch sensing signal will be limited, which needs further improvement. In addition, during the touch time TT of the touch circuit operation, because the level of the substrate voltage VPSUB must be lower than the lowest point of the second driving voltage VGL waveform, the voltage difference between the first driving voltage VGH and the second driving voltage VGL cannot reach the limit value of 32 volts, which needs further improvement.

[0006] by Figure 3 Taking the traditional TDDI circuit IC driving the low-temperature polysilicon (LTPS) panel as an example, when the first driving voltage VGH is too small, the trough of the first driving voltage VGH within the touch time TT may touch the first lower limit voltage VDPA, causing the touch sensing signal to be clamped by the diode D1 and its amplitude to be limited, which needs further improvement. Summary of the invention

[0007] Therefore, the present invention proposes a touch and display driver integration (TDDI) circuit to effectively solve the above problems encountered in the prior art.

[0008] A preferred specific embodiment according to the present invention is a touch and display driver integration (TDDI) circuit. In this embodiment, the TDDI circuit is used to drive the panel. The TDDI circuit includes: a first pin; a second pin; a third pin; a fourth pin, coupled to the first pin through a first external capacitor, for providing a first driving voltage, and the fourth pin is also coupled to a first lower limit voltage; a fifth pin, coupled to the second pin through a second external capacitor, for providing a second driving voltage; a sixth pin, coupled to the third pin through a third external capacitor, for providing a substrate voltage, and the sixth pin is also coupled to a second lower limit voltage and a ground voltage respectively; a first low-dropout regulator, for providing a specific voltage; a second low-dropout regulator, for providing an output signal; a first switch, coupled between the first pin and the first low-dropout regulator, and is controlled by a first control signal; a second switch, coupled between the first pin and the first preset voltage, and controlled by a second control signal; a third switch, coupled between the second pin and the second preset voltage, and controlled by a third control signal; a fourth switch, coupled between the second pin and the first preset voltage, and controlled by a fourth control signal; a fifth switch, coupled between the third pin and the second preset voltage, and controlled by the first control signal; a sixth switch, coupled between the third pin and the second low-dropout regulator, and controlled by the second control signal; and a seventh switch, coupled between the fifth pin and the sixth pin, and controlled by the first control signal.

[0009] In one embodiment, the panel is an amorphous silicon (a-Si) panel. During the display time, the first control signal and the third control signal are at a high level and the second control signal and the fourth control signal are at a low level, causing the first switch, the third switch, the fifth switch and the seventh switch to be turned on and the second switch, the fourth switch and the sixth switch to be turned off, and the first driving voltage has the original voltage value.

[0010] In one embodiment, at the first time t1, the display time ends and the touch time begins, the first control signal changes from a high level to a low level, the second control signal changes from a low level to a high level, the third control signal remains at a high level, and the fourth control signal remains at a low level, so that the second switch, the third switch, and the sixth switch are turned on and the first switch, the fourth switch, the fifth switch, and the seventh switch are turned off, and the first driving voltage drops from the original voltage value by a specific voltage to reduce the maximum voltage difference between the maximum value of the first driving voltage and the substrate voltage.

[0011] In one embodiment, at the second time t2, the first control signal is still maintained at a low level, the second control signal is still maintained at a high level, the third control signal changes from a high level to a low level, and the fourth control signal changes from a low level to a high level, so that the second switch, the fourth switch and the sixth switch are turned on and the first switch, the third switch, the fifth switch and the seventh switch are turned off, and the first driving voltage, the second driving voltage and the first preset voltage all drop by the same voltage.

[0012] In one embodiment, between the second time t2 and the third time t3, the first driving voltage, the second driving voltage and the first preset voltage all change in the same driving sine wave.

[0013] In one embodiment, at the third time t3, the first control signal is still maintained at a low level, the second control signal is still maintained at a high level, the third control signal changes from a low level to a high level, and the fourth control signal changes from a high level to a low level, so that the second switch, the third switch and the sixth switch are turned on and the first switch, the fourth switch, the fifth switch and the seventh switch are turned off, and the first driving voltage, the second driving voltage and the first preset voltage all rise by the same voltage.

[0014] In one embodiment, at the fourth time t4, the touch time ends and enters the display time, the first control signal changes from a low level to a high level, the second control signal changes from a high level to a low level, the third control signal is still maintained at a high level and the fourth control signal is still maintained at a low level, so that the first switch, the third switch, the fifth switch and the seventh switch are turned on and the second switch, the fourth switch and the sixth switch are turned off, and the first driving voltage rises by the first voltage to the original voltage value.

[0015] In one embodiment, during the touch time, the lowest point of the waveform of the second driving voltage is higher than the substrate voltage.

[0016] In one embodiment, the first external capacitor, the second external capacitor, the third external capacitor, the first lower limit voltage, the second lower limit voltage and the ground voltage are disposed on a circuit board.

[0017] In one embodiment, the panel is a low-temperature polycrystalline silicon (LTPS) panel. During the display time, the first control signal and the third control signal are at a high level and the second control signal and the fourth control signal are at a low level, causing the first switch, the third switch, the fifth switch and the seventh switch to be turned on and the second switch, the fourth switch and the sixth switch to be turned off, and the first driving voltage has the original voltage value.

[0018] In one embodiment, at the first time t1, the display time ends and the touch time begins, the first control signal changes from a high level to a low level, the second control signal changes from a low level to a high level, the third control signal remains at a high level, and the fourth control signal remains at a low level, so that the second switch, the third switch, and the sixth switch are turned on and the first switch, the fourth switch, the fifth switch, and the seventh switch are turned off, and the first driving voltage rises from the original voltage value by a specific voltage to increase the maximum voltage difference between the maximum value of the first driving voltage and the substrate voltage.

[0019] In one embodiment, at the second time t2, the first control signal is still maintained at a low level, the second control signal is still maintained at a high level, the third control signal changes from a high level to a low level, and the fourth control signal changes from a low level to a high level, so that the second switch, the fourth switch and the sixth switch are turned on and the first switch, the third switch, the fifth switch and the seventh switch are turned off, and the first driving voltage, the second driving voltage and the first preset voltage all drop by the same voltage.

[0020] In one embodiment, between the second time t2 and the third time t3, the first driving voltage, the second driving voltage and the first preset voltage all change in the same driving sine wave, the lowest point of the sine wave of the first driving voltage is higher than the first lower limit voltage and the difference between the two is widened to a specific voltage.

[0021] In one embodiment, at the third time t3, the first control signal is still maintained at a low level, the second control signal is still maintained at a high level, the third control signal changes from a low level to a high level, and the fourth control signal changes from a high level to a low level, so that the second switch, the third switch and the sixth switch are turned on and the first switch, the fourth switch, the fifth switch and the seventh switch are turned off, and the first driving voltage, the second driving voltage and the first preset voltage all rise by the same voltage.

[0022] In one embodiment, at the fourth time t4, the touch time ends and enters the display time, the first control signal changes from a low level to a high level, the second control signal changes from a high level to a low level, the third control signal is still maintained at a high level and the fourth control signal is still maintained at a low level, so that the first switch, the third switch, the fifth switch and the seventh switch are turned on and the second switch, the fourth switch and the sixth switch are turned off, and the first driving voltage drops by a first voltage to the original voltage value.

[0023] In one embodiment, during the touch time, the lowest point of the waveform of the second driving voltage is higher than the substrate voltage.

[0024] Another preferred specific embodiment according to the present invention is also a TDDI circuit. In this embodiment, the TDDI circuit is used to drive the panel. The TDDI circuit includes: a first pin; a second pin; a third pin; a fourth pin, coupled to the first pin through a first external capacitor, for providing a first driving voltage, and a first lower limit voltage is also coupled between the fourth pin and the first external capacitor; a fifth pin, coupled to the second pin through a second external capacitor, for providing a second driving voltage; a sixth pin, coupled to the third pin through a third external capacitor, for providing a substrate voltage, and a second lower limit voltage is also coupled between the sixth pin and the third external capacitor; a second low voltage dropout regulator, for providing an output signal; a first first switch, coupled between the first pin and the first lower limit voltage, when the panel is an amorphous silicon panel, the first first switch is controlled by the first first control signal to be turned on; a second first switch, coupled Connected between the first pin and the second lower limit voltage, when the panel is a low-temperature polysilicon panel, the second first switch is controlled by the second first control signal to be turned on; the second switch is coupled between the first pin and the first preset voltage, and is controlled by the second control signal; the third switch is coupled between the second pin and the second preset voltage, and is controlled by the third control signal; the fourth switch is coupled between the second pin and the first preset voltage, and is controlled by the fourth control signal; the fifth switch is coupled between the third pin and the second preset voltage, and is controlled by the first control signal; the sixth switch is coupled between the third pin and the second low voltage dropout regulator, and is controlled by the second control signal; and the seventh switch is coupled between the fifth pin and the sixth pin, and is controlled by the first control signal.

[0025] Another preferred specific embodiment according to the present invention is also a TDDI circuit. In this embodiment, the TDDI circuit is used to drive the panel. The TDDI circuit includes: a first pin; a second pin; a third pin; a fourth pin coupled to the first pin through a first external capacitor to provide a first driving voltage, and the fourth pin is also coupled to a first lower limit voltage; a fifth pin coupled to the second pin through a second external capacitor to provide a second driving voltage; a sixth pin coupled to the third pin through a third external capacitor to provide a substrate voltage, and the sixth pin is also coupled to a second lower limit voltage and a ground voltage respectively; a third low-dropout regulator to provide a specific voltage; a second low-dropout regulator to provide an output signal; a first switch coupled between the first pin and the second preset voltage, and is controlled by controlled by a first control signal; a second switch coupled between the first pin and the first preset voltage and controlled by the second control signal; a third switch coupled between the second pin and the third low voltage dropout regulator and controlled by the third control signal; a fourth switch coupled between the second pin and the first preset voltage and controlled by the fourth control signal; a fifth switch coupled between the third pin and the third low voltage dropout regulator and controlled by the first control signal; a sixth switch coupled between the third pin and the second low voltage dropout regulator and controlled by the second control signal; and a seventh switch coupled between the fifth pin and the sixth pin and controlled by the first control signal.

[0026] Another preferred specific embodiment according to the present invention is also a TDDI circuit. In this embodiment, the TDDI circuit is used to drive the panel. The TDDI circuit includes: a first pin; a second pin; a third pin; a fourth pin, coupled to the first pin through a first external capacitor, for providing a first driving voltage, and the fourth pin is also coupled to a first lower limit voltage; a fifth pin is coupled to the second pin through a second external capacitor, for providing a second driving voltage; a sixth pin is coupled to the third pin through a third external capacitor, for providing a substrate voltage, and the sixth pin and the third external capacitor are also respectively coupled to a second lower limit voltage; a second low voltage dropout regulator is used to provide an output signal; a first switch is coupled between the first pin and the second preset voltage, and is controlled by a first control signal; a second switch is coupled between the first pin and the first preset voltage, and is controlled by the second control signal; the third switch is coupled between the second pin and the second preset voltage, and is controlled by the third control signal; the fourth switch is coupled between the second pin and the third preset voltage, and is controlled by the fourth control signal, wherein the third preset voltage is obtained by offsetting the first preset voltage; the fifth switch is coupled between the third pin and the second preset voltage, and is controlled by the first control signal; the sixth switch is coupled between the third pin and the second low-dropout regulator, and is controlled by the second control signal; and the seventh switch is coupled between the fifth pin and the sixth pin, and is controlled by the first control signal.

[0027] Compared to the prior art, when the TDDI circuit proposed in the present invention is applied to an amorphous silicon (a-Si) panel, the voltage difference between the first driving voltage (VGH) and the second driving voltage (VGL) can reach a limit value of 32 volts, and can also be used to increase the amplitude space of the touch sensing signal; when it is applied to a low-temperature polycrystalline silicon (LTPS) panel, it can be used to increase the voltage amplitude of the touch sensing signal, thereby effectively solving many problems encountered by the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 Schematic diagram of a traditional TDDI circuit.

[0029] Figure 2 The timing diagram of the traditional TDDI circuit driving the amorphous silicon (a-Si) panel to operate in the display time and touch time.

[0030] Figure 3 The timing diagram of the traditional TDDI circuit driving the low-temperature polysilicon (LTPS) panel to operate in the display time and touch time.

[0031] Figure 4 FIG. 4 is a schematic diagram of a TDDI circuit according to a preferred embodiment of the present invention.

[0032] Figure 5 It is a schematic diagram of the TDDI circuit of the present invention driving the amorphous silicon (a-Si) panel to operate in displaying time.

[0033] Figure 6 It is a schematic diagram of the TDDI circuit of the present invention driving an amorphous silicon (a-Si) panel to operate at the first time t1 within the touch time.

[0034] Figure 7 It is a timing diagram of the TDDI circuit of the present invention driving the amorphous silicon (a-Si) panel to operate in the display time and the touch time.

[0035] Figure 8 It is a schematic diagram of the TDDI circuit of the present invention driving a low temperature polysilicon (LTPS) panel to operate in displaying time.

[0036] Fig. 9 It is a schematic diagram of the TDDI circuit of the present invention driving a low temperature polysilicon (LTPS) panel to operate at the first time t1 within the touch time.

[0037] Fig.10 It is a timing diagram of the TDDI circuit of the present invention driving the low temperature polysilicon (LTPS) panel to operate in the display time and the touch time.

[0038] Figures 11 to 13They are schematic diagrams of TDDI circuits in other preferred embodiments of the present invention.

[0039] Fig.14 for Fig.13 0045. A timing diagram of the first preset voltage VRCM and the third preset voltage VRCM_VGLSHIFT of the TDDI circuit in FIG.

[0040] Description of main component symbols:

[0041] IC…Touch and Display Driver Integrated (TDDI) Circuit

[0042] VGH_CAP_REF…1st pin

[0043] VGL_CAP_REF…2nd pin

[0044] PSUB_CAP_REF…Pin 3

[0045] GH…Pin 4

[0046] GL…5th pin

[0047] PSUB…Pin 6

[0048] VGH…First drive voltage

[0049] VGL…Second driving voltage

[0050] VPSUB…Baseboard voltage

[0051] SHIFT_VGH_LDO…First low dropout regulator

[0052] PSUB_LDO…Second low dropout regulator

[0053] SW1…First switch

[0054] SW2…Second switch

[0055] SW3…The third switch

[0056] SW4…Fourth switch

[0057] SW5…Fifth switch

[0058] SW6…Sixth switch

[0059] SW7…Seventh switch

[0060] CVGH…First external capacitor

[0061] CVGL…Second external capacitor

[0062] CPSUB…third external capacitor

[0063] VDPA…First lower limit voltage

[0064] VDNA…Second lower voltage limit

[0065] GND…ground voltage

[0066] PCB…Circuit Board

[0067] D1…Diode

[0068] D2…Diode

[0069] D3…Diode

[0070] CT1…First control signal

[0071] CT2…Second control signal

[0072] CT3…The third control signal

[0073] CT4…Fourth control signal

[0074] VSHFT_VGH…specific voltage

[0075] PSUBLDO_OUT…output signal

[0076] VRCM…First preset voltage

[0077] VSSA…Second preset voltage

[0078] DT…Display time

[0079] TT…Touch Time

[0080] t1…first time

[0081] t2…second time

[0082] t3…third time

[0083] t4…the fourth time

[0084] VREFP…First reference voltage

[0085] VREFN…Second reference voltage

[0086] CT11…First control signal

[0087] CT21…Second first control signal

[0088] SW1_ASi…1st switch

[0089] SW1_LTPS…Second first switch

[0090] SHIFT_VGL_LDO…Third low dropout regulator

[0091] VSHFT_VGL…specific voltage

[0092] VRCM_VGLSHIFT…Third preset voltage DETAILED DESCRIPTION

[0093] A preferred embodiment of the present invention is a touch and display driver integrated (TDDI) circuit. In this embodiment, the TDDI circuit is coupled to a panel to drive the panel to provide display and touch functions. There is no specific limitation on the type of panel, which may be a liquid crystal display panel or a light emitting diode display panel, but is not limited thereto.

[0094] Please refer to Figure 4 , Figure 4 This is a schematic diagram of the TDDI circuit in this embodiment. Figure 4 As shown, the TDDI circuit IC includes a first pin VGH_CAP_REF, a second pin VGL_CAP_REF, a third pin PSUB_CAP_REF, a fourth pin GH, a fifth pin GL, a sixth pin PSUB, a first low voltage dropout regulator SHIFT_VGH_LDO, a second low voltage dropout regulator PSUB_LDO, a first switch SW1, a second switch SW2, a third switch SW3, a fourth switch SW4, a fifth switch SW5, a sixth switch SW6, and a seventh switch SW7.

[0095] The fourth pin GH is coupled to the first pin VGH_CAP_REF through the first external capacitor CVGH to provide the first driving voltage VGH. The fourth pin GH is also coupled to the first lower limit voltage VDPA, and the first lower limit voltage VDPA can be a positive voltage. The fifth pin GL is coupled to the second pin VGL_CAP_REF through the second external capacitor CVGL to provide the second driving voltage VGL. The sixth pin PSUB is coupled to the third pin PSUB_CAP_REF through the third external capacitor CPSUB to provide the substrate voltage VPSUB. The sixth pin PSUB is also coupled to the second lower limit voltage VDNA and the ground voltage GND respectively.

[0096] The first low voltage dropout regulator SHIFT_VGH_LDO is used to provide a specific voltage VSHFT_VGH. The second low voltage dropout regulator PSUB_LDO is used to provide an output signal PSUBLDO_OUT. The first switch SW1 is coupled between the first pin VGH_CAP_REF and the first low voltage dropout regulator SHIFT_VGH_LDO, and the on or off of the first switch SW1 is controlled by the first control signal CT1. The second switch SW2 is coupled between the first pin VGH_CAP_REF and the first preset voltage VRCM, and the on or off of the second switch SW2 is controlled by the second control signal CT2. The third switch SW3 is coupled between the second pin VGL_CAP_REF and the second preset voltage VSSA, and the on or off of the third switch SW3 is controlled by the third control signal CT3. The fourth switch SW4 is coupled between the second pin VGL_CAP_REF and the first preset voltage VRCM, and the on or off of the fourth switch SW4 is controlled by the fourth control signal CT4. The fifth switch SW5 is coupled between the third pin PSUB_CAP_REF and the second preset voltage VSSA, and the on / off of the fifth switch SW5 is controlled by the first control signal CT1. The sixth switch SW6 is coupled between the third pin PSUB_CAP_REF and the second low dropout regulator PSUB_LDO, and the on / off of the sixth switch SW6 is controlled by the second control signal CT2. The seventh switch SW7 is coupled between the fifth pin GL and the sixth pin PSUB, and the on / off of the seventh switch SW7 is controlled by the first control signal CT1.

[0097] It should be noted that the first external capacitor CVGH, the second external capacitor CVGL, the third external capacitor CPSUB, the first lower limit voltage VDPA, the second lower limit voltage VDNA and the ground voltage GND are disposed on the circuit board PCB, but the present invention is not limited thereto.

[0098] In practical applications, the TDDI circuit IC can be coupled to an amorphous silicon (a-Si) panel and used to drive the amorphous silicon (a-Si) panel to operate in display mode and touch mode at different times.

[0099] Please also refer to Figures 5 to 7 , Figure 5 and Figure 6 They are schematic diagrams of the TDDI circuit IC driving the amorphous silicon (a-Si) panel to operate in display time and touch time; Figure 7 The timing diagram of the TDDI circuit IC driving the amorphous silicon (a-Si) panel to operate in the display time and touch time.

[0100] like Figure 5 and Figure 7As shown, in the display time (charge pump on) DT before the first time t1, the first control signal CT1 and the third control signal CT3 are at a high level and the second control signal CT2 and the fourth control signal CT4 are at a low level, so that the first switch SW1, the third switch SW3, the fifth switch SW5 and the seventh switch SW7 in the TDDI circuit IC are turned on and the second switch SW2, the fourth switch SW4 and the sixth switch SW6 are turned off. At this time, the first driving voltage VGH has an original voltage value (for example, 18V, but not limited thereto).

[0101] like Figure 6 and Figure 7 As shown, at the first time t1, the display time DT ends and the touch time (charging pump off) TT begins, the first control signal CT1 changes from a high level to a low level, the second control signal CT2 changes from a low level to a high level, the third control signal CT3 is still maintained at a high level and the fourth control signal CT4 is still maintained at a low level, so that the second switch SW2, the third switch SW3 and the sixth switch SW6 in the TDDI circuit IC are turned on and the first switch SW1, the fourth switch SW4, the fifth switch SW5 and the seventh switch SW7 are turned off, and the first driving voltage VGH at the first time t1 drops from the original voltage value (for example, 18 volts, but not limited thereto) to a specific voltage VSHFT_VGH (for example, 2 volts, but not limited thereto) and becomes an adjusted voltage value (for example, 16 volts, but not limited thereto).

[0102] Therefore, if Figure 7 As shown, the voltage difference (VGH-VPSUB) between the adjusted voltage value of the first driving voltage VGH (for example, 16 volts, but not limited thereto) and the substrate voltage VPSUB (for example, -14.4 volts, but not limited thereto) will be increased from the prior art ( Figure 2 ) is reduced from 32.4 volts to 30.4 volts.

[0103] At the second time t2, the TDDI circuit IC still operates within the touch time (charge pump off) TT, the first control signal CT1 is still maintained at a low level, the second control signal CT2 is still maintained at a high level, the third control signal CT3 changes from a high level to a low level, and the fourth control signal CT4 changes from a low level to a high level, so that the second switch SW2, the fourth switch SW4 and the sixth switch SW6 are turned on and the first switch SW1, the third switch SW3, the fifth switch SW5 and the seventh switch SW7 are turned off. At this time, the first driving voltage VGH, the second driving voltage VGL and the first preset voltage VRCM all drop by the same voltage (for example, 1 volt, but not limited thereto).

[0104] Between the second time t2 and the third time t3, the TDDI circuit IC still operates in the touch time (charge pump off) TT, and the first driving voltage VGH, the second driving voltage VGL and the first preset voltage VRCM all change in the same driving sine wave.

[0105] At the third time t3, the TDDI circuit IC still operates within the touch time (charge pump off) TT, the first control signal CT1 is still maintained at a low level, the second control signal CT2 is still maintained at a high level, the third control signal CT3 changes from a low level to a high level, and the fourth control signal CT4 changes from a high level to a low level, so that the second switch SW2, the third switch SW3 and the sixth switch SW6 in the TDDI circuit IC are turned on and the first switch SW1, the fourth switch SW4, the fifth switch SW5 and the seventh switch SW7 are turned off. At this time, the first driving voltage VGH, the second driving voltage VGL and the first preset voltage VRCM all rise to the same voltage (for example, 1 volt, but not limited thereto).

[0106] like Figure 5 and Figure 7 As shown, at the fourth time t4, the touch time (charge pump off) TT ends and the display time (charge pump on) DT begins, the first control signal CT1 changes from a low level to a high level, the second control signal CT2 changes from a high level to a low level, the third control signal CT3 is still maintained at a high level and the fourth control signal CT4 is still maintained at a low level, so that the first switch SW1, the third switch SW3, the fifth switch SW5 and the seventh switch SW7 in the TDDI circuit IC are turned on and the second switch SW2, the fourth switch SW4 and the sixth switch SW6 are turned off. At this time, the first driving voltage VGH rises to a specific voltage VSHFT_VGH (for example, 2 volts, but not limited thereto) to the original voltage value (for example, 18 volts, but not limited thereto).

[0107] It should be noted that during the touch time (charge pump off) TT from time t1 to time t4 , the lowest point of the waveform of the second driving voltage VGL (eg, -14V, but not limited thereto) is higher than the substrate voltage VPSUB (eg, -14.4V, but not limited thereto).

[0108] In practical applications, the TDDI circuit IC can also be coupled to a low temperature polysilicon (LTPS) panel and used to drive the low temperature polysilicon (LTPS) panel to operate in display and touch modes at different times.

[0109] Please also refer to Figures 8 to 10 , Figure 8 and Fig. 9 They are schematic diagrams of the TDDI circuit IC driving the low-temperature polysilicon (LTPS) panel to operate in display time and touch time; Fig.10The timing diagram of the TDDI circuit IC driving the low-temperature polysilicon (LTPS) panel to operate in the display time and touch time.

[0110] like Figure 8 and Fig.10 As shown, in the display time (charge pump is turned on) DT before the first time t1, the first control signal CT1 and the third control signal CT3 are at a high level and the second control signal CT2 and the fourth control signal CT4 are at a low level, so that the first switch SW1, the third switch SW3, the fifth switch SW5 and the seventh switch SW7 in the TDDI circuit IC are turned on and the second switch SW2, the fourth switch SW4 and the sixth switch SW6 are turned off. At this time, the first driving voltage VGH has an original voltage value (for example, 10V, but not limited thereto).

[0111] like Fig. 9 and Fig.10 As shown, at the first time t1, the display time (charge pump on) DT ends and the touch time (charge pump off) TT begins, the first control signal CT1 changes from a high level to a low level, the second control signal CT2 changes from a low level to a high level, the third control signal CT3 is still maintained at a high level and the fourth control signal CT4 is still maintained at a low level, so that the second switch SW2, the third switch SW3 and the sixth switch SW6 in the TDDI circuit IC are turned on and the first switch SW1, the fourth switch SW4, the fifth switch SW5 and the seventh switch SW7 are turned off. At this time, the first driving voltage VGH will rise from the original voltage value (for example, 10 volts, but not limited thereto) to a specific voltage VSHFT_VGH (for example, 2 volts, but not limited thereto) and become the adjusted voltage value (for example, 12 volts, but not limited thereto).

[0112] Therefore, if Fig.10 As shown, the voltage difference (VGH-VPSUB) between the adjusted voltage value of the first driving voltage VGH (for example, 12 volts, but not limited thereto) and the substrate voltage VPSUB (for example, -12.9 volts, but not limited thereto) will be increased from the prior art ( Figure 3 ) is increased from 22.9 volts to 24.9 volts.

[0113] At the second time t2, the TDDI circuit IC still operates within the touch time (charging pump is turned off) TT, the first control signal CT1 is still maintained at a low level, the second control signal CT2 is still maintained at a high level, the third control signal CT3 changes from a high level to a low level, and the fourth control signal CT4 changes from a low level to a high level, causing the second switch SW2, the fourth switch SW4 and the sixth switch SW6 in the TDDI circuit IC to be turned on and the first switch SW1, the third switch SW3, the fifth switch SW5 and the seventh switch SW7 to be turned off, and the first driving voltage VGH, the second driving voltage VGL and the first preset voltage VRCM all drop by the same voltage (for example, 1.5 volts, but not limited to this).

[0114] Between the second time t2 and the third time t3, the TDDI circuit IC still operates within the touch time (charging pump off) TT, and the first driving voltage VGH, the second driving voltage VGL and the first preset voltage VRCM all change in the same driving sine wave. The lowest point of the sine wave of the first driving voltage VGH (for example, 8.5 volts, but not limited thereto) is higher than the first lower limit voltage VDPA (for example, 6.5 volts, but not limited thereto) and the difference between the two is widened to a specific voltage VSHFT_VGH (for example, 2 volts, but not limited thereto), so that the amplitude of the first preset voltage VRCM can be increased from 2 volts to a maximum of 4 volts. Compared with the traditional method, the touch sensing signal is clamped by the diode D1 and its amplitude is limited.

[0115] At the third time t3, the TDDI circuit IC still operates within the touch time (charge pump off) TT, the first control signal CT1 is still maintained at a low level, the second control signal CT2 is still maintained at a high level, the third control signal CT3 changes from a low level to a high level, and the fourth control signal CT4 changes from a high level to a low level, so that the second switch SW2, the third switch SW3, and the sixth switch SW6 in the TDDI circuit IC are turned on, and the first switch SW1, the fourth switch SW4, the fifth switch SW5, and the seventh switch SW7 are turned off. At this time, the first driving voltage VGH, the second driving voltage VGL, and the first preset voltage VRCM all rise to the same voltage (for example, 1.5 volts, but not limited thereto).

[0116] like Figure 8 and Fig.10As shown, at the fourth time t4, the touch time (charge pump off) TT ends and the display time (charge pump on) DT begins, the first control signal CT1 changes from a low level to a high level, the second control signal CT2 changes from a high level to a low level, the third control signal CT3 is still maintained at a high level and the fourth control signal CT4 is still maintained at a low level, so that the first switch SW1, the third switch SW3, the fifth switch SW5 and the seventh switch SW7 are turned on and the second switch SW2, the fourth switch SW4 and the sixth switch SW6 are turned off. At this time, the first driving voltage VGH drops from the adjusted voltage value (for example, 12 volts, but not limited thereto) to a specific voltage VSHFT_VGH (for example, 2 volts, but not limited thereto) to the original voltage value (for example, 10 volts, but not limited thereto).

[0117] It should be noted that during the touch time (charge pump off) TT from time t1 to time t4 , the lowest point of the waveform of the second driving voltage VGL (eg, -12.5V, but not limited thereto) is higher than the substrate voltage VPSUB (eg, -12.9V, but not limited thereto).

[0118] Please refer to Figures 11 to 13 , Figures 11 to 13 They are schematic diagrams of TDDI circuits in other preferred embodiments of the present invention.

[0119] At Fig.11 In the illustrated embodiment, the TDDI circuit IC includes a first pin VGH_CAP_REF, a second pin VGL_CAP_REF, a third pin PSUB_CAP_REF, a fourth pin GH, a fifth pin GL, a sixth pin PSUB, a second low dropout regulator PSUB_LDO, a first first switch SW1_ASi, a second first switch SW1_LTPS, a second switch SW2, a third switch SW3, a fourth switch SW4, a fifth switch SW5, a sixth switch SW6 and a seventh switch SW7.

[0120] The fourth pin GH is coupled to the first pin VGH_CAP_REF through the first external capacitor CVGH. The fourth pin GH is used to provide a first driving voltage VGH. The fourth pin GH is also coupled to the first lower limit voltage VDPA, and the first lower limit voltage VDPA is a positive voltage. The fifth pin GL is coupled to the second pin VGL_CAP_REF through the second external capacitor CVGL. The fifth pin GL is used to provide a second driving voltage VGL. The sixth pin PSUB is coupled to the third pin PSUB_CAP_REF through the third external capacitor CPSUB. The sixth pin PSUB is used to provide a substrate voltage VPSUB. The sixth pin PSUB is also coupled to the second lower limit voltage VDNA and the ground voltage GND respectively. The second low dropout regulator PSUB_LDO is used to provide an output signal PSUBLDO_OUT.

[0121] The second switch SW2 is coupled between the first pin VGH_CAP_REF and the first preset voltage VRCM. The second switch SW2 is controlled by the second control signal CT2. The third switch SW3 is coupled between the second pin VGL_CAP_REF and the second preset voltage VSSA. The third switch SW3 is controlled by the third control signal CT3. The fourth switch SW4 is coupled between the second pin VGL_CAP_REF and the first preset voltage VRCM. The fourth switch SW4 is controlled by the fourth control signal CT4. The fifth switch SW5 is coupled between the third pin PSUB_CAP_REF and the second preset voltage VSSA. The fifth switch SW5 is controlled by the first control signal CT1. The sixth switch SW6 is coupled between the third pin PSUB_CAP_REF and the second low dropout regulator PSUB_LDO. The sixth switch SW6 is controlled by the second control signal CT2. The seventh switch SW7 is coupled between the fifth pin GL and the sixth pin PSUB. The seventh switch SW7 is controlled by the first control signal CT1.

[0122] It should be noted that Fig.11 Examples and Figure 4The embodiment of the present invention is different in that: the first first switch SW1_ASi is coupled between the first pin VGH_CAP_REF and the first lower limit voltage VDPA. The second first switch SW1_LTPS is coupled between the first pin VGH_CAP_REF and the second lower limit voltage VDNA. When the TDDI circuit IC is coupled to an amorphous silicon (a-Si) panel, the first first switch SW1_ASi is controlled by the first first control signal CT11 and turned on. When the TDDI circuit IC is coupled to a low-temperature polycrystalline silicon (LTPS) panel, the second first switch SW1_LTPS is controlled by the second first control signal CT21 and turned on. In other words, the TDDI circuit IC selectively turns on the first first switch SW1_ASi or the second first switch SW1_LTPS according to whether the panel it drives is an amorphous silicon (a-Si) panel or a low-temperature polycrystalline silicon (LTPS) panel.

[0123] At Fig.12 In the illustrated embodiment, the TDDI circuit IC includes a first pin VGH_CAP_REF, a second pin VGL_CAP_REF, a third pin PSUB_CAP_REF, a fourth pin GH, a fifth pin GL, a sixth pin PSUB, a second low dropout regulator PSUB_LDO, a third low dropout regulator SHIFT_VGL_LDO, a first switch SW1, a second switch SW2, a third switch SW3, a fourth switch SW4, a fifth switch SW5, a sixth switch SW6 and a seventh switch SW7.

[0124] The fourth pin GH is coupled to the first pin VGH_CAP_REF through the first external capacitor CVGH. The fourth pin GH is used to provide a first driving voltage VGH. The fourth pin GH is also coupled to the first lower limit voltage VDPA, and the first lower limit voltage VDPA can be a positive voltage. The fifth pin GL is coupled to the second pin VGL_CAP_REF through the second external capacitor CVGL. The fifth pin GL is used to provide a second driving voltage VGL. The sixth pin PSUB is coupled to the third pin PSUB_CAP_REF through the third external capacitor CPSUB. The sixth pin PSUB is used to provide a substrate voltage VPSUB. The sixth pin PSUB is also coupled to the second lower limit voltage VDNA and the ground voltage GND respectively. The second low dropout regulator PSUB_LDO is used to provide an output signal PSUBLDO_OUT. The third low dropout regulator SHIFT_VGL_LDO is used to provide a specific voltage VSHFT_VGL.

[0125] The first switch SW1 is coupled between the first pin VGH_CAP_REF and the second preset voltage VSSA. The first switch SW1 is controlled by the first control signal CT1. The second switch SW2 is coupled between the first pin VGH_CAP_REF and the first preset voltage VRCM. The second switch SW2 is controlled by the second control signal CT2. The third switch SW3 is coupled between the second pin VGL_CAP_REF and the third low dropout regulator SHIFT_VGL_LDO. The third switch SW3 is controlled by the third control signal CT3. The fourth switch SW4 is coupled between the second pin VGL_CAP_REF and the first preset voltage VRCM. The fourth switch SW4 is controlled by the fourth control signal CT4. The fifth switch SW5 is coupled between the third pin PSUB_CAP_REF and the third low dropout regulator SHIFT_VGL_LDO. The fifth switch SW5 is controlled by the first control signal CT1. The sixth switch SW6 is coupled between the third pin PSUB_CAP_REF and the second low dropout regulator PSUB_LDO. The sixth switch SW6 is controlled by the second control signal CT2. The seventh switch SW7 is coupled between the fifth pin GL and the sixth pin PSUB. The seventh switch SW7 is controlled by the first control signal CT1.

[0126] It should be noted that Fig.12 Examples and Figure 4 The difference of the embodiment is that: Fig.12 The third low voltage dropout regulator SHIFT_VGL_LDO in the embodiment is coupled to one end of the third switch SW3 and the fifth switch SW5, and one end of the first switch SW1 is coupled to the second preset voltage VSSA. Figure 4 The first low dropout regulator SHIFT_VGH_LDO is coupled to one end of the first switch SW1 , and one end of the third switch SW3 and the fifth switch SW5 are coupled to the second preset voltage VSSA.

[0127] At Fig.13 In the illustrated embodiment, the TDDI circuit IC includes a first pin VGH_CAP_REF, a second pin VGL_CAP_REF, a third pin PSUB_CAP_REF, a fourth pin GH, a fifth pin GL, a sixth pin PSUB, a second low dropout regulator PSUB_LDO, a first switch SW1, a second switch SW2, a third switch SW3, a fourth switch SW4, a fifth switch SW5, a sixth switch SW6 and a seventh switch SW7.

[0128] The fourth pin GH is coupled to the first pin VGH_CAP_REF through the first external capacitor CVGH. The fourth pin GH is used to provide a first driving voltage VGH. The fourth pin GH is also coupled to the first lower limit voltage VDPA, and the first lower limit voltage VDPA can be a positive voltage. The fifth pin GL is coupled to the second pin VGL_CAP_REF through the second external capacitor CVGL. The fifth pin GL is used to provide a second driving voltage VGL. The sixth pin PSUB is coupled to the third pin PSUB_CAP_REF through the third external capacitor CPSUB. The sixth pin PSUB is used to provide a substrate voltage VPSUB. The sixth pin PSUB is also coupled to the second lower limit voltage VDNA, and the second lower limit voltage VDNA can be a negative voltage. The second low dropout regulator PSUB_LDO is used to provide an output signal PSUBLDO_OUT. The first switch SW1 is coupled between the first pin VGH_CAP_REF and the second preset voltage VSSA. The first switch SW1 is controlled by the first control signal CT1. The second switch SW2 is coupled between the first pin VGH_CAP_REF and the first preset voltage VRCM. The second switch SW2 is controlled by the second control signal CT2. The third switch SW3 is coupled between the second pin VGL_CAP_REF and the second preset voltage VSSA. The third switch SW3 is controlled by the third control signal CT3. The fourth switch SW4 is coupled between the second pin VGL_CAP_REF and the third preset voltage VRCM_VGLSHIFT. The fourth switch SW4 is controlled by the fourth control signal CT4. The third preset voltage VRCM_VGLSHIFT is obtained by offsetting the first preset voltage VRCM. The fifth switch SW5 is coupled between the third pin PSUB_CAP_REF and the second preset voltage VSSA. The fifth switch SW5 is controlled by the first control signal CT1. The sixth switch SW6 is coupled between the third pin PSUB_CAP_REF and the second low dropout regulator PSUB_LDO. The sixth switch SW6 is controlled by the second control signal CT2. The seventh switch SW7 is coupled between the fifth pin GL and the sixth pin PSUB and is controlled by the first control signal CT1.

[0129] It should be noted that Fig.13 Examples and Figure 4 The difference of the embodiment is that: Fig.13 One end of the first switch SW1, the third switch SW3 and the fifth switch SW5 are all coupled to the second preset voltage VSSA, and one end of the second switch SW2 and the fourth switch SW4 are respectively coupled to the first preset voltage VRCM and the third preset voltage VRCM_VGLSHIFT, wherein the third preset voltage VRCM_VGLSHIFT is obtained by offsetting the first preset voltage VRCM. For example, Fig.14As shown, the third preset voltage VRCM_VGLSHIFT is obtained by shifting the first preset voltage VRCM upward by 4 volts, but the present invention is not limited thereto. This also shifts the second driving voltage VGL upward by 4 volts.

[0130] Compared to the prior art, when the TDDI circuit proposed in the present invention is applied to an amorphous silicon (a-Si) panel, the voltage difference between the first driving voltage (VGH) and the second driving voltage (VGL) can reach a limit value of 32 volts, and can also be used to increase the amplitude space of the touch sensing signal; when it is applied to a low-temperature polycrystalline silicon (LTPS) panel, it can be used to increase the voltage amplitude of the touch sensing signal, thereby effectively solving many problems encountered by the prior art.

Claims

1. A touch control and display driver integrated circuit for driving a panel, characterized in that: include: First pin; The second pin; The third pin; A fourth pin, coupled to the first pin via a first external capacitor, for providing a first driving voltage, and the fourth pin is also coupled to a first lower limit voltage; A fifth pin, coupled to the second pin via a second external capacitor, for providing a second driving voltage; A sixth pin, coupled to the third pin through a third external capacitor, for providing a substrate voltage, and the sixth pin is also coupled to a second lower limit voltage and a ground voltage respectively; A first low voltage dropout regulator, for providing a specific voltage; A second low dropout voltage regulator, for providing an output signal; A first switch is coupled between the first pin and the first low dropout regulator and is controlled by a first control signal; A second switch is coupled between the first pin and the first preset voltage and is controlled by a second control signal; A third switch is coupled between the second pin and a second preset voltage and is controlled by a third control signal; a fourth switch, coupled between the second pin and the first preset voltage, and controlled by a fourth control signal; a fifth switch, coupled between the third pin and the second preset voltage, and controlled by the first control signal; a sixth switch, coupled between the third pin and the second low dropout regulator, and controlled by the second control signal; as well as The seventh switch is coupled between the fifth pin and the sixth pin and is controlled by the first control signal.

2. The touch control and display driver integrated circuit according to claim 1, wherein: The panel is an amorphous silicon panel. During the display time, the first control signal and the third control signal are at a high level and the second control signal and the fourth control signal are at a low level, so that the first switch, the third switch, the fifth switch and the seventh switch are turned on and the second switch, the fourth switch and the sixth switch are turned off, and the first driving voltage has an original voltage value.

3. The touch control and display driver integrated circuit as claimed in claim 2, wherein: At the first time, the display time ends and enters the touch time, the first control signal changes from a high level to a low level, the second control signal changes from a low level to a high level, the third control signal is still maintained at a high level and the fourth control signal is still maintained at a low level, so that the second switch, the third switch and the sixth switch are turned on and the first switch, the fourth switch, the fifth switch and the seventh switch are turned off, and the first driving voltage drops from the original voltage value by the specific voltage to reduce the maximum voltage difference between the maximum value of the first driving voltage and the substrate voltage.

4. The touch control and display driver integrated circuit as claimed in claim 3, wherein: At the second time, the first control signal is still maintained at a low level, the second control signal is still maintained at a high level, the third control signal changes from a high level to a low level, and the fourth control signal changes from a low level to a high level, so that the second switch, the fourth switch and the sixth switch are turned on and the first switch, the third switch, the fifth switch, and the seventh switch are turned off, and the first driving voltage, the second driving voltage and the first preset voltage all drop by the same voltage.

5. The touch control and display driver integrated circuit as claimed in claim 4, wherein: Between the second time and the third time, the first driving voltage, the second driving voltage and the first preset voltage all change in the same driving sine wave.

6. The touch control and display driver integrated circuit as claimed in claim 5, wherein: At the third time, the first control signal is still maintained at a low level, the second control signal is still maintained at a high level, the third control signal changes from a low level to a high level, and the fourth control signal changes from a high level to a low level, so that the second switch, the third switch and the sixth switch are turned on and the first switch, the fourth switch, the fifth switch and the seventh switch are turned off, and the first driving voltage, the second driving voltage and the first preset voltage all rise by the same voltage.

7. The touch control and display driver integrated circuit as claimed in claim 6, wherein: At the fourth time, the touch time ends and enters the display time, the first control signal changes from a low level to a high level, the second control signal changes from a high level to a low level, the third control signal is still maintained at a high level and the fourth control signal is still maintained at a low level, so that the first switch, the third switch, the fifth switch and the seventh switch are turned on and the second switch, the fourth switch and the sixth switch are turned off, and the first driving voltage rises by the first voltage to the original voltage value.

8. The touch control and display driver integrated circuit as claimed in claim 3, wherein: During the touch time, the lowest point of the waveform of the second driving voltage is higher than the substrate voltage.

9. The touch control and display driver integrated circuit as claimed in claim 1, wherein: The first external capacitor, the second external capacitor, the third external capacitor, the first lower limit voltage, the second lower limit voltage and the ground voltage are arranged on a circuit board.

10. The touch control and display driver integrated circuit as claimed in claim 1, wherein: The panel is a low-temperature polysilicon panel. During the display time, the first control signal and the third control signal are at a high level and the second control signal and the fourth control signal are at a low level, so that the first switch, the third switch, the fifth switch and the seventh switch are turned on and the second switch, the fourth switch and the sixth switch are turned off, and the first driving voltage has an original voltage value.

11. The touch control and display driver integrated circuit as claimed in claim 10, wherein: At the first time, the display time ends and enters the touch time, the first control signal changes from a high level to a low level, the second control signal changes from a low level to a high level, the third control signal is still maintained at a high level and the fourth control signal is still maintained at a low level, so that the second switch, the third switch and the sixth switch are turned on and the first switch, the fourth switch, the fifth switch and the seventh switch are turned off, and the first driving voltage rises from the original voltage value to the specific voltage to increase the maximum voltage difference between the maximum value of the first driving voltage and the substrate voltage.

12. The touch control and display driver integrated circuit according to claim 11, wherein: At the second time, the first control signal is still maintained at a low level, the second control signal is still maintained at a high level, the third control signal changes from a high level to a low level, and the fourth control signal changes from a low level to a high level, so that the second switch, the fourth switch and the sixth switch are turned on and the first switch, the third switch, the fifth switch and the seventh switch are turned off, and the first driving voltage, the second driving voltage and the first preset voltage all drop by the same voltage.

13. The touch control and display driver integrated circuit as claimed in claim 12, wherein: Between the second time and the third time, the first driving voltage, the second driving voltage and the first preset voltage all change in the same driving sine wave, the lowest point of the sine wave of the first driving voltage is higher than the first lower limit voltage and the difference between the two is pulled to the specific voltage.

14. The touch control and display driver integrated circuit as claimed in claim 13, wherein: At the third time, the first control signal is still maintained at a low level, the second control signal is still maintained at a high level, the third control signal changes from a low level to a high level, and the fourth control signal changes from a high level to a low level, so that the second switch, the third switch, and the sixth switch are turned on and the first switch, the fourth switch, the fifth switch, and the seventh switch are turned off, and the first driving voltage, the second driving voltage, and the first preset voltage all rise by the same voltage.

15. The touch control and display driver integrated circuit as claimed in claim 14, wherein: At the fourth time, the touch time ends and enters the display time, the first control signal changes from a low level to a high level, the second control signal changes from a high level to a low level, the third control signal is still maintained at a high level and the fourth control signal is still maintained at a low level, so that the first switch, the third switch, the fifth switch and the seventh switch are turned on and the second switch, the fourth switch and the sixth switch are turned off, and the first driving voltage drops by a first voltage to the original voltage value.

16. The touch control and display driver integrated circuit as claimed in claim 11, wherein: During the touch time, the lowest point of the waveform of the second driving voltage is higher than the substrate voltage.

17. A touch control and display driver integrated circuit for driving a panel, characterized in that: include: First pin; The second pin; The third pin; A fourth pin is coupled to the first pin through a first external capacitor to provide a first driving voltage, and a first lower limit voltage is also coupled between the fourth pin and the first external capacitor; A fifth pin, coupled to the second pin via a second external capacitor, for providing a second driving voltage; A sixth pin is coupled to the third pin through a third external capacitor to provide a substrate voltage, and a second lower limit voltage is coupled between the sixth pin and the third external capacitor respectively; A second low dropout voltage regulator, for providing an output signal; A first first switch is coupled between the first pin and the first lower limit voltage, and when the panel is an amorphous silicon panel, the first first switch is controlled by a first first control signal to be turned on; A second first switch is coupled between the first pin and the second lower limit voltage, and when the panel is a low temperature polysilicon panel, the second first switch is controlled by a second first control signal to be turned on; A second switch is coupled between the first pin and the first preset voltage and is controlled by a second control signal; A third switch is coupled between the second pin and a second preset voltage and is controlled by a third control signal; a fourth switch, coupled between the second pin and the first preset voltage, and controlled by a fourth control signal; a fifth switch, coupled between the third pin and the second preset voltage, and controlled by the first control signal; a sixth switch, coupled between the third pin and the second low dropout regulator, and controlled by the second control signal; as well as The seventh switch is coupled between the fifth pin and the sixth pin and is controlled by the first control signal.

18. A touch control and display driver integrated circuit for driving a panel, characterized in that: include: First pin; The second pin; The third pin; A fourth pin, coupled to the first pin via a first external capacitor, for providing a first driving voltage, and the fourth pin is also coupled to a first lower limit voltage; A fifth pin, coupled to the second pin via a second external capacitor, for providing a second driving voltage; A sixth pin, coupled to the third pin through a third external capacitor, for providing a substrate voltage, and the sixth pin is also coupled to a second lower limit voltage and a ground voltage respectively; A second low dropout voltage regulator, for providing an output signal; A third low dropout voltage regulator, for providing a specific voltage; A first switch is coupled between the first pin and a second preset voltage and is controlled by a first control signal; A second switch is coupled between the first pin and the first preset voltage and is controlled by a second control signal; A third switch is coupled between the second pin and the third low dropout regulator and is controlled by a third control signal; a fourth switch, coupled between the second pin and the first preset voltage, and controlled by a fourth control signal; a fifth switch, coupled between the third pin and the third low dropout regulator, and controlled by the first control signal; a sixth switch, coupled between the third pin and the second low dropout regulator, and controlled by the second control signal; as well as The seventh switch is coupled between the fifth pin and the sixth pin and is controlled by the first control signal.

19. A touch control and display driver integrated circuit for driving a panel, characterized in that: include: First pin; The second pin; The third pin; A fourth pin, coupled to the first pin via a first external capacitor, for providing a first driving voltage, and the fourth pin is also coupled to a first lower limit voltage; A fifth pin, coupled to the second pin via a second external capacitor, for providing a second driving voltage; A sixth pin is coupled to the third pin through a third external capacitor to provide a substrate voltage, and a second lower limit voltage is coupled between the sixth pin and the third external capacitor respectively; A second low dropout voltage regulator, for providing an output signal; A first switch is coupled between the first pin and a second preset voltage and is controlled by a first control signal; A second switch is coupled between the first pin and the first preset voltage and is controlled by a second control signal; A third switch is coupled between the second pin and the second preset voltage and is controlled by a third control signal; a fourth switch, coupled between the second pin and a third preset voltage, and controlled by a fourth control signal, wherein the third preset voltage is obtained by offsetting the first preset voltage; a fifth switch, coupled between the third pin and the second preset voltage, and controlled by the first control signal; a sixth switch, coupled between the third pin and the second low dropout regulator, and controlled by the second control signal; as well as The seventh switch is coupled between the fifth pin and the sixth pin and is controlled by the first control signal.

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