High-performance data processing system and method

Abstract

The invention discloses a high-performance data processing system and method, and relates to the technical field of data processing, and the system comprises the steps that an AD9625 analog-to-digital conversion module receives an input analog signal, converts the input analog signal into a digital signal, and sends the digital signal to a ZYNQ7Z100 data processing module; the ZYNQ7Z100 data processing control module is used for processing the digital signal and sending the processed digital signal to an AD9739 digital-to-analog conversion module; the AD9739 digital-to-analog conversion module is used for converting the processed digital signal into an analog signal and outputting the analog signal to the outside through the radio frequency joint connector; the LMK04828 clock module is used for providing high-precision and low-jitter clock signals for the whole system; and the power management module is used for providing a power supply for the system for power supply.

Description

Technical Field

[0001] The present invention relates to the technical field of data processing, and in particular to a high-performance data processing system and method. Background Art

[0002] With the rapid development of science and technology, the requirements for data processing speed, accuracy and stability are getting higher and higher. In the fields of communications, radar and electronic countermeasures, a large amount of high-speed and high-precision data needs to be processed. Traditional data processing systems have certain limitations in processing speed, accuracy and reliability, and it is difficult to meet the needs of modern applications. Summary of the invention

[0003] In order to solve the deficiencies mentioned in the above background technology, the purpose of the present invention is to provide a high-performance data processing system and method to solve the problems faced by the existing data processing in terms of speed, accuracy and stability.

[0004] In a first aspect, the purpose of the present invention can be achieved by the following technical solution: a high-performance data processing system, comprising:

[0005] AD9625 analog-to-digital conversion module: used to receive the input analog signal, convert the input analog signal into a digital signal, and send the digital signal to the ZYNQ7Z100 data processing module;

[0006] ZYNQ7Z100 data processing control module: used to process digital signals and send the processed digital signals to the AD9739 digital-to-analog conversion module;

[0007] AD9739 digital-to-analog conversion module: used to convert the processed digital signal into an analog signal and output the analog signal through the RF connector;

[0008] LMK04828 clock module: used to provide high-precision, low-jitter clock signals for the entire system;

[0009] Power management module: It is used to provide power supply to the system.

[0010] In combination with the first aspect, in certain implementations of the first aspect, the system further includes: the AD9625 analog-to-digital conversion module and the ZYNQ7Z100 data processing control module are connected using a high-speed serial bus JESD204B interface.

[0011] In combination with the first aspect, in certain implementations of the first aspect, the system further includes: the AD9739 digital-to-analog conversion module and the ZYNQ7Z100 data processing control module are interconnected using an LVDS interface.

[0012] In combination with the first aspect, in certain implementations of the first aspect, the system further includes: the maximum sampling rate of the high-speed serial bus JESD204B interface and the LVDS interface supports 2.5GSPS.

[0013] In combination with the first aspect, in some implementations of the first aspect, the system further includes: the process in which the AD9625 analog-to-digital conversion module converts the input analog signal into a digital signal includes: in the initial stage, the ZYNQ7Z100 PS terminal converts the relevant parameters set by the host computer into the register values ​​of the AD9625 and configures the relevant register parameters into the AD9625 using the SPI protocol data; in the data sampling stage, the AD9625 converts the input analog signal into a digital signal, and the sampled signal enters the first-stage analog-to-digital conversion module and is compared with a reference threshold, and a residual signal is formed through a multiplication DAC, and the calculation formula of the residual signal is:

[0014] v i+1 =2*(v i +(b i -0.5)v ref / 2)

[0015] where v i is the current stage input signal, b i is the comparison result of the current level, v ref is the reference voltage;

[0016] After completing the first-level conversion, the residual signal of the first level is passed to the next level as the input of the next level, and the process of comparing and generating residual signals is repeated. Each level performs the same operation and the conversion accuracy of each level is improved. After conversion and correction at all levels, the final digital output is obtained, and the data output is completed using the high-speed serdes interface JESD204B interface.

[0017] In combination with the first aspect, in some implementations of the first aspect, the system also includes: the process of the ZYNQ7Z100 data processing control module processing the digital signal: the process of the ZYNQ7Z100 data processing control module processing the digital signal includes host computer instruction parsing, register value sending, IQ processing of quantized data, FFT processing, ABS operation and rotation point budget, data waveform generation and DMA processing, wherein the instruction parsing includes the reception and transmission and parsing of host computer data: the ZYNQ7Z100 PS end receives the Ethernet message sent by the host computer to complete the parsing, and then configures the parsed parameters in the form of registers to the PL end and related interface chips, and the register values ​​are mainly sent to AD9625, AD9729 and LMK04828 chips, etc. The related chips are interconnected with ZYNQ7Z100 using the SPI protocol. After the ZYNQ7Z100 PS end parses the host computer data into register configuration data, the data is sent to the corresponding hardware chip in the form of serial data through the SPI interface.

[0018] In combination with the first aspect, in some implementations of the first aspect, the system further includes: the process of the AD9739 digital-to-analog conversion module converting the processed digital signal into an analog signal is divided into a process of configuring registers, inputting data, data conversion, and outputting analog signals, wherein in the process of configuring registers, the ZYNQ7Z100 PS end converts the data sent by the host computer into configuration register parameters and configures the relevant parameters to the internal registers of the AD9739 through the SPI interface, including setting its working mode, output current, and clock mode, and the data input process is ZYNQ7Z100 The PL end generates a modulation wave according to the modulation parameters sent by the PS end. If it is voice data modulation, the modulation waveform sent by the PS end is read from the DDR through the FIFO. Then, in the dual-port LVDSDDR format, the input data is input simultaneously through two ports. The DDR mode is adopted, and data sampling is performed using both the rising and falling edges of the clock. During the data conversion process, the digital-to-analog conversion circuit inside the AD9739 converts the input digital signal into a differential current signal output. When outputting an analog signal, the analog signal after digital-to-analog conversion is output from the output port in the form of a differential current, converted into a differential voltage output through an external resistor, and then converted into a single-ended RF signal through a balun for output.

[0019] In a second aspect, in order to achieve the above-mentioned object, the present invention discloses a high-performance data processing method, the method comprising the following steps:

[0020] Acquire an input analog signal, perform analog-to-digital conversion on the input analog signal, and obtain a digital signal;

[0021] The digital signal is processed to obtain a processed digital signal, and the processed digital signal is converted from digital to analog to obtain an analog signal, wherein a high-precision, low-jitter clock signal is added during the conversion process.

[0022] In another aspect of the present invention, in order to achieve the above-mentioned purpose, a terminal device is disclosed, including a memory, a processor, and a computer program stored in the memory and capable of running on the processor, characterized in that the memory stores a computer program capable of running on the processor, and when the processor loads and executes the computer program, a high-performance data processing system as described above is adopted.

[0023] In another aspect of the present invention, in order to achieve the above-mentioned purpose, a computer-readable storage medium is disclosed, in which a computer program is stored. When the computer program is loaded and executed by a processor, a high-performance data processing system as described above is adopted.

[0024] Beneficial effects of the present invention:

[0025] The present invention adopts the JESD204B interface for design, and through serial transmission, the pin connection between chips is greatly reduced, the complexity of the whole system and the difficulty of PCB wiring are reduced; the high-speed ADC and DAC are adopted for design, the speed and accuracy of data processing are improved, and more complex application requirements can be met; the low-noise and low-jitter LMK04828 clock generator is adopted, the jitter and noise of the system are greatly reduced, and the stability and reliability of the system are improved; the structure and configuration of the system are optimized, and the cost and power consumption are reduced; through the ingenious combination and optimized configuration of AD9625, AD9739 and LMK04828, the data processing capability of high speed, high accuracy and high stability is realized, and the present invention can be widely used in communication, audio processing, industrial control and other related fields. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0027] Figure 1 It is a schematic diagram of the system structure of the present invention;

[0028] Figure 2 It is a schematic diagram of the system module layout of the present invention;

[0029] Figure 3 It is a principle block diagram of the system module of the present invention;

[0030] Figure 4 It is a tree diagram of the power management module of the present invention;

[0031] Figure 5 It is a functional block diagram of the system of the present invention;

[0032] Figure 6 It is a schematic flow chart of the method of the present invention. DETAILED DESCRIPTION

[0033] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0034] Embodiment 1:

[0035] The following is an introduction to the relevant terms involved in the embodiments of the present application:

[0036] Analog-to-digital and digital-to-analog conversion is the process of converting continuous analog quantity into discrete digital quantity, which is called analog-to-digital conversion. The reverse is called digital-to-analog conversion. They are important links in analog and digital control systems. Since the signal values ​​obtained by various sensors and the input of electromechanical devices are analog voltage or current values, and these analog values ​​cannot be used with digital signals, they must go through analog-to-digital and digital-to-analog conversion. This mutual conversion is widely used in remote control and telemetry, digital instruments, computing components, analog-to-digital hybrid computer systems and digital mapping.

[0037] like Figure 1 As shown, a high-performance data processing system comprises:

[0038] AD9625 analog-to-digital conversion module: used to receive the input analog signal, convert the input analog signal into a digital signal, and send the digital signal to the ZYNQ7Z100 data processing module;

[0039] The AD9625 analog-to-digital conversion module and the ZYNQ7Z100 data processing control module are connected using a high-speed serial bus JESD204B interface;

[0040] The process of the AD9625 analog-to-digital conversion module converting the input analog signal into a digital signal: The process of the AD9625 analog-to-digital conversion module converting the input analog signal into a digital signal includes its register configuration, sampling, and conversion processes. In the initial stage, the ZYNQ7Z100 PS end converts the relevant parameters set by the host computer into the register values ​​of the AD9625 and configures the relevant register parameters into the AD9625 with SPI protocol data to ensure that the AD9625 operates according to the relevant parameters set by the host computer. In the data sampling stage, the AD9625 converts the input analog signal into a digital signal. The AD9625 is a pipeline ADC, so multiple cascades are used to complete the conversion of analog data to digital signals. After the sampled signal enters the first-stage analog-to-digital conversion module, it is compared with a reference threshold and forms a residual signal through a multiplication DAC (MDAC). The calculation formula for the residual signal is v i+1 =2*(v i +(b i -0.5)v ref / 2), where v i is the current stage input signal, b i is the comparison result of the current level (0 or 1), v ref is the reference voltage. After completing the first-level conversion, the residual signal of the first level is passed to the next level as the input of the next level, and the above-mentioned comparison and residual signal generation process is repeated. Each level performs similar operations and the conversion accuracy of each level is gradually improved. During the entire conversion process, ADCs at different levels are processing different sampling data, which greatly improves the conversion speed. Due to the time difference between the ADCs at each level during the conversion process, the digital outputs of each level need to be realigned through a shift register with a variable length. At the same time, due to the error transmission and accumulation in the pipeline structure, digital correction is also required to improve the accuracy of the conversion. After conversion and correction at all levels, the final digital output is obtained, and the data output is completed with a high-speed serdes interface (JESD204B interface).

[0041] The AD9625 analog-to-digital conversion module can realize spectrum analysis and data analysis of signals. The spectrum analysis function includes frequency scanning and fixed frequency monitoring. The frequency scanning function can realize signal search within a wide frequency band. The host computer can realize spectrum monitoring of fixed signals and capture and analysis of frequency hopping signals based on the above-mentioned fixed channel frequency monitoring. In the frequency sweep mode, the start frequency, end frequency and frequency step value of the signal can be set by the host computer, and the set related parameters can be sent to the PS end of ZYNQ7Z100 in the form of an instruction packet. The PS end receives and parses the instruction packet information sent by the host computer, converts the start frequency and end frequency of the scan into the local oscillator frequency value of the frequency conversion module, and calculates the local oscillator register value corresponding to the frequency value, and sends the calculated register value to the PL end. In addition, according to the frequency step value set by the host computer, the frequency step of the local oscillator and the operation length of the FFT inside the PL are coupled. When the PS end of ZYNQ7Z100 completes the sending of all parameters and gives the scanning instruction, it waits for the terminal signal of the FPGA end and prepares to read the frequency sweep data. After the frequency sweep signal is digitally quantized by AD9625, the data is converted into I / Q channels for analysis, and FFT calculation is performed, and then ABS operation and rotation point calculation are performed to obtain effective amplitude-frequency data. The acquired amplitude-frequency data is saved to the DDR inside the high-performance data processing system and the terminal signal value PS is given to notify the PS end to obtain the data. During the working process, in order to improve the scanning efficiency, the FFT calculation configures the next frequency of the local oscillator when the IQ data is saved and ready for FFT, so that the next frame of data can be calculated after one frame of FFT calculation. In the design, the sampling clock of the ADC is set to 2457.6MHz. After the DDC function and fixed 8-decimation function inside the AD9625, the data sampling rate of the output signal is 307.2Msps, the maximum output signal bandwidth can reach 300MHz, and the actual effective support bandwidth is 240MHz. In the fixed frequency monitoring mode, the host computer software sets the center frequency, monitoring bandwidth, demodulation bandwidth and other parameters of the monitoring spectrum. The host computer sends the set related parameters to the PS end in the form of an instruction packet. The PS end receives the instruction packet information sent by the host computer and parses it. After the analysis is completed, the register value of the local oscillator is calculated according to the corresponding frequency value, and then sent to the PL end of ZYNQ7Z100. The PL end sends the configuration of the local oscillator to its internal register in the form of a register. In addition, according to the intermediate frequency monitoring bandwidth set by the host computer, the operation length of the internal FFT of the FPGA is completed, and the sampling rate value of the data channel is sent to the PL end according to the set demodulation bandwidth, and waits for the IQ data returned by the PL end. When the PS end sends all parameters and gives a scan instruction, it waits for the interrupt signal of the FPGA end and prepares to read the intermediate frequency spectrum data and baseband IQ data, and perform FFT analysis.In the data generation stage, the PS end of ZYNQ7Z100 converts the waveform to be generated into data and stores it in the DDR of the PL end, and reads the data to the FIFO through the DDR driver segment, and then performs integer multiple interpolation processing on the read data and performs interpolation channel matching according to different rates. After the rate matching is completed, the IQ data is subjected to IQ modulation processing, and up to 8 modulated signals can be generated concurrently.

[0042] ZYNQ7Z100 data processing control module: used to process digital signals and send the processed digital signals to the AD9739 digital-to-analog conversion module;

[0043] The process of ZYNQ7Z100 data processing control module processing digital signals:

[0044] The process of digital signal processing by the ZYNQ7Z100 data processing control module includes host computer instruction parsing, register value sending, IQ processing of quantized data, FFT processing, ABS operation and rotation point budget, data waveform generation and DMA processing. The instruction parsing includes the reception and sending of host computer data: the ZYNQ7Z100 PS receives the Ethernet message sent by the host computer to complete the parsing, and then configures the parsed parameters in the form of registers to the PL end and related interface chips to realize the parsing and sending of data. The register value sending is mainly AD9625, AD9729 and LMK04828 chips, etc. The related chips are interconnected with ZYNQ7Z100 using the SPI protocol. After the ZYNQ7Z100 PS parses the host computer data into register configuration data, it sends the data to the corresponding hardware chip in serial data through the SPI interface.

[0045] The AD9739 digital-to-analog conversion module and the ZYNQ7Z100 data processing control module are interconnected using an LVDS interface;

[0046] The process of the AD9739 digital-to-analog conversion module converting the processed digital signal into an analog signal:

[0047] The process of the AD9739 digital-to-analog conversion module converting the processed digital signal into an analog signal: The process of the AD9739 digital-to-analog conversion module converting the processed digital signal into an analog signal is divided into the process of configuring registers, inputting data, data conversion, and outputting analog signals. In the process of configuring registers, the ZYNQ7Z100 PS end converts the data sent by the host computer into configuration register parameters and configures the relevant parameters to the internal registers of the AD9739 through the SPI interface, including setting its working mode, output current, clock mode and other parameters. The data input process is that the ZYNQ7Z100 PL end generates a modulation wave according to the modulation parameters sent by the PS end. If it is voice data modulation, the modulation waveform sent by the PS end is read from the DDR through the FIFO. Then, in the dual-port LVDSDDR format, the input data is input simultaneously through two ports (DB0 and DB1), and the DDR mode is adopted, that is, the data is sampled using both the rising and falling edges of the clock, which can increase the data conversion rate. During the data conversion process, the digital-to-analog conversion circuit inside the AD9739 converts the input digital signal into a differential current signal output, and the output current is programmable in the range of 8.66mA to 31.66mA. When outputting analog signals, the analog signals after digital-to-analog conversion are output from the output port in the form of differential current, converted into differential voltage output through external resistors, and then converted into single-ended RF signals through baluns for output.

[0048] The maximum sampling rate of the high-speed serial bus JESD204B interface and LVDS interface supports 2.5GSPS;

[0049] AD9739 digital-to-analog conversion module: used to convert the processed digital signal into an analog signal and output the analog signal through the RF connector;

[0050] LMK04828 clock module: used to provide high-precision, low-jitter clock signals to the entire system; ensuring stable operation of the system and accurate data exchange;

[0051] Power management module: used to provide power to the system.

[0052] The controller converts the external input power supply into the power supply required by the relevant chips in the board. The internal power tree of the entire system is as follows: Figure 4 .

[0053] Specifically, the present invention is further described below by way of embodiments:

[0054] like Figure 3The system hardware architecture is designed with ZYNQ 7Z100 FPGA master chip, based on ARM Cortex-A9 core, combining programmable logic (PL) and on-chip processing system (PS). The onboard PS side and PL side are designed with 1 32-bit 1GB DDR interface, 1 256Mb QSPI FLASH interface and 1 8GB EMMC interface respectively. The system clock includes 1 33.33MHz PS side system clock and 50MHz PL side reference clock. The design leads to an analog output interface RF_OUT, an analog input interface RF_IN, an external reference clock input interface 100MHz, a 10 / 100 / 1000Mbps adaptive Ethernet interface, a USB interface supporting USB2.0 protocol, an SD card interface for debugging and an RS232 debugging serial port.

[0055] like Figure 5 As shown in the figure, in the actual application process, the working parameters of the whole system are first set through the host computer system, such as setting the sampling frequency of the AD9625 analog-to-digital conversion module, the signal output amplitude of the AD9739 digital-to-analog conversion module, etc. The control module receives the relevant parameters sent by the host computer to further complete the parameter setting of the internal related modules. For example, the input analog signal is converted into a digital signal through the AD9625 analog-to-digital conversion module, and the digital signal is filtered, encoded, etc. in the data processing module. The processed digital signal is then converted into an analog signal output through the AD9739 digital-to-analog conversion module. In the whole process, the LMK04828 clock generation module clock provides a stable reference clock signal for the whole system to ensure the synchronous operation of the whole module.

[0056] Embodiment 2: In the second aspect, as Figure 6 To achieve the above object, the present invention discloses a high-performance data processing method, which includes the following steps:

[0057] S101: Acquire an input analog signal, perform analog-to-digital conversion on the input analog signal, and obtain a digital signal;

[0058] S102: Process the digital signal to obtain a processed digital signal, and perform digital-to-analog conversion on the processed digital signal to obtain an analog signal, wherein a high-precision, low-jitter clock signal is added during the conversion process.

[0059] Based on the same inventive concept, the present invention also provides a computer device, which includes: one or more processors, and a memory for storing one or more computer programs; the program includes program instructions, and the processor is used to execute the program instructions stored in the memory. The processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. It is the computing core and control core of the terminal, which is used to implement one or more instructions, specifically for loading and executing one or more instructions in a computer storage medium to implement the above method.

[0060] It needs to be further explained that, based on the same inventive concept, the present invention also provides a computer storage medium, on which a computer program is stored, and the computer program is executed by a processor to execute the above method. The storage medium can adopt any combination of one or more computer-readable media. The computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. The computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electrical, magnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples (non-exhaustive list) of computer-readable storage media include: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present invention, a computer-readable storage medium can be any tangible medium containing or storing a program, which can be used by an instruction execution system, device or device or used in combination with it.

[0061] In the description of this specification, the description with reference to the terms "one embodiment", "example", "specific example", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0062] The above shows and describes the basic principles, main features and advantages of the present disclosure. Those skilled in the art should understand that the present disclosure is not limited by the above embodiments, and the above embodiments and descriptions are only for explaining the principles of the present disclosure. Without departing from the spirit and scope of the present disclosure, the present disclosure may have various changes and improvements, and these changes and improvements fall within the scope of the present disclosure to be protected.

Claims

1. A high performance data processing system, characterized in that: include: AD9625 analog-to-digital conversion module: used to receive the input analog signal, convert the input analog signal into a digital signal, and send the digital signal to the ZYNQ7Z100 data processing module; ZYNQ7Z100 data processing control module: used to process digital signals and send the processed digital signals to the AD9739 digital-to-analog conversion module; AD9739 digital-to-analog conversion module: used to convert the processed digital signal into an analog signal and output the analog signal through the RF connector; LMK04828 clock module: used to provide high-precision, low-jitter clock signals for the entire system; Power management module: It is used to provide power supply to the system.

2. A high performance data processing system according to claim 1, characterized in that: The AD9625 analog-to-digital conversion module and the ZYNQ7Z100 data processing control module are connected using a high-speed serial bus JESD204B interface.

3. A high performance data processing system according to claim 1, characterized in that: The AD9739 digital-to-analog conversion module and the ZYNQ7Z100 data processing control module are interconnected using an LVDS interface.

4. A high performance data processing system according to claim 2, characterized in that: The high-speed serial bus JESD204B interface and the LVDS interface support a maximum sampling rate of 2.5 GSPS.

5. A high performance data processing system according to claim 1, characterized in that: The process of the AD9625 analog-to-digital conversion module converting the input analog signal into a digital signal includes: in the initial stage, the ZYNQ7Z100 PS terminal converts the relevant parameters set by the host computer into the register values ​​of the AD9625 and configures the relevant register parameters into the AD9625 with the SPI protocol data; in the data sampling stage, the AD9625 converts the input analog signal into a digital signal, and the sampled signal enters the first-level analog-to-digital conversion module and is compared with a reference threshold, and a residual signal is formed through a multiplication DAC. The calculation formula of the residual signal is: v i+1 =2*(v i +(b i -0.5)v ref / 2) where v i is the current stage input signal, b i is the comparison result of the current level, v ref is the reference voltage; After completing the first-level conversion, the residual signal of the first level is passed to the next level as the input of the next level, and the process of comparing and generating residual signals is repeated. Each level performs the same operation and the conversion accuracy of each level is improved. After conversion and correction at all levels, the final digital output is obtained, and the data output is completed using the high-speed serdes interface JESD204B interface.

6. A high performance data processing system according to claim 1, characterized in that: The process of digital signal processing by the ZYNQ7Z100 data processing control module: The process of digital signal processing by the ZYNQ7Z100 data processing control module includes host computer instruction parsing, register value sending, IQ processing of quantized data, FFT processing, ABS operation and rotation point budgeting, data waveform generation and DMA processing, wherein instruction parsing includes receiving and sending and parsing host computer data: the ZYNQ7Z100 PS end receives the Ethernet message sent by the host computer to complete the parsing, and then configures the parsed parameters in the form of registers to the PL end and related interface chips. The register values ​​sent are mainly AD9625, AD9729 and LMK04828 chips, etc. The related chips are interconnected with ZYNQ7Z100 using the SPI protocol. After the ZYNQ7Z100 PS end parses the host computer data into register configuration data, the data is sent to the corresponding hardware chip in the form of serial data through the SPI interface.

7. A high performance data processing system according to claim 1, characterized in that: The process of converting the processed digital signal into an analog signal by the AD9739 digital-to-analog conversion module is divided into the process of configuring registers, inputting data, data conversion, and outputting analog signals. In the process of configuring registers, the ZYNQ7Z100 PS end converts the data sent by the host computer into configuration register parameters and configures the relevant parameters to the internal registers of the AD9739 through the SPI interface, including setting its working mode, output current, and clock mode. The data input process is ZYNQ7Z100 The PL end generates a modulation wave according to the modulation parameters sent by the PS end. If it is voice data modulation, the modulation waveform sent by the PS end is read from the DDR through the FIFO. Then, in the dual-port LVDSDDR format, the input data is input simultaneously through two ports. The DDR mode is adopted, and data sampling is performed using both the rising and falling edges of the clock. During the data conversion process, the digital-to-analog conversion circuit inside the AD9739 converts the input digital signal into a differential current signal output. When outputting an analog signal, the analog signal after digital-to-analog conversion is output from the output port in the form of a differential current, converted into a differential voltage output through an external resistor, and then converted into a single-ended RF signal through a balun for output.

8. A high performance data processing method, characterized in that: The method comprises the following steps: Acquire an input analog signal, perform analog-to-digital conversion on the input analog signal, and obtain a digital signal; The digital signal is processed to obtain a processed digital signal, and the processed digital signal is converted from digital to analog to obtain an analog signal, wherein a high-precision, low-jitter clock signal is added during the conversion process.

9. A terminal device, comprising a memory, a processor, and a computer program stored in the memory and capable of running on the processor, characterized in that: The memory stores a computer program that can be run on the processor, and when the processor loads and executes the computer program, a high-performance data processing system as described in any one of claims 1 to 7 is adopted.

10. A computer-readable storage medium having a computer program stored therein, characterized in that: When the computer program is loaded and executed by the processor, a high-performance data processing system according to any one of claims 1 to 7 is used.

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