Random number generation device based on multi-random number chip
By using multiple random number chips in the random number generation device and dynamic management of chip select controller and clock controller, the problems of insufficient generation rate of a single random number chip and high cost of true random number cards are solved, and efficient and low-cost random number output is achieved, improving the reliability and security of the system.
Patent Information
- Application Number
- CN202411610545.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-12
- Publication Date
- 2025-03-07
AI Technical Summary
In the case where a large number of random numbers are needed, the random number generation rate of the existing true random number chip is insufficient, and the cost of the true random number card is too high, making it difficult to meet the demand for high-speed random number output.
A random number generation device based on multiple random number chips is designed, and through the cooperation of a chip selection controller and a clock controller, the working state of multiple random number chips are dynamically selected and controlled to achieve efficient random number generation and output.
The device can ensure efficient generation and output of random numbers while reducing costs, improving system reliability and security, and extending the service life of random numbers chips.
Smart Images
Figure CN119576279A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of random number generation, and more specifically, the present invention relates to a random number generation device based on multiple random number chips. Background Art
[0002] Random numbers have many uses. For example, they can be used to generate one-time passwords (OTPs). To avoid attacks, their randomness is very important. Otherwise, by observing several one-time passwords, it is possible to predict the next password. In addition, random number sequences are widely used in cryptography, which is indispensable for new communication technologies such as the fifth generation of mobile communication technology (5G) and the Internet of Things (IoT).
[0003] Currently, the devices used to generate true random numbers include true random number chips and true random number cards. Among them, the most commonly used true random number is the true random number chip. These chips are generally small in size and low in power consumption, but the speed of generating random numbers is also low; while the true random number card is larger in size, higher in performance, and more expensive, but the price of a random number card is often a thousand times that of a random number chip.
[0004] When a large number of random numbers are needed, if a random number card is used, there is a problem of high cost. If a single random number chip is used, the random number generation rate of the random number chip may not meet the requirements of high-speed random number output. Summary of the invention
[0005] The present invention provides a random number generating device based on multiple random number chips, aiming to improve the above problems.
[0006] The present invention is implemented as follows: a random number generation device based on a multi-random number chip, the device comprising:
[0007] Multiple random number chips;
[0008] a chip select controller connected to the chip enable signal input pins, warning signal output pins and output enable control pins of all random number chips, and used to determine the currently working random number chip based on the rate of external random number reading;
[0009] A clock controller connected to the data acquisition clock pins of all random number chips and used to control the random number generation rate of the random number chips;
[0010] A storage unit, connected to the data output pins of all random number chips, for caching the random numbers generated by the random number chips;
[0011] The output controller is connected to the storage unit, the chip selection controller and the clock controller, and is used to control the output of the random number cached in the storage unit.
[0012] Furthermore, the chip select controller calculates the number m of random number chips that need to be started. Among them, V is the rate of external random number reading, and S is the random number generation rate of the random number chip.
[0013] Furthermore, the selection process of the random number chip to be started is as follows:
[0014] The chip select controller randomly selects a random number chip as the master random number chip, selects and starts m slave random number chips based on the random number generated by the master random number chip, and the master random number chip stops working.
[0015] Furthermore, the selection process of the main random number chip is as follows:
[0016] When starting the device, the chip select controller sets the chip enable signals of all random chips to a high level to put them in working state, and at the same time controls the output enable control pin to a low level to put them in output state;
[0017] The output controller randomly selects a random number from the random number cache queue, takes the last 32 bits of the currently selected random number, takes the modulus of the 32-bit value D and the total number of random number chips n to obtain a value P, and sets the Pth random number chip as the main random number chip, and the other random number chips as slave random number chips;
[0018] The chip select controller controls the control output enable control pin of the main random number chip to be low level to make it in output state, and the output enable control pin of the slave random number chip to be high level to make it in non-output state.
[0019] Furthermore, the selection process of m random number chips is as follows:
[0020] (41) The main random number chip generates a random number R, takes the last 32 bits of the random number R, and modulos the 32-bit value d with the total number of random number chips n to obtain a value p;
[0021] (42) Detect whether the output enable control pin of the pth random number chip is at a low level. If the detection result is yes, return to step (41). If the detection result is no, set the output enable control pin of the pth random number chip to a low level to put it in an output state, thereby completing a startup from the random number chip;
[0022] (43) Repeat steps (41) and (42) until m slave random number chips are started, and the chip select controller controls the output enable control pin of the master random number chip to be high level to make it in a non-output state.
[0023] Furthermore, when there is no need to read random numbers externally, the chip select controller controls the output enable control pin of the master random number chip to be at a low level, and the output enable control pin of the slave random number chip to be at a high level.
[0024] Furthermore, when the random number chip fails self-test during operation, the warning signal output pin outputs a high level, and the chip select controller sets the chip enable signal of the corresponding random number chip to a low level to put it in a non-operating state.
[0025] Furthermore, the random numbers in the storage unit are stored in a random number cache queue, and the cache area is set as an array of M rows and N columns. The random numbers generated and output by each random number chip are stored in the random number cache queue by column, and the random numbers are read out by row from the random number cache queue.
[0026] Furthermore, the storage unit feeds back the random number cache queue state to the output controller. If the number of random numbers cached in the storage unit is small, the clock output of the clock controller is increased. Otherwise, the number of random numbers cached in the storage unit is large, and the clock output of the clock controller is reduced.
[0027] The random number generation device based on the multi-random number chip provided by the present invention has the following beneficial technical effects:
[0028] (1) By using multiple random number chips in combination, the device can basically still be used normally when a single point failure occurs in the random number chip; randomly selecting and enabling random number chips can ensure that the usage frequency of each random number chip is similar, extend the life of the random number chip, and effectively avoid external threats to the characteristic analysis of the random number chip;
[0029] (2) A high random number generation rate is achieved by combining multiple random number chips, and the cost is relatively low;
[0030] (3) The random number cache queue can effectively increase the random number output speed and play a buffering role. At the same time, the random number cache queue can also organize the input of each random number chip into a queue, and can interleave and mix the inputs of multiple random number chips to further improve their randomness. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] Figure 1 A schematic diagram of the structure of a random number generation device based on a multi-random number chip provided in an embodiment of the present invention;
[0032] Figure 2 A schematic diagram of pin connections of a random number chip provided in an embodiment of the present invention;
[0033] Figure 3 A schematic diagram of the storage structure of a random number cache queue provided by an embodiment of the present invention. Implementation
[0035] The specific implementation modes of the present invention are further explained in detail below by describing the embodiments with reference to the accompanying drawings, so as to help those skilled in the art to have a more complete, accurate and in-depth understanding of the inventive concept and technical solution of the present invention.
[0036] Figure 1 A schematic diagram of the structure of a random number generation device based on a multi-random number chip provided in an embodiment of the present invention. For ease of description, only the part related to the embodiment of the present invention is shown. The system includes:
[0037] Multiple random number chips;
[0038] a chip select controller connected to the chip enable signal input pins, warning signal output pins and output enable control pins of all random number chips, and used to determine the currently working random number chip based on the rate of external random number reading;
[0039] A clock controller, connected to the data acquisition clock pins of all random number chips, for controlling the random number generation frequency of the random number chips;
[0040] A storage unit, connected to the data output pins of all random number chips, for caching the random numbers generated by the random number chips;
[0041] The output controller is connected to the storage unit, the chip selection controller and the clock controller, and is used to control the output of the random number cached in the storage unit.
[0042] When the random number chip fails the self-test, the warning signal output pin outputs a high level, and the chip select controller sets the chip enable signal of the corresponding random number chip to a low level. The random number chip does not work, and at the same time controls the output enable control pin to a high level, and the data output pin stops outputting data; when the chip select controller selects a random number chip to generate random numbers, the chip enable signal of the corresponding random number chip is set to a high level, and at the same time controls the output enable control pin to a low level.
[0043] Taking the most common quantum random number chip QRNG300 in SOP8 package as an example, pin 1 is the chip enable signal input pin (EN), with a built-in pull-up resistor. The chip works normally when it is floating or at a high level; pin 2 is the warning signal output pin (D_VALID), which indicates the random number randomness self-test. When it is set to 0, the random number is output normally, and when it is set to 1, the chip needs to be reset; pin 5 is the data output pin (DO), which is the data output terminal; pin 6 is the output enable control pin When the level is low, the internal data is output to the DATA port. When it is suspended or high, the data output terminal is high configuration. Pin 7 is the data acquisition clock pin (CLK). When pin 1 is set to a low level, the chip stops working. When the random number self-test inside the chip fails, pin 2 will output a high level (set to 1). When pin 6 is set to a high level, the data output stops. The connection diagram of the random number chip, chip select controller, and clock controller is shown in the figure. Figure 2 shown.
[0044] Since the maximum output frequency of each random number chip has an upper limit, when the outside needs more random numbers, even if a higher clock is given to the random number chip, it will not help. Therefore, the present invention first inputs the random number output by the random number chip into the random number cache queue in the storage unit, and outputs it to the outside through the cache queue by the output controller. The random number cache queue can collect the random numbers of multiple random number chips at one time, and then output them in batches to the outside, thereby improving the data output efficiency; while being able to buffer the changes in the speed of external reading, the random numbers input by each random number chip are sorted into queues, and the multiple random numbers are interleaved to improve randomness.
[0045] The random number generation speed S of each random number chip is related to the input clock frequency. The output controller triggers the clock controller to control the output frequency (output speed) of the random number chip. The storage unit feeds back the random number cache queue status to the output controller. If the number of random numbers cached in the storage unit is small, the clock output of the clock controller is increased. Conversely, the number of random numbers cached in the storage unit is large, and the clock output of the clock controller is reduced.
[0046] The device has n random number chips, and the random number generation rate of each random number chip is S. The device generates random numbers at a rate of n*S. When such a high rate of random numbers is not needed externally, the chip select controller is triggered by the output controller to start the generation of random numbers by some random number chips. The specific operation is as follows: the chip select controller randomly selects a random number chip as the main random number chip, and after m slave random number chips are selected and started based on the random numbers generated by the main random number chip, the main random number chip stops working.
[0047] In the embodiment of the present invention, the selection process of the primary random number chip is as follows:
[0048] When the random number output device is started, the chip select controller starts all random number chips, that is, the chip enable signals of all random number chips are set to a high level, and the output enable control pin is controlled to a low level at the same time;
[0049] Determine the master random number chip: the output controller selects a random number from the random number cache queue, takes the last 32 bits of the currently selected random number, takes the modulus (D%n) of the 32-bit value D and the total number of random number chips n, and obtains the value P, and sets the Pth random number chip as the master random number chip, controls the control output enable control pin of the master random number chip to a low level, and the other random number chips are slave random number chips, and the output enable control pins of the slave random number chips are high levels.
[0050] When there is no need to read random numbers externally, the chip select controller controls the output enable control pin of the master random number chip to be low level, and the output enable control pin of the slave random number chip to be high level, thereby stopping the output of random numbers.
[0051] When there is a need to read random numbers externally, the chip select controller determines the number m of slave random number chips that need to be started. or Among them, V is the rate of external random number reading, S is the random number generation rate of the random number chip, the slave random number chip to be started is randomly determined by the main random number chip, the main random number chip randomly generates random numbers for selecting and starting other random number chips, and the main random number chip sends the randomly generated random numbers to the chip select controller, and the chip select controller determines and controls the output enable control pin of the corresponding random number chip to be low. This method can effectively balance the working time of each random number chip, improve the overall life of the random number chip, and is conducive to improving security.
[0052] In the embodiment of the present invention, the determination process of m slave random number chips is specifically as follows:
[0053] (41) The main random number chip generates a random number R, takes the last 32 bits of the random number R, and modulos the 32-bit value d with the total number of random number chips n (d%n) to obtain a value p;
[0054] (42) Detect whether the output enable control pin of the pth random number chip is at a low level. If the detection result is yes, return to step (41). If the detection result is no, set the output enable control pin of the pth random number chip to a low level to complete a startup from the random number chip.
[0055] (43) Repeat steps (41) and (42) until m slave random number chips are started, the chip select controller controls the output enable control pin of the master random number chip to be high level, and the master random number chip stops working. At this time, the m slave random number chips generate random numbers at the same time.
[0056] If an alarm is generated during the process of outputting random numbers from a random number chip, the chip select controller will set the chip enable signal of the corresponding slave random number chip to a low level, stop the slave random number chip, and randomly enable other slave random number chips to replace the failed slave random number chip; if an alarm is generated during the process of outputting random numbers from a master random number chip, the chip select controller will set the chip enable signal of the master random number chip to a low level, stop the master random number chip, and randomly reselect the master random number chip; if too many current random number chips fail, resulting in the random number generation rate not meeting the requirements, the device will alarm externally and request a reduced output speed.
[0057] In the embodiment of the present invention, the random numbers stored in the random number cache queue are stored in a matrix interleaved manner, and the cache area is set to an array of M rows and N columns. The random numbers generated and output by each random number chip are stored in the random number cache queue by column. When reading the random numbers from the random number cache queue, they are read out by row. Assuming that there are n random number chips working, there are n columns of random numbers input into the random number cache queue. The data working mode of the random number cache area is as follows: Figure 3 shown.
[0058] In an embodiment of the present invention, the apparatus may provide random numbers for at least one virtual machine or device. When providing random numbers for multiple virtual machines or devices, the rate V of externally reading random numbers is the sum of the required reading rates of all virtual machines.
[0059] The random number generation device based on the multi-random number chip provided by the present invention has the following beneficial effects:
[0060] (1) By combining multiple random number chips, the random number output rate is effectively improved, which greatly improves the problem of insufficient output rate of a single random number chip; (2) By combining multiple random number chips, even if some random number chips fail, other random number chips can still output random numbers normally, thereby improving their reliability; (3) The main random number chip is randomly selected, and the working slave random number chip is randomly selected by the main random number chip to ensure that the probability of use of each random number chip is similar, and some random number chips will not be overused and affect their lifespan. In addition, randomly selecting random number chips can effectively avoid external consistency attacks, and random number output is safer; (4) The input clock of the random number chip is configured as needed to control its output speed, and some random number chips are selectively started to work through the chip select controller, which can effectively reduce power consumption.
[0061] The present invention has been described exemplarily. Obviously, the specific implementation of the present invention is not limited to the above-mentioned method. As long as various non-substantial improvements are made using the method concept and technical solution of the present invention, or the concept and technical solution of the present invention are directly applied to other occasions without improvement, they are all within the protection scope of the present invention.
Claims
1. A random number generation device based on a multi-random number chip, characterized in that: The device comprises: Multiple random number chips; a chip select controller connected to the chip enable signal input pins, warning signal output pins and output enable control pins of all random number chips, and used to determine the currently working random number chip based on the rate of external random number reading; A clock controller connected to the data acquisition clock pins of all random number chips and used to control the random number generation rate of the random number chips; A storage unit, connected to the data output pins of all random number chips, for caching the random numbers generated by the random number chips; The output controller is connected to the storage unit, the chip selection controller and the clock controller, and is used to control the output of the random number cached in the storage unit.
2. The random number generation device based on multiple random number chips as claimed in claim 1, characterized in that: The chip select controller calculates the number of random number chips m that need to be started. Among them, V is the rate of external random number reading, and S is the random number generation rate of the random number chip.
3. The random number generation device based on multiple random number chips as claimed in claim 2, characterized in that: The selection process of the random number chip to be started is as follows: The chip select controller randomly selects a random number chip as the master random number chip, selects and starts m slave random number chips based on the random number generated by the master random number chip, and the master random number chip stops working.
4. The random number generation device based on multiple random number chips as claimed in claim 3, characterized in that: The selection process of the main random number chip is as follows: When starting the device, the chip select controller sets the chip enable signals of all random chips to a high level to put them in working state, and at the same time controls the output enable control pin to a low level to put them in output state; The output controller randomly selects a random number from the random number cache queue, takes the last 32 bits of the currently selected random number, takes the modulus of the 32-bit value D and the total number of random number chips n to obtain a value P, and sets the Pth random number chip as the main random number chip, and the other random number chips as slave random number chips; The chip select controller controls the output enable control pin of the main random number chip to be at a low level so that it is in an output state, and controls the output enable control pin of the slave random number chip to be at a high level so that it is in a non-output state.
5. The random number generation device based on multiple random number chips as claimed in claim 3, characterized in that: The selection process of m random number chips is as follows: (41) The main random number chip generates a random number R, takes the last 32 bits of the random number R, and modulos the 32-bit value d with the total number of random number chips n to obtain a value p; (42) Detect whether the output enable control pin of the pth random number chip is at a low level. If the detection result is yes, return to step (41). If the detection result is no, set the output enable control pin of the pth random number chip to a low level to put it in an output state, thereby completing a startup from the random number chip; (43) Repeat steps (41) and (42) until m slave random number chips are started, and the chip select controller controls the output enable control pin of the master random number chip to be high level to make it in a non-output state.
6. The random number generation device based on multiple random number chips as claimed in claim 2, characterized in that: When there is no need to read random numbers externally, the chip select controller controls the output enable control pin of the master random number chip to be low level, and the output enable control pin of the slave random number chip to be high level.
7. The random number generation device based on multiple random number chips as claimed in claim 1, characterized in that: When the random number chip fails the self-test during operation, the warning signal output pin outputs a high level, and the chip select controller sets the chip enable signal of the corresponding random number chip to a low level to put it in a non-operating state.
8. The random number generation device based on multiple random number chips as claimed in claim 1, characterized in that: The random numbers in the storage unit are stored in a random number cache queue. The cache area is set as an array of M rows and N columns. The random numbers generated and output by each random number chip are stored in the random number cache queue by column. When reading random numbers from the random number cache queue, they are read out by row.
9. The random number generation device based on multiple random number chips as claimed in claim 8, characterized in that: The storage unit feeds back the random number cache queue status to the output controller. If the number of random numbers cached in the storage unit is small, the clock output of the clock controller is increased. Otherwise, the number of random numbers cached in the storage unit is large, and the clock output of the clock controller is reduced.