Encryption and decryption rapid processing system and method, storage medium and electronic equipment
By designing a fast encryption and decryption processing system, using the parallel processing method of the data management module and the security logic computing module, the problem of high cost of existing encryption and decryption processing circuits is solved, and efficient and low-cost encryption and decryption processing is achieved.
Patent Information
- Application Number
- CN202311110622.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-08-30
- Publication Date
- 2025-03-07
AI Technical Summary
In order to meet high performance requirements, existing encryption and decryption processing circuits lead to higher costs.
A rapid encryption and decryption processing system is designed, including a data management module and multiple security logic computing modules. The data management module is responsible for obtaining the pending data, parsing and dividing it into multiple processing items, and the security logic computing module processes these processing items in parallel to obtain the encryption or decryption processing results.
By reducing the requirements for host configuration, dedicated chip CPU and scheduling software, a low-cost encryption and decryption fast processing system is achieved, while improving the throughput of encryption and decryption processing.
Smart Images
Figure CN119577851A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of computer technology, and in particular to a fast encryption and decryption processing system, method, storage medium and electronic device. Background Art
[0002] With the rapid development of information technology, the amount of calculation that computers have to process is getting bigger and bigger. Therefore, for encryption and decryption operations of large amounts of data, dedicated chips are usually used to increase the operation rate. In the case of requiring a higher encryption and decryption processing throughput, relevant technicians usually adopt the following two solutions: one is to use multiple dedicated chips in parallel and distribute data through an external host; the other is to use high-performance dedicated chips. The existing high-performance dedicated chips are generally implemented in a way that there are multiple dedicated encryption and decryption circuit cores inside, and the chip core CPU and software distribute data. Since the first method requires an increase in the configuration requirements of the external host, and the second method has extremely high requirements for the CPU and scheduling software of the dedicated chip, both methods require a large amount of capital investment in actual applications.
[0003] To address the above-mentioned problems, no effective solution has been proposed yet. Summary of the invention
[0004] The embodiments of the present application provide a fast encryption and decryption processing system, method, storage medium and electronic device to at least solve the technical problem in the related art that the encryption and decryption processing circuits are required to meet high performance requirements, resulting in high costs for the encryption and decryption processing circuits.
[0005] According to one aspect of an embodiment of the present application, there is provided an encryption and decryption fast processing system, the encryption and decryption fast processing system comprising: a data management module and a security logic calculation module, wherein the data management module is used to obtain the data to be processed of the upper computer, and process the data to be processed, and determine the control signal and multiple sub-data to be processed corresponding to the data to be processed; the security logic calculation module is multiple in number and connected to the data management module, and is used to divide the received sub-data to be processed into multiple processing items, and process the multiple processing items in parallel according to the control signal to obtain multiple processing results; the multiple processing results corresponding to each sub-data to be processed are merged to obtain the target processing result corresponding to the data to be processed, wherein the target processing result includes: an encryption processing result or a decryption processing result.
[0006] In an exemplary embodiment, the data management module includes an acquisition unit and a decoding unit, wherein the acquisition unit is used to group the data to be processed and send the grouped groups of data to be processed to the decoding unit, wherein each group of data to be processed after grouping includes at least instruction data; the decoding unit is connected to the acquisition unit, and is used to decode the instruction data in each group of data to be processed after grouping to obtain a control signal corresponding to the instruction data and sub-data to be processed corresponding to the instruction data.
[0007] In an exemplary embodiment, the data management module further includes a command register connected to the decoding unit and used to store control signals corresponding to instruction data of multiple groups of data to be processed and sub-data to be processed corresponding to the instruction data.
[0008] In an exemplary embodiment, the security logic computing module includes: a computing pipeline, a resource allocator, and a stream processing unit, wherein the computing pipeline is connected to the command register and is used to send multiple processing items corresponding to the segmented sub-data to be processed to the stream processing unit; the resource allocator is connected to the computing pipeline and is used to determine the allocation of corresponding computing resources to the stream processing unit based on the multiple processing items; the stream processing unit is connected to the resource allocator and is used to process the processing items based on the computing resources to obtain processing results corresponding to the processing items.
[0009] In an exemplary embodiment, the stream processing unit is also used to combine multiple logic operation systems and / or multiple sequential logic systems according to a control signal to obtain encryption operation resources; or, to combine multiple logic operation systems and / or multiple sequential logic systems according to a control signal to obtain decryption operation resources.
[0010] In an exemplary embodiment, the logic operation system includes at least one of the following: a logic gate system, a logic AND system, a logic OR system, and a logic XOR system; the sequential logic system includes at least one of the following: a shifter, a latch, a counter, and a comparator.
[0011] In an exemplary embodiment, the parallel operation dimension of the security logic calculation module is determined according to the number of sub-data to be processed in the data management module and the preset number of resources.
[0012] According to another aspect of an embodiment of the present application, a method for rapid encryption and decryption processing is also provided, including: obtaining data to be processed from a host computer; parsing the data to be processed to determine a control signal and multiple sub-data to be processed corresponding to the data to be processed; dividing each sub-data to be processed to obtain multiple processing items, and processing the multiple processing items in parallel through a control signal to obtain multiple processing results corresponding to each sub-data to be processed; merging the multiple processing results of each sub-data to be processed to obtain a target processing result corresponding to the data to be processed, wherein the target processing result includes: an encryption processing result or a decryption processing result.
[0013] According to another aspect of an embodiment of the present application, a computer-readable storage medium is further provided, in which a computer program is stored, wherein the computer program is configured to execute the above-mentioned fast encryption and decryption processing method when running.
[0014] According to another aspect of an embodiment of the present application, there is also provided an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the above-mentioned fast encryption and decryption processing method through the computer program.
[0015] Through the above system, the data management module parses the data to be processed obtained from the host computer to obtain the control signal and multiple sub-data to be processed corresponding to the data to be processed, and then multiple security logic calculation modules respectively divide the multiple sub-data to be processed in turn to obtain multiple processing items, and process the multiple processing items in parallel according to the control signal to obtain multiple processing results; the multiple processing results corresponding to each sub-data to be processed are merged to obtain the encryption processing result or decryption processing result corresponding to the data to be processed. The above system solution provides a low-cost encryption and decryption fast processing system, which reduces the requirements for host configuration, dedicated chip CPU and scheduling software, while improving the throughput of encryption and decryption processing, thereby solving the technical problem in the related technology that the encryption and decryption processing circuit is high in cost to meet the high performance requirements. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:
[0017] Figure 1 It is a hardware structure block diagram of a server of a fast encryption and decryption processing system according to an embodiment of the present application;
[0018] Figure 2 It is a schematic diagram of the structure of an optional encryption and decryption fast processing system of an embodiment of the present application;
[0019] Figure 3 is a schematic diagram of the structure of an optional data management module 22 according to an embodiment of the present application;
[0020] Figure 4 is a schematic diagram of the structure of an optional safety logic calculation module 24 according to an embodiment of the present application;
[0021] Figure 5 is a schematic diagram of the structure of another optional encryption and decryption fast processing system according to an embodiment of the present application;
[0022] Figure 6 It is a flowchart of a fast encryption and decryption processing method according to an embodiment of the present application. DETAILED DESCRIPTION
[0023] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.
[0024] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.
[0025] In addition, the relevant information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data for display, data for analysis, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties. For example, an interface is set up between this system and the relevant user or organization. Before obtaining relevant information, it is necessary to send an acquisition request to the aforementioned user or organization through the interface, and obtain relevant information after receiving the consent information fed back by the aforementioned user or organization.
[0026] Example 1
[0027] The method embodiments provided in the embodiments of the present application can be executed in a mobile terminal, a computer terminal or a similar computing device. Figure 1 1 is a hardware structure block diagram of a server of a fast encryption and decryption processing system according to an embodiment of the present application. Figure 1 As shown, the server may include one or more ( Figure 1 Only one is shown in the figure) a processor 102 (the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data. In an exemplary embodiment, the server may also include a transmission device 106 and an input / output device 108 for communication functions. It can be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the above server. Figure 1 More or fewer components as shown, or with Figure 1 Equivalent functions or comparisons shown Figure 1 A different configuration with more features is shown.
[0028] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the encryption and decryption fast processing system in the embodiment of the present application. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, to implement the above method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage systems, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories may be connected to the secure text via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.
[0029] The transmission device 106 is used to receive or send data via a network. The specific example of the above network may include a wireless network provided by a communication provider of the computer terminal 10. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.
[0030] In this embodiment, a fast encryption and decryption processing system is provided. Figure 2 is a structural block diagram of an optional encryption and decryption fast processing system according to an embodiment of the present application, such as Figure 2 As shown, the system includes at least the following components:
[0031] The data management module 22 is used to obtain the data to be processed from the host computer, process the data to be processed, and determine the control signal and multiple sub-data to be processed corresponding to the data to be processed;
[0032] There are multiple security logic calculation modules 24, which are connected to the data management module 22. They are used to divide the received sub-data to be processed into multiple processing items, and process the multiple processing items in parallel according to the control signal to obtain multiple processing results; merge the multiple processing results corresponding to each sub-data to be processed to obtain the target processing result corresponding to the data to be processed, wherein the target processing result includes: an encryption processing result or a decryption processing result.
[0033] Through the above system, the data management module parses the data to be processed obtained from the host computer to obtain the control signal and multiple sub-data to be processed corresponding to the data to be processed, and then multiple security logic calculation modules respectively divide the multiple sub-data to be processed in turn to obtain multiple processing items, and process the multiple processing items in parallel according to the control signal to obtain multiple processing results; the multiple processing results corresponding to each sub-data to be processed are merged to obtain the encryption processing result or decryption processing result corresponding to the data to be processed. The above system solution provides a low-cost encryption and decryption fast processing system, which reduces the requirements for host configuration, dedicated chip CPU and scheduling software, while improving the throughput of encryption and decryption processing, thereby solving the technical problem that the existing encryption and decryption processors in the related technology will lead to high cost of encryption and decryption processing circuits when meeting high performance requirements.
[0034] The components within each of the above modules will be described in further detail below.
[0035] Optionally, the data management module 22 of the embodiment of the present application is a CDM (Computer Data Master), which is a hardware design architecture. In CDM, the processor hardware itself is responsible for scheduling the instruction stream (Instruction Stream) without the need for software to participate in the scheduling. By using CDM, the overhead of software participation can be reduced, while improving the efficiency of parallel execution of instructions.
[0036] As an optional implementation, Figure 3 is a schematic diagram of the structure of an optional data management module 22 according to an embodiment of the present application, such as Figure 3 As shown, the data management module 22 includes an acquisition unit 221 and a decoding unit 222, wherein:
[0037] The acquisition unit 221 is used to group the data to be processed and send the grouped groups of data to be processed to the decoding unit 222, wherein each group of data to be processed includes at least instruction data;
[0038] The decoding unit 222 is connected to the acquiring unit 221 and is used to decode the instruction data in each group of the to-be-processed data to obtain the control signal corresponding to the instruction data and the to-be-processed sub-data corresponding to the instruction data.
[0039] Among them, the above-mentioned acquisition unit 221 groups the data to be processed from the upper computer to obtain multiple groups of sub-data to be processed including instruction data, and sends the multiple groups of sub-data to be processed to the decoding unit 222 in sequence; then the decoding unit 222 decodes the instruction data in each group of data to be processed to obtain the control signal corresponding to the instruction data and the sub-data to be processed corresponding to the instruction data.
[0040] Specifically, the instruction data can be decoded in the following manner to obtain the control signal corresponding to the instruction data: the instruction data is parsed to obtain different fields, including but not limited to the operation code (opcode), operand (operand), and register identifier, the instruction type of the instruction data is determined according to the operation code field, such as arithmetic logic instruction, memory access instruction, etc., and the corresponding register or memory address is parsed into the actual operand according to the operation code field, and the corresponding control signal is generated according to the instruction type and the operation result of the operand, wherein the control signal can be used to control different functional units of the processor, such as the arithmetic logic unit, the memory unit, etc. According to the above process, the control signal corresponding to the instruction data can be generated, and the instruction can be correctly executed later according to the generated control signal.
[0041] Optionally, the data management module 22 further includes a command register 223, and the command register 223 is connected to the decoding unit 222, wherein the command register 223 is used to store control signals corresponding to instruction data of multiple groups of data to be processed and sub-data to be processed corresponding to the instruction data.
[0042] As an optional implementation, the above-mentioned safety logic calculation module 24 includes multiple safety logic calculation modules 24, and the multiple safety logic calculation modules 24 are in parallel relationship. Figure 4 is a schematic diagram of the structure of an optional safety logic calculation module 24 according to an embodiment of the present application, such as Figure 4 As shown, each security logic computing module 24 includes: a computing pipeline 241, a resource allocator 242, and a stream processing unit 243, wherein:
[0043] The computing pipeline 241 is connected to the command register 223 and is used to send the multiple processing items obtained by dividing the sub-data to be processed to the stream processing unit 243;
[0044] A resource allocator 242, connected to the computing pipeline 241, is used to determine the allocation of corresponding computing resources to the stream processing unit 243 according to each processing item;
[0045] The stream processing unit 243 is connected to the resource allocator 242 and is used to process the processing items according to the computing resources to obtain processing results corresponding to the processing items.
[0046] Specifically, the computing pipeline 241 can send the multiple processing items obtained by splitting the sub-data to be processed stored in the command register 223 to the resource allocator 242, and the resource allocator 242 allocates corresponding computing resources to the stream processing unit 243 according to the processing content of each processing item; the stream processing unit 243 executes the corresponding processing items according to the computing resources to obtain the corresponding processing results.
[0047] It should be noted that the logic of each security logic computing module 24 composed of the computing pipeline 241, the resource allocator 242, and the stream processing unit 243 is the same, but the processed data may not be exactly the same. Therefore, the encryption and decryption processing efficiency can be improved through parallel processing, and finally the processing results output by multiple security logic computing modules 24 can be merged to obtain the overall processing result of the data to be processed.
[0048] Optionally, the stream processing unit 243 is also used to combine multiple logic operation systems and / or multiple sequential logic systems according to a control signal to obtain encryption operation resources; or, to combine multiple logic operation systems and / or multiple sequential logic systems according to a control signal to obtain decryption operation resources.
[0049] Specifically, the stream processing unit 243 in the embodiment of the present application combines the underlying operator logic circuits of multiple commonly used encryption and decryption operations according to the control signal to obtain corresponding operation resources, thereby realizing flexible operator reorganization to form different encryption and decryption methods. Among them, the above-mentioned logic operation system includes but is not limited to: logic gate system, logic and system, logic or system, logic exclusive or system; the sequential logic system includes but is not limited to: shifter, latch, counter, comparator, controller.
[0050] Furthermore, the parallel operation dimension of the security logic calculation module 24 is determined according to the number of sub-data to be processed in the data management module 22 and the preset number of resources.
[0051] Specifically, the data management module 22 can obtain multiple sub-data to be processed after parsing the data to be processed. Therefore, the encryption and decryption fast processing system can determine the number of security logic calculation modules 24 according to the data volume of the sub-data to be processed and the preset number of computing resources. That is to say, if the computing resource data cannot be provided to the stream processing unit 243 of the security logic calculation module 24 of a certain path, the branch operation will be reduced accordingly.
[0052] Figure 5 is a schematic diagram of the structure of another optional encryption and decryption fast processing system according to an embodiment of the present application, such as Figure 5 As shown, CDM (Computer Data Master) is the data management module 22 in the embodiment of the present application, CDM PIPE (Computer Data Master Pipeline) is the computing pipeline 241 in the embodiment of the present application, SA (Source Allocate) is the resource allocator 242 in the embodiment of the present application, SP (Stream processor) is the computing pipeline 241 in the embodiment of the present application, SA (Source Allocate) is the stream processing unit 243 in the embodiment of the present application, and CDM PIE, SA, SP together constitute a Secure Engine, that is, the security logic computing module 24 in the embodiment of the present application. Therefore, CDM is performed by hardware devices to obtain and distribute data accordingly, and the Secure Engine is responsible for processing branch data, wherein the processing logic of each Secure Engine branch is the same, but the processing data is not the same, and finally the processing results of each Secure Engine are combined to obtain the overall processing result.
[0053] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the embodiment of the present application can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, a disk, or an optical disk), and includes a number of instructions for a terminal device (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods of the following embodiments of the present application.
[0054] Figure 6 is a flowchart of a fast encryption and decryption processing method according to an embodiment of the present application; Figure 6 As shown, the following steps S602-S608 are included, wherein:
[0055] Step S602, obtaining the data to be processed from the host computer;
[0056] Step S604, analyzing the data to be processed, and determining a control signal and a plurality of sub-data to be processed corresponding to the data to be processed;
[0057] Step S606, dividing each sub-data to be processed into multiple processing items, and processing the multiple processing items in parallel through a control signal to obtain multiple processing results corresponding to each sub-data to be processed;
[0058] Step S608, merging the multiple processing results of each sub-data to be processed to obtain a target processing result corresponding to the data to be processed, wherein the target processing result includes: an encryption processing result or a decryption processing result.
[0059] Through the above steps, the data to be processed obtained from the host computer is first parsed to obtain the control signal and multiple sub-data to be processed corresponding to the data to be processed, and then the multiple sub-data to be processed are divided in turn to obtain multiple processing items, and the multiple processing items are processed in parallel according to the control signal to obtain multiple processing results; the multiple processing results corresponding to each sub-data to be processed are merged to obtain the encryption processing result or decryption processing result corresponding to the data to be processed. The above system solution provides a low-cost encryption and decryption fast processing system, which reduces the requirements for host configuration, dedicated chip CPU and scheduling software, and improves the throughput of encryption and decryption processing, thereby solving the technical problem that the encryption and decryption processing circuit in the related technology is high in cost in order to meet the high performance requirements.
[0060] Example 2
[0061] According to an embodiment of the present application, a non-volatile storage medium is also provided, in which a program is stored, wherein when the program is running, the device where the non-volatile storage medium is located is controlled to execute the encryption and decryption fast processing method in Example 1.
[0062] Optionally, the device where the non-volatile storage medium is located implements the following steps by running the program:
[0063] Step S602, obtaining the data to be processed from the host computer;
[0064] Step S604, analyzing the data to be processed, and determining a control signal and a plurality of sub-data to be processed corresponding to the data to be processed;
[0065] Step S606, dividing each sub-data to be processed into multiple processing items, and processing the multiple processing items in parallel through a control signal to obtain multiple processing results corresponding to each sub-data to be processed;
[0066] Step S608, merging the multiple processing results of each sub-data to be processed to obtain a target processing result corresponding to the data to be processed, wherein the target processing result includes: an encryption processing result or a decryption processing result.
[0067] According to an embodiment of the present application, a processor is also provided, which is used to run a program, wherein the encryption and decryption fast processing method in Example 1 is executed when the program is running.
[0068] Optionally, the following steps are performed when the program is running:
[0069] Optionally, the device where the non-volatile storage medium is located implements the following steps by running the program:
[0070] Step S602, obtaining the data to be processed from the host computer;
[0071] Step S604, analyzing the data to be processed, and determining a control signal and a plurality of sub-data to be processed corresponding to the data to be processed;
[0072] Step S606, dividing each sub-data to be processed into multiple processing items, and processing the multiple processing items in parallel through a control signal to obtain multiple processing results corresponding to each sub-data to be processed;
[0073] Step S608, merging the multiple processing results of each sub-data to be processed to obtain a target processing result corresponding to the data to be processed, wherein the target processing result includes: an encryption processing result or a decryption processing result.
[0074] According to an embodiment of the present application, an electronic device is also provided, which includes one or more processors; a memory for storing one or more programs, so that when the one or more programs are executed by one or more processors, the one or more processors are implemented to run the programs, wherein the program is configured to execute the encryption and decryption fast processing method in the above-mentioned embodiment 1 when running.
[0075] Optionally, the processor is configured to implement the following steps by executing a computer program:
[0076] Optionally, the device where the non-volatile storage medium is located implements the following steps by running the program:
[0077] Step S602, obtaining the data to be processed from the host computer;
[0078] Step S604, analyzing the data to be processed, and determining a control signal and a plurality of sub-data to be processed corresponding to the data to be processed;
[0079] Step S606, dividing each sub-data to be processed into multiple processing items, and processing the multiple processing items in parallel through a control signal to obtain multiple processing results corresponding to each sub-data to be processed;
[0080] Step S608, merging the multiple processing results of each sub-data to be processed to obtain a target processing result corresponding to the data to be processed, wherein the target processing result includes: an encryption processing result or a decryption processing result.
[0081] The serial numbers of the above-mentioned embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.
[0082] In the above embodiments of the present application, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant description of other embodiments.
[0083] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are only schematic. For example, the division of units can be a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.
[0084] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed over multiple units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.
[0085] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.
[0086] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the relevant technology or all or part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, server or network device, etc.) to perform all or part of the steps of each embodiment method of the present application. The aforementioned storage medium includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, disk or optical disk, etc. Various media that can store program codes.
[0087] The above are only preferred implementations of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.
Claims
1. A fast encryption and decryption processing system, characterized in that: The encryption and decryption fast processing system includes: a data management module and a security logic calculation module, wherein: The data management module is used to obtain the data to be processed from the host computer, process the data to be processed, and determine the control signal and multiple sub-data to be processed corresponding to the data to be processed; The security logic calculation module is multiple in number and connected to the data management module, and is used to divide the received sub-data to be processed into multiple processing items, and process the multiple processing items in parallel according to the control signal to obtain multiple processing results; merge the multiple processing results corresponding to each of the sub-data to be processed to obtain a target processing result corresponding to the data to be processed, wherein the target processing result includes: an encryption processing result or a decryption processing result.
2. The system according to claim 1, characterized in that The data management module includes an acquisition unit and a decoding unit, wherein: The acquisition unit is used to group the data to be processed, and send the grouped multiple groups of the data to be processed to the decoding unit, wherein each group of the data to be processed includes at least instruction data; The decoding unit is connected to the acquisition unit, and is used to decode the instruction data in each group of the to-be-processed data to obtain a control signal corresponding to the instruction data and sub-data to be processed corresponding to the instruction data.
3. The system according to claim 2, characterized in that The data management module also includes a command register connected to the decoding unit and used to store control signals corresponding to instruction data of multiple groups of data to be processed and sub-data to be processed corresponding to the instruction data.
4. The system according to claim 3, characterized in that The security logic computing module includes: a computing pipeline, a resource allocator, and a stream processing unit, wherein: The computing pipeline is connected to the command register and is used to send the multiple processing items corresponding to the segmented sub-data to be processed to the stream processing unit; The resource allocator is connected to the computing pipeline and is used to determine the allocation of corresponding computing resources to the stream processing unit according to the plurality of processing items; The stream processing unit is connected to the resource allocator, and is used to process the processing item according to the computing resources to obtain the processing result corresponding to the processing item.
5. The system according to claim 4, characterized in that The stream processing unit is also used to combine multiple logic operation systems and / or multiple sequential logic systems according to the control signal to obtain encryption operation resources; or, to combine multiple logic operation systems and / or multiple sequential logic systems according to the control signal to obtain decryption operation resources.
6. The system according to claim 5, characterized in that The logic operation system includes at least one of the following: a logic gate system, a logic AND system, a logic OR system, and a logic XOR system; the sequential logic system includes at least one of the following: a shifter, a latch, a counter, and a comparator.
7. The system according to claim 1, characterized in that The parallel operation dimension of the security logic calculation module is determined according to the number of sub-data to be processed in the data management module and the preset number of resources.
8. A fast encryption and decryption processing method, characterized in that: include: Get the data to be processed from the host computer; Parsing the data to be processed to determine a control signal and a plurality of sub-data to be processed corresponding to the data to be processed; Each of the sub-data to be processed is divided into a plurality of processing items, and the plurality of processing items are processed in parallel through the control signal to obtain a plurality of processing results corresponding to each of the sub-data to be processed; The multiple processing results of each of the sub-data to be processed are combined to obtain a target processing result corresponding to the data to be processed, wherein the target processing result includes: an encryption processing result or a decryption processing result.
9. A non-volatile storage medium, characterized in that: The non-volatile storage medium stores a computer program, wherein the device where the non-volatile storage medium is located executes the encryption and decryption fast processing method according to claim 8 by running the computer program.
10. An electronic device, characterized in that: include: A memory and a processor, wherein the processor is used to run a program stored in the memory, wherein the encryption and decryption fast processing method according to claim 8 is executed when the program is run.