A design method for radiation-resistant key circuits based on magnetic random access memory

Abstract

The present invention discloses a method for designing radiation-resistant key circuits based on magnetic random access memory. A double module redundancy (DMR) radiation-resistant standard cell reinforcement method is proposed for the basic combinational logic units in the write drive circuit, word line decoding / drive circuit and column selection circuit, and a radiation-resistant standard cell library is established. The radiation-resistant cell library is configured and the layout is drawn around 15 standard cells, and the data accuracy is verified by simulation. Compared with the traditional triple module redundancy (TMR) reinforcement solution, the power consumption, layout area and delay time are greatly reduced while maintaining the radiation-resistant performance.

Description

Technical Field

[0001] The invention belongs to the field of integrated circuits, and in particular relates to a method for designing a radiation-resistant key circuit based on a magnetic random access memory. Background Art

[0002] With the continuous advancement of electronic technology, integrated circuits are widely used in various fields, including harsh environments such as high voltage, high temperature, toxic or corrosive gases, and special scenarios with strong radiation. Under most harsh conditions, appropriate packaging technology can ensure the normal operation of electronic products. However, in the face of radiation environment, integrated circuits are susceptible to high-energy photons and particles, ionization and collision phenomena occur, causing irreversible damage to packaged semiconductor devices. In this case, packaging and shielding are often ineffective, and may even further aggravate radiation damage due to secondary reactions triggered in the packaging materials. Therefore, radiation-resistant technology has become a key direction of integrated circuit reliability research. With the rapid development of aerospace and nuclear industries, especially the rapid growth of the satellite industry, higher requirements are placed on the radiation-resistant design of memory. Although radiation-resistant logic design is relatively mature, radiation-resistant design for memory, especially the optimization of peripheral key circuits, is still a weak link in current technology. Memory faces multiple challenges in the development of radiation-resistant electronic products: on the one hand, although the traditional three-mode redundant reinforcement solution can improve radiation resistance, its area and power consumption are too high to meet the demand for efficient design at advanced process nodes; on the other hand, when high-energy particles act on semiconductor and insulator materials in integrated circuits, temporary damage will occur, namely soft errors including single particle effects, total dose effects and displacement damage. The release of charge generated by the single particle effect will cause a short spike in the voltage on the circuit node, namely glitch. The glitch will be captured by the bistable structure in the sequential logic unit, eventually leading to abnormal level flipping of the storage node. Therefore, it is necessary to improve the design of key circuits around the memory to effectively deal with the challenge of node potential flipping while reducing area and power consumption.

[0003] Magnetic Tunnel Junction (MTJ) is the core storage element of MRAM. Because it uses the electron spin characteristics to store data instead of traditional charge storage, there is no known interaction mechanism between it and ionizing radiation, so it exhibits high radiation tolerance. However, in the radiation test of commercial MRAM products, read errors caused by radiation particle impact are still observed. These soft errors are usually temporary and not permanent failures of the MTJ unit itself. The root cause lies in the radiation sensitivity of CMOS peripheral circuits. Therefore, in order to improve system reliability, it is urgent to carry out radiation hardening (RH) optimization design for peripheral key circuits to block glitches during the forward transmission of signals and effectively alleviate the soft error problem. Summary of the invention

[0004] The present invention aims to provide a method for designing a key circuit of a magnetic random access memory that is resistant to radiation, so as to solve the problem of soft errors caused by radiation in CMOS peripheral circuits in the prior art and to improve the reliability of MRAM in a radiation environment.

[0005] In order to solve the above technical problems, the specific technical solutions of the present invention are as follows:

[0006] A radiation-resistant key circuit design based on magnetic random access memory is proposed. For the peripheral circuits including write drive circuits, word line decoding and drive circuits and column selection circuits, a dual-mode redundant standard combinational logic unit radiation hardening (RH) method is proposed for the basic combinational logic units therein. After hardening the basic combinational logic unit circuits, standard combinational logic units with standardized design are obtained. A radiation-resistant standard cell library is established around 15 standard combinational logic unit circuits. The standard combinational logic units in the radiation-resistant standard cell library are used in the peripheral circuit design, which can filter out glitches during signal transmission, resist single particle effects, and ensure high system reliability.

[0007] The standard combinational logic unit circuit obtained by the dual-mode redundant standard combinational logic unit anti-radiation reinforcement RH method duplicates the combinational logic unit circuit module that needs to be reinforced twice, and cross-connects the PMOS tubes and NMOS tubes between different logics in the combinational logic unit circuit to connect the same input and output ends. The reinforced circuit is a dual-input dual-output structure, and the PMOS tubes and NMOS tubes in the same logic are not placed together, thereby preventing a single particle from overturning the circuit of a combinational logic unit at the same time, ensuring the normal operation of the circuit.

[0008] The peripheral circuit generates a read enable signal RDEN and a write enable signal WTEN by inputting a WEB signal, thereby controlling the switching of read and write operations; in the design, every 16 rows of bit lines (BL) and source lines (SL) reuse a set of read and write circuits to form a subarray. A complete 256Kb storage array consists of 32 subarrays, and 32 bits of data are read and written simultaneously each time, so the input data DIN and the output data DOUT are both 32 bits; the address signal ADDR has a total of 13 bits, of which the lower four-bit address signal ADDR<3:0> is used for column selection of BL and SL; the upper nine-bit address signal ADDR<12:4> is used to generate a 512-bit word line (WL) signal, and different operating voltages are selected according to the RDEN and WTEN signals to work.

[0009] Furthermore, the dual-mode redundant radiation-resistant reinforcement method reduces the design complexity and area and power consumption while reducing circuit changes. The traditional triple-mode redundant design will replicate the unit module that needs to be reinforced three times and add a voting circuit, which will increase the area and power consumption by more than two times. The dual-mode redundant design avoids the soft errors that cannot be handled in the voting circuit by removing the voting structure, effectively saving area and power consumption while further reducing the probability of soft errors.

[0010] In the combinational logic unit designed based on the dual-mode redundant anti-radiation reinforcement method, there are two dual-input and dual-output redundant modules, namely two groups of logics including PMOS tubes and NMOS tubes, which are formed by cross-connections between different logics; this connection structure can effectively realize the separation of control signals, so even if an input signal is affected by radiation and has transient burr fluctuations, it will only last for a very short time and the driving ability is not strong, while the unaffected signal maintains a stable strong drive, so it will not affect the final output result; through such an anti-radiation reinforcement implementation method based on dual-mode redundancy, particle beams can be prevented from knocking over multiple nodes at the same time.

[0011] Furthermore, in the write drive circuit, a combinational logic gate circuit and a level converter are included, wherein all the combinational logic units adopt a radiation-resistant standard unit library; the input signal Din and the inverted signal obtained through the RH inverter are respectively sent to the level converter through the RH or-not gate, and then connected to the WBL and WSL of the write column selection circuit; the other input of the two RH or-not gates is the WTEN signal through the RH inverter; the WTEN signal is a control signal, and different BL and SL voltages are generated through WTEN to complete the data writing to the storage unit; the voltage switching from 0.9V to 1.8V is completed through the level converter, and the switched high voltage is applied to the storage unit through the write column selection transmission gate;

[0012] The transistors in the level converter are all high-voltage IO tubes. The signal ZN is generated by the input signal through a VDDL low-voltage inverter, and the signal IN is generated by ZN through another VDDL low-voltage inverter. The level converter circuit adopts a fully cross-coupled structure of NMOS tubes and PMOS tubes, so that the size of the node where the ZN signal is located is VDDL instead of VSS in static state, thereby effectively reducing the source-drain voltage on the NMOS tube and reducing the static leakage current.

[0013] Furthermore, in the decoding and word line driving circuits, in order to effectively block the propagation of glitches, all the combinational logic units therein adopt radiation-resistant standard cell libraries; the circuit first obtains the WL voltage in the low voltage domain by the 9-512 decoder with enable, and then each WL voltage enters its own word line driving circuit;

[0014] The 9-512 decoder with enable is composed of a 4-16 decoder with enable and a 5-32 decoder through AND operation, and a total of 512 RH logic AND gates are required, while the 5-32 decoder can be obtained by a 3-8 decoder and a 2-4 decoder through AND operation, and a total of 32 RH logic AND gates are required; the 4-16 decoder with enable is obtained by a 4-16 decoder without enable and an EN signal through a logical operation; when the array performs read and write operations and the enable end EN signal is at a high level, the decoder works normally, determines the voltage of each WL, and selects the corresponding WL; when no read and write operations are performed, the enable end EN signal is at a low level, the output of the decoder is all zero, and all WLs are grounded;

[0015] The word line driving circuit is composed of a level converter and a gate, and the WL voltage switches the voltage domain according to the operation type; the 9-bit address is passed through the 9-512 decoder to obtain the 512-bit WL voltage, but since the voltage domains of the read operation and the write operation are different, the read operation is performed in the 0.9V low voltage domain, and the write operation needs to be performed in the 1.8V high voltage domain, so these 512 WL voltages can only be directly applied to the WL during the read operation, and need to be converted to the high voltage domain before being applied to the WL during the write operation; the circuit divides the WL voltage into two paths, one of which is the low voltage domain voltage, and the other is converted to the high voltage domain through the level converter, and the two voltages are connected to the gate circuit, and different voltages are gated to the WL through the read and write enable signals;

[0016] In the gate circuit, in order to prevent the 1.8V voltage on WL from turning on the transmission tube during the write operation, the control signals WTEN and RDEN of the transmission tube must be converted to the high voltage domain by a level converter and then applied to the gate of the transmission gate; in order to prevent the transmission gate from being broken down by an excessively high write voltage, the transistors in the transmission gate must use high-voltage-resistant IO tubes.

[0017] Furthermore, in the column selection circuit including the write column selection circuit and the read column selection circuit, the logic AND gate is replaced by a radiation-resistant standard combinational logic unit reinforced with dual-mode redundancy; the circuit selects a group of BL and SL from 16 BL and SL, and sends them to the corresponding write circuit through the transmission gate during the write operation, and sends them to the corresponding read circuit through the transmission tube during the read operation;

[0018] In the write column selection control circuit, the lower four-bit address signal ADDR<3:0> generates a signal through a 4-16 decoder to select a specific BL and SL. After the decoded signal is logically ANDed with the write enable signal WTEN, a transmission gate control signal of the low voltage domain is obtained; since the voltage between BL and SL is a high voltage during the write operation, in order to ensure that the transmission gate can transmit the signal normally and avoid abnormal opening, the result of the logical AND operation needs to be transmitted to the level converter for voltage conversion to obtain a high voltage; the level converter outputs two levels, one high and one low, which are used as control signals for the transmission gate of the write column selection circuit; the write column selection circuit requires a total of 16 level converters;

[0019] The read column selection circuit includes a 4-16 decoder and 16 combinational logic units. Since the read operation is performed in the low voltage domain, the signal generated by the 4-16 decoder of ADDR<3:0> is logically ANDed with the read enable signal RDEN to directly generate the control signal of the gate of the transmission tube in the read column selection circuit. Therefore, the read column selection control circuit can achieve normal operation without an additional level converter.

[0020] The radiation-resistant key circuit design method based on magnetic random access memory of the present invention has the following advantages:

[0021] (1) The dual-mode redundant standard unit reinforcement method studied in this invention reduces the design complexity and area and power consumption while reducing circuit changes; the traditional three-mode redundant design will copy the unit module that needs to be reinforced three times and add a voting circuit, resulting in an increase of more than two times in area and power consumption, while the dual-mode redundant design avoids the soft errors that cannot be handled in the voting circuit by removing the voting structure, effectively saving area and power consumption while further reducing the probability of soft errors. Compared with the C-element reinforcement method, the dual-mode redundant structure does not need to be customized according to different irradiation environments, avoids the design complexity caused by adding latches at the input and output ends, and has higher reliability.

[0022] (2) The CMOS peripheral circuits studied in the present invention, including the control circuit, write drive circuit, word line decoding / driving circuit and column selection circuit, all have basic combinational logic units that use a dual-mode redundant standard cell reinforcement method, thereby filtering out glitches during signal transmission, resisting single-particle effects, and improving the reliability of MRAM in a radiation environment. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a principle comparison diagram of the existing three-mode redundant reinforcement method and the dual-mode redundant reinforcement method provided by the implementation of the present invention;

[0024] Figure 2 It is a structural diagram of a dual-mode redundancy reinforcement method provided by the embodiment of the present invention applied to an inverter circuit;

[0025] Figure 3 It is a state simulation curve of the particle impact phenomenon specifically solved by the present invention when different charge amounts are injected;

[0026] Figure 4 It is a schematic diagram for verifying the anti-radiation function of the inverter provided by the embodiment of the present invention;

[0027] Figure 5 It is a transient simulation diagram for verifying the anti-radiation function of the inverter provided by the implementation of the present invention;

[0028] Figure 6 It is a schematic diagram of the overall circuit layout provided by the implementation of the present invention;

[0029] Figure 7 is a schematic diagram of a write drive circuit provided by the present invention;

[0030] Figure 8 It is a schematic diagram of a decoder circuit and a word line driving circuit provided by the present invention;

[0031] Fig. 9 It is a schematic diagram of a read column selection circuit and a write column selection circuit provided by the present invention. DETAILED DESCRIPTION

[0032] In order to better understand the purpose, structure and function of the present invention, the following is a further detailed description of a key radiation-resistant circuit design based on a magnetic random access memory of the present invention in conjunction with the accompanying drawings.

[0033] The radiation-resistant key circuit based on magnetic random access memory described in the present invention includes a write drive circuit, a word line decoding / driving circuit and a column selection circuit. A method for strengthening the radiation-resistant standard combinational logic unit of a dual-mode redundant standard combinational logic unit is proposed to obtain a dual-mode redundant standard combinational logic unit. Therefore, the present invention uses radiation-resistant standard units to design the basic combinational logic unit of the peripheral key circuit, such as Figure 6 As shown. Figure 1 As shown in FIG. 1 , the dual-mode redundant standard combinational logic unit has two dual-input and dual-output redundant modules, namely two groups of logics including PMOS tubes and NMOS tubes, which are formed by cross-connections between different logics. Figure 7As shown, the write drive circuit includes a dual-mode redundant combinational logic gate circuit (including 2 RH inverters and 2 RH NOR gates) and 2 NMOS tubes and PMOS tubes fully cross-coupled level converters. The word line decoding circuit is an enabled 9-512 decoder, which is composed of a 4-16 decoder with enable and a 5-32 decoder through an RH AND gate, and the 5-32 decoder is obtained by a 3-8 decoder and a 2-4 decoder through an RH AND gate. The enabled 4-16 decoder is obtained by a non-enabled 4-16 decoder and the EN signal through a logical operation. As shown Figure 8 As shown in FIG. 1 , the word line driving circuit is composed of a level converter and a gate, and the gate circuit includes two level converters and two transmission gates. In the read column selection circuit, the control signal output by the read column selection control circuit is connected to the gate of the NMOS transmission tube in the sub-array. The read column selection control circuit includes a 4-16 decoder without enable and 16 RH AND gates. Fig. 9 As shown, in the write column select circuit, the write column select control circuit outputs two levels, one high and one low, formed by a level converter, which are connected to the gate of the transmission gate in the sub-array as a control signal. The write column select control circuit includes a 4-16 decoder, 16 RH AND gates and 16 level converters.

[0034] like Figure 1 As shown in the figure, compared with the traditional three-module redundant reinforcement method, the dual-module redundant standard combinational logic unit can make more use of the existing standard unit structure, reduce circuit changes, reduce design complexity, and improve reliability. Most importantly, since the three-module redundant reinforcement method will copy the circuit module that needs to be reinforced three times and add a voting circuit, this method will more than double the area and power consumption of a single reinforcement unit, so the dual-module redundant structure can save more area and power consumption. At the same time, the three-module redundant structure cannot handle soft errors that occur in the voting circuit, and since there is no voting circuit in the dual-module redundant structure, the probability of soft errors is further reduced.

[0035] The dual-mode redundant standard combinational logic unit is a dual-input dual-output structure. The PMOS tubes and NMOS tubes in different logics are cross-connected and connected to the same input and output terminals. The PMOS tubes and NMOS tubes in the same logic are not placed together, so as to prevent a single particle from knocking over the circuit of a unit at the same time and ensure the normal operation of the circuit. The invention establishes radiation-resistant standard units around 15 standard combinational logic unit circuits, including 4 dual-mode redundant inverters with different driving capabilities, 3 dual-mode redundant two-input NAND gates, 3 dual-mode redundant two-input NOR gates, 3 dual-mode redundant buffers, 1 dual-mode redundant three-input NAND gate and 1 dual-mode redundant XOR gate.

[0036] like Figure 2As shown, taking the inverter as an example, whether it is a traditional inverter or an inverter reinforced with dual-mode redundant radiation resistance, each output node is connected to a pull-up PMOS tube and a pull-down NMOS tube, but the gates of the pull-up tube and the pull-down tube of the traditional inverter are connected to the same input signal, while the pull-up tube and the pull-down tube input of the dual-mode redundant inverter are connected to different input signals IN1 and IN2, respectively, to achieve the separation of the control signal. Therefore, even if an input signal is affected by radiation, its instantaneous glitch wave will only last for a very short time, and the driving ability is not strong, while the unaffected signal maintains a stable strong drive, so it will not affect the final output result, and dual-mode redundant radiation resistance reinforcement is achieved.

[0037] The shape of the single-particle charge injection pulse satisfies the double exponential model. In order to simulate the circuit being affected by the single-particle transient effect, the common practice of single-particle simulation at the circuit level is to abstract the single-particle charge injection into a double exponential current source model, use a double exponential current source connected to the sensitive node to simulate the impact of the single-particle effect on the circuit sensitive node, and describe it in VerilogA language. Connecting the output of the double exponential current source to a sensitive node can simulate the node being hit by a particle. Figure 3 The double exponential current curves under different charge injection conditions are shown. As the charge amount increases, the current source peak value gradually increases.

[0038] The design of dual-mode redundant standard cells requires functional verification. Taking the inverter as an example, Figure 4 A buffer is built by connecting two dual-mode redundant inverters end to end. In normal operation, the two input terminals IN1 and IN2 are at the same level. In order to verify the radiation resistance function, reverse double exponential current injection is performed when the input is low and high to simulate the burrs in the combinational logic link. Figure 5 As shown, it can be seen that there is no level flip in the output after the two-stage inverter, but the potential value fluctuates slightly, indicating that the burr is eliminated in the process of forward propagation of the signal. It is also verified that other dual-mode redundant standard units can eliminate the burr in the propagation and have good radiation resistance.

[0039] like Figure 7The figure shows the schematic diagram of the write drive circuit, in which the combinational logic gate circuits are all reinforced with dual-mode redundancy. The WTEN signal is a control signal, and different BL and SL voltages are generated through WTEN to complete the data writing of a storage unit. In order to ensure that the data writing can be completed stably within a fixed time and improve the writing success rate, a high voltage of 1.8V is used to complete the writing operation. This voltage can not only shorten the writing time but also ensure that the MTJ is not broken down. A level converter is used to complete the switching from 0.9V to 1.8V voltage, and the switched high voltage is applied to the storage unit through the write column selection transmission gate. When writing data "0", the current flows from BL to SL, and when writing data "1", the current flows from SL to BL. For the level converter, when the IN signal is low, the ZN signal obtained by the low-voltage inverter is 0.9V, that is, the gate voltage of the N2 tube is 0.9V, so the N2 tube is turned on, and its drain is pulled to the ground. At this time, the P1 tube is turned on, and its drain is pulled to 1.8V, and then through the inverter composed of the P3 tube and the N3 tube, the output is 0V. When IN increases from 0V to 0.9V, the gate of the N2 tube decreases from 0.9V to 0V, the N1 tube is turned on, and the N2 tube is cut off, so that the drain of the N1 tube is pulled down from 1.8V to 0V, and then the drain voltage of the N1 tube decreases, so that the drain-source voltage of the P1 tube increases from 0, and quickly enters the linear area from the deep linear area. The P1 tube that enters the linear area has current, and the N1 tube that enters the saturation area also has current. Since the width-to-length ratio of the NMOS tube in the design is greater than that of the PMOS tube, the saturation region current of the N1 tube is greater than the linear region current of the P1 tube, so that the drain potential of the N1 tube is successfully pulled down in the competition with the P1 tube, and continuously discharges from VDDH to the ground.

[0040] like Figure 8 The schematic diagram of the decoder circuit and the word line driver circuit is shown, in which all combinational logic gate circuits also use a dual-mode redundant structure to block the propagation of glitches in the circuit. When the array performs read and write operations and the enable end EN signal is high, the decoder works normally, determines the voltage of each word line, and selects the corresponding word line. When no read and write operations are performed, the enable end EN signal is low, the output of the decoder is all zero, and all word lines are grounded. After the word line voltage in the low voltage domain is obtained by the 9-512 decoder with enable, each word line voltage enters its own word line driver circuit. In the word line driver circuit, the word line voltage is divided into two paths, one is the low voltage domain voltage, and the other is converted to the high voltage domain through the level converter. The two voltages are connected to the selector, and different voltages are selected to the word line through the read and write enable signal.

[0041] like Fig. 9The following figure shows the read column selection circuit and the write column selection circuit, in which all gate circuits are designed with radiation-resistant standard cells reinforced with dual-mode redundancy. In the write column selection control circuit, the lower four-bit address signal ADDR<3:0> generates a signal through a 4-16 decoder to select a specific BL and SL. After the decoded signal is logically ANDed with the write enable signal WTEN, a transmission gate control signal in the low voltage domain is obtained. The signal is transmitted to the level converter for voltage conversion and outputs two levels, one high and one low, which are used as control signals for the transmission gate in the write column selection circuit. In the read column selection control circuit, the read operation is performed in the low voltage domain. The signal obtained after the decoded signal ADDR<3:0> is ANDed with the read enable signal RDEN is the gate control signal of the transmission tube in the read column selection circuit.

[0042] It is to be understood that the present invention is described by some embodiments, and it is known to those skilled in the art that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. In addition, under the teachings of the present invention, these features and embodiments may be modified to adapt to specific circumstances and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the scope of protection of the present invention.

Claims

1. A method for designing radiation-resistant key circuits based on magnetic random access memory, characterized in that: For the peripheral circuits including write drive circuit, word line decoding and drive circuit and column selection circuit, a dual-mode redundant standard combinational logic unit radiation hardening RH method is proposed for the basic combinational logic unit; after the basic combinational logic unit circuit is hardened, a standard combinational logic unit with standardized design is obtained, and a radiation-resistant standard cell library is established around 15 standard combinational logic unit circuits, and the standard combinational logic units in the radiation-resistant standard cell library are used in the peripheral circuit design; The standard combinational logic unit circuit obtained by the dual-mode redundant standard combinational logic unit anti-radiation reinforcement RH method is to replicate the combinational logic unit circuit module that needs to be reinforced twice, and cross-connect the PMOS tubes and NMOS tubes between different logics in the combinational logic unit circuit. The reinforced circuit is a dual-input dual-output structure to prevent a single particle from overturning the circuit of a combinational logic unit at the same time; The peripheral circuit generates a read enable signal RDEN and a write enable signal WTEN by inputting a WEB signal, thereby controlling the switching of the read operation and the write operation; in the design, every 16 rows of bit lines BL and source lines SL reuse a set of read and write circuits, which are defined as a sub-array. A complete 256Kb storage array has 32 sub-arrays, and 32 bits of data are read and written simultaneously each time, so the input data DIN and the output data DOUT are both 32 bits; the input data DIN is sent to the write drive circuit, and then connected to the WBL and WSL of the write column selection circuit; the address signal ADDR has a total of 13 bits, of which the lower four-bit address signal ADDR<3:0> is sent to the read column selection circuit or the write column selection circuit to select the columns of BL and SL; the upper nine-bit address signal ADDR<12:4> is used to generate a 512-bit word line WL signal, and different operating voltages are selected to work according to the RDEN and WTEN signals generated by the word line decoding and driving circuit.

2. The method for designing a radiation-resistant key circuit based on a magnetic random access memory according to claim 1, characterized in that: The write drive circuit includes a combinational logic gate circuit and a level converter, wherein all the combinational logic units adopt a radiation-resistant standard unit library; the input signal Din and the inverted signal obtained through the RH inverter are respectively sent to the level converter through the RH or-not gate, and then connected to the WBL and WSL of the write column selection circuit; the other input of the two RH or-not gates is the WTEN signal through the RH inverter; the WTEN signal is a control signal, and different BL and SL voltages are generated through WTEN to complete the data writing of a storage unit; the voltage switching from 0.9V to 1.8V is completed through the level converter, and the high voltage after switching is applied to the storage unit through the write column selection transmission gate; The transistors in the level converter are all high-voltage resistant IO tubes. The signal ZN is obtained by input through a VDDL low-voltage inverter, and the signal IN is obtained by ZN through another VDDL low-voltage inverter. The level converter circuit adopts a fully cross-coupled structure of NMOS tubes and PMOS tubes to reduce static leakage current.

3. The method for designing a radiation-resistant key circuit based on a magnetic random access memory according to claim 1, characterized in that: In the decoding and word line driving circuits, all the combinational logic cells use radiation-resistant standard cell libraries to block the propagation of glitches in the circuits. The decoding and word line driving circuits first obtain the WL voltage in the low voltage domain from a 9-512 decoder with enable EN, and then each WL voltage enters its own word line driving circuit. The 9-512 decoder with enable EN is obtained by performing an AND operation on a 4-16 decoder with an enable signal EN and a 5-32 decoder, requiring a total of 512 RH logic AND gates, and the 5-32 decoder is obtained by performing an AND operation on a 3-8 decoder and a 2-4 decoder, requiring a total of 32 RH logic AND gates; the 4-16 decoder with enable signal EN is obtained by performing a logical operation on a 4-16 decoder without enable and the EN signal; during the read and write operation of the array, the enable end EN signal is at a high level, and the decoder works normally; when no read and write operation is performed, the enable end EN signal is at a low level, and the output of the decoder is all zero; The word line driving circuit is composed of a level converter and a gate. Due to the different voltage domains of read and write operations, the circuit divides the WL voltage into two paths, one of which is a low voltage domain voltage, and the other is converted to a high voltage domain through a level converter. The two voltages are connected to the gate circuit, and different voltages are gated to WL through read and write enable signals; In the gate circuit, in order to prevent the 1.8V voltage on WL from turning on the transmission tube during the write operation, the control signals WTEN and RDEN of the transmission tube must be converted to the high voltage domain by a level converter and then connected to the gate of the transmission gate; in order to prevent the transmission gate from being broken down by an excessively high write voltage, the transistors in the transmission gate must use high-voltage-resistant IO tubes.

4. The method for designing a radiation-resistant key circuit based on a magnetic random access memory according to claim 1, characterized in that: In the column selection circuit including the write column selection circuit and the read column selection circuit, all the combinational logic units therein adopt the radiation-resistant standard cell library; the circuit selects a group of BL and SL from 16 BL and SL, and sends them to the corresponding write circuit through the transmission gate during the write operation, and sends them to the corresponding read circuit through the NMOS transmission tube during the read operation; In the write column selection circuit, the lower four bits of the address ADDR<3:0> are connected to the 4-16 decoder to select BL and SL, and the decoded signal is logically ANDed with the write enable signal WTEN to obtain a transmission gate control signal of the low voltage domain; the result after the logical AND operation is connected to the level converter; the output result of the level converter is two levels, one high and one low, which are used as the gate control signal of the transmission gate in the write column selection circuit, and a total of 16 level conversion circuits are required; The read column selection circuit includes a 4-16 decoder and 16 combinational logic units. Since the read operation is performed in the low voltage domain, the signal obtained by performing a logic AND operation between the decoded signal ADDR<3:0> and the read enable signal RDEN is the gate control signal of the transmission tube in the read column selection circuit.

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