Automatic layout method for electronic components of circuit board

Abstract

The invention provides an automatic layout method for electronic components of a circuit board, and the method comprises the steps: exporting functional modules in a schematic circuit diagram into an independent circuit netlist, carrying out the layout modeling of the components through employing a single-layer binary tree structure, and carrying out the layout modeling of the whole circuit based on a multi-layer binary tree structure. Therefore, a multi-layer nested binary tree structure is formed. An optimization algorithm is combined with a heuristic strategy, and circuit performance parameters such as wire length, layout area and signal integrity are used as optimization targets to carry out iterative optimization on the layout model. And automatically generating a detailed layout scheme of the circuit board according to the optimized layout model. Before layout, preprocessing of a schematic circuit diagram is carried out, after layout, verification of a layout scheme is carried out, and it is ensured that all design constraints are met. The circuit board design efficiency and quality can be remarkably improved, the workload of manual adjustment is reduced, the risk of design reworking is reduced, and the automatic design level is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic components of a circuit board, and more specifically, to an automatic layout method of electronic components of a circuit board. Background Art

[0002] The layout of electronic components on a circuit board is an important part of electronic design automation (EDA). As electronic devices develop towards miniaturization, high performance and multi-functionality, the density of components on circuit boards continues to increase, causing layout design to become increasingly complex. Traditional manual layout methods are not only inefficient, but also difficult to meet the requirements of modern circuit boards for accuracy and performance. Therefore, automated layout methods have become the key to solving this problem.

[0003] Among the existing automated layout methods, many technologies rely on fixed algorithms and heuristic rules. These methods often lack flexibility and are difficult to adapt to circuit board designs of different types and complexities. In addition, when dealing with high-density circuit boards, these methods often fail to fully consider the interaction between components and the requirements of circuit performance, resulting in limited optimization space for layout solutions.

[0004] In order to improve the level of automation and optimization quality of layout, it is necessary to develop a new layout method that can better simulate the actual physical characteristics and electrical performance requirements of the circuit board while being flexible enough to adapt to different design needs. Summary of the invention

[0005] The present invention provides a method for automatic layout of electronic components of a circuit board, aiming to solve the limitations of the prior art and achieve more efficient and accurate automatic layout.

[0006] A method for automatically placing electronic components on a circuit board, the method comprising the following steps:

[0007] Export each functional module in the circuit schematic diagram as an independent circuit netlist;

[0008] Layout modeling is performed for each group of components based on a single-level binary tree structure, and a single-level binary tree with the same number of nodes as the number of components is generated for each group of components, where each node represents an actual component;

[0009] The layout modeling of the entire circuit is performed based on a multi-level binary tree structure. A multi-level binary tree with the same number of nodes as the number of groups is generated according to the grouping result of the circuit netlist. Each node represents a group of components. The single-level binary tree is nested in the corresponding node of the multi-level binary tree to form a multi-level nested binary tree structure.

[0010] An optimization algorithm combined with a heuristic strategy is used to iteratively optimize the layout model based on circuit performance parameters;

[0011] Automatically generate a detailed layout plan for the circuit board based on the optimized layout model.

[0012] As a further improvement of the present application, each functional module in the circuit schematic diagram is exported as an independent circuit netlist, including:

[0013] Identify functional modules in circuit schematics;

[0014] According to the connection relationship of the functional modules, the related components are allocated to the corresponding circuit netlist.

[0015] As a further improvement of the present application, layout modeling is performed for each group of components based on a single-level binary tree structure, and a single-level binary tree with the same number of nodes as the number of components is generated for each group of components, where each node represents an actual component including:

[0016] Assign a unique identifier to each component;

[0017] Determine the level and position of nodes in a single-level binary tree based on the electrical characteristics and physical size of the components.

[0018] As a further improvement of the present application, the layout modeling of the entire circuit is performed based on a multi-level binary tree structure, and a multi-level binary tree with a number of nodes equal to the number of groups is generated according to the grouping result of the circuit netlist, including:

[0019] Assigning a unique group identifier to each circuit netlist;

[0020] According to the electrical characteristics and physical size of the circuit netlist, the level and position of the nodes in the multi-level binary tree are determined.

[0021] As a further improvement of the present application, an optimization algorithm combined with a heuristic strategy is used to iteratively optimize the layout model with circuit performance parameters, including:

[0022] Define the evaluation function of the optimization algorithm, which includes line length, layout area and signal integrity;

[0023] Each possible layout solution is scored using an evaluation function;

[0024] The layout solution with the highest score is selected as the optimized layout model.

[0025] As a further improvement of the present application, the detailed layout scheme of the circuit board is automatically generated according to the optimized layout model, including:

[0026] Convert the optimized layout model into a physical layout of the circuit board;

[0027] Generate a layout drawing of the circuit board, including the location coordinates of the components and the paths of the connecting lines.

[0028] As a further improvement of the present application, the optimization algorithm includes a particle swarm optimization algorithm, including:

[0029] Initialize the particle swarm, each particle represents a layout plan;

[0030] Iteratively search for the optimal layout solution through the particle swarm optimization algorithm;

[0031] Update the particle's position and velocity until the preset number of iterations is reached or the optimization goal is met.

[0032] As a further improvement of the present application, the layout modeling of each group of components based on a single-level binary tree structure further includes:

[0033] For each component, determine its branching strategy in a single-level binary tree according to its electrical characteristics and physical size;

[0034] According to the electrical connection relationship between components, the connection mode of nodes in a single-level binary tree is adjusted.

[0035] As a further improvement of the present application, the layout modeling of the entire circuit based on the multi-level binary tree structure also includes:

[0036] For each circuit netlist, determine its position in the multi-level binary tree according to its electrical characteristics and physical size;

[0037] According to the electrical connection relationship between the circuit netlists, the connection mode of the nodes in the multi-level binary tree is adjusted.

[0038] As a further improvement of the present application, before exporting each functional module in the circuit schematic diagram into an independent circuit netlist, it also includes: preprocessing the circuit schematic diagram, including removing non-electrical elements and standardized component symbols;

[0039] After automatically generating a detailed layout plan of the circuit board according to the optimized layout model, the method also includes: verifying the layout plan to ensure that the layout plan meets all constraints of the circuit design.

[0040] The above embodiments of the present invention have at least the following beneficial effects:

[0041] The circuit board electronic component automatic layout method of the present invention effectively represents the complex relationship between circuit components by introducing a multi-level binary tree structure, thereby improving the accuracy of layout modeling. This method can not only handle the layout problem of high-density circuit boards, but also adapt to circuit board designs of different scales and complexities, and has high flexibility and adaptability.

[0042] By combining optimization algorithms and heuristic strategies, the method of the present invention can automatically search and optimize layout solutions under the guidance of multiple circuit performance parameters. This not only improves the efficiency of layout, but also ensures the quality of the layout solution and the performance of the circuit board, and reduces the possibility of design rework.

[0043] In addition, the method of the present invention also includes the steps of preprocessing the circuit schematic and verifying the layout scheme, which further improves the accuracy and reliability of the layout. Through automated preprocessing and verification, designers can focus more on design innovation and optimization rather than tedious manual adjustment work, thereby greatly improving design efficiency and product quality. In general, the present invention provides an innovative automated layout method, which not only improves the efficiency and quality of circuit board design, but also brings new development opportunities to the field of electronic design automation. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The above and other objects, features and advantages of the exemplary embodiments of the present invention will become readily understood by reading the detailed description below with reference to the accompanying drawings. In the accompanying drawings, several embodiments of the present invention are shown in an exemplary and non-limiting manner, in which:

[0045] Figure 1 A schematic diagram of a flow chart of a method for automatic layout of electronic components of a circuit board provided by an embodiment of the present invention;

[0046] Figure 2 A schematic diagram of a layout data structure provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0047] The principles and spirit of the present invention will be described below with reference to several exemplary embodiments. It should be understood that these embodiments are provided only to enable those skilled in the art to better understand and implement the present invention, and are not intended to limit the scope of the present invention in any way. On the contrary, these embodiments are provided to make the present invention more thorough and complete, and to fully convey the scope of the present invention to those skilled in the art.

[0048] Those skilled in the art know that the embodiments of the present invention can be implemented as a system, device, apparatus, method or computer program product. Therefore, the present invention can be specifically implemented in the following forms, namely: complete hardware, complete software (including firmware, resident software, microcode, etc.), or a combination of hardware and software.

[0049] It should be noted that any number of elements in the drawings is for illustration rather than limitation, and any naming is only for distinction and does not have any limiting meaning.

[0050] Reference below Figure 1 , Figure 1 FIG. 1 is a flow chart of a method for automatically placing electronic components on a circuit board according to the present invention. Figure 1 As shown, a method for automatic layout of electronic components of a circuit board comprises the following steps:

[0051] Export each functional module in the circuit schematic diagram as an independent circuit netlist;

[0052] Layout modeling is performed for each group of components based on a single-level binary tree structure, and a single-level binary tree with the same number of nodes as the number of components is generated for each group of components, where each node represents an actual component;

[0053] The layout modeling of the entire circuit is performed based on a multi-level binary tree structure. A multi-level binary tree with the same number of nodes as the number of groups is generated according to the grouping result of the circuit netlist. Each node represents a group of components. The single-level binary tree is nested in the corresponding node of the multi-level binary tree to form a multi-level nested binary tree structure.

[0054] An optimization algorithm combined with a heuristic strategy is used to iteratively optimize the layout model based on circuit performance parameters;

[0055] Automatically generate a detailed layout plan for the circuit board based on the optimized layout model.

[0056] It should be noted that this embodiment is intended to describe in detail the specific steps of a method for automatic layout of electronic components of a circuit board, which involves exporting the functional modules of a circuit schematic diagram into a circuit netlist and using a binary tree structure to model the component layout. The circuit schematic diagram refers to a diagram describing circuit components and their connection relationships, and the circuit netlist is a tabular representation of the connection relationship of components in the circuit schematic diagram.

[0057] Specifically, in this embodiment, it is first necessary to identify each functional module in the circuit schematic, which can be done automatically by circuit design software or manually by a designer. The components in each functional module will be assigned to a corresponding circuit netlist according to their electrical connection relationship. The circuit netlist can be generated using existing EDA tools, such as Cadence or Altium Designer.

[0058] Preferably, the export of the circuit schematic can be automated using a scripting language to improve efficiency. When allocating components, priority parameters can be set to ensure that key components are allocated to the corresponding circuit netlist first. In addition, the generation of the circuit netlist can also be optimized according to the electrical characteristics and physical dimensions of the components to meet different design requirements.

[0059] Component layout modeling based on a single-level binary tree structure refers to using a single-level binary tree data structure to represent the layout relationship of each group of components. The single-level binary tree is a special tree structure, and each node has at most two child nodes.

[0060] Each component in a single-level binary tree will be assigned a unique identifier, which can be the component's model, number or other unique identification information. The level and position of the node will be determined based on the component's electrical characteristics and physical size to ensure the rationality of the component layout and the optimization of circuit performance.

[0061] The construction of a single-level binary tree can be done in a bottom-up manner, that is, a node is created for each component first, and then these nodes are arranged hierarchically according to the electrical connection relationship and physical layout requirements. The hierarchy and position of the nodes can be automatically determined by the algorithm, or manually adjusted by the designer based on experience.

[0062] The multi-level binary tree structure is used to model the layout of the entire circuit, which is an innovation of this method. By nesting a single-level binary tree in a multi-level binary tree, the relative positions and connection relationships between components can be more accurately represented.

[0063] The construction of a multi-level binary tree starts with the grouping results of the circuit netlist, and each group corresponds to a node of the multi-level binary tree. Each node represents a group of components, and the child nodes of the node are single-level binary trees composed of these components. Such a structure can be recursively constructed until all components are included in the multi-level binary tree.

[0064] Preferably, layout constraints can be introduced during the construction of the multi-level binary tree, such as the minimum distance between components, the direction of signal lines, etc. These constraints can be used as input parameters of the optimization algorithm to ensure that the final layout solution meets the design requirements. In addition, the structure of the multi-level binary tree can also be adjusted according to the complexity of the circuit and the design requirements to achieve a better layout effect.

[0065] It should be noted that the optimization algorithm is combined with the heuristic strategy to iteratively optimize the layout model, which is a key step to ensure the quality of the layout solution. The optimization algorithm can adopt a variety of strategies, such as genetic algorithm, simulated annealing algorithm or particle swarm optimization algorithm.

[0066] Specifically, the evaluation function of the optimization algorithm can include circuit performance parameters such as line length, layout area and signal integrity. These parameters will be quantified into numerical values ​​to facilitate calculation and comparison by the algorithm. For example, line length can be expressed as the weighted sum of the total length of all connecting lines, layout area can be expressed as the total area of ​​the circuit board occupied by components, and signal integrity can be evaluated by the impedance matching of the signal line and the degree of signal interference.

[0067] During the iteration of the optimization algorithm, each layout solution will be scored according to the evaluation function. The solution with a higher score is considered to be a better layout solution. The algorithm will gradually approach the optimal solution through iterative search. During the iteration process, a fitness value error threshold can be set. When the difference between the score of the current optimal solution and the score of the global optimal solution is less than the threshold, the algorithm can stop iterating. This can improve the efficiency of the algorithm while ensuring the quality of the solution.

[0068] The goal of this method is to automatically generate a detailed layout plan for the circuit board based on the optimized layout model, and convert the optimized layout model into an actual circuit board layout, including the location coordinates of the components and the paths of the connecting lines.

[0069] The conversion of the layout model can be achieved through computer-aided design (CAD) software. In this process, the position coordinates of the components will be accurately determined to facilitate the subsequent circuit board manufacturing. At the same time, the path of the connection line will also be optimized to reduce the line length, avoid signal interference and meet the circuit performance requirements.

[0070] Preferably, the generated layout drawings include detailed location information of components, detailed paths of connecting lines, and necessary design parameters. This information can be stored in the form of vector graphics for further editing and modification. In addition, the layout drawings can also be output in different formats as needed, such as DWG, DXF or Gerber files, etc., to adapt to different manufacturing processes and equipment requirements.

[0071] In some embodiments, exporting each functional module in the circuit schematic diagram into an independent circuit netlist includes:

[0072] Identify functional modules in circuit schematics;

[0073] According to the connection relationship of the functional modules, the related components are allocated to the corresponding circuit netlist.

[0074] Specifically, EDA tools can be used to identify functional modules in circuit schematics, which is done through the software's built-in automatic recognition algorithm, which identifies modules based on the type of components, how they are connected, and their role in the circuit. For example, an amplifier module may include a transistor, several resistors, and capacitors, which are connected together in a specific way. The recognition process can also be combined with manual adjustments by designers. After automatic recognition, designers can check the recognition results and make corrections as needed to ensure the accuracy and completeness of the module. In addition, for complex or non-standard circuit designs, designers may need to manually define functional modules.

[0075] After the functional modules are identified, the related components are assigned to the corresponding circuit netlist according to the connection relationship of these modules. The assignment process can be achieved by analyzing the connection between components. For example, if a resistor and a transistor are connected in the circuit schematic, they will be assigned to the same circuit netlist. This process can be done automatically by algorithms or manually by designers.

[0076] The allocation process can also take into account the electrical characteristics of the components, such as resistance values, capacitance values, etc. For example, components with similar electrical characteristics may be allocated to the same or different circuit netlists, depending on their role and connection relationship in the circuit. In addition, the allocation process can also be optimized according to design requirements and manufacturing constraints to ensure that the generated circuit netlist not only meets the design requirements, but also facilitates subsequent layout and manufacturing.

[0077] Preprocessing steps include removing non-electrical elements from the schematic, such as comments, borders, etc., and standardizing component symbols to ensure that they meet the requirements of EDA tools. These steps help reduce errors and ambiguities in subsequent processing.

[0078] Preprocessing can also include topological sorting of the circuit schematic to ensure that components and connections are arranged in a logical order. This helps improve the efficiency and accuracy of subsequent circuit netlist generation. In addition, the preprocessing step can also optimize the circuit schematic according to design requirements and manufacturing constraints to ensure that the generated circuit netlist not only meets the design requirements, but also facilitates subsequent layout and manufacturing.

[0079] In some embodiments, layout modeling is performed for each group of components based on a single-level binary tree structure, and a single-level binary tree having the same number of nodes as the number of components is generated for each group of components, where each node represents an actual component and includes:

[0080] Assign a unique identifier to each component;

[0081] Determine the level and position of nodes in a single-level binary tree based on the electrical characteristics and physical size of the components.

[0082] It should be noted that the process of modeling the layout of each group of components based on a single-level binary tree structure includes assigning a unique identifier to each component and determining the level and position of the nodes in the binary tree according to the electrical characteristics and physical size of the component. In this process, the single-level binary tree structure, except for the root node, each node has only one child node, which is used to simplify the complexity of the layout and improve the efficiency of modeling.

[0083] First, a unique identifier is assigned to each component. This can be done with an automated tool, where the tool goes through all the components in the circuit netlist and generates a unique identifier for each component based on its attributes, such as model, parameters, or function. For example, a resistor might be assigned an identifier of "R123," where "R" indicates that it is a resistor and "123" is its unique serial number.

[0084] Preferably, the generation of a unique identifier can be combined with the type and properties of the component to ensure consistency and traceability in circuit design. For example, the identifier can include the resistance, capacitance or other key parameters of the component to facilitate rapid identification of the component in subsequent circuit analysis and testing.

[0085] After determining the unique identifier of each component, the next step is to determine their level and position in a single-level binary tree based on the electrical characteristics and physical dimensions of the components. This step is to ensure that the layout of the components not only meets the electrical requirements of the circuit, but also takes into account the actual physical limitations. The electrical characteristics of the component include its operating voltage, current capacity, and signal frequency, while the physical dimensions involve the size, shape, and mounting requirements of the component. For example, a high-power resistor may need to be placed at the edge of the circuit board to facilitate heat dissipation, while a high-frequency capacitor may need to be placed as close as possible to its associated amplifier to reduce parasitic effects.

[0086] More specifically, the level and position of nodes in the binary tree can be automatically determined by an algorithm that takes into account the electrical connection relationship between components and the physical layout requirements. For example, an algorithm may place all components that need to be closely connected on the same branch or adjacent branches, while placing those components that are relatively independent electrically on different branches. In addition, the algorithm can also optimize the spatial arrangement of components on the circuit board based on their physical size and shape to achieve the best layout density and performance.

[0087] In some embodiments, the entire circuit is layout modeled based on a multi-level binary tree structure, and generating a multi-level binary tree with a number of nodes equal to the number of groups according to the grouping result of the circuit netlist includes:

[0088] Assigning a unique group identifier to each circuit netlist;

[0089] According to the electrical characteristics and physical size of the circuit netlist, the level and position of the nodes in the multi-level binary tree are determined.

[0090] Each node of the multi-level binary tree can have multiple child nodes, which are used to represent the hierarchical relationship and layout position of the components in the circuit. Assigning a unique group identifier to each circuit netlist can be done by an automated tool, where the tool traverses all circuit netlists and generates a unique identifier for each netlist based on its attributes (such as functional module, circuit type, or design parameters). For example, a circuit netlist for a power management module may be assigned an identifier "PM123", where "PM" indicates that it is a power management module, and "123" is its unique serial number.

[0091] The level and position of nodes in a multi-level binary tree can be automatically determined by an algorithm that takes into account the electrical connection relationship and physical layout requirements between circuit netlists. For example, an algorithm may place all netlists that need to be closely connected on the same branch or adjacent branches, while placing those relatively electrically independent netlists on different branches. In addition, the algorithm can also optimize their spatial arrangement on the circuit board based on the physical size and shape of the netlists to achieve the best layout density and performance.

[0092] In some embodiments, using an optimization algorithm combined with a heuristic strategy to iteratively optimize a layout model using circuit performance parameters includes:

[0093] Define the evaluation function of the optimization algorithm, which includes line length, layout area and signal integrity;

[0094] Each possible layout solution is scored using an evaluation function;

[0095] The layout solution with the highest score is selected as the optimized layout model.

[0096] The optimization direction is guided by circuit performance parameters to ensure that the final layout solution is optimal in both electrical performance and physical layout. The optimization algorithm is used to find the best solution under given parameters and constraints. The heuristic strategy refers to the use of experience and intuition to guide the search process to improve optimization efficiency.

[0097] First, define an evaluation function for the optimization algorithm, which will comprehensively consider circuit performance parameters such as line length, layout area, and signal integrity. The purpose of the evaluation function is to quantify the pros and cons of the layout scheme and provide evaluation criteria for the optimization algorithm. For example, line length can be used as an indicator to evaluate the complexity of circuit board wiring, layout area is related to the space utilization of the circuit board, and signal integrity involves the electromagnetic compatibility and signal quality of the circuit.

[0098] The evaluation function can be designed as a weighted sum, where each performance parameter is assigned a weight to reflect its importance in the overall optimization goal. The choice of weights can be based on design requirements, circuit type, or expected application scenarios. For example, for a high-frequency circuit that focuses on signal quality, the weight of signal integrity may be set higher.

[0099] Exemplarily, the evaluation function is shown in the following formula.

[0100] f(s)=w1·L(s)+w2·A(s)+w3·I(s);

[0101] Among them, L(s) represents the total length of all connecting lines in the layout scheme, reflecting the complexity of wiring and potential signal transmission delay; A(s) represents the circuit board area occupied by the layout scheme, reflecting the space utilization. I(s) represents the signal integrity of the layout scheme, which can be evaluated by indicators such as impedance matching of signal lines and signal interference level. w1, w2, and w3 are weight coefficients, which reflect the relative importance of different performance parameters in the overall optimization goal. The choice of weight coefficients can be determined according to specific design requirements and circuit characteristics.

[0102] More specifically,

[0103]

[0104]

[0105]

[0106] Among them, d i，j represents the length of the connecting line between element i and element j, and n is the total number of connecting line segments. k represents the area occupied by the kth component, and m is the total number of components. p represents the quantitative value of the pth signal integrity factor, and q is the total number of factors. This formula uses a penalty term to reduce the score of the layout solution when there is a signal integrity problem.

[0107] It should be noted that after scoring each possible layout solution through the evaluation function, the optimization algorithm will select the layout solution with the highest score as the optimized layout model. In each iteration of the algorithm, the layout solution is updated according to the result of the evaluation function, gradually approaching the optimal solution.

[0108] The optimization process can adopt a variety of strategies, such as genetic algorithms, simulated annealing algorithms or particle swarm optimization algorithms, which can effectively find the optimal solution in a complex search space. In each iteration, the algorithm generates a new layout plan, calculates its evaluation function value, and decides whether to accept the new plan based on this value.

[0109] Preferably, the optimization algorithm can include some specific operations to improve the search efficiency, for example, adopting a strategy combining local search and global search, or introducing randomness to avoid falling into a local optimal solution. In addition, the algorithm can also set some stop conditions, such as reaching a preset number of iterations, the improvement of the evaluation function value is lower than a certain threshold, or reaching a predetermined calculation time limit, to ensure that the optimization process is completed within a reasonable time. Through these measures, the optimization algorithm can balance the breadth and depth of the search, and finally find a layout solution that meets the circuit performance requirements and has high feasibility.

[0110] In some embodiments, automatically generating a detailed layout solution of a circuit board according to the optimized layout model includes:

[0111] Convert the optimized layout model into a physical layout of the circuit board;

[0112] Generate a layout drawing of the circuit board, including the location coordinates of the components and the paths of the connecting lines.

[0113] Automatically generating a detailed layout plan for a circuit board based on the optimized layout model includes converting the optimized layout model into a physical layout of the circuit board and generating a layout drawing of the circuit board, which contains the position coordinates of the components and the paths of the connecting lines. The physical layout refers to the actual placement of the components on the circuit board, and the layout drawing is a visual representation of these placements and connecting lines.

[0114] Specifically, converting the optimized layout model into the physical layout of the circuit board can be accomplished by an automated layout generation tool, which determines the exact placement of each component on the circuit board based on the component positions and connection relationships in the optimized model. For example, the tool may automatically calculate the coordinates of the component on the circuit board based on its size and shape, while taking into account layout constraints such as minimum spacing requirements and signal line directions.

[0115] The generation of the physical layout can use adaptive algorithms that dynamically adjust the placement of components based on the size and shape of the board to maximize space utilization and meet design requirements. For example, the algorithm may identify space-constrained areas on the board and adjust component placement accordingly to avoid conflicts and ensure layout feasibility.

[0116] After the physical layout is generated, a layout drawing of the board is generated to create a detailed visual representation of the location of all components on the board and the paths of the connecting lines. The layout drawing usually includes the precise coordinates of the components, the width and number of layers of the connecting lines, and any necessary design parameters.

[0117] Specifically, the generation of layout drawings can be done through computer-aided design (CAD) software, which can create an accurate circuit board layout based on physical layout data. This drawing can be exported in multiple formats, such as DWG, DXF or Gerber files, to facilitate the use of different manufacturing processes and equipment.

[0118] Layout drawings can also include additional design information, such as component values, model numbers, and manufacturer information, as well as the board's layer stackup and material specifications. This information is critical to the manufacture and testing of circuit boards, improving production efficiency and ensuring the quality of the final product.

[0119] In addition, the generated layout drawings can be further reviewed and verified to ensure that they meet all design requirements and manufacturing standards. This may include simulation analysis of the electrical performance of the layout, as well as detailed inspection of the physical characteristics of the layout to identify any potential problems or room for improvement. Through these measures, it can be ensured that the generated circuit board layout solution not only meets the design requirements, but also has high production feasibility.

[0120] In some embodiments, the optimization algorithm comprises a particle swarm optimization algorithm, comprising:

[0121] Initialize the particle swarm, each particle represents a layout plan;

[0122] Iteratively search for the optimal layout solution through the particle swarm optimization algorithm;

[0123] Update the particle's position and velocity until the preset number of iterations is reached or the optimization goal is met.

[0124] Particle Swarm Optimization (PSO) is a computational method that simulates the social behavior of a flock of birds or a school of fish to find the optimal solution. In this embodiment, the iterative process of the PSO algorithm is used to search for the optimal circuit board layout solution.

[0125] Specifically, a particle swarm is initialized, where each particle represents a possible layout solution. Each particle has a random position and velocity in the search space, and these parameters correspond to the position and possible adjustments of components in the layout solution. For example, the position of a particle can be represented as a set of component coordinates, and the velocity can be represented as the adjustment of these coordinates.

[0126] Preferably, the initialization of the particle swarm can be done by random generation or based on some heuristic rules. For example, an initial layout scheme can be generated based on the electrical characteristics and physical dimensions of the components, and then a particle swarm is generated based on this. In addition, the number of particles and the dimension of the search space can be determined according to the complexity of the problem and the computing resources.

[0127] It should be noted that after initializing the particle swarm, the next step is to iteratively search for the optimal layout solution through the particle swarm optimization algorithm. In each iteration, each particle updates its position and velocity based on its own experience and the experience of the group. The experience of a particle is usually guided by the optimal solution it finds (individual optimality), while the experience of the group is guided by the optimal solution found among all particles (global optimality).

[0128] Specifically, the particle update rule can be expressed as:

[0129] v i (t+1)=w·v i (t)+c1·r1·(p i -x i (t))+c2·r2·(p g -x i (t))[x i (t+1)

[0130] =x i (t)+v i (t+1)

[0131] in:

[0132] v i (t) is the velocity of particle i at time t.

[0133] x i (t) is the position of particle i at time t.

[0134] w is the inertia weight, which controls the degree of updating of particle velocity.

[0135] c1 and c2 are learning factors that control the degree to which the particle responds to the individual optimum and the global optimum, respectively.

[0136] r1 and r2 are random numbers used to increase the randomness of the search process.

[0137] p i is the individual optimal position of particle i.

[0138] p g is the global optimal position of the group.

[0139] The update of particles can optimize the search process by adjusting the algorithm parameters. For example, the inertia weight w, learning factors c1 and c2 can be dynamically adjusted to balance the global and local nature of the search. In addition, some constraint processing mechanisms such as Penalty functions or boundary processing strategies can be introduced to ensure that the update of particles does not exceed the predetermined search space.

[0140] During the iteration process, the position and velocity of each particle are continuously updated until the preset number of iterations is reached or the optimization goal is met. This can be achieved by setting a fitness function that evaluates the quality of the layout solution represented by each particle. When the fitness values ​​of all particles in the particle swarm do not improve significantly in consecutive iterations, it can be considered that the algorithm has converged to the optimal solution or close to the optimal solution.

[0141] Through the iterative search process of the particle swarm optimization algorithm, the optimal or near-optimal circuit board layout solution can be effectively found in a complex layout space, thereby improving the automation level and optimization quality of the layout.

[0142] In some embodiments, performing layout modeling for each group of components based on a single-level binary tree structure further includes:

[0143] For each component, determine its branching strategy in a single-level binary tree according to its electrical characteristics and physical size;

[0144] According to the electrical connection relationship between components, the connection mode of nodes in a single-level binary tree is adjusted.

[0145] Detailed analysis of the electrical characteristics and physical dimensions of each component, including the component's operating voltage, current capacity, signal frequency, resistance, capacitance, inductance, and the size, shape, and installation requirements of the component. This information can be obtained from the component's data sheet or automatically imported through circuit design software.

[0146] Preferably, the electrical characteristics and physical size information of the component will be used to determine its branching strategy in a single-level binary tree. For example, high-power or high-heat components may require more space and heat dissipation measures, so the branching strategy in the binary tree will tend to place them at the edge of the circuit board or in a location with sufficient heat dissipation channels. Similarly, for high-frequency signal components, it may be necessary to place them near the signal source to reduce signal transmission delay and interference.

[0147] After determining the preliminary branching strategy for components in a single-level binary tree, the next step is to adjust the connection method of the nodes according to the electrical connection relationship between the components. This step is to ensure the electrical performance and signal integrity of the circuit. For example, for components that need to be closely connected, such as amplifiers and components in their feedback networks, their nodes in the binary tree may be placed in adjacent positions to reduce the length and complexity of the connection lines.

[0148] The electrical connection relationship between components can be analyzed through circuit schematics or circuit netlists. Based on this information, it can be determined which components need to be directly connected, which components have signal interactions, and which components need to be electrically isolated. These connection relationships will guide the specific connection method of the nodes in the binary tree to ensure the electrical performance and signal integrity of the circuit.

[0149] Preferably, the connection mode of the nodes can also be optimized according to the specific requirements and design constraints of the circuit. For example, for complex circuit designs, additional rules may need to be introduced to deal with special electrical or physical requirements, such as avoiding the crossing of signal lines, ensuring the correct layout of power and ground lines, and considering electromagnetic compatibility (EMC) requirements. Through these optimization measures, the layout quality and performance of the circuit board can be further improved.

[0150] In some embodiments, performing layout modeling on the entire circuit based on the multi-level binary tree structure further includes:

[0151] For each circuit netlist, determine its position in the multi-level binary tree according to its electrical characteristics and physical size;

[0152] According to the electrical connection relationship between the circuit netlists, the connection mode of the nodes in the multi-level binary tree is adjusted.

[0153] A detailed analysis of the electrical characteristics and physical dimensions of each circuit netlist includes the netlist's operating voltage, current capacity, signal frequency, and the size, shape, and installation requirements of the components in the netlist. This information can be automatically obtained through circuit design software or manually entered by designers based on experience and component data sheets.

[0154] Preferably, the electrical characteristics and physical size information of the circuit netlist will be used to determine its position in the multi-level binary tree. For example, for a netlist containing high-power or high-heat components, it may be necessary to place it at the edge of the circuit board or in a location with sufficient heat dissipation channels, so the position in the multi-level binary tree will tend to be in these areas. Similarly, for a high-frequency signal netlist, it may be necessary to place it near the signal source to reduce signal transmission delay and interference.

[0155] After determining the initial position of the circuit netlist in the multi-level binary tree, the next step is to adjust the node connection method based on the electrical connection relationship between the netlists. For example, for netlists that need to be closely connected, such as a processor and its memory modules, their nodes in the binary tree may be placed in adjacent positions to reduce the length and complexity of the connection lines.

[0156] Specifically, the electrical connection relationship between netlists can be determined through the interaction analysis of circuit schematics or circuit netlists. Based on this information, it can be determined which netlists need to be directly connected, which netlists have signal interactions, and which netlists need to be electrically isolated. These connection relationships will guide the specific connection method of nodes in the multi-level binary tree to ensure the electrical performance and signal integrity of the circuit.

[0157] The way nodes are connected can also be optimized based on the specific requirements and design constraints of the circuit. For example, for complex circuit designs, additional rules may need to be introduced to handle special electrical or physical requirements, such as avoiding the crossing of signal lines, ensuring the correct layout of power and ground lines, and considering electromagnetic compatibility (EMC) requirements. Through these optimization measures, the layout quality and performance of the circuit board can be further improved.

[0158] In some embodiments, before exporting each functional module in the circuit schematic diagram as an independent circuit netlist, the method further includes: preprocessing the circuit schematic diagram, including removing non-electrical elements and standardized component symbols;

[0159] After automatically generating a detailed layout plan of the circuit board according to the optimized layout model, the method also includes: verifying the layout plan to ensure that the layout plan meets all constraints of the circuit design.

[0160] In some embodiments, pre-processing comprises:

[0161] 1. Remove non-electrical elements: Remove comments, borders, non-functional symbols, etc. in the schematic to ensure that the exported circuit netlist only contains components and connection information related to the circuit function.

[0162] 2. Standardized component symbols: Ensure that all component symbols follow unified naming rules and representation methods to facilitate recognition and processing by automated tools.

[0163] 3. Check component parameters: Verify the completeness and accuracy of component parameters to ensure that the electrical characteristics and physical size information of all components have been correctly entered.

[0164] Preferably, the preprocessing step can be performed by automated tools that can identify and process various elements in the circuit schematic and perform corresponding operations according to preset rules. For example, the automated tool can have a series of built-in filter conditions to identify and remove non-electrical elements, and can also standardize and verify component symbols and parameters.

[0165] It should be noted that after generating the detailed layout plan of the circuit board, the next step is to verify the layout plan. The purpose of the verification step is to ensure that the layout plan meets all the constraints of the circuit design, including electrical performance requirements, physical layout restrictions, thermal management requirements, etc.

[0166] 1. Electrical performance verification: Use simulation analysis to check whether electrical performance indicators such as signal integrity, power integrity and electromagnetic compatibility meet design requirements.

[0167] 2. Physical layout check: Ensure that the location of all components and connection lines comply with the physical layout constraints, such as minimum spacing, stacking structure and mounting requirements.

[0168] 3. Thermal management assessment: Evaluate the heat distribution and heat dissipation paths in the layout solution to ensure that the temperature of key components is within a safe range.

[0169] The verification step can be performed by automated simulation and analysis tools that can perform a comprehensive check and evaluation of the layout solution. For example, signal integrity analysis tools can be used to evaluate the impedance matching and transmission delay of signal lines, and thermal simulation tools can be used to evaluate the thermal performance of the board.

[0170] The verification step can also include manual review and adjustments by the designer. The designer can identify potential problems based on experience and intuition and make necessary optimizations. In addition, the verification process can also be an iterative process in which the layout solution is optimized and verified multiple times until all design constraints and performance requirements are met.

[0171] The automatic layout method of electronic components for circuit boards of the present invention significantly improves the efficiency and quality of circuit board design by comprehensively using multi-level binary tree modeling and advanced optimization algorithms. Using this method, designers can quickly generate layout solutions that meet complex electrical and physical requirements, greatly reducing the workload and design cycle of manual adjustments. In addition, by introducing preprocessing and verification steps in the design process, the high reliability and accuracy of the layout solution are ensured, and the risk of design rework is reduced. In general, the present invention not only improves the level of automation in circuit board design, but also brings innovative solutions to the field of electronic design automation, which helps to promote the development of related technologies.

[0172] The above descriptions are only some preferred embodiments of the present invention and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the embodiments of the present invention is not limited to the technical solutions formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above inventive concept. For example, the above features are replaced with (but not limited to) technical features with similar functions disclosed in the embodiments of the present invention to form a technical solution.

Claims

1. A method for automatic layout of electronic components on a circuit board, characterized in that: The method comprises the following steps: Export each functional module in the circuit schematic diagram as an independent circuit netlist; Layout modeling is performed for each group of components based on a single-level binary tree structure, and a single-level binary tree with the same number of nodes as the number of components is generated for each group of components, where each node represents an actual component; The layout modeling of the entire circuit is performed based on a multi-level binary tree structure. A multi-level binary tree with the same number of nodes as the number of groups is generated according to the grouping result of the circuit netlist. Each node represents a group of components. The single-level binary tree is nested in the corresponding node of the multi-level binary tree to form a multi-level nested binary tree structure. An optimization algorithm combined with a heuristic strategy is used to iteratively optimize the layout model based on circuit performance parameters; Automatically generate a detailed layout plan for the circuit board based on the optimized layout model.

2. The method according to claim 1, characterized in that Exporting each functional module in the circuit schematic into an independent circuit netlist includes: Identify functional modules in circuit schematics; According to the connection relationship of the functional modules, the related components are allocated to the corresponding circuit netlist.

3. The method according to claim 1, characterized in that The layout modeling of each group of components is carried out based on a single-level binary tree structure. A single-level binary tree with the same number of nodes as the number of components is generated for each group of components. Each node represents an actual component including: Assign a unique identifier to each component; Determine the level and position of nodes in a single-level binary tree based on the electrical characteristics and physical size of the components.

4. The method according to claim 1, characterized in that The layout modeling of the entire circuit is performed based on a multi-level binary tree structure. A multi-level binary tree with the number of nodes equal to the number of groups is generated according to the grouping results of the circuit netlist, including: Assigning a unique group identifier to each circuit netlist; According to the electrical characteristics and physical size of the circuit netlist, the level and position of the nodes in the multi-level binary tree are determined.

5. The method according to claim 1, characterized in that The optimization algorithm is combined with a heuristic strategy to iteratively optimize the layout model with circuit performance parameters, including: Define the evaluation function of the optimization algorithm, which includes line length, layout area and signal integrity; Each possible layout solution is scored using an evaluation function; The layout solution with the highest score is selected as the optimized layout model.

6. The method according to claim 1, characterized in that The detailed layout plan of the circuit board is automatically generated based on the optimized layout model, including: Convert the optimized layout model into a physical layout of the circuit board; Generate a layout drawing of the circuit board, including the location coordinates of the components and the paths of the connecting lines.

7. The method according to claim 1, characterized in that The optimization algorithm includes a particle swarm optimization algorithm, including: Initialize the particle swarm, each particle represents a layout plan; Iteratively search for the optimal layout solution through the particle swarm optimization algorithm; Update the particle's position and velocity until the preset number of iterations is reached or the optimization goal is met.

8. The method according to claim 1, characterized in that Layout modeling for each group of components based on a single-level binary tree structure also includes: For each component, determine its branching strategy in a single-level binary tree according to its electrical characteristics and physical size; According to the electrical connection relationship between components, the connection mode of nodes in a single-level binary tree is adjusted.

9. The method according to claim 1, characterized in that: Layout modeling of the entire circuit based on a multi-level binary tree structure also includes: For each circuit netlist, determine its position in the multi-level binary tree according to its electrical characteristics and physical size; According to the electrical connection relationship between the circuit netlists, the connection mode of the nodes in the multi-level binary tree is adjusted.

10. The method according to claim 1, characterized in that Before exporting each functional module in the circuit schematic diagram into an independent circuit netlist, the method further includes: preprocessing the circuit schematic diagram, including removing non-electrical elements and standardized component symbols; After automatically generating a detailed layout plan of the circuit board according to the optimized layout model, the method also includes: verifying the layout plan to ensure that the layout plan meets all constraints of the circuit design.

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