Synchronous escape wiring method and device based on multiple commodity flows and medium

Abstract

The invention discloses a synchronous escape wiring method and device based on multiple commodity flows and a medium, and the method comprises the steps: building a GPA wiring diagram graph based on a chip grid pin array, and building an irregular pin array wiring diagram graph according to an array of missing pins; according to the created GPA wiring diagram graph, creating an escape boundary node in the synchronous escape wiring; according to the creation of the escape boundary node, creating a synchronous escape overall wiring diagram graph; according to the created synchronous escape overall wiring diagram graph, creating a synchronous escape wiring model based on multiple commodity flows; solving the synchronous escape wiring model to obtain a wiring result, and designing the constraint of grouping on the same layer in the synchronous escape wiring; and optimizing a wiring path of the synchronous escape wiring model, and accelerating synchronous escape wiring according to an optimization result. According to the method, through modeling of the wiring constraint and path optimization method, multiple acceleration methods are supported to act at the same time, and the efficiency of the system is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and more specifically, particularly relates to a synchronous escape wiring method, device and medium based on multiple commodity flows. Background Art

[0002] As an important part of PCB design, wiring has a significant impact on the design cycle and system reliability. BGA is a widely used chip packaging method, usually in the form of a pin array. Escape wiring is mainly aimed at BGA wiring scenarios. It is necessary to determine the escape path from the pad inside the BGA to the boundary. It is an important stage in the PCB wiring process. Synchronous escape wiring is a detailed scenario of escape wiring. It is a collaborative wiring problem with multiple BGAs. The escape order between the two BGAs needs to match to avoid the intersection of the wire nets between the BGAs. The escape order will affect the escape path of the wire net inside the BGA and the final wiring result, and even the originally solvable problem becomes unsolvable.

[0003] Existing synchronous escape routing methods are usually divided into two steps: determining the escape order and completing the routing path. If the first BGA is first escaped out of order, and the second BGA is escaped in order to match the order of the first BGA, the second BGA will most likely fail to escape. If the escape order is determined first, and then the two BGAs are escaped in order, the quality of the final routing is largely affected by the escape order determined in the previous step, and may even cause the synchronous escape routing to fail. At the same time, a high-quality escape order consumes a lot of time. Therefore, a method is needed to consider the escape order and routing path at the same time and complete the synchronous escape routing in the same step. Summary of the invention

[0004] The purpose of this section is to summarize some aspects of embodiments of the present invention and briefly introduce some preferred embodiments. Some simplifications or omissions may be made in this section and the specification abstract and the invention title of this application to avoid blurring the purpose of this section, the specification abstract and the invention title, and such simplifications or omissions cannot be used to limit the scope of the present invention.

[0005] In view of the above or existing problems of the synchronous escape wiring method based on multiple commodity flows, the present invention is proposed.

[0006] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0007] The embodiment of the present invention provides a synchronous escape routing method based on multiple commodity flows, including: creating a GPA routing graph based on a chip grid pin array, creating an irregular pin array routing graph based on an array of missing pins;

[0008] According to the created GPA wiring graph, create an escape boundary node node in the synchronous escape wiring;

[0009] According to the creation of the escape boundary node node, the synchronous escape overall wiring graph graph is created;

[0010] According to the creation of the synchronous escape overall wiring graph, a synchronous escape wiring model based on multiple commodity flows is created;

[0011] By solving the synchronous escape routing model, a routing result is obtained, and constraints for grouping the same layer in the synchronous escape routing are designed;

[0012] The wiring path of the synchronous escape wiring model is optimized, and the synchronous escape wiring is accelerated according to the optimization result.

[0013] As a preferred solution of the synchronous escape wiring method based on multi-commodity flow of the present invention, wherein: the GPA wiring graph is created based on the chip grid pin array, and the irregular pin array wiring graph is created according to the array of missing pins, including:

[0014] According to the pin arrangement characteristics of GPA, every four adjacent pins of GPA are used as block tiles, the line width and line spacing constraints of synchronous escape routing are converted into the capacity constraints of block tiles, and the GPA is divided into adjacent capacity and diagonal capacity;

[0015] Create intermediate nodes and edges corresponding to the capacity constraints in the tile, and create edges between nodes corresponding to adjacent tiles;

[0016] According to the positional relationship between the missing pins and the pins to be connected or other pins, three basic types of missing pins are proposed to improve the pin array wiring diagram in order to make full use of wiring resources.

[0017] As a preferred solution of the synchronous escape wiring method based on multi-commodity flow of the present invention, wherein: the creation of the escape boundary node node in the synchronous escape wiring according to the created wiring graph graph includes:

[0018] For a block tile located at an escape boundary boundary of the grid pin array GPA, an escape boundary node node corresponding to an intermediate node of the block tile is created, and the intermediate node is interconnected with the node node.

[0019] As a preferred solution of the synchronous escape wiring method based on multi-commodity flow of the present invention, wherein: the synchronous escape overall wiring graph is created according to the creation of the escape boundary node node, including:

[0020] Determine the relationship between the number of escape boundary nodes and the pins to be connected of the left and right BGAs:

[0021] When the number of escape boundary nodes of both is greater than the number of pins to be connected, first sort the escape boundary nodes in a clockwise or counterclockwise order, take all the escape boundary nodes of the left BGA as the first column, and create a virtual node with one less column than the number of nodes in the current column as the next column;

[0022] At the same time, create a virtual edge edge from the i-th and i+1-th nodes node in the current column to the i-th virtual node node in the next column, until the number of virtual nodes in the current column is the same as the number of escape boundary nodes of the right BGA;

[0023] Finally, a virtual edge is created between the jth virtual node in this column and the jth escape boundary node of the BGA on the right, completing the creation of the overall wiring graph.

[0024] As a preferred solution of the synchronous escape wiring method based on multiple commodity flows of the present invention, wherein: the synchronous escape wiring model based on multiple commodity flows is created according to the creation of the synchronous escape overall wiring graph, including:

[0025] Determine the value range of the decision variable x(n,e) to be 0 or 1;

[0026] When the decision variable is 1, it means that the network n uses the edge e in the wiring graph graph for wiring;

[0027] When the decision variable is 0, it means that edge e is not used when routing network n;

[0028] At the same time, the value range of n is all wire nets, and the value range of e is all directed edges in the wiring diagram.

[0029] As a preferred solution of the synchronous escape wiring method based on multi-commodity flow of the present invention, wherein: the synchronous escape wiring model is solved to obtain the wiring result, and the constraints of grouping the same layer in the synchronous escape wiring are designed, including:

[0030] The optimization goal is determined to be to minimize the total line length and avoid loops in the wiring path of the wire net. The wiring result is obtained by solving the model.

[0031] Add node capacity constraints based on the flow demand constraints, flow conservation constraints, and edge capacity constraints of multi-commodity flows to limit the total usage of nodes to not exceed the node capacity limit and avoid the intersection of network wiring paths;

[0032] Create a bottom wiring graph below the top layer where the pins are located, and assign a via as an edge in the overall wiring graph to the pins to be connected. The via connects the node node of the top wiring graph with the node node of the bottom layer.

[0033] By adding any two nets n in the same group, using the constraint that the total number of vias is equal, the grouping same layer constraint is implemented, and at the same time, a candidate via set is specified for the net n;

[0034] If the through hole is not in the candidate through hole set of the net n, a constraint condition that the corresponding decision variable is 0 is added to the model.

[0035] As a preferred solution of the synchronous escape wiring method based on multi-commodity flow of the present invention, wherein: the wiring path of the synchronous escape wiring model is optimized, and the synchronous escape wiring is accelerated according to the optimization result, including:

[0036] Taking the node node in the wiring graph as the object, add the terms related to the angles of the incoming and outgoing edges at the node node to the optimization target, and change the optimization target from a quadratic term to a linear term by adding new decision variables, completing the linearization conversion and realizing the minimization of path bending;

[0037] The direct connection between the starting point and the end point of the wire net n is used as the heuristic edge. On the basis of the basic cost, the heuristic cost related to the distance and angle of the heuristic edge is added to the edge in the wiring graph, thereby improving the optimization objective function and achieving wiring acceleration.

[0038] A synchronous escape wiring device based on multiple commodity flows, characterized by comprising:

[0039] A BGA wiring diagram creation module is used to create a GPA wiring diagram graph based on the chip grid pin array, create an irregular pin array wiring diagram graph according to the array of missing pins, and create an escape boundary node node in the synchronous escape wiring according to the created GPA wiring diagram graph;

[0040] An overall wiring diagram creation module is used to create a synchronous escape overall wiring diagram graph according to the escape boundary node node created;

[0041] A model building module, used for creating a synchronous escape wiring model based on multiple commodity flows according to the synchronous escape overall wiring graph;

[0042] A constraint design module, used for obtaining a wiring result by solving the synchronous escape wiring model, and designing constraints for grouping the same layer in the synchronous escape wiring;

[0043] The model path optimization module optimizes the routing path of the synchronous escape routing model and accelerates the synchronous escape routing according to the optimization result.

[0044] A computing device, comprising:

[0045] at least one processor, memory, and input-output unit;

[0046] The memory is used to store a computer program, and the processor is used to call the computer program stored in the memory to execute the steps of the synchronous escape routing method based on multiple commodity flows.

[0047] A computer-readable storage medium includes instructions, which, when executed on a computer, cause the computer to execute the steps of a synchronous escape routing method based on multi-commodity flows.

[0048] The beneficial effects of the present invention are as follows: the present invention provides a synchronous escape wiring method based on multi-commodity flows, which has the advantage that it completes the determination of the escape order and the wiring path in the same step, and by modeling the multi-layer synchronous escape wiring constraints and path optimization methods, the overall wiring path bending can be minimized while ensuring the synchronization rate. In addition, the synchronous escape wiring method supports multiple acceleration methods to act simultaneously to improve the efficiency of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0050] Figure 1 A flowchart of a synchronous escape routing method based on multiple commodity flows is provided in an embodiment of the present invention.

[0051] Figure 2 A schematic structural diagram of a synchronous escape wiring device based on multiple commodity flows provided in an embodiment of the present invention.

[0052] Figure 3 A schematic structural diagram of a medium according to an embodiment of the present invention is schematically shown.

[0053] Figure 4 A schematic diagram of the structure of a computing device according to an embodiment of the present invention is schematically shown.

[0054] Figure 5 A wiring diagram of a GPA with an adjacent capacity of 1 and a diagonal capacity of 2 is provided in an embodiment of a synchronous escape wiring method based on multi-commodity flows provided in an embodiment of the present invention.

[0055] Figure 6 A GPA wiring diagram with an adjacent capacity of 2 and a diagonal capacity of 3 is provided in an embodiment of a synchronous escape wiring method based on multi-commodity flows provided in an embodiment of the present invention.

[0056] Figure 7 A schematic diagram of three basic types of missing pins in an embodiment of a synchronous escape routing method based on multi-commodity flows provided by an embodiment of the present invention.

[0057] Figure 8 A schematic diagram of virtual nodes and virtual edges between pin arrays of an embodiment of a synchronous escape routing method based on multi-commodity flows provided by an embodiment of the present invention.

[0058] Fig. 9 A schematic diagram of a through-hole edge of an embodiment of a synchronous escape routing method based on multiple commodity flows provided in an embodiment of the present invention.

[0059] Fig.10 A schematic diagram of a wire net heuristic edge of an embodiment of a synchronous escape routing method based on multiple commodity flows provided in an embodiment of the present invention.

[0060] In the drawings, the same or corresponding reference numerals represent the same or corresponding parts. DETAILED DESCRIPTION

[0061] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are described in detail below in conjunction with the accompanying drawings.

[0062] In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0063] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The term "in one embodiment" that appears in different places in this specification does not necessarily refer to the same embodiment, nor does it refer to a separate or selective embodiment that is mutually exclusive with other embodiments.

[0064] Example 1

[0065] Reference below Figure 1 , Figure 1 This is a flow chart of a synchronous escape routing method based on multi-commodity flows provided in one embodiment of the present invention. It should be noted that the embodiments of the present invention can be applied to any applicable scenario.

[0066] Figure 1 The process of the synchronous escape routing method based on multiple commodity flows provided by an embodiment of the present invention shown includes:

[0067] S1: Based on the chip grid pin array, create a GPA wiring graph, create an irregular pin array wiring graph according to the array of missing pins, and create an escape boundary node in the synchronous escape wiring according to the created wiring graph.

[0068] Preferably, Figure 5 and Figure 6 As shown, a grid pin array (GPA) wiring graph is created. According to the GPA pin arrangement characteristics, every four adjacent pins of the GPA are used as block tiles. The line width and line spacing constraints of the synchronous escape wiring are converted into capacity constraints of the block tiles. The GPA is divided into adjacent capacity and diagonal capacity, and intermediate nodes and edges corresponding to the capacity constraints are created in the block tiles, and edges are created between the nodes corresponding to adjacent block tiles.

[0069] Preferably, Figure 7 As shown, an irregular pin array wiring graph with missing pins is created, and three basic types of missing pins are proposed according to the positional relationship between the missing pins and the pins to be connected or other pins, so as to improve the pin array wiring graph and make full use of wiring resources.

[0070] Preferably, Figure 8 As shown, an escape boundary node node in the synchronous escape routing is created, and for a block tile located at the escape boundary boundary of the grid pin array GPA, an escape boundary node node corresponding to the middle node of the block tile is created, and the middle node is interconnected with the node node.

[0071] S2: Based on the created escape boundary node node, the synchronous escape overall wiring graph graph is created.

[0072] Preferably, a synchronous escape overall wiring graph is created to determine the relationship between the escape boundary nodes of the left and right BGAs and the number of pins to be connected:

[0073] When the number of escape boundary nodes of both is greater than the number of pins to be connected, first sort the escape boundary nodes node according to the clockwise or counterclockwise rule, take all the escape boundary nodes of the left BGA as the first column, and create a virtual node with one column less than the number of nodes in the current column as the next column, and at the same time create a virtual edge from the i-th and i+1-th nodes node of the current column to the i-th virtual node node of the next column, until the number of virtual nodes in the current column is the same as the number of escape boundary nodes of the right BGA, finally create a virtual edge between the j-th virtual node in this column and the j-th escape boundary node of the right BGA to complete the creation of the overall wiring graph.

[0074] S3: Create a synchronous escape wiring model based on multiple commodity flows based on the synchronous escape overall wiring graph.

[0075] Preferably, the value range of the decision variable x(n,e) is determined to be 0 or 1. When the decision variable is 1, it means that the line network n uses the edge e in the wiring graph graph for wiring. When the decision variable is 0, it means that the edge e is not used when the line network n is wired. At the same time, the value range of n is all the line networks, and the value range of e is all the directed edges in the wiring graph.

[0076] S4: By solving the synchronous escape routing model, a routing result is obtained, and constraints for grouping the same layer in the synchronous escape routing are designed.

[0077] Preferably, the optimization goal is determined to minimize the total line length, avoid loops in the wiring path of the wire network, and obtain the wiring result by solving the model;

[0078] Add node capacity constraints based on the flow demand constraints, flow conservation constraints, and edge capacity constraints of multi-commodity flows to limit the total usage of nodes to not exceed the node capacity limit and avoid the intersection of network wiring paths;

[0079] like Fig. 9 As shown, first create the bottom wiring graph below the top layer where the pins are located, and assign vias to the pins to be connected. The vias serve as edges in the overall wiring graph, which connect the nodes of the top wiring graph and the nodes of the bottom layer.

[0080] By adding the constraint that the sum of the number of vias used by any two nets n in the same group is equal, the group same layer constraint is implemented, and at the same time, a candidate via set is specified for net n;

[0081] If the through hole is not in the candidate through hole set of the net n, a constraint condition that the corresponding decision variable is 0 is added to the model.

[0082] S5: Optimize the routing path of the synchronous escape routing model, and accelerate the synchronous escape routing according to the optimization result.

[0083] Preferably, Fig.10 As shown in the figure, taking the node node in the wiring graph as the object, adding the terms related to the angles of the incoming and outgoing edges at the node node to the optimization objective, and changing the optimization objective from a quadratic term to a linear term by adding new decision variables, completing the linearization conversion and realizing the minimization of path bending;

[0084] The direct connection between the starting point and the end point of the wire net n is used as the heuristic edge. On the basis of the basic cost, the heuristic cost related to the distance and angle of the heuristic edge is added to the edge in the wiring graph, thereby improving the optimization objective function and achieving wiring acceleration.

[0085] Example 2

[0086] Another embodiment of the present invention:

[0087] Preferably, a Point class is designed, including the attributes of horizontal coordinate x, vertical coordinate y, and layer index layer; a Node class is designed to inherit the Point class and include the attribute index id, flow, network number net, and capacity capacity, where flow is 1 or -1, which respectively indicates the starting point or end point of the net network, and 0 indicates other nodes.

[0088] Preferably, an Edge class is designed, which includes the attributes of a starting node start, an ending node end, a capacity capacity, and a cost cost; a Rect class is designed, which includes the attributes of a left boundary horizontal coordinate left, a right boundary horizontal coordinate left, an upper boundary vertical coordinate top, and a lower boundary vertical coordinate bottom.

[0089] Preferably, a Pin class is designed, which includes attributes: column index x, row index y, line net, group identifier group, whether it is a starting point flag, candidate through hole set avaiableVias, and candidate channel set avaiableSwitchEdges.

[0090] Preferably, a BGA class is designed and inherits the Rect class, which contains the attributes of the number of rows of pins height, the number of columns width, the set of pins to be connected pins, the set of missing pins missPins, the adjacent capacity orthogonalCapacity, the diagonal capacity diagonalCapacity, and the escape boundary boundary.

[0091] Preferably, the MCFSolver class is designed to include the properties of two horizontally placed BGA objects bgas, the number of wire nets netNum, the wire net set nets, the vertex set nodes, the edge set edges, the two-dimensional flow matrix flows, the total wire length totalWireLength, the total number of through holes totalViaNum, the total number of bends totalBendNum, and the total running time totalRuntime.

[0092] Specifically, in the main function, first construct the MCFSolver object mcf and initialize its attribute bgas. Traverse each tile block of each BGA, create nodes and edges that meet the BGA capacity constraints in the current tile, and create edges between the adjacent tiles and the corresponding nodes of the current tile when there are other tiles in the four directions adjacent to the current tile.

[0093] If the current tile is on the escape boundary boundary of the BGA, an escape node escnode is created in the boundary, and an edge edge is created from the corresponding node in the tile to the escape node; if there is a pin in the pins or missPins in the BGA properties in the current tile, a node node and an edge edge are newly created or removed according to the three basic types; all escape nodes located on the left side of the BGA are sorted in a clockwise direction, and all escape nodes located on the right side of the BGA are sorted in a counterclockwise direction, and the side with more escape nodes is selected to create virtual nodes imgNode and virtual edges imgEdge in a column-by-column descending manner, and all created nodes and edges as well as virtual nodes and virtual edges are set to the properties nodes and edges respectively.

[0094] Similarly, create the underlying wiring diagram and through-holes, traverse all nets and all nodes in nodes, and if the current net is equal to the attribute net of the current node, set the corresponding flows to the flow attribute of the current node. Initialize the cplex model model and create a decision variable x(n, e), where the value range of x(n, e) is 0 or 1, add flow demand constraints, flow conservation constraints, edge capacity constraints, node capacity constraints, net candidate through-hole constraints to the model, and set the optimization goal to minimize the total cost. Solve the model model. If the model has a feasible solution, convert the feasible solution according to the rule that when the decision variable x(n, e) is 1, net n uses edge e for wiring, and when it is 0, net n does not use edge e for wiring, and obtain the wiring result. Finally, calculate the total line length, total number of through-holes, total number of bends, total running time and display the output.

[0095] After introducing the method of the exemplary embodiment of the present invention, next, refer to Figure 2 A synchronous escape wiring device based on multiple commodity flows according to an exemplary embodiment of the present invention is described, and the device includes:

[0096] A BGA wiring diagram creation module is used to create a GPA wiring diagram graph based on the chip grid pin array, create an irregular pin array wiring diagram graph according to the array of missing pins, and create an escape boundary node node in the synchronous escape wiring according to the created GPA wiring diagram graph;

[0097] An overall wiring diagram creation module is used to create a synchronous escape overall wiring diagram graph according to the escape boundary node node created;

[0098] A model building module, used for creating a synchronous escape wiring model based on multiple commodity flows according to the synchronous escape overall wiring graph;

[0099] A constraint design module, used for obtaining a wiring result by solving the synchronous escape wiring model, and designing constraints for grouping the same layer in the synchronous escape wiring;

[0100] The model path optimization module optimizes the routing path of the synchronous escape routing model and accelerates the synchronous escape routing according to the optimization result.

[0101] After introducing the method and apparatus of the exemplary embodiment of the present invention, next, reference is made to Figure 3 For a description of a computer-readable storage medium according to an exemplary embodiment of the present invention, please refer to Figure 3 , the computer-readable storage medium shown is a CD 30, on which a computer program (i.e., a program product) is stored. When the computer program is executed by the processor, it will implement the steps recorded in the above method implementation method, for example, based on the chip grid pin array, a GPA wiring diagram graph is created, and according to the array of missing pins, an irregular pin array wiring diagram graph is created; according to the created GPA wiring diagram graph, an escape boundary node node in the synchronous escape wiring is created; according to the created escape boundary node node, a synchronous escape overall wiring diagram graph is created; according to the created synchronous escape overall wiring diagram graph, a synchronous escape wiring model based on multiple commodity flows is created; by solving the synchronous escape wiring model, a wiring result is obtained, and constraints for grouping the same layer in the synchronous escape wiring are designed; the wiring path of the synchronous escape wiring model is optimized, and the synchronous escape wiring is accelerated according to the optimization result; the specific implementation method of each step will not be repeated here.

[0102] It should be noted that examples of the computer-readable storage medium may also include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other optical or magnetic storage media, which are not listed here one by one.

[0103] After introducing the method, apparatus and medium of the exemplary embodiments of the present invention, next, reference is made to Figure 4 A computing device for synchronous escape routing based on multiple commodity flows according to an exemplary embodiment of the present invention.

[0104] Figure 4 A block diagram of an exemplary computing device 40 suitable for implementing embodiments of the present invention is shown, and the computing device 40 may be a computer system or a server. Figure 4 The computing device 40 shown is only an example and should not bring any limitation to the functionality and scope of use of the embodiments of the present invention.

[0105] like Figure 4 As shown, the components of the computing device 40 may include, but are not limited to: one or more processors or processing units 401, a system memory 402, and a bus 403 connecting different system components (including the system memory 402 and the processing unit 401).

[0106] The computing device 40 typically includes a variety of computer system readable media. These media can be any available media that can be accessed by the computing device 40, including volatile and non-volatile media, removable and non-removable media.

[0107] System memory 402 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 4021 and / or cache memory 4022. Computing device 40 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, ROM 4023 may be used to read and write non-removable, non-volatile magnetic media ( Figure 4 is not shown in the Figure 4As shown in FIG. 4 , a disk drive for reading and writing a removable non-volatile disk (e.g., a "floppy disk") and an optical disk drive for reading and writing a removable non-volatile optical disk (e.g., a CD-ROM, a DVD-ROM, or other optical media) may be provided. In these cases, each drive may be connected to bus 403 via one or more data medium interfaces. System memory 402 may include at least one program product having a set (e.g., at least one) of program modules that are configured to perform the functions of various embodiments of the present invention.

[0108] A program / utility 4025 having a set (at least one) of program modules 4024 may be stored, for example, in system memory 402, and such program modules 4024 include, but are not limited to, an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment. Program modules 4024 generally perform the functions and / or methods of the embodiments described herein.

[0109] The computing device 40 may also communicate with one or more external devices 404 (e.g., a keyboard, a pointing device, a display, etc.). Such communication may be performed via an input / output (I / O) interface 405. Furthermore, the computing device 40 may also communicate with one or more networks (e.g., a local area network (LAN), a wide area network (WAN), and / or a public network, such as the Internet) via a network adapter 406. Figure 4 As shown, the network adapter 406 communicates with other modules (such as the processing unit 401, etc.) of the computing device 40 via the bus 403. It should be understood that although Figure 4 Not shown, other hardware and / or software modules may be used in conjunction with computing device 40 .

[0110] The processing unit 401 executes various functional applications and data processing by running the program stored in the system memory 402, for example, based on the chip grid pin array, a GPA wiring graph is created, and according to the array of missing pins, an irregular pin array wiring graph is created; according to the created GPA wiring graph, an escape boundary node node in the synchronous escape wiring is created; according to the created escape boundary node node, a synchronous escape overall wiring graph is created; according to the created synchronous escape overall wiring graph, a synchronous escape wiring model based on multiple commodity flows is created; by solving the synchronous escape wiring model, a wiring result is obtained, and constraints for grouping the same layer in the synchronous escape wiring are designed; the wiring path of the synchronous escape wiring model is optimized, and the synchronous escape wiring is accelerated according to the optimization result. The specific implementation method of each step will not be repeated here. It should be noted that although several units / modules or sub-units / sub-modules of the synchronous escape wiring device based on multiple commodity flows are mentioned in the above detailed description, this division is only exemplary and not mandatory. In fact, according to an embodiment of the present invention, the features and functions of two or more units / modules described above can be embodied in one unit / module. Conversely, the features and functions of one unit / module described above can be further divided into multiple units / modules to be embodied.

[0111] In the description of the present invention, it should be noted that the terms “first”, “second” and “third” are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0112] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0113] In the several embodiments provided by the present invention, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. The device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, and the indirect coupling or communication connection of devices or units can be electrical, mechanical or other forms.

[0114] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0115] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0116] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium that is executable by a processor. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, and other media that can store program codes.

[0117] Finally, it should be noted that the above-described embodiments are only specific implementations of the present invention, which are used to illustrate the technical solutions of the present invention, rather than to limit them. The protection scope of the present invention is not limited thereto. Although the present invention is described in detail with reference to the above-described embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-described embodiments within the technical scope disclosed by the present invention, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

[0118] In addition, although the operations of the method of the present invention are described in a specific order in the drawings, this does not require or imply that the operations must be performed in this specific order, or that all the operations shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps.

Claims

1. A synchronous escape routing method based on multiple commodity flows, characterized in that: include: Based on the chip grid pin array, create a GPA wiring graph, and based on the array of missing pins, create an irregular pin array wiring graph; According to the created GPA wiring graph, create an escape boundary node node in the synchronous escape wiring; According to the creation of the escape boundary node node, the synchronous escape overall wiring graph graph is created; According to the creation of the synchronous escape overall wiring graph, a synchronous escape wiring model based on multiple commodity flows is created; By solving the synchronous escape routing model, a routing result is obtained, and constraints for grouping the same layer in the synchronous escape routing are designed; The wiring path of the synchronous escape wiring model is optimized, and the synchronous escape wiring is accelerated according to the optimization result.

2. The synchronous escape routing method based on multiple commodity flows according to claim 1, characterized in that: The method of creating a GPA wiring graph based on the chip grid pin array and creating an irregular pin array wiring graph according to the array of missing pins includes: According to the pin arrangement characteristics of GPA, every four adjacent pins of GPA are used as block tiles, the line width and line spacing constraints of synchronous escape routing are converted into the capacity constraints of block tiles, and the GPA is divided into adjacent capacity and diagonal capacity; Create intermediate nodes and edges corresponding to the capacity constraints in the tile, and create edges between nodes corresponding to adjacent tiles; According to the positional relationship between the missing pins and the pins to be connected or other pins, three basic types of missing pins are proposed to improve the pin array wiring diagram in order to make full use of wiring resources.

3. The synchronous escape wiring method based on multiple commodity flows according to claim 1, characterized in that: The step of creating an escape boundary node node in the synchronous escape wiring according to the created wiring graph graph includes: For a block tile located at an escape boundary boundary of the grid pin array GPA, an escape boundary node node corresponding to an intermediate node of the block tile is created, and the intermediate node is interconnected with the node node.

4. The synchronous escape wiring method based on multiple commodity flows according to claim 1, characterized in that: The step of creating a synchronous escape overall wiring graph graph according to the creation of the escape boundary node node includes: Determine the relationship between the escape boundary nodes of the left and right BGAs and the number of pins to be connected: When the number of escape boundary nodes of both is greater than the number of pins to be connected, first sort the escape boundary nodes in a clockwise or counterclockwise order, take all the escape boundary nodes of the left BGA as the first column, and create a virtual node with one less column than the number of nodes in the current column as the next column; At the same time, create a virtual edge edge from the i-th and i+1-th nodes node in the current column to the i-th virtual node node in the next column, until the number of virtual nodes in the current column is the same as the number of escape boundary nodes of the right BGA; Finally, a virtual edge is created between the jth virtual node in this column and the jth escape boundary node of the BGA on the right, completing the creation of the overall wiring graph.

5. The synchronous escape wiring method based on multiple commodity flows according to claim 1, characterized in that: The step of creating a synchronous escape overall wiring graph based on the synchronous escape wiring model based on multiple commodity flows includes: Determine the value range of the decision variable x(n,e) to be 0 or 1; When the decision variable is 1, it means that the network n uses the edge e in the wiring graph graph for wiring; When the decision variable is 0, it means that edge e is not used when routing network n; At the same time, the value range of n is all wire nets, and the value range of e is all directed edges in the wiring diagram.

6. The synchronous escape routing method based on multiple commodity flows according to claim 1, characterized in that: The synchronous escape routing model is solved to obtain a routing result, and constraints for grouping the same layer in the synchronous escape routing are designed, including: The optimization goal is determined to be to minimize the total line length and avoid loops in the wiring path of the wire net. The wiring result is obtained by solving the model. Add node capacity constraints based on the flow demand constraints, flow conservation constraints, and edge capacity constraints of multi-commodity flows to limit the total usage of nodes to not exceed the node capacity limit and avoid the intersection of network wiring paths; Create a bottom wiring graph below the top layer where the pins are located, and assign a via as an edge in the overall wiring graph to the pins to be connected. The via connects the node node of the top wiring graph with the node node of the bottom layer. By adding any two nets n in the same group, using the constraint that the total number of vias is equal, the grouping same layer constraint is implemented, and at the same time, a candidate via set is specified for the net n; If the through hole is not in the candidate through hole set of the net n, a constraint condition that the corresponding decision variable is 0 is added to the model.

7. The synchronous escape routing method based on multiple commodity flows according to claim 1, characterized in that: The step of optimizing the routing path of the synchronous escape routing model and accelerating the synchronous escape routing according to the optimization result includes: Taking the node node in the wiring graph as the object, add the terms related to the angles of the incoming and outgoing edges at the node node to the optimization target, and change the optimization target from a quadratic term to a linear term by adding new decision variables, completing the linearization conversion and realizing the minimization of path bending; The direct connection between the starting point and the end point of the wire net n is used as the heuristic edge. On the basis of the basic cost, the heuristic cost related to the distance and angle of the heuristic edge is added to the edge in the wiring graph, thereby improving the optimization objective function and achieving wiring acceleration.

8. A synchronous escape wiring device based on multiple commodity flows, characterized in that: include: A BGA wiring diagram creation module is used to create a GPA wiring diagram graph based on the chip grid pin array, create an irregular pin array wiring diagram graph according to the array of missing pins, and create an escape boundary node node in the synchronous escape wiring according to the created GPA wiring diagram graph; An overall wiring diagram creation module is used to create a synchronous escape overall wiring diagram graph according to the escape boundary node node created; A model building module, used for creating a synchronous escape wiring model based on multiple commodity flows according to the synchronous escape overall wiring graph; A constraint design module, used for obtaining a wiring result by solving the synchronous escape wiring model, and designing constraints for grouping the same layer in the synchronous escape wiring; The model path optimization module optimizes the routing path of the synchronous escape routing model and accelerates the synchronous escape routing according to the optimization result.

9. A computing device, comprising: at least one processor, memory, and input-output unit; The memory is used to store a computer program, and the processor is used to call the computer program stored in the memory to execute the steps of the synchronous escape wiring method based on multi-commodity flow as described in any one of claims 1 to 7.

10. A computer-readable storage medium comprising instructions, which, when executed on a computer, enables the computer to execute the steps of the synchronous escape routing method based on multi-commodity flows as claimed in any one of claims 1 to 7.

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