Neuron circuit based on asynchronous pulse normal form
By designing a neuronal circuit based on the asynchronous pulse paradigm, the membrane voltage accumulation, leakage and emission functions of biological neurons are simulated, and the asynchronous handshake processing mechanism is adopted, the problem of mismatch between the existing neuron circuit and biological neurons is solved, and efficient and low-power signal processing capabilities are achieved.
Patent Information
- Application Number
- CN202411503650.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-25
- Publication Date
- 2025-03-07
AI Technical Summary
The existing neuronal circuits do not match the working mechanism of biological neurons, resulting in high power consumption, clock offset, electromagnetic interference, poor scalability, lack of leakage functions, resulting in reduced signal processing capabilities and weakened memory capabilities.
A neuron circuit based on the asynchronous pulse paradigm is designed, including initialization and integration modules, pulse distribution modules, leakage modules and asynchronous handshake communication modules, which simulate the membrane voltage accumulation, leakage and emission functions of biological neurons, and reduce power consumption through the asynchronous handshake processing mechanism.
The computing power and efficiency similar to biological neurons are achieved, which reduces the overall power consumption of the circuit, improves the noise immunity and performance, and reduces the circuit implementation cost.
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Abstract
Description
Technical Field
[0001] The present application belongs to the technical field of integrated circuit design, and in particular, relates to a neuron circuit based on an asynchronous pulse paradigm. Background Art
[0002] In recent years, the spiking neural network (SNN), known as the third generation of neural networks, is expected to truly realize brain-like artificial intelligence due to its advantages such as rich spatiotemporal dynamic characteristics, diverse encoding mechanisms, and event-driven characteristics that match hardware. However, the neural networks and learning algorithms implemented by computing devices represented by CPUs and GPUs are currently facing bottlenecks such as power consumption, speed, and data bandwidth. The root cause is that under the traditional von Neumann architecture, the storage unit and computing unit of the chip are separated, and data needs to be moved between the two units through the bus, resulting in latency and power consumption. In addition, the chip's information processing capabilities are restricted by the bus bandwidth, thus forming the "storage wall" and "power wall" problems. In order to break through the traditional von Neumann architecture, many research institutions and companies have developed SNN hardware acceleration platforms represented by brain-like computing circuits. Neuron circuits are the basic units that constitute brain-like computing circuits. They perform complex logical calculations by simulating and replicating the functions of biological neurons - receiving, processing, and transmitting information.
[0003] Disadvantages of existing neuronal circuits:
[0004] (1) It does not match the actual working mechanism of biological neurons. Building a global clock tree will bring about problems such as high power consumption, clock offset, electromagnetic interference, and poor scalability.
[0005] (2) The lack of a “leakage” function similar to that of biological neurons weakens the dynamic behavior of neurons, resulting in excessive response of the circuit to continuous input and decreased memory ability;
[0006] (3) Analog neuron circuits are susceptible to interference from external environmental factors, resulting in inaccurate signal processing. At the same time, they are difficult to fine-tune and maintain, which leads to challenges in achieving complex and high-density integration. Summary of the invention
[0007] In order to solve the deficiencies in the prior art, this application proposes a neuron circuit based on an asynchronous pulse paradigm, which is described in detail as follows:
[0008] A neuron circuit based on an asynchronous pulse paradigm, comprising:
[0009] Initialization and integration module, used to calculate the membrane voltage of neurons and realize the accumulation function in the calculation process;
[0010] The pulse issuing module is used to determine whether the membrane voltage of the neuron reaches a preset threshold and decide the pulse issuing according to the judgment result;
[0011] The leakage module is used to simulate the natural decay process of the membrane voltage of neurons when there is no stimulation input;
[0012] An asynchronous handshake communication module is used to send a handshake signal to the pulse issuing module and the leakage module after the initialization and integration modules complete the accumulation to realize an asynchronous working mechanism;
[0013] Among them, the first input terminal of the initialization and integration module is connected to the set voltage, the first input terminal of the pulse issuance module is connected to the second input terminal of the initialization and integration module and the input terminal of the leakage module respectively, the first input terminal of the asynchronous handshake communication module is connected to the first output terminal of the pulse issuance module; the output terminal of the initialization and integration module is grounded.
[0014] Optionally, the leakage module includes: a second D trigger, a third NMOS tube, and a fourth NMOS tube; wherein the input port d of the second D trigger is connected to a high-level signal, and the output port Q of the second D trigger is connected to the G pole of the third NMOS tube; the D pole of the third NMOS tube is the input end of the leakage module, the S pole of the third NMOS tube is connected to the D pole of the fourth NMOS tube, the G pole of the fourth NMOS tube is connected to the second control signal, and the S pole of the fourth NMOS tube is grounded.
[0015] Optionally, the pulse issuing module includes: a first PMOS tube, a first NMOS tube and a second NMOS tube, a comparator, a first NOR gate, a first D flip-flop and a third D flip-flop, a second AND gate and a third AND gate;
[0016] The comparison port of the comparator is the first input terminal of the pulse issuing module, and the D pole of the first PMOS tube is connected to the voltage source port of the comparator;
[0017] The output end of the comparator is connected to the first input end of the first NOR gate, and the second input end of the first NOR gate is connected to the setting control signal;
[0018] The output port of the first NOR gate is connected to the clock port CP of the first D flip-flop, and the output port Q of the first D flip-flop is connected to the first input port of the second AND gate;
[0019] The output port bc of the second AND gate is respectively connected to the G pole of the second NMOS tube, the first input port of the third AND gate and the clock port CP of the third D flip-flop;
[0020] The value inverting output port QN of the third D flip-flop is connected to the second input port of the third AND gate, and the output port of the third AND gate outputs a pulse signal;
[0021] The G pole of the first NMOS tube is connected to the first control signal, the S pole of the first NMOS tube is connected to the D pole of the second NMOS tube, and the S pole of the second NMOS tube is grounded.
[0022] Optionally, the asynchronous handshake communication module includes a second NOR gate and a first AND gate; the second input port of the second NOR gate is connected to the output port of the first NOR gate, the output port of the second NOR gate is connected to the first input port of the first AND gate, and the output port of the first AND gate outputs an asynchronous handshake signal.
[0023] Optionally, the initialization and integration module includes: a bidirectional transmission gate and a capacitor; the first input port of the bidirectional transmission gate is the first input end of the initialization and integration module, the second input port of the bidirectional transmission gate is the second input end of the initialization and integration module, and the second input port of the bidirectional transmission gate is connected to the positive end of the capacitor; the negative end of the capacitor is the output end of the initialization and integration module.
[0024] Optionally, the positive end of the capacitor is also connected to the current input signal and the first input end of the pulse issuing module; wherein the first input end of the pulse issuing module is the D pole of the first NMOS tube.
[0025] The beneficial effects brought about by the technical solutions provided by some embodiments of the present application include at least:
[0026] 1. It realizes the accumulation, leakage and emission functions similar to biological neurons, and effectively enhances the computing power and efficiency of the system by simulating the dynamic change process of the potential of biological neurons;
[0027] 2. By introducing an asynchronous handshake processing mechanism to process asynchronous pulse input signals, the overall power consumption of the circuit is reduced to a certain extent;
[0028] 3. By adopting a mixed digital-analog design approach, the circuit's noise resistance and performance are improved while the circuit implementation cost is effectively reduced.
[0029] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or understood by practicing the present application. The purpose and other advantages of the present application are realized and obtained by the structures specifically pointed out in the description, claims and drawings.
[0030] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings.
[0031] Advantages of additional aspects of the present application will be given in part in the following description, and in part will become apparent from the following description, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0033] Figure 1 A neuron circuit with asymmetric output characteristics in the existing solution shown in this application;
[0034] Figure 2 A wiring diagram of a neuron circuit based on an asynchronous pulse paradigm shown in an embodiment of the present application;
[0035] Figure 3 This is a working timing diagram of a neuron circuit based on an asynchronous pulse paradigm shown in an embodiment of the present application. DETAILED DESCRIPTION
[0036] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.
[0037] When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Instead, they are only examples of methods and systems consistent with some aspects of the present application as detailed in the attached claims.
[0038] In the description of the present application, it should be understood that the terms "first", "second", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to the specific circumstances. In addition, in the description of the present application, unless otherwise specified, "multiple" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the previously associated objects are in an "or" relationship.
[0039] Existing neural circuits almost all adopt the synchronous design paradigm, which controls the coordinated work between various modules by introducing a global clock signal; however, as integrated circuit technology gradually penetrates into the deep submicron level, the synchronous design paradigm faces multiple challenges, such as complex timing allocation, limited working speed, high power consumption, and difficulty in synchronizing the working status of various modules; at the same time, since the biological nervous system itself has event-driven characteristics, it will work when a pulse arrives and there will be no activity at other times, that is, no additional energy consumption. Therefore, neural circuits based on the synchronous design paradigm may not fit the actual biological working mechanism.
[0040] In addition, most neuronal circuits include current accumulation units, pulse emission units, and voltage reset units, which can accumulate the sum of synaptic excitations and release pulses when the membrane voltage of the neuron is higher than the threshold, while resetting the membrane voltage to the resting value; in fact, biological neurons also have a "leakage" characteristic, and their membrane voltage will gradually return to the resting potential when no new stimulus input is received. This characteristic can help regulate the activation state of neurons, filter out background noise, and prevent over-activation, thereby ensuring that neurons remain highly sensitive and responsive to new and important signals. Therefore, neuronal circuits that lack the "leakage" characteristic cannot better mimic biological dynamic behavior, and may face problems such as over-saturation of signal responses, reduced ability to distinguish important and secondary information, and low energy efficiency and reduced processing accuracy due to continuous activation.
[0041] At present, neuron circuits are generally divided into two categories: analog and digital. The analog type directly simulates the accumulation of synaptic excitation by the membrane capacitor of biological neurons through the accumulation of current by capacitors. It can achieve a high degree of integration, but the circuit stability is low and the dynamic characteristics of neurons that can be achieved are limited. The digital type uses multi-bit accumulators, multipliers, and control units to simulate the accumulation of synaptic excitation by membrane capacitors. It has a short development cycle and strong anti-interference ability, but occupies a large area.
[0042] Existing solutions such as Figure 1 As shown, it is constructed only by PMOS transistors, NMOS transistors and capacitors, including basic components such as inverters and current mirrors, which can simplify circuit design and manufacturing processes, help reduce device size and reduce costs; the current signal from the synaptic structure charges the capacitor marked as C1 (C1 acts as the body cell of the biological neuron) to realize the signal integration function of the neuron; when the voltage of C1 exceeds the set threshold value V TH When the N6 MOS tube is turned on first, the output V OUT At the same time, the second inverter of the two inverter stages in series starts to work and outputs V OUTPull up to VDD, so as to achieve asymmetric output of pulses; finally, the N7 MOS tube will be turned on to reset the voltage of C1 to the resting potential, in preparation for receiving the next round of current signals. The asymmetric output structure introduced in this neuron circuit can more accurately simulate the action potential of biological neurons, improve the recognition accuracy and reliability of signal timing, and may reduce the number of pulses required to transmit the same information between neurons. This circuit is an analog circuit that is easily affected by the environment. It does not have a leakage function and cannot more comprehensively simulate the dynamic behavior of biological neurons. In addition, it adopts a synchronous design paradigm, which results in high power consumption when pulse events are sparse.
[0043] To solve the above problems, this application provides the following technical solutions:
[0044] A neuron circuit based on an asynchronous pulse paradigm, comprising:
[0045] Initialization and integration module, used to calculate the membrane voltage of neurons and realize the accumulation function in the calculation process;
[0046] Specifically, the initialization and integration module implements the “accumulation” function in the form of charge;
[0047] In a feasible specific implementation scheme, it includes: a bidirectional transmission gate and a capacitor; the first input port of the bidirectional transmission gate is the first input terminal of the initialization and integration module, the second input port of the bidirectional transmission gate is the second input terminal of the initialization and integration module, and the second input port of the bidirectional transmission gate is connected to the positive end of the capacitor; the negative end of the capacitor is the output terminal in the initialization and integration module, and the membrane voltage here is the voltage across the capacitor.
[0048] The pulse issuing module is used to determine whether the membrane voltage of the neuron reaches a preset threshold and decide the pulse issuing according to the judgment result;
[0049] In a feasible specific implementation scheme, it includes: a first PMOS transistor, a first NMOS transistor and a second NMOS transistor, a comparator, a first NOR gate, a first D flip-flop and a third D flip-flop, a second AND gate and a third AND gate;
[0050] The comparison port of the comparator is the first input terminal of the pulse issuing module, and the D pole of the first PMOS tube is connected to the voltage source port of the comparator;
[0051] The output end of the comparator is connected to the first input end of the first NOR gate, and the second input end of the first NOR gate is connected to the set reset signal;
[0052] The output port of the first NOR gate is connected to the clock port CP of the first D flip-flop, and the output port Q of the first D flip-flop is connected to the first input port of the second AND gate;
[0053] The output port bc of the second AND gate is respectively connected to the G pole of the second NMOS tube, the first input port of the third AND gate and the clock port CP of the third D flip-flop;
[0054] The value inverting output port QN of the third D flip-flop is connected to the second input port of the third AND gate, and the output port of the third AND gate outputs a pulse signal;
[0055] The G pole of the first NMOS tube is connected to the first control signal, the S pole of the first NMOS tube is connected to the D pole of the second MOS tube, and the S pole of the second NMOS tube is grounded.
[0056] The leakage module is used to simulate the natural decay process of the membrane voltage of neurons when there is no stimulation input;
[0057] In a feasible specific implementation scheme, the leakage module includes: a second D trigger, a third NMOS tube, and a fourth NMOS tube; wherein the input port d of the second D trigger is connected to a high-level signal, and the output port Q of the second D trigger is connected to the G pole of the third NMOS tube; the D pole of the third NMOS tube is the input end of the leakage module, the S pole of the third NMOS tube is connected to the D pole of the fourth NMOS tube, the G pole of the fourth NMOS tube is connected to the second control signal, and the S pole of the fourth NMOS tube is grounded.
[0058] An asynchronous handshake communication module is used to send a handshake signal to the pulse issuing module and the leakage module after the initialization and integration modules complete the accumulation to realize an asynchronous working mechanism;
[0059] Among them, the first input terminal of the initialization and integration module is connected to the set voltage, the first input terminal of the pulse issuance module is connected to the second input terminal of the initialization and integration module and the input terminal of the leakage module respectively, the first input terminal of the asynchronous handshake communication module is connected to the first output terminal of the pulse issuance module; the output terminal of the initialization and integration module is grounded.
[0060] Specifically, in a feasible implementation scheme, the asynchronous handshake communication module includes a second NOR gate and a first AND gate; the second input port of the second NOR gate is connected to the output port of the first NOR gate, the output port of the second NOR gate is connected to the first input port of the first AND gate, and the output port of the first AND gate outputs an asynchronous handshake signal.
[0061] During the specific implementation process, the positive end of the capacitor is also connected to the current input signal and the first input end of the pulse issuing module; wherein the first input end of the pulse issuing module is the D pole of the first NMOS tube.
[0062] In order to further explain the neuron circuit of the present application, a specific example is now given, referring to Figure 2, where the second D flip-flop is D2, the third NMOS tube is N3, the fourth NMOS tube is N4, the first PMOS tube is P1, the first NMOS tube is N1, the second NMOS tube is N2, the comparator is Comp, the first NOR gate is NOR1, the first D flip-flop is D1 and the third D flip-flop is D3, the second AND gate is AND2 and the third AND gate is AND3, the second NOR gate is NOR2, the first AND gate is AND1, the bidirectional transmission gate is Tgate1, and the capacitor is C mem The specific composition and principle are introduced as follows:
[0063] The initialization and integration module consists of a bidirectional transmission gate Tgate1 and a capacitor C mem The upper and lower control ports of Tgate1 are connected to the PRst and PRst_n signals respectively. In addition, one of its input ports (i.e., the first input port of the bidirectional transmission gate in the embodiment) is connected to the voltage Vset, and the other input port (i.e., the second input port of the bidirectional transmission gate) is connected to C mem In addition, C mem The positive end is also connected to the current input signal I(t), a comparison port of the comparator Comp, the D pole of the NMOS transistor N1, and the D pole of the NMOS transistor N3, and its negative end is connected to the ground signal VG.
[0064] The leakage module consists of a D flip-flop D2 and two NMOS transistors N3 and N4. The numerical input port d of D2 is connected to tiehi (fixed high-level signal), the clock port CP is connected to the trigger signal, the reset port rst is connected to the set signal, and the numerical output port Q, i.e. c_leak, is connected to the G pole of N3. The S pole of N3 and the D pole of N4 are connected to each other. The G pole of N4 is connected to the control signal ctrl2 (i.e. the second control signal), which is a manually set voltage value that can be adjusted to control the leakage rate of the membrane voltage; its S pole is connected to VG.
[0065] The pulse module consists of a PMOS tube P1, two NMOS tubes N1 and N2, a comparator Comp, a NOR gate NOR1, two D flip-flops D1 and D3, and two AND gates AND2 and AND3. Comp has three input ports, Vmem is used as the input voltage of the comparator's comparison port, Vth is connected to Comp as the reference comparison voltage, and a bias voltage port is also configured, which is connected to the D pole of P1, while the G pole of P1 is connected to the Set_comp signal, and the S pole of P1 is connected to the voltage source VP. The output of the comparator is y <0> The output port y of NOR1 is connected to an input port of NOR1 (i.e., the first input port of the first NOR gate in the embodiment), and the other input port of NOR1 (i.e., the second input port of the first NOR gate in the embodiment) is connected to a reset signal set, which controls the operation of the entire neuron circuit. <1> (i.e. the output port of the first NOR gate) is connected to the clock port of D1, while the numerical input port d of D1 is connected to tiehi, the reset port rst is connected to the Set_comp signal, and the numerical output port Q is also y <2> Connect to one input port of AND2 (i.e., the first input port of the second AND gate). The other input port of AND2 is connected to the Set_compn signal, and its output port bc is simultaneously connected to the G pole of N2, an input port of AND3 (i.e., the first input port of the third AND gate), and the clock port CP of D3. The numerical input port d of D3 is connected to tiehi, the reset port rst is connected to the set signal, the numerical inverted output port QN, i.e., qn, is connected to the other input port of AND3 (i.e., the second input port of the third AND gate), and the output port of AND3 outputs the pulse signal Out_pulse. The G pole of N1 is connected to the control signal ctrl1 (the first control signal), which is a manually set voltage value that can be adjusted to control the reset rate when the membrane potential reaches the threshold; the S pole of N1 and the D pole of N2 are connected to each other, and the S pole of N2 is connected to VG.
[0066] The asynchronous handshake communication module consists of a NOR gate NOR2 and an AND gate AND1. One input port of NOR2 is connected to the Set_comp signal, the other input port (i.e., the second input port of the second NOR gate) is connected to the output port of NOR1, and its output port is connected to one input port of AND1 (i.e., the first input port of the first AND gate). The other input port of AND1 is connected to trigger, and its output port outputs the asynchronous handshake signal Ack.
[0067] The working process of the neuron circuit of this application is divided into three stages: (1) initialization stage. (2) signal processing stage. (3) asynchronous handshake communication stage. The working sequence is as follows: Figure 3 As shown;
[0068] The working principle of the neuron circuit in the embodiment of the present application will be gradually introduced below:
[0069] (1) Initialization phase
[0070] During the initialization phase, the control signal PRst that activates the bidirectional transmission gate will act as the capacitance (C mem )Voltage mem Charge to the initial membrane voltage value V set , so that the neuron is in a resting state and ready for subsequent neural activity. Here the capacitor C mem The voltage on is the membrane voltage in this application.
[0071] (2) Signal processing stage
[0072] During the signal processing phase, the control signal PRst is disabled until the neuron capacitor voltage V needs to be reinitialized. mem At the same time, when the presynaptic neuron outputs a pulse signal, the Set_comp signal is turned on to allow the neuron in the neuron circuit to work, and before it starts working, the set signal is briefly turned on to reset the status of each module in the neuron circuit. In addition, the control signal ctrl1 is used to control the G pole voltage of the NMOS transistor N1. When C mem When it is necessary to restore to the resting potential, the voltage value of ctrl1 can be changed to change C mem The discharge rate of the control signal ctrl2 is used to control the G pole voltage of the NMOS transistor N4, and the C mem The control signal trigger is used to determine whether the amount of charge provided by the synaptic structure reaches a predetermined value. If so, the trigger will present a short pulse state.
[0073] The output pulse from the presynaptic neuron is multiplied by the corresponding synaptic weight value, and the accumulated current is continuously fed to the capacitor C mem Charging to achieve the "accumulation" function, since synapses have two types: excitatory and inhibitory, the capacitor C mem The voltage V obtained by accumulating charge mem It may increase or decrease. mem During the charging process, the voltage value V mem With the threshold value V set th The comparison is made through the comparator Comp. In addition, when the neuron is inactive, the PMOS transistor P1 will stop the operation of Comp to reduce the power consumption of the circuit. mem Higher than V thThen Comp outputs a high level (y <0> =1), and at the same time, D flip-flop D1 detects y <1> The rising edge of y <2> is set to tiehi (tiehi is high level), which makes bc output high level and turns on NMOS transistor N2. mem It will discharge to the ground, i.e. the quiescent potential, through the path formed by N1 and N2, and Comp will output a low level (y <0> =0). At the same time, the D flip-flop D3 detects the rising edge of bc, so qn outputs a low level, and then acts on the bc signal through the AND gate AND3 to briefly output a pulse signal Out_pulse, to achieve a "firing" function similar to that of biological neurons. mem Lower than V th Then Comp outputs a low level (y <0> =0), so D1 does not detect y <1> The rising edge of y <2> Maintaining a low level, the N2 transistor continues to be turned off, blocking C mem The discharge path does not send the pulse signal Out_pulse.
[0074] When the control signal trigger reaches a high level, the D flip-flop D2 detects the rising edge of trigger and the output c_leak is high, thereby turning on the NMOS transistor N3. mem The pathway formed by N3 and N4 gradually decays to the resting potential over time, achieving a "leakage" function similar to that of biological neurons.
[0075] (3) Asynchronous handshake communication phase
[0076] In the asynchronous handshake communication phase, when the output y of the comparator Comp <0> When the neuron is in working state and the control signal trigger is high, the asynchronous handshake signal Ack is activated and rises to a high level, and the Set_comp signal is turned off to stop the neuron from working, realizing an asynchronous handshake operation, waiting for the next output pulse signal of the front neuron to arrive before working again, that is, the Set_comp signal is activated again, and before that, the set signal is briefly activated to make y <2> , qn, and c_leak are reset to a low level to ensure the stability of subsequent work.
[0077] The main advantages of this application example over existing solutions are:
[0078] (1) Existing solutions rely on a global clock to synchronize signals, which is not only prone to clock offset, but can also cause electromagnetic interference and face scalability challenges when integrated on a large scale. This example uses asynchronous handshake control signals to allow neuron circuits to work independently without a global clock. This design is closer to the event-driven mechanism of biological nervous systems, improves the flexibility and reliability of signal processing, and also reduces design complexity, making the circuit easier to expand and integrate.
[0079] (2) The existing scheme design lacks the simulation of the "leakage" behavior of biological neurons, which limits the authenticity of the circuit's dynamic behavior and causes the circuit's stability to decrease when there is no signal input. This example simulates the natural decay process of the neuron's potential when there is no stimulation by introducing the "leakage" function. This not only increases the biological authenticity of the circuit, but also helps reduce the interference of irrelevant signals and improves the long-term stability of the circuit, making it more accurate and effective in simulating complex neural dynamics.
[0080] (3) Existing solutions are sensitive to environmental factors and are easily affected by temperature and voltage changes, which poses an obstacle to accurate signal processing and large-scale integration. The digital-analog hybrid design in this example combines the high stability of digital circuits with the rich dynamic characteristics of analog circuits. This hybrid approach not only improves the robustness of the circuit and reduces the impact of external interference, but also optimizes power consumption and area, making it possible to build a high-density, low-energy neural network.
[0081] The present application provides a neuron circuit based on an asynchronous pulse paradigm, the design of which realizes the accumulation, leakage and emission functions similar to those of biological neurons, and effectively enhances the computing power and efficiency of the system by simulating the dynamic change process of the potential of biological neurons. In addition, the circuit introduces an asynchronous handshake processing mechanism to process asynchronous pulse input signals, thereby reducing the overall power consumption of the circuit to a certain extent. Moreover, since the present invention adopts a digital-analog hybrid design method, the anti-noise ability of the circuit is improved, and the performance of the circuit is further improved while reducing the implementation cost of the circuit. Neuron circuits are of great significance to the construction of brain-like computing circuits. The present invention provides an effective way to achieve more efficient and low-power neural network computing, and lays a solid foundation for building an artificial intelligence system that is close to the computing power of the human brain.
[0082] Although this specification is described according to implementation modes, not every implementation mode includes only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.
[0083] In the description of the present application, it should be noted that relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, invention, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, invention, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, invention, article or device including the elements.
[0084] Therefore, the above description is only a preferred embodiment of the present application and is not intended to limit the scope of implementation of the present application; that is, all equivalent changes made according to the scope of the claims of the present application are within the protection scope of the claims of the present application.
[0085] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present application, which are used to illustrate the technical solutions of the present application, rather than to limit them. The protection scope of the present application is not limited thereto. Although the present application is described in detail with reference to the above-mentioned embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-mentioned embodiments within the technical scope disclosed in the present application, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.
[0086] The applicant of this application has made a detailed explanation and description of the implementation examples of this application in conjunction with the drawings in the specification. However, those skilled in the art should understand that the above implementation examples are only preferred implementation schemes of this application, and the detailed description is only to help readers better understand the spirit of this application, and it is not a limitation on the scope of protection of this application. On the contrary, any improvements or modifications based on the inventive spirit of this application should fall within the scope of protection of this application.
Claims
1. A neuron circuit based on an asynchronous pulse paradigm, characterized in that: include: Initialization and integration module, used to calculate the membrane voltage of neurons and realize the accumulation function in the calculation process; The pulse issuing module is used to determine whether the membrane voltage of the neuron reaches a preset threshold and decide the pulse issuing according to the judgment result; The leakage module is used to simulate the natural decay process of the membrane voltage of neurons when there is no stimulation input; An asynchronous handshake communication module is used to send a handshake signal to the pulse issuing module and the leakage module after the initialization and integration modules complete the accumulation to realize an asynchronous working mechanism; Among them, the first input terminal of the initialization and integration module is connected to the set voltage, the first input terminal of the pulse issuance module is respectively connected to the second input terminal of the initialization and integration module and the input terminal of the leakage module, the first input terminal of the asynchronous handshake communication module is connected to the first output terminal of the pulse issuance module; the output terminal of the initialization and integration module is grounded.
2. The neuron circuit based on the asynchronous pulse paradigm according to claim 1, characterized in that: The leakage module includes: a second D trigger, a third NMOS tube, and a fourth NMOS tube; wherein the input port d of the second D trigger is connected to a high-level signal, and the output port Q of the second D trigger is connected to the G pole of the third NMOS tube; the D pole of the third NMOS tube is the input end of the leakage module, the S pole of the third NMOS tube is connected to the D pole of the fourth NMOS tube, the G pole of the fourth NMOS tube is connected to the second control signal, and the S pole of the fourth NMOS tube is grounded.
3. The neuron circuit based on the asynchronous pulse paradigm according to claim 1, characterized in that: The pulse issuing module includes: a first PMOS tube, a first NMOS tube and a second NMOS tube, a comparator, a first NOR gate, a first D flip-flop and a third D flip-flop, a second AND gate and a third AND gate; The comparison port of the comparator is the first input terminal of the pulse issuing module, and the D pole of the first PMOS tube is connected to the voltage source port of the comparator; The output end of the comparator is connected to the first input end of the first NOR gate, and the second input end of the first NOR gate is connected to the set reset signal; The output port of the first NOR gate is connected to the clock port CP of the first D flip-flop, and the output port Q of the first D flip-flop is connected to the first input port of the second AND gate; The output port bc of the second AND gate is respectively connected to the G pole of the second NMOS tube, the first input port of the third AND gate and the clock port CP of the third D flip-flop; The value inverting output port QN of the third D flip-flop is connected to the second input port of the third AND gate, and the output port of the third AND gate outputs a pulse signal; The G pole of the first NMOS tube is connected to the first control signal, the S pole of the first NMOS tube is connected to the D pole of the second NMOS tube, and the S pole of the second NMOS tube is grounded.
4. The neuron circuit based on the asynchronous pulse paradigm according to claim 1, characterized in that: The asynchronous handshake communication module includes a second NOR gate and a first AND gate; the second input port of the second NOR gate is connected to the output port of the first NOR gate, the output port of the second NOR gate is connected to the first input port of the first AND gate, and the output port of the first AND gate outputs an asynchronous handshake signal.
5. The neuron circuit based on the asynchronous pulse paradigm according to claim 1, characterized in that: The initialization and integration module comprises: a bidirectional transmission gate and a capacitor; the first input port of the bidirectional transmission gate is the first input end of the initialization and integration module, the second input port of the bidirectional transmission gate is the second input end of the initialization and integration module, the second input port of the bidirectional transmission gate is connected to the positive end of the capacitor; the negative end of the capacitor is the output end of the initialization and integration module.
6. The neuron circuit based on the asynchronous pulse paradigm according to claim 5, characterized in that: The positive end of the capacitor is also connected to the first input end of the current input signal and pulse distribution module; The first input terminal of the pulse issuing module is the D pole of the first NMOS tube.