Memory block-based memory
By designing a memory block-based structure in memory and selecting memory units using DC SA and decoder, the problem that existing memory cannot activate a large number of SAs when data is read is solved, achieving faster data read and write speeds and higher compatibility.
Patent Information
- Application Number
- CN202411433541.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-14
- Publication Date
- 2025-03-07
AI Technical Summary
When existing memory reads data, it is impossible to activate a large number of DC sensing amplifiers (SAs) at the same time, resulting in slow data reading and writing speeds and incompatible with DDR4's page mode.
A memory based on memory block is designed, using DC SA, the memory units that need to be read or written are selected through the row decoder and the column decoder, and the data reading and writing operations are realized using a data latch and a write header.
It improves the data reading and writing speed of the memory, saves electricity, and is compatible with the page mode of DDR4, achieving faster data transmission rates.
Smart Images
Figure CN119580792A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of integrated circuits, and in particular to a memory based on a storage block. Background Art
[0002] DDR4 (Double Data Rate 4 Synchronous Dynamic Random Access Memory) is a commonly used memory. Figure 7 This is a circuit diagram of a memory cell (Cell) and a SA (sense amplifier) in DDR4. Figure 7 Only one memory cell and one SA are shown, but there are multiple memory cells and multiple SAs in the actual DDR4 memory array. Typically, each row of the memory array has thousands of memory cells connected to the same WL (WordLine). Each column of the memory array has thousands of memory cells connected to the same BL (Bit Line). In addition, there is an SA connected between each BL pair (Bit Line Pair), that is, BL and BL / (complementary bit line). The SA consists of a simple cross-coupled inverter pair, each SA includes four transistors M2, M3, M4 and M5. Each memory cell includes a transistor M6 and a capacitor C.
[0003] During DDR4 standby mode, SA is disabled by raising the voltage of SetP to Vdd (operating voltage) and pulling the voltage of SetN down to GND (ground). BL and BL / are connected together and precharged to 1 / 2 Vdd. When DDR4 starts a read operation, BL and BL / are disconnected from the precharge voltage and become floating. The voltage on WL is raised to turn on transistor M7. Figure 7 As shown, if the data stored in the memory cell is 1, that is, the capacitor C is full of charge, charge sharing occurs between BL and the capacitor C. Because the charge in the memory cell is added to BL, the BL voltage begins to rise, making the voltage of BL slightly higher than the voltage of BL / , about 100mV. SA detects this voltage difference, then transistor M1 is turned off and transistor M6 is turned on, thereby activating SA and raising the voltage of point Q to Vdd by setting BL to Vdd and BL / to GND, that is, latching data 1. Data 1 is then transmitted to the data I / O (input-output port).
[0004] In this read operation, the data 1 stored in the memory cell is lost due to charge sharing with BL, which is called destructive read. Therefore, in order to recover the read data, the data needs to be written back to capacitor C. Keeping transistor M7 turned on, the latched data 1 is automatically written back to capacitor C through BL. In this way, the entire read operation is completed.
[0005] For the case where the data stored in the memory cell is 0, it is similar to the case where the data stored is 1 as mentioned above and will not be repeated here. Here, the BL is floating during sensing, so the cross-coupled inverter pair can be used as a SA in the absence of a DC current, and it is suitable for narrow BL spacing, and the BL can also write the read data back to the capacitor C. Typically, for Gb-level memories, that is, memories including billions of memory cells, 16K (16,000) SAs can be activated in a single row access. In each row access with a typical cycle time of 50ns, 16Kb (ie 2KB) of data is latched, which means a bandwidth of 40GB / s. Based on this principle, DDR4 can have very fast data read and write speeds.
[0006] However, some other memories, such as PCM (Phase Change Memory), ReRAM (Resistive Random Access Memory), and STT-MRAM (Spin Transfer Torque Magnetic Random Access Memory), cannot use SA like DDR4 because the BL is not floating when these memories are reading data. The storage cells of these memories need to obtain DC current through the BL. Therefore, the SA of these memories is usually a current mirror circuit with a relatively large area, which makes it impossible to place the SA between each BL pair. Therefore, these memories cannot activate as many SAs at the same time as DDR4, so it is impossible to use a page-based access mode like DDR. Although a 256Mb / 1Gb STT MRAM similar to DDR3 / DDR4 has been recently announced, because it is difficult to implement a DDR-like page mode in the STT MRAM array, this STT MRAM has a very long delay and its data rate is much lower than SDRAM DDR3 / DDR4. In addition, this STT MRAM is also incompatible with the JEDEC (Joint Electron Device Engineering Council) standard in terms of performance, function and package pin configuration.
[0007] Therefore, the industry is in urgent need of a memory using direct current SA with fast data reading and writing speed. Summary of the invention
[0008] The present invention aims to provide a memory using direct current SA with fast data reading and writing speed.
[0009] The memory based on the memory block of the present invention comprises: a memory block group, a local data bus and a pre-decoder line electrically connected to the memory block group, a global data bus electrically connected to the local data bus, and a data input-output interface electrically connected to the global data bus, the memory block group comprises a plurality of memory blocks, the memory blocks comprise: a row decoder, a column decoder; and a plurality of memory sub-blocks; the number of memory sub-blocks in each memory block is equal to the burst length; the memory sub-block comprises: a memory array, which comprises a plurality of memory cells; a direct current sense amplifier, which is electrically connected to the memory array and used to read the data stored in the memory array; a write head, which is electrically connected to the memory array and used to write data into the memory cells of the memory array; and a data latch, which is electrically connected to the direct current sense amplifier and the write head; In a read operation, the row decoder and the column decoder select the storage unit to be read according to the row address and the column address transmitted from the pre-decoder line, the DC sense amplifier reads the read data in the selected storage unit, and sends the read data to the data latch for latching, and then transmits the read data to the data input-output interface through the local data bus and the global data bus. In a write operation, the row decoder and the column decoder select the storage unit to be written according to the row address and the column address transmitted from the pre-decoder line, the data input-output interface transmits the write data to the data latch for latching through the global data bus and the local data bus, and the write head writes the write data latched in the data latch into the selected storage unit.
[0010] The memory of the present invention can improve the data reading and writing speed of the memory and save electric energy. BRIEF DESCRIPTION OF THE DRAWINGS
[0011] Figure 1 is a schematic block diagram of a memory of the present invention.
[0012] Figure 2 It is a schematic block diagram of a storage block and a storage sub-block of the memory of the present invention.
[0013] Figure 3 It is a flow chart of the method for reading data from the memory of the present invention.
[0014] Figure 4 is a timing diagram of a read operation of the memory of the present invention.
[0015] Figure 5 It is a flowchart of the method of writing data into the memory of the present invention.
[0016] Figure 6 is a timing diagram of the write operation of the memory of the present invention.
[0017] Figure 7 This is a circuit diagram of a memory cell and SA in DDR4.
[0018] Explanation of symbols
[0019] 10 storage blocks
[0020] 11 Storage sub-blocks
[0021] 12 DC SA
[0022] 13WH
[0023] 14 Data latch
[0024] 15 Storage Array
[0025] 100 storage block groups
[0026] 101 Local Data Bus
[0027] 102 pre-decoder line
[0028] 103 Global Data Bus
[0029] 200 data I / O DETAILED DESCRIPTION
[0030] The memory and data reading and writing method thereof of the present invention will be described in detail below with reference to the accompanying drawings. Figure 1 is a schematic block diagram of the memory of the present invention. Figure 1 As shown, the memory of the present invention comprises: a memory block group 100, a local data bus 101 and a pre-decoder line 102 electrically connected to the memory block group 100, a global data bus 103 electrically connected to the local data bus 101, and a data I / O 200 electrically connected to the global data bus 103. The memory in this embodiment is PCM, but the present invention is not limited thereto. In other embodiments, it may be other memories using direct current SA. In this embodiment, the local data bus 101 and the pre-decoder line 102 extend in the horizontal direction, and the global data bus 103 extends in the vertical direction. The global data bus 103 is universal for reading and writing, but the present invention is not limited thereto. In other embodiments, it may also be a separate read bus and write bus.
[0031] The storage block group 100 includes a plurality of storage blocks 10. In this embodiment, each storage block group 100 includes 8 storage blocks 10. In other embodiments, the number of storage blocks 10 may also be other values.
[0032] Figure 2 Schematic block diagram of a memory block and a memory sub-block of the memory of the present invention. Figure 2 As shown, the storage block 10 includes: a row decoder, a column decoder, and a plurality of storage sub-blocks 11. The number of storage sub-blocks 11 in each storage block 10 is equal to the burst length. The memory of this embodiment adopts a DDR4-like mode, and the burst length is 8, so each storage block 10 of the memory of this embodiment includes 8 storage sub-blocks 11.
[0033] The storage sub-block 11 includes: a storage array 15, which includes a plurality of storage cells; a direct current SA 12, which is electrically connected to the storage array 15 and is used to read data stored in the storage array 15; a WH (write head) 13, which is electrically connected to the storage array 15 and is used to write data into the storage cells of the storage array 15; and a data latch 14, which is electrically connected to the direct current SA 12 and the WH 13.
[0034] In the read operation, the row decoder and the column decoder select the storage unit to be read according to the row address and the column address transmitted from the pre-decoder line 102, the DC SA 12 reads the read data in the selected storage unit, and sends the read data to the data latch 14 for latching, and then transmits the read data to the data I / O 200 through the local data bus 101 and the global data bus 103.
[0035] In a write operation, the row decoder and the column decoder select the storage unit to be written according to the row address and the column address transmitted from the pre-decoder line 102, the data I / O 200 transmits the write data to the data latch 14 through the global data bus 103 and the local data bus 101 for latching, and the WH 13 writes the write data latched in the data latch 14 into the selected storage unit.
[0036] Specifically, the memory block 10 further includes: a plurality of WLs, a plurality of BLs, a control circuit and a timing circuit.
[0037] The memory cells of each row in the memory array 15 are electrically connected to a WL, and the memory cells of each column are electrically connected to a BL. The row decoder is electrically connected to the plurality of WLs, and is used to select the WL according to the row address transmitted from the pre-decoder line 102. The column decoder is electrically connected to the plurality of BLs, and is used to select the BL according to the column address transmitted from the pre-decoder line 102. Based on the selected WL and BL, the memory cell to be read or the memory cell to be written is selected.
[0038] The number of BLs in each storage sub-block 11 depends on the density of the memory chip, which is in the megabit (Mb) or gigabit (Gb) level. Usually, there are 64 to 512 BLs in each storage sub-block 11 , and these BLs share one DC SA 12 and one WH 13 .
[0039] The following describes the method for reading and writing data in the memory of the present invention.
[0040] First, the method of data reading is described. Figure 3 is a flow chart of a method for reading data from a memory of the present invention, such as Figure 3 As shown, the data reading method of the memory of the present invention includes:
[0041] Address latching step S101: the row address and the column address are transmitted to the storage block 10 through the pre-decoder line 102, the storage block 10 latches the row address in the row decoder, latches the column address in the column decoder, and then the storage block 10 disconnects from the pre-decoder line 102. In this embodiment, the row address and the column address are issued by the pre-decoder arranged outside the storage block 10, and the pre-decoder transmits the row address and the column address to the storage block 10 through the pre-decoder line 102.
[0042] Data reading step S102: The storage unit to be read is selected according to the row address and the column address, the DC SA 12 corresponding to the selected storage unit reads the read data stored in the selected storage unit, and latches the read data in the data latch 14 corresponding to the selected storage unit, and then sends the read data to the local data bus 101.
[0043] In this embodiment, the row decoder selects a WL of the storage block 10 according to the row address, such as Figure 2 The column decoder selects 8 BLs of the storage block 10 according to the column address, as shown in FIG. Figure 2 As shown by the vertical dotted line in . Because the memory of this embodiment adopts a DDR4-like mode, there are 8 BLs in this embodiment. However, the present invention is not limited to this, and in other embodiments, it can also be other numbers. In this way, 8 storage cells can be selected on the selected WL. Then the 8 DC SAs 12 corresponding to the 8 storage cells read the data stored in the 8 storage cells, and latch the read 8 data in the corresponding 8 data latches 14 respectively, and then send the 8 data to the local data bus 101.
[0044] Standby step S103: the memory block 10 reconnects to the pre-decoder line 102 and enters a standby state, waiting for the pre-decoder line 102 to transmit the next row address and column address.
[0045] Transmission step S104: 8 read data are transmitted to the data I / O 200 via the local data bus 101 and the global data bus 103. Because the memory of this embodiment adopts a DDR4-like mode, and the global data bus 103 of the DDR4 mode is just 8 bits wide, it can just transmit these 8 read data.
[0046] Therefore, through the memory and the data reading method of the present invention, during the reading process, for one data I / O 200, only 8 DC SAs 12 need to be activated, instead of activating 16K SAs like the existing DDR4, which can save a lot of power.
[0047] Figure 4 is a timing diagram of the read operation of the memory of the present invention. Figure 4 As shown, after the first row address and the first column address are issued, the storage block 10 starts the data reading step S102. In actual operation, the row address is usually sent first, and then the column address is sent. Therefore, after the first column address (column address 1) is issued, and after a period of delay, the column address 1 reaches the storage block 10, and then the storage block 10 starts the data reading step S102. The duration of the data reading step S102 is called the read cycle Tr. After the read cycle Tr, the storage block 10 sends the read data to the local data bus 101. Then after a period of time, the read data is transmitted to the data I / O 200 through the local data bus 101 and the global data bus 103. That is, after the column address 1 is issued, after CASL (Column Address Strobe latency, column address selection pulse delay), the read data is transmitted to the data I / O 200. In addition, Figure 4 The tCCD (CAS to CASDelay) in the figure represents the interval time between two column addresses.
[0048] Since the memory block 10 disconnects the pre-decoder line 102 once the row address and column address are latched, the next address can be sent while the memory block 10 is reading data. Figure 4 It can be seen that the storage block 10 is still in the first read cycle Tr, that is, the column address 2 has been issued before the first data reading step S102 is completed.
[0049] Preferably, the duration of the read cycle Tr is less than or equal to the time for the read data to be transmitted at the data I / O 200, and the sending time of the column address is controlled so that when the next set of read data is transmitted to the data I / O 200, the data I / O 200 has just completed the transmission of the previous set of read data.
[0050] like Figure 4As shown, in this embodiment, the time for transmitting 8 data (8-bit burst data) at the data I / O 200 is 5ns, and the read cycle Tr is also 5ns. And the sending time of the column address 2 is controlled so that after the column address 2 is sent, after the CASL, when the second group of read data arrives at the data I / O 200, the data I / O 200 just completes the transmission of the first group of read data. In this way, a seamless continuous burst mode can be achieved. That is, data is always being transmitted at the data I / O 200. Generally speaking, when the memory implements a seamless continuous burst mode, the data rate becomes the maximum.
[0051] although Figure 4 What is shown in is the column address, but if the row and column addresses are provided at the same time, the storage block 10 only needs to process different row addresses and column addresses for each read operation to achieve seamless continuous burst. Therefore, this means that seamless continuous burst mode can be achieved through random row access. In other words, it can maintain the maximum data rate of any random row address access, that is, 3200MB / s. Compared with DDR, this is a significant advantage. For example, a read cycle of DDR4 is typically 50ns, so the random row access data rate is 1 / 10 of the maximum data rate (5ns / 50ns), which is only 320MB / s. Therefore, using the memory and data reading method of the present invention, a faster reading speed can be obtained.
[0052] The method of data writing is described below. Figure 5 is a flow chart of a method for writing data into a memory of the present invention, as shown in Figure 5 As shown, the method for writing data into a memory of the present invention comprises:
[0053] Address latching step S201 : sending the row address and column address to the storage block 10 through the pre-decoder line 102 , the storage block 10 latches the row address in the row decoder, latches the column address in the column decoder, and then disconnects the pre-decoder line 102 .
[0054] Transmission step S202 : the data I / O 200 transmits 8 write data to the storage block 10 through the global data bus 103 and the local data bus 101 .
[0055] Data writing step S203: the storage unit to be written is selected according to the row address and the column address, and then the write data transmitted by the local data bus 101 is latched in the corresponding first data latch 14 or the second data latch 24, and finally the write data is written into the selected storage unit through the corresponding first WH 13 or the second WH 23.
[0056] In this embodiment, the row decoder selects a WL of the storage block 10 according to the row address, and the column decoder selects 4 first BLs and 4 second BLs of the storage block 10 according to the column address, thereby selecting 8 storage cells to be written, and then the 8 write data transmitted from the local data bus 101 are respectively latched in the 4 first data latches 14 and the 4 second data latches 24 corresponding to the selected 8 storage cells, and finally the 8 write data are written into the selected 8 storage cells through the corresponding 4 first WHs 13 and 4 second WHs 23.
[0057] Standby step S204: the memory block 10 reconnects to the pre-decoder line 102 and enters a standby state, waiting for the pre-decoder to send the next row address and column address.
[0058] Figure 6 1 is a timing diagram of the write operation of the memory of the present invention. Similar to the read operation, after the column address 1 is issued, after WCL (Write CAS Latency), the data I / O 200 sends 8 write data to the storage block 10 through the global data bus 103 and the local data bus 101, and the storage block 10 starts the data writing step S203. The duration of the data writing step S203 is called the write cycle Tw. In addition, after the column address 1 is issued, after tCCD, the column address 2 is issued, and so on.
[0059] Preferably, the write cycle Tw is less than or equal to the time for data transmission of the write data at the data I / O 200, and the sending time of the column address is controlled so that when the next set of write data arrives at the data I / O 200, the data I / O 200 has just completed the transmission of the previous set of write data.
[0060] like Figure 6 As shown, in this embodiment, the time for transmitting 8-bit burst data at the data I / O 200 is 5ns, and the write cycle Tw is also 5ns. And the sending time of column address 2 is controlled so that after the column address 2 is sent, after WCL, when the second group of write data arrives at the data I / O 200, the data I / O 200 just completes the transmission of the first group of write data. In this way, a seamless continuous burst mode can be achieved. That is, data is always being transmitted at the data I / O 200. Therefore, by using the memory and data writing method of the present invention, a faster write speed can be obtained.
[0061] Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Any professional and technical personnel in the field may make various necessary changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope defined by the attached claims.
Claims
1. A memory based on a storage block comprises: A storage block group (100), a local data bus (101) and a pre-decoder line (102) electrically connected to the storage block group (100), a global data bus (103) electrically connected to the local data bus (101), and a data input / output interface (200) electrically connected to the global data bus (103). The storage block group (100) comprises a plurality of storage blocks (10), wherein the storage block (10) comprises: a row decoder, a column decoder, and a plurality of storage sub-blocks (11), wherein the number of storage sub-blocks (11) in each storage block (10) is equal to the burst length; The storage sub-block (11) comprises: A storage array (15) comprising a plurality of storage cells; a direct current sensing amplifier (12), which is electrically connected to the storage array (15) and is used to read data stored in the storage array (15); a write head (13), which is electrically connected to the storage array (15) and is used to write data into storage cells of the storage array (15); and a data latch (14) electrically connected to the DC sense amplifier (12) and the write head (13); In a read operation, the row decoder and the column decoder select the storage unit to be read according to the row address and the column address transmitted by the pre-decoder line (102), the DC sense amplifier (12) reads the read data in the selected storage unit, sends the read data to the data latch (14) for latching, and then transmits the read data to the data input-output interface (200) through the local data bus (101) and the global data bus (103). In a write operation, the row decoder and the column decoder select the storage unit to be written according to the row address and the column address transmitted by the pre-decoder line (102), the data input-output interface (200) transmits the write data to the data latch (14) for latching through the global data bus (103) and the local data bus (101), and the write head (13) writes the write data latched in the data latch (14) into the selected storage unit.
2. The memory according to claim 1, wherein: The storage block (10) further comprises: a plurality of word lines, a plurality of bit lines, a control circuit and a timing circuit, The memory cells in each row of the memory array (15) are electrically connected to one of the word lines, and the memory cells in each column are electrically connected to one of the bit lines; The row decoder is electrically connected to the plurality of word lines and is used to select the word line according to the row address transmitted from the pre-decoder line (102); The column decoder is electrically connected to the plurality of bit lines and is used to select the bit lines according to the column address transmitted from the pre-decoder line (102); The memory cell to be read or the memory cell to be written is selected according to the selected word line and bit line.