A memory and its operation method, a memory system

Abstract

This disclosure provides a memory and its operation method, as well as a memory system. The memory includes: a memory cell array and peripheral circuitry coupled to the memory cell array; the memory cell array includes multiple memory blocks, each memory block including multiple memory strings; each memory string includes an upper select transistor, a memory cell, and a lower select transistor connected in series between a bit line and a source line; wherein all lower select transistors in the same memory block form a lower select transistor set; the peripheral circuitry is configured to: perform programming operations on the memory cells in the memory blocks; and perform erase operations on at least a portion of the lower select transistors in the lower select transistor set.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a memory and its operation method, and a memory system. Background Technology

[0002] With the continuous development of semiconductor technology, memory manufacturing technology has gradually transitioned from simple planar structures to more complex three-dimensional structures, thereby increasing integration density by arranging memory cells three-dimensionally on a substrate.

[0003] Therefore, improvements are still needed to the memory and its operation methods to increase its integration density. Summary of the Invention

[0004] In view of the above, embodiments of the present disclosure provide a memory and its operation method, and a memory system.

[0005] To achieve the above objectives, the technical solution disclosed herein is implemented as follows:

[0006] This disclosure provides a memory, the memory including: a memory cell array and peripheral circuitry coupled to the memory cell array; the memory cell array includes a plurality of memory blocks, each memory block including a plurality of memory strings; each memory string includes an upper select transistor, a memory cell and a lower select transistor connected in series between a bit line and a source line; wherein all lower select transistors in the same memory block form a lower select transistor set;

[0007] The peripheral circuit is configured as follows:

[0008] Perform programming operations on the storage cells in the storage block;

[0009] An erasure operation is performed on at least a portion of the lower selection tubes in the set of lower selection tubes.

[0010] In some embodiments, within the same memory block, multiple lower select transistors in different memory strings are interconnected, electrically isolated from each other and equidistant from the source lines; the lower select transistor set includes multiple first lower select transistor sets, each first lower select transistor set including multiple lower select transistors equidistant from the source lines and having different threshold voltages;

[0011] The peripheral circuit is specifically configured as follows:

[0012] Based on the fact that multiple downselect transistors in the first downselect transistor set have different threshold voltages, programming and verification operations are performed on the memory cells in the memory block.

[0013] In some embodiments, the peripheral circuit is specifically configured as follows:

[0014] Perform an erase operation on all the lower selection tubes in the first set of lower selection tubes;

[0015] The lower select transistors in at least one of the first lower select transistor sets that are closest to the source line are programmed to have a preset threshold voltage.

[0016] The remaining lower select transistors in the first lower select transistor set are programmed to have the target threshold voltage.

[0017] In some embodiments, the peripheral circuit is specifically configured as follows:

[0018] An erase operation is performed on all the lower select transistors in the first lower select transistor set, such that at least one lower select transistor in the first lower select transistor set that is closest to the source line has a preset threshold voltage.

[0019] The remaining lower select transistors in the first lower select transistor set are programmed to have a target threshold voltage.

[0020] In some embodiments, the peripheral circuit is specifically configured as follows:

[0021] Perform single-level cell (SLC) programming operations on the remaining lower selection transistors in the first set of lower selection transistors;

[0022] Among them, the lower select transistors with preset threshold voltage in the first set of lower select transistors are used to generate gate-induced drain leakage current during the turn-off and erase operations in the programming operation.

[0023] In some embodiments, the downselect transistor set further includes at least one second downselect transistor set located between the source line and the first downselect transistor set, each second downselect transistor set including a plurality of downselect transistors at the same distance from the source line;

[0024] During the programming operation of the memory cells in the memory block, a turn-off voltage is applied to the lower selection transistors in the second set of lower selection transistors.

[0025] In some embodiments, the peripheral circuit is specifically configured as follows:

[0026] Perform an erase operation on all the lower selectors in the second set of lower selectors;

[0027] Perform programming operations on all the lower selection tubes in the second set of lower selection tubes;

[0028] During the programming operation of the remaining lower select transistors in the first lower select transistor set, a turn-off voltage is applied to the lower select transistors in the second lower select transistor set.

[0029] In some embodiments, the lower select transistor set further includes a plurality of first dummy cell sets, each of the first dummy cell sets including a plurality of first dummy cells at the same distance from the source line, and the first dummy cell sets are located between different first lower select transistor sets or between the first lower select transistor set and the second lower select transistor set.

[0030] In some embodiments, the peripheral circuit is specifically configured as follows:

[0031] Perform an erase operation on all the first dummy cells in the first set of dummy cells.

[0032] In some embodiments, when the first set of dummy cells is located between different sets of the first lower selection transistors, the peripheral circuit is specifically configured as follows:

[0033] Program the first dummy units in all the first dummy unit sets to make the first dummy units in the first dummy unit sets have a target threshold voltage;

[0034] When the first set of dummy units is located between the first set of lower selection transistors and the second set of lower selection transistors, the peripheral circuit is specifically configured as follows:

[0035] Programming operations are performed on all the first dummy units in the first dummy unit set so that all the first dummy units in the first dummy unit set have a preset threshold voltage; wherein, the first dummy units in the first dummy unit set with the preset threshold voltage are used to generate gate-induced drain leakage current during the turn-off and erase operations in the programming operation.

[0036] In some embodiments, the memory string further includes a plurality of second dummy units located between the memory cell and the lower select transistor, and the memory block includes a plurality of sets of second dummy units, each set of second dummy units including a plurality of second dummy units at the same distance from the source line;

[0037] The peripheral circuit is specifically configured as follows:

[0038] Perform an erase operation on all second dummy cells in the set of second dummy cells;

[0039] Program the second dummy units in the entire set of the second dummy units to make the second dummy units in the set of the second dummy units have a target threshold voltage.

[0040] In a second aspect, embodiments of this disclosure provide a memory system, the memory system comprising:

[0041] The memory as described in the above technical solution; and

[0042] A controller coupled to the memory and configured to control the memory.

[0043] Thirdly, embodiments of this disclosure provide a method for operating a memory, the memory including multiple memory blocks, each memory block including multiple memory strings; each memory string including an upper select transistor, a memory cell and a lower select transistor connected in series between a bit line and a source line; wherein all lower select transistors in the same memory block form a lower select transistor set;

[0044] The operation method includes:

[0045] Perform programming operations on the storage cells in the storage block;

[0046] An erasure operation is performed on at least a portion of the lower selection tubes in the set of lower selection tubes.

[0047] In some embodiments, within the same memory block, multiple lower select transistors in different memory strings are interconnected, electrically isolated from each other and equidistant from the source lines; the lower select transistor set includes multiple first lower select transistor sets, each first lower select transistor set including multiple lower select transistors equidistant from the source lines and having different threshold voltages;

[0048] The programming operation on the storage cells in the storage block includes:

[0049] Based on the fact that multiple downselect transistors in the first downselect transistor set have different threshold voltages, programming and verification operations are performed on the memory cells in the memory block.

[0050] In some embodiments, the erasing operation on at least a portion of the lower selector tubes in the lower selector tube set includes:

[0051] Perform an erase operation on all the lower selection tubes in the first set of lower selection tubes;

[0052] After performing the erase operation on at least a portion of the lower selector tubes in the lower selector tube set, the operation method further includes:

[0053] The lower select transistors in at least one of the first lower select transistor sets that are closest to the source line are programmed to have a preset threshold voltage.

[0054] The remaining lower select transistors in the first lower select transistor set are programmed to have a target threshold voltage.

[0055] In some embodiments, the erasing operation on at least a portion of the lower selector tubes in the lower selector tube set includes:

[0056] An erase operation is performed on all the lower select transistors in the first lower select transistor set, such that at least one lower select transistor in the first lower select transistor set that is closest to the source line has a preset threshold voltage.

[0057] After performing the erase operation on at least a portion of the lower selector tubes in the lower selector tube set, the operation method further includes:

[0058] The remaining lower select transistors in the first lower select transistor set are programmed to have a target threshold voltage.

[0059] In some embodiments, the programming operation on the remaining lower selectors in the first lower selector set includes:

[0060] Perform single-level cell (SLC) programming operations on the remaining lower selection transistors in the first set of lower selection transistors;

[0061] Among them, the lower select transistors with preset threshold voltage in the first set of lower select transistors are used to generate gate-induced drain leakage current during the turn-off and erase operations in the programming operation.

[0062] In some embodiments, the downselect transistor set further includes at least one second downselect transistor set located between the source line and the first downselect transistor set, each second downselect transistor set including a plurality of downselect transistors at the same distance from the source line;

[0063] During the programming operation of the memory cells in the memory block, a turn-off voltage is applied to the lower selection transistors in the second set of lower selection transistors.

[0064] In some embodiments, the erasing operation on at least a portion of the lower selector tubes in the lower selector tube set includes:

[0065] Perform an erase operation on all the lower selectors in the second set of lower selectors;

[0066] After performing the erase operation on at least a portion of the lower selector tubes in the lower selector tube set, the operation method further includes:

[0067] Perform programming operations on all the lower selection tubes in the second set of lower selection tubes;

[0068] The step of programming the remaining lower-select transistors in the first lower-select transistor set to have a target threshold voltage includes:

[0069] During the programming operation of the remaining lower select transistors in the first lower select transistor set, a turn-off voltage is applied to the lower select transistors in the second lower select transistor set.

[0070] In some embodiments, the lower select transistor set further includes a plurality of first dummy cell sets, each of the first dummy cell sets including a plurality of first dummy cells at the same distance from the source line, and the first dummy cell sets are located between different first lower select transistor sets or between the first lower select transistor set and the second lower select transistor set.

[0071] In some embodiments, the erasing operation on at least a portion of the lower selector tubes in the lower selector tube set includes:

[0072] Perform an erase operation on all the first dummy cells in the first set of dummy cells.

[0073] In some embodiments, when the first set of dummy cells is located between different sets of first lower selection tubes, after performing the erase operation on at least a portion of the lower selection tubes in the lower selection tube sets, the operation method further includes:

[0074] Program the first dummy units in all the first dummy unit sets to make the first dummy units in the first dummy unit sets have a target threshold voltage;

[0075] When the first set of dummy units is located between the first set of lower selection tubes and the second set of lower selection tubes, after performing an erase operation on at least a portion of the lower selection tubes in the set of lower selection tubes, the operation method further includes:

[0076] Programming operations are performed on all the first dummy units in the first dummy unit set so that all the first dummy units in the first dummy unit set have a preset threshold voltage; wherein, the first dummy units in the first dummy unit set with the preset threshold voltage are used to generate gate-induced drain leakage current during the turn-off and erase operations in the programming operation.

[0077] In some embodiments, the memory string further includes a plurality of second dummy units located between the memory cell and the lower select transistor, and the memory block includes a plurality of sets of second dummy units, each set of second dummy units including a plurality of second dummy units at the same distance from the source line;

[0078] While performing the erase operation on at least a portion of the lower selection tubes in the lower selection tube set, the operation method further includes:

[0079] Perform an erase operation on all second dummy cells in the set of second dummy cells;

[0080] After performing the erase operation on at least a portion of the lower selector tubes in the lower selector tube set, the operation method further includes:

[0081] Program the second dummy units in the entire set of the second dummy units to make the second dummy units in the set of the second dummy units have a target threshold voltage.

[0082] This disclosure provides a memory and its operation method, as well as a memory system. The memory includes: a memory cell array and peripheral circuitry coupled to the memory cell array; the memory cell array includes multiple memory blocks, each memory block including multiple memory strings; each memory string includes an upper select transistor, a memory cell, and a lower select transistor connected in series between a bit line and a source line; wherein all lower select transistors in the same memory block form a lower select transistor set; the peripheral circuitry is configured to: perform programming operations on the memory cells in the memory block; and perform erase operations on at least a portion of the lower select transistors in the lower select transistor set. In this disclosure, after programming the memory cells in the memory block, at least a portion of the lower select transistors in the lower select transistor set can be erased. This allows for subsequent readjustment of some lower select transistors to form lower select transistors with a preset threshold voltage, used to generate gate-induced drain leakage current during turn-off and erase operations in the programming operation. Furthermore, the remaining lower select transistors can be used to store data, thereby increasing storage density. Attached Figure Description

[0083] Figure 1A A simplified schematic diagram of the lower selection tube provided for some embodiments;

[0084] Figure 1B A simplified circuit diagram of the downselect transistor provided for some embodiments;

[0085] Figure 2A A simplified schematic diagram of the structure of the lower selection tube provided in the embodiments of this disclosure;

[0086] Figure 2B A simplified circuit diagram of the lower selection transistor provided in an embodiment of this disclosure;

[0087] Figure 3 A schematic diagram of a lower selector transistor with different threshold voltages provided in an embodiment of this disclosure;

[0088] Figure 4 A waveform diagram illustrating the programming operation of word lines provided in an embodiment of this disclosure;

[0089] Figure 5 A schematic diagram of the memory structure provided in the embodiments of this disclosure;

[0090] Figure 6 A schematic diagram of a memory including a storage cell array provided for an embodiment of this disclosure;

[0091] Figure 7 A cross-sectional schematic diagram of a storage cell array including storage strings provided for embodiments of this disclosure;

[0092] Figure 8 This is a schematic diagram of the structure of the lower selection tube assembly provided in an embodiment of the present disclosure;

[0093] Figure 9 Waveform diagrams are provided for the erasure and programming operations on the lower selection tube set according to embodiments of this disclosure;

[0094] Figure 10 A waveform diagram is provided for programming operations on a first set of dummy units according to an embodiment of this disclosure;

[0095] Figure 11 This is a schematic diagram illustrating the operation of the lower selection tube set according to an embodiment of the present disclosure;

[0096] Figure 12 A schematic diagram of the structure of a memory system provided in an embodiment of this disclosure;

[0097] Figure 13 A schematic diagram of an electronic device provided in an embodiment of this disclosure;

[0098] Figure 14A A schematic diagram of a memory card with memory provided in an embodiment of this disclosure;

[0099] Figure 14B A schematic diagram of a solid-state drive with memory provided in an embodiment of this disclosure;

[0100] Figure 15 This is a flowchart illustrating a memory operation method provided in an embodiment of the present disclosure. Detailed Implementation

[0101] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0102] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0103] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0104] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0105] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0106] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0107] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0108] As memory technology (e.g., 3D NAND flash memory) continues to advance, the required programming time (Tprog) is becoming increasingly shorter, while the size of CMOS (Complementary Metal Oxide Semiconductor) circuit designs is also shrinking. A memory may include a cell array and peripheral circuitry coupled to it. When the area of ​​the charge pump in the peripheral circuitry shrinks, it affects the charge pump's ability to ramp up and down the voltage across the cell array, thus weakening the driving capability of the peripheral circuitry and consequently increasing the programming time.

[0109] refer to Figure 1A and Figure 1B , Figure 1A A simplified schematic diagram of the lower selection tube provided for some embodiments. Figure 1B A simplified circuit diagram of the downselect transistor provided for some embodiments. For example... Figure 1A As shown, the memory block 100 includes multiple memory strings connected in parallel between the bit line (BL) and the source line (SL); each memory string includes a lower select transistor 104, a memory cell (MC), and an upper select transistor 102 connected in series between the bit line and the source line; the lower select transistor 104 is located between the source line and the memory cell, and can also be called a source selective transistor (SST); the memory cell is located between the lower select transistor 104 and the upper select transistor 102, and the upper select transistor 102 is located between the memory cell and the bit line, and can also be called a drain selective transistor (DST). Multiple memory cells at the same level in different memory strings within the same memory block 100 are interconnected to form a word line (WL) 106, i.e., multiple memory cells at the same level are interconnected; multiple up select transistors 102 at the same level in different memory strings within the same memory block 100 are electrically isolated from each other, i.e., multiple up select transistors 102 at the same level are electrically isolated from each other; multiple down select transistors 104 at the same level in different memory strings within the same memory block 100 are electrically isolated from each other, i.e., multiple down select transistors 104 at the same level are electrically isolated from each other.

[0110] like Figure 1A As shown, multiple upper select transistors 102 located at the same level are electrically isolated from each other through a drain-select gate isolation structure 112; multiple lower select transistors 104 located at the same level are electrically isolated from each other through a source-select gate isolation structure 114. Figure 1A The diagram shows two lower selector transistors 104 located at the same level, which are electrically connected to the first driver 108 and the second driver 110, respectively.

[0111] It should be noted that "same level" refers to the same height in the direction perpendicular to the substrate. Multiple lower select transistors located at the same level refer to multiple lower select transistors that are equidistant from the source line; or, multiple lower select transistors located at the same level refer to multiple lower select transistors that are equidistant from the bit line.

[0112] For example, such as Figure 1BAs shown, the memory block 100 may include two finger memory regions, namely, Finger1 and Finger2; adjacent finger memory regions are electrically isolated from each other through a source-select gate isolation structure 114; the upper select transistors 102 in the two finger memory regions of the same memory block 100 are electrically isolated from each other, and the lower select transistors 104 in the two finger memory regions of the same memory block 100 are electrically isolated from each other. Each finger memory region includes two memory strings, namely, Str0 and Str1 (or Str2 and Str3); the upper select transistors 102 in the two memory strings of the same finger memory region are electrically isolated from each other, and the lower select transistors 104 in the two memory strings of the same finger memory region are interconnected. Furthermore, Figure 1B The lower selectors 104 in the same storage block 100 shown are all connected to the Array Common Source (ACS).

[0113] refer to Figure 2A and Figure 2B , Figure 2A This is a simplified schematic diagram of the lower selection tube provided in an embodiment of this disclosure. Figure 2B A simplified circuit diagram of the lower selection transistor provided in an embodiment of this disclosure. (See attached diagram.) Figure 2A As shown, the memory block 200 includes multiple memory strings connected in parallel between the bit line and the source line; each memory string includes a lower select transistor 204, a memory cell, and an upper select transistor 202 connected in series between the bit line and the source line. Multiple memory cells at the same level in different memory strings within the same memory block 200 are interconnected to form a word line 206, i.e., multiple memory cells at the same level are interconnected; multiple upper select transistors 102 at the same level in different memory strings within the same memory block 200 are electrically isolated from each other, i.e., multiple upper select transistors 102 at the same level are electrically isolated from each other; multiple lower select transistors 104 at the same level in different memory strings within the same memory block 200 are interconnected, i.e., multiple lower select transistors 104 at the same level are electrically isolated from each other. Figure 2A The diagram shows that the lower selector tubes at the same horizontal level are connected to the first driver 208, and the lower selector tubes at another horizontal level are connected to the second driver 210.

[0114] For example, such as Figure 2B As shown, the upper select transistors 202 in two pointer memory areas within the same memory block 200 are electrically isolated from each other, while the lower select transistors 204 in two pointer memory areas within the same memory block 200 are interconnected. Similarly, the upper select transistors 202 in two memory strings within the same pointer memory area are electrically isolated from each other, while the lower select transistors 204 in two memory strings within the same pointer memory area are interconnected.

[0115] In this embodiment of the disclosure, each memory string may include a plurality of downselect transistors connected in series. At least one of the downselect transistors has a first threshold voltage, and the remaining downselect transistors have a second threshold voltage different from the first threshold voltage. In the same memory block, some downselect transistors at the same level have the first threshold voltage, and the remaining downselect transistors have the second threshold voltage.

[0116] refer to Figure 3 , Figure 3 This is a schematic diagram of a downselect transistor with different threshold voltages provided in an embodiment of this disclosure. For example, as shown... Figure 3 As shown, each memory string includes two downselect transistors connected in series. Memory strings Str0 and Str1 each include a first downselect transistor 204a and a second downselect transistor 204b connected in series. The first downselect transistor 204a and the second downselect transistor 204b have different threshold voltages. For example, the first downselect transistor 204a has a first threshold voltage V1, and the second downselect transistor 204b has a second threshold voltage V2, and the first threshold voltage V1 is less than the second threshold voltage V2.

[0117] Both storage strings Str2 and Str3 include a third downselect transistor 204c and a fourth downselect transistor 204d connected in series; the third downselect transistor 204c and the fourth downselect transistor 204d have different threshold voltages. For example, the third downselect transistor 204c has a second threshold voltage V2, and the fourth downselect transistor 204d has a first threshold voltage V1. The first downselect transistor 204a and the third downselect transistor 204c, located at the same level, are interconnected, and the first downselect transistor 204a and the third downselect transistor 204c have different threshold voltages; the second downselect transistor 204b and the fourth downselect transistor 204d, located at the same level, are interconnected, and the second downselect transistor 204b and the fourth downselect transistor 204d have different threshold voltages.

[0118] In this embodiment of the disclosure, the lower selection transistor can have different threshold voltages, either on a storage string or a storage area basis. For example... Figure 3As shown, taking the storage area as a unit and making the lower selection transistors have different threshold voltages as an example, a voltage greater than the second threshold voltage V2 can be applied to the first lower selection transistor 204a and the third lower selection transistor 204c located at the same level, so that the first lower selection transistor 204a and the third lower selection transistor 204c are both turned on; and a voltage greater than the first threshold voltage V1 and less than the second threshold voltage V2 can be applied to the second lower selection transistor 204b and the fourth lower selection transistor 204d located at the same level, so that the fourth lower selection transistor 204d is turned on and the second lower selection transistor 204b is turned off; in this way, the storage strings str2 and str3 in the storage area Finger2 can be turned on and the storage strings str0 and str1 in the finger storage area Finger1 can be turned off.

[0119] Similarly, a voltage greater than the first threshold voltage V1 and less than the second threshold voltage V2 can be applied to the first lower select transistor 204a and the third lower select transistor 204c, which are located at the same level, so that the first lower select transistor 204a is turned on and the third lower select transistor 204c is turned off; and a voltage greater than the second threshold voltage V2 can be applied to the second lower select transistor 204b and the fourth lower select transistor 204d, which are located at the same level, so that both the second lower select transistor 204b and the fourth lower select transistor 204d are turned on; in this way, the memory strings str0 and str1 in the finger memory area Finger1 can be turned on and the memory strings str2 and str3 in the finger memory area Finger2 can be turned off. By using the lower select transistors with different threshold voltages, different finger memory areas (or memory strings) can be selectively turned on.

[0120] Figure 3 The illustration shows that all the downselect transistors in the memory block have two threshold voltages: a first threshold voltage V1 and a second threshold voltage V2. In fact, this embodiment does not specifically limit the number of threshold voltages possessed by all the downselect transistors; an appropriate number of threshold voltages can be selected based on actual conditions.

[0121] refer to Figure 4 , Figure 4 A waveform diagram illustrating the programming operation of word lines provided in an embodiment of this disclosure. For example... Figure 4 As shown, each memory string includes an upper select transistor, a memory cell, and a lower select transistor connected in series between the bit line and the source line; wherein, multiple upper select transistors at the same level are electrically isolated from each other, forming an upper select transistor set 212; multiple memory cells at the same level are interconnected to form a word line 206; multiple lower select transistors at the same level are interconnected, and all lower select transistors in the same memory block form a lower select transistor set 218.

[0122] The storage string also includes: a top dummy cell located between the upper select tube and the storage cell, and a bottom dummy cell located between the lower select tube and the storage cell; wherein, a plurality of top dummy cells located at the same level are interconnected to form a top dummy word line 214, and a plurality of bottom dummy cells located at the same level are interconnected to form a bottom dummy word line 216 (i.e., a second dummy cell set 226).

[0123] For example, all downselect transistors in the same memory block form a downselect transistor set 218. The downselect transistor set 218 may include multiple first downselect transistor sets 220, each first downselect transistor set 220 including multiple downselect transistors at the same distance from the source line and having different threshold voltages. One first downselect transistor set 220 corresponds to a layer of multiple interconnected downselect transistors at the same level, and the threshold voltages of the multiple downselect transistors included in one first downselect transistor set 220 are different.

[0124] In some embodiments, the multiple lower select transistors included in the first lower select transistor set 220 can be programmed to have different threshold voltages. The multiple lower select transistors included in the first lower select transistor set 220 can be used for selective conduction in verification and read operations. The first lower select transistor set 220 can also be referred to as the bottom selective gate cut (BSG cut) or an electrical selector.

[0125] For example, the lower select transistor set 218 may further include at least one second lower select transistor set 222, each second lower select transistor set 222 including a plurality of lower select transistors that are equidistant from the source line and interconnected; wherein the second lower select transistor set 222 is located between the source line and the first lower select transistor set 220.

[0126] In some embodiments, the plurality of bottom select transistors included in the second bottom select transistor set 222 can be programmed to have a preset threshold voltage. The plurality of bottom select transistors included in the second bottom select transistor set 222 can be used to generate gate-induced drain leakage current during turn-off and erase operations in the programming operation. The second bottom select transistor set can also be referred to as a common bottom selector (BSG), i.e., a common BSG.

[0127] For example, the lower select transistor set 218 may also include a plurality of first dummy cell sets 224, each of the first dummy cell sets 224 including a plurality of first dummy cells that are equidistant from the source line and interconnected with each other; wherein the first dummy cell sets 224 are located between different first lower select transistor sets 220 or between the first lower select transistor set 220 and the second lower select transistor set 222. Figure 4 This illustrates that the first set of dummy units 224 is located between different sets of first lower selection tubes 220.

[0128] In some embodiments, programming and verification operations are performed on memory cells in memory block 200 based on the different threshold voltages of multiple downselect transistors in the first downselect transistor set 220.

[0129] like Figure 4 As shown, the memory string containing the memory cell to be programmed is used as the selection string, and other memory strings are non-selection strings; the word line containing the memory cell to be programmed is used as the selection word line, and other word lines are non-selection word lines; the bit line connected to the selection string is used as the selection bit line, and other bit lines are non-selection bit lines. During programming, a bit-line programming voltage, such as ground voltage Vss, is applied to the select bit lines, and a programmable disable voltage, such as high voltage Vdd or Vcc, is applied to the non-select bit lines; a turn-on voltage, such as high voltage Vcc, is applied to the upper select transistor of the select string, and a turn-off voltage, such as ground voltage Vss, is applied to the upper select transistor of the non-select string; a word-line programming voltage, such as programming voltage Vpgm, is applied to the select word lines, and a pass voltage, such as pass voltage Vpass, is applied to the non-select word lines, the top dummy word lines, and the bottom dummy word lines (i.e., the second dummy cell set); at this time, during programming, a turn-off voltage, such as ground voltage Vss, is applied to the first lower select transistor set, the second lower select transistor set, and the first dummy cell set in the lower select transistor set; a ground voltage Vss is also applied to the source line.

[0130] During the verification operation, a verification voltage, such as a verification voltage Vpv, is applied to the select word line. At this point, different voltages can be applied to the multiple lower select transistors in the select string, based on the fact that they have different threshold voltages. (Return to reference) Figure 3 If the fingering memory area Finger1 is the selected fingering memory area, based on the fact that the first lower select transistor 204a and the second lower select transistor 204b have different threshold voltages, the voltage applied to the first lower select transistor 204a (i.e., Low Vpass) ensures that the first lower select transistor 204a is turned on, and the voltage applied to the second lower select transistor 204b (i.e., High Vpass) ensures that the second lower select transistor 204b is turned on. In this way, the channel of the select string can be turned on.

[0131] In a memory block, based on the different threshold voltages of multiple down-select transistors in a memory string, during the programming-verification operation of memory cells, the combination of threshold voltages and bias voltages between different layers enables selective shutdown of different memory strings or memory areas. This reduces the load on the driving capability of the peripheral circuitry, shortens the rise or fall time of the memory array voltage ramp, and thus reduces programming time. However, setting multiple sets of first down-select transistors in a memory block may waste memory space.

[0132] In view of this, embodiments of the present disclosure provide a memory and its operation method. In these embodiments, after programming the memory cells in the memory block, at least a portion of the lower select transistors in the lower select transistor set can be erased. Subsequently, some of the lower select transistors can be re-trimned to form a common BSG. The common BSG can be used to generate gate-induced drain leakage current during the turn-off and erase operations in the programming operation. Furthermore, the remaining lower select transistors can be used as memory cells to store data. Thus, while reducing programming time using electrical select transistors, storage density can also be increased.

[0133] refer to Figure 5 and Figure 6 , Figure 5 This is a schematic diagram of the structure of a memory provided in an embodiment of this disclosure. Figure 6 This is a schematic diagram of a memory including a storage cell array, provided for an embodiment of this disclosure. Figure 5 and Figure 6 As shown, this embodiment of the present disclosure provides a memory 300, which includes: a memory cell array 302 and a peripheral circuit 304 coupled to the memory cell array 302; the memory cell array 302 includes a plurality of memory blocks 306, each memory block 306 including a plurality of memory strings 310; each memory string 310 includes an upper select transistor 314, a memory cell 308 and a lower select transistor 312 connected in series between a bit line 322 and a source line 316; wherein, all the lower select transistors 312 in the same memory block 306 form a lower select transistor set;

[0134] The aforementioned peripheral circuit 304 is configured as follows:

[0135] Perform programming operations on the storage cells in storage block 306;

[0136] At least a portion of the lower selector tubes in the lower selector tube set 218 are erased.

[0137] In this embodiment of the disclosure, after the programming operation of the memory cell in the memory block is completed, at least a portion of the lower select transistors in the lower select transistor set can be erased. Subsequently, some of the lower select transistors can be readjusted to form a lower select transistor with a preset threshold voltage, which can be used as a normal BSG, that is, used to generate gate-induced drain leakage current during the turn-off and erase operations in the programming operation. The remaining lower select transistors can then be used as memory cells to store data, thereby increasing the storage density.

[0138] like Figure 6 As shown, the memory 300 may include a memory cell array 302 and peripheral circuitry 304 coupled to the memory cell array 302. The memory cell array 302 may be a NAND flash memory cell array, wherein the memory cells 308 are provided in the form of an array of memory strings 310, each memory string 310 on a substrate ( Figure 6 (Not shown in the diagram) Extending vertically upwards. In some embodiments, each memory string 310 includes a plurality of memory cells 308 that are series-coupled and vertically stacked. Each memory cell 308 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 308. Each memory cell 308 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0139] In some embodiments, each storage cell 308 may be a single-level cell (SLC) having two possible storage states and thus being able to store one bit of data. For example, an SLC may have a first storage state "1" and a second storage state "0", where the threshold voltage distribution of the first storage state "1" may correspond to a first voltage range, and the threshold voltage distribution of the second storage state "0" may correspond to a second voltage range. The first storage state is an erase state, and the second storage state is a programmable state. In some embodiments, each storage cell 308 may be a multi-level cell (MLC) capable of storing more than a single bit of data in more than four storage states. For example, an MLC may store two bits of data per cell, three bits of data per cell (also known as a triple-level cell (TLC)), or four bits of data per cell (also known as a quad-level cell (QLC)). Each MLC may be programmed to take a voltage range of possible threshold voltage distributions. In one example, if each MLC stores two bits of data, the MLC can have a first storage state "11", a second storage state "10", a third storage state "01", and a fourth storage state "00". Here, the threshold voltage distributions for the first, second, third, and fourth storage states correspond to the first, second, third, and fourth voltage ranges, respectively. The first storage state is the erase state, and the second, third, and fourth storage states are all programming states. Similarly, a TLC can have 8 storage states, including an erase state and 7 programming states; a QLC can have 16 storage states, including an erase state and 15 programming states.

[0140] like Figure 6 As shown, each memory string 310 may include a lower select transistor 312 at its source end and an upper select transistor 314 at its drain end. The lower select transistor 312 and the upper select transistor 314 may be configured to activate the selected memory string 310 (column of the array) during read and program operations. In some embodiments, the sources of memory strings 310 in the same memory block 306 are coupled via the same source line 316 (e.g., common SL). In other words, in some embodiments, all memory strings 310 in the same memory block 306 have a common source line. In some embodiments, the drain of the upper select transistor 314 of each memory string 310 is coupled to a corresponding bit line 322, which may be accessible via an output bus ( Figure 6 (Not shown in the diagram) Read or write data from bit line 322.

[0141] like Figure 6As shown, memory strings 310 can be organized into multiple memory blocks 306, each of which can have a source line 316 (e.g., a common SL coupled to ground). In some embodiments, each memory block 306 is the basic unit for an erase operation, i.e., all memory cells 308 on the same memory block 306 are erased simultaneously. To erase memory cells 308 in a selected memory block, the source lines 316 of the selected memory block and unselected memory blocks on the same plane as the selected memory block can be biased with an erase voltage Vers (e.g., a high positive voltage (e.g., 20V or higher)). It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 308 of adjacent memory strings 310 can be coupled via word lines 324, which select which row of memory cells 308 is affected by read and program operations. In some embodiments, each word line 324 is coupled to a memory page 326 of the memory cell 308. Each word line 324 may include a plurality of control gates (gate electrodes) at each memory cell 308 in the corresponding memory page 326 and gate lines coupling the control gates.

[0142] It should be noted that, Figure 6 The illustrated storage page is a physical page, referring to a storage unit at the physical layer. The basic data unit for programming and reading operations is the logical page. For SLC, each storage unit can store 1 bit of information, so the information stored in one storage unit (i.e., 1 physical page) at the physical layer corresponds to the information of 1 logical page. For MLC, each storage unit can store 1 bit of information, so the information stored in one storage unit (i.e., 1 physical page) at the physical layer corresponds to the information of 2 logical pages. For TLC, each storage unit can store 1 bit of information, so the information stored in one storage unit (i.e., 1 physical page) at the physical layer corresponds to the information of 3 logical pages. For QLC, each storage unit can store 1 bit of information, so the information stored in one storage unit (i.e., 1 physical page) at the physical layer corresponds to the information of 4 logical pages.

[0143] refer to Figure 7 , Figure 7 This is a cross-sectional schematic diagram of a storage cell array including storage strings, provided as an embodiment of this disclosure. Figure 7As shown, the memory string 310 may extend vertically through the memory stack layer 330 above the substrate 328. The substrate 328 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0144] The memory stack layer 330 may include alternating gate conductive layers 332 and gate dielectric layers 334. The number of pairs of gate conductive layers 332 and gate dielectric layers 334 in the memory stack layer 330 may determine the number of memory cells 308 in the memory cell array 302. The gate conductive layers 332 may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 332 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 332 includes a doped polysilicon layer. Each gate conductive layer 332 may include a control gate surrounding the memory cell 308 and may extend laterally at the top of the memory stack layer 330 as a drain select gate line 320, at the bottom of the memory stack layer 330 as a source select gate line 318, or between the drain select gate line 320 and the source select gate line 318 as a word line 324.

[0145] like Figure 7 As shown, the memory string 310 includes a channel structure extending vertically through the memory stack layer 330. In some embodiments, the channel structure includes channel holes filled with one or more semiconductor materials (e.g., as a semiconductor channel) and one or more dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polycrystalline silicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a memory layer (also referred to as a "charge trap / memory layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, tunneling layer, memory layer, and barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The memory layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0146] According to some embodiments, wells (e.g., P-wells and / or N-wells) may be formed in substrate 328, and the source terminal of memory string 310 may be in contact with the well. For example, a source line may be coupled to the well to apply an erase voltage to the well (i.e., the source of the memory string) during an erase operation. In some embodiments, the memory string may also include a channel plug at the drain terminal of memory string 310. It should be understood that, although in Figure 7 Additional components, not shown in the diagram, can form the memory cell array 302. These additional components include, but are not limited to, gate line gaps / source contacts, local contacts, interconnect layers, etc.

[0147] Return to reference Figure 6 The peripheral circuitry 304 can be coupled to the memory cell array 302 via bit line 322, word line 324, source line 316, source-select-gate line 318, and drain-select-gate line 320. The peripheral circuitry 304 can include any suitable analog, digital, and mixed-signal circuitry to facilitate the operation of the memory cell array 302 by applying voltage and / or current signals to each target memory cell 308 and sensing voltage and / or current signals from each target memory cell 308 via bit line 322, word line 324, source line 316, source-select-gate line 318, and drain-select-gate line 320. The peripheral circuitry 304 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology.

[0148] refer to Figure 8 , Figure 8 This is a schematic diagram of the structure of the lower selection tube assembly provided in an embodiment of this disclosure. (See diagram below.) Figure 8 As shown in Figure (a), the lower select transistor set 218 may include multiple first lower select transistor sets 220, each first lower select transistor set 220 including multiple lower select transistors at the same distance from the source line and the multiple lower select transistors having different threshold voltages. Each first lower select transistor set 220 corresponds to one layer of lower select transistors.

[0149] Figure 8 Figure (a) illustrates the two first lower selection tube sets 220. Figure 8 Figure (b) illustrates eight first lower selection tube sets 220. In fact, the embodiments of this disclosure do not have a special limitation on the number of first lower selection tube sets, and an appropriate number of first lower selection tube sets can be set according to the actual situation.

[0150] refer to Figure 9 , Figure 9 Waveform diagrams are provided for erasing and programming operations on the lower selection transistor set according to embodiments of this disclosure. For example... Figure 8 and Figure 9As shown, after programming all memory cells of the memory block, an erase operation is performed on at least a portion of the lower select transistors in the lower select transistor set. The basic unit of the erase operation is the memory block. During the process of the source line voltage of the selected memory block rising from the ground voltage Vss to the erase voltage Vers, after a preset time, the upper select transistor set 212, top dummy word line 214, word line 206, bottom dummy word line 216 (i.e., the second dummy cell set 226), first lower select transistor set 220, first dummy cell set 224 and second lower select transistor set 222 of the selected memory block are changed from being applied with a first voltage (e.g., ground voltage Vss) to being floating. Here, the preset time can be set according to actual needs. When the voltage of the source line of the selected memory block reaches the erase voltage Vers, the voltages of the upper select transistor set 212, the top dummy word line 214, the word line 206, the bottom dummy word line 216 (i.e., the second dummy cell set 226), the first lower select transistor set 220, the first dummy cell set 224, and the second lower select transistor set 222 in the corresponding memory block will stabilize at the second voltage due to coupling; the second voltage is also called the hold and release (H&R) voltage.

[0151] It should be understood that the voltage difference between the source line of the selected memory block and the corresponding upper select transistor set, top dummy word line, word line, bottom dummy word line (i.e., second dummy cell set), first lower select transistor set, first dummy word line set, and second lower select transistor set is the effective erase voltage. When the erase voltage on the source line of the selected memory block remains unchanged, the longer the preset duration, the longer the voltage on the upper select transistor set, top dummy word line, word line, bottom dummy word line (i.e., second dummy cell set), first lower select transistor set, first dummy word line set, and second lower select transistor set in the memory block is forced to be maintained at the first voltage for a longer period of time. As a result, the coupling time on the source line is shorter, and the final stable second voltage on the corresponding upper select transistor set, top dummy word line, word line, bottom dummy word line (i.e., second dummy cell set), first lower select transistor set, first dummy word line set, and second lower select transistor set is smaller, and the voltage value of the effective erase voltage is larger. Therefore, the erasure depth can be adjusted by changing the preset duration and adjusting / changing the effective erasure voltage value.

[0152] like Figure 9As shown, when the lower select transistor set includes the first lower select transistor set, after programming all memory cells of the memory block, the purpose of the erase operation is to erase the first lower select transistor set, without erasing the word lines. Therefore, during the erase operation, the voltage on the first lower select transistor set is forced to be held at the first voltage for a relatively long preset time, the final stable second voltage on the first lower select transistor set is relatively small, and the effective erase voltage value is relatively large; while the voltage on the word lines is forced to be held at the first voltage for a relatively short preset time, the final stable second voltage on the word lines is relatively large, and the effective erase voltage value is relatively small; thus, a larger erase depth can be achieved for the first lower select transistor set, and a smaller erase depth for the word lines.

[0153] It should be noted that, as Figure 9 As shown, the voltage waveform diagram for erasing the first set of lower select transistors includes solid and dashed lines. Solid lines represent the application of a low bias voltage to the first set of lower select transistors, while dashed lines represent the holding voltage reached due to coupling. If this first set of lower select transistors is subsequently used as a memory cell, the voltage indicated by the solid line is used; otherwise, the voltage indicated by the dashed line is used. In other words, if the first set of lower select transistors is subsequently used as a memory cell, the erase depth of this set should be greater. This avoids insufficient erase depth on the lower select transistors in the first set of lower select transistors, which could affect subsequent memory functionality.

[0154] In some embodiments, the peripheral circuit 304 is specifically configured as follows:

[0155] Perform an erase operation on all the lower selection tubes in the first lower selection tube set 218;

[0156] The lower select transistors in at least one first lower select transistor set 220 that are closest to the source line are programmed to have a preset threshold voltage.

[0157] The remaining lower select transistors in the first lower select transistor set 220 are programmed to have the target threshold voltage.

[0158] Here, after erasing all the lower select transistors in the first lower select transistor set, readjustment can be performed; where the erasure depth is the same for all the first lower select transistor sets during the erasure operation, the readjustment refers to readjusting the threshold voltage of the lower select transistors.

[0159] During the erasure and readjustment process of the entire first lower select transistor set, the entire first lower select transistor set can be divided into two parts. The first part is arranged adjacent to the source line, and after erasure and readjustment, the first part can be used as a general BSG. The second part is arranged adjacent to the first part, and after erasure, the second part can be used as a memory cell. This disclosure embodiment does not impose any special limitations on the number of first lower select transistors included in the first part or the number of first lower select transistors included in the second part.

[0160] In some embodiments, readjusting the first portion refers to programming the first set of lower select transistors included in the first portion so that all lower select transistors in the first set of lower select transistors have a preset threshold voltage. Thus, the lower select transistors included in the first portion can be used as ordinary BSGs, i.e., used to generate gate-induced drain leakage current during turn-off and erase operations in the programming operation. In other words, converting the first set of lower select transistors into ordinary BSGs requires performing an erase operation before programming.

[0161] like Figure 9 As shown in the dashed box, applying a programming voltage Vpgm to a portion of the lower select transistors refers to programming these lower select transistors so that they have a preset threshold voltage. In this way, these lower select transistors can be used as ordinary BSGs.

[0162] In some embodiments, the ability to use the second portion as a storage unit after an erase operation means that the first set of lower select transistors included in the second portion can be erased and then programmed to give the lower select transistors in the first set of lower select transistors included in the second portion a target threshold voltage; thus, the lower select transistors included in the second portion can be used as storage units. In other words, converting the first set of lower select transistors into storage units only requires an erase operation.

[0163] like Figure 9 As shown, applying a programming voltage Vpgm to a portion of the bottom dummy word lines (i.e., the second dummy cell set) and a portion of the lower select transistors refers to performing a programming operation on a portion of the second dummy cell set and a portion of the lower select transistors. In other words, the second dummy cell set and a portion of the lower select transistors can be used as memory cells. Figure 9 The diagram shows the lower selector responsible for shutting down, which has been readjusted to a normal BSG.

[0164] This disclosure does not specifically limit the range of the preset threshold voltage. The down-select transistors used as ordinary BSGs have a preset threshold voltage. These down-select transistors only need to generate gate-induced drain leakage current during turn-off and erase operations in programming operations. This disclosure also does not specifically limit the range of the target threshold voltage. The down-select transistors used as memory cells have a target threshold voltage. These down-select transistors can be programmed for storing data.

[0165] In some embodiments, the peripheral circuit 304 is specifically configured as follows:

[0166] An erase operation is performed on all the lower select transistors in the first lower select transistor set 220, so that at least one lower select transistor in the first lower select transistor set 220 that is closest to the source line has a preset threshold voltage.

[0167] The remaining lower select transistors in the first lower select transistor set 220 are programmed to have the target threshold voltage.

[0168] Here, during the erase operation of all the lower select transistors in the first lower select transistor set, the entire first lower select transistor set can be divided into two parts: the first part is adjacent to the source line; the second part is adjacent to the first part; the erase depth of the first part and the second part are different; more specifically, the erase depth of the first part is less than the erase depth of the second part. After the erase operation of all the lower select transistors in the first lower select transistor set, the lower select transistors included in the first part have a preset threshold voltage. Thus, the lower select transistors included in the first part can be used as ordinary BSGs, that is, used to generate gate-induced drain leakage current during the turn-off and erase operations in the programming operation. In other words, converting the first lower select transistor set into a normal BSG only requires an erase operation. At this time, it is not necessary to... Figure 9 The process of applying voltage, as shown in the dashed box, allows for the acquisition of a standard BSG without the need for readjustment.

[0169] In some embodiments, the first set of downselect transistors included in the second portion is programmed such that the downselect transistors in the first set of downselect transistors included in the second portion have a target threshold voltage; thus, the downselect transistors included in the second portion can be used as memory cells. In other words, converting the first set of downselect transistors into memory cells only requires an erase operation.

[0170] This disclosure does not specifically limit the number of the first set of downselect transistors included in the first part, nor the number of the first set of downselect transistors included in the second part. This disclosure also does not specifically limit the range of the preset threshold voltage; the downselect transistors used as ordinary BSGs have a preset threshold voltage, and these downselect transistors only need to be able to generate gate-induced drain leakage current during turn-off and erase operations in programming operations. This disclosure also does not specifically limit the range of the target threshold voltage; the downselect transistors used as memory cells have a target threshold voltage, and these downselect transistors can be programmed for storing data.

[0171] In some embodiments, the peripheral circuit 304 is specifically configured as follows:

[0172] Perform single-level cell SLC programming operations on the remaining lower selection transistors in the first lower selection transistor set 220;

[0173] Among them, the lower selection transistors with preset threshold voltage in the first lower selection transistor set 220 are used to generate gate-induced drain leakage current during the turn-off and erase operations in the programming operation.

[0174] Here, the first set of selector transistors is converted into memory cells. These memory cells can then be programmed to achieve the target threshold voltage. More specifically, SLC programming can be performed on these memory cells to achieve the target threshold voltage.

[0175] like Figure 8 As shown in Figure (a), the lower select transistor set 218 may further include at least one second lower select transistor set 222, each second lower select transistor set 222 including multiple lower select transistors at the same distance from the source line; wherein, the second lower select transistor set 222 is located between the source line and the first lower select transistor set 220. Each second lower select transistor set 222 corresponds to one layer of lower select transistors.

[0176] Figure 8 Figures (a) and (b) both illustrate two second lower select transistor sets 222, which are located between the source line and the first lower select transistor set 220. This embodiment of the present disclosure does not impose a special limitation on the number of second lower select transistor sets, and can be flexibly selected according to actual conditions.

[0177] In some embodiments, the lower select transistor set 218 further includes at least one second lower select transistor set 222 located between the source line and the first lower select transistor set 220, each second lower select transistor set 222 including a plurality of lower select transistors at the same distance from the source line;

[0178] During the programming operation of the memory cell in memory block 200, a turn-off voltage is applied to the lower selection transistor in the second lower selection transistor set 222.

[0179] refer to Figure 4 During the programming operation of the memory cells in the memory block, a turn-off voltage, such as ground voltage Vss, is applied to the second set of lower select transistors 222 in the lower select transistor set. That is to say, the second set of lower select transistors 222 refers to a general BSG, which is used to generate gate-induced drain leakage current during the turn-off and erase operations in the programming operation.

[0180] In some embodiments, the aforementioned peripheral circuit is specifically configured as follows:

[0181] Perform an erase operation on all the lower selectors in the second lower selector set 222;

[0182] Perform programming operations on all the lower selectors in the set 222 of the second lower selectors;

[0183] During the programming operation of the remaining lower select transistors in the first lower select transistor set 220, a turn-off voltage is applied to the lower select transistors in the second lower select transistor set 222.

[0184] Here, after erasing all the lower select transistors in the second lower select transistor set, readjustment can be performed. Readjustment here means programming all the lower select transistors in the second lower select transistor set so that they all have a preset threshold voltage. In other words, all the lower select transistors in the second lower select transistor set can continue to be used as ordinary BSGs, i.e., used to generate gate-induced drain leakage current during the turn-off and erase operations in the programming operation.

[0185] Furthermore, it should be noted that it is also possible to omit the erase operation on the lower selectors in the second lower selector set (or, if the erase operation has a small erase depth), and instead readjust some of the lower selectors in the first lower selector set, that is, to convert some of the lower selectors in the first lower selector set into ordinary BSGs. Here, considering that after the erase operation on the first lower selector set, the lower selectors in the second lower selector set may not be able to be effectively turned off, it is necessary to readjust the portion of the first lower selector set that has already undergone the erase operation to form an ordinary BSG.

[0186] like Figure 9As shown, when the lower selection transistor set includes a second lower selection transistor set, the voltage on the second lower selection transistor set is forced to be maintained at the first voltage for a short preset time, the final stable second voltage on the second lower selection transistor set is larger, and the effective erase voltage value is smaller; thus, a smaller erase depth can be achieved on the second lower selection transistor set.

[0187] like Figure 8 As shown in Figures (a) and (b), in some embodiments, the lower select transistor set 218 may further include a plurality of first dummy unit sets 224, each of which includes a plurality of first dummy units that are equidistant from the source line and interconnected with each other; wherein the first dummy unit sets 224 are located between different first lower select transistor sets 220 or between the first lower select transistor set 220 and the second lower select transistor set 222.

[0188] Figure 8 Figure (a) illustrates a first dummy unit set 224 located between different first lower selection tube sets 220; Figure 8 Figure (b) illustrates two first dummy unit sets 224 located between different first lower select transistor sets 220, and three first dummy unit sets 224 located between different first lower select transistor sets 220. This embodiment of the present disclosure does not impose any special limitations on the number of first dummy unit sets or the arrangement relationship between the first dummy unit sets and the first lower select transistor sets; flexible selection can be made according to actual conditions. In this embodiment of the present disclosure, setting first dummy unit sets between different first lower select transistor sets can buffer the hot carrier injection (HCI) caused by the potential difference formed during the verification operation, thereby preventing threshold voltage drift of the lower select transistors in the first lower select transistor set.

[0189] In some embodiments, the peripheral circuit 304 is specifically configured as follows:

[0190] Perform an erase operation on the first dummy cells in the set 224 of all first dummy cells.

[0191] like Figure 9As shown, the voltage waveform diagram for erasing the first set of dummy cells includes solid and dashed lines. Solid lines represent the application of a low bias voltage to the first set of dummy cells, while dashed lines represent the holding voltage reached due to coupling. If the first set of dummy cells is subsequently used as a memory cell, the voltage indicated by the solid line is used; otherwise, the voltage indicated by the dashed line is used. In other words, if the first set of dummy cells is subsequently used as a memory cell, the erase depth of the first set of dummy cells is greater. This avoids insufficient erase depth of the first dummy cells in the first set of dummy cells, which could affect subsequent memory functionality.

[0192] In some embodiments, when the first dummy cell set 224 is located among different first lower selection transistor sets 220, the aforementioned peripheral circuit 304 is specifically configured as follows:

[0193] Program the first dummy cells in the set 224 of all first dummy cells to make the first dummy cells in the set 224 of first dummy cells have a target threshold voltage;

[0194] When the first dummy unit set 224 is located between the first lower selection transistor set 220 and the second lower selection transistor set 222, the aforementioned peripheral circuit 304 is specifically configured as follows:

[0195] Programming operations are performed on all the first dummy units in the first dummy unit set 224 so that all the first dummy units in the first dummy unit set 224 have a preset threshold voltage; wherein, the first dummy units in the first dummy unit set 224 with the preset threshold voltage are used to generate gate-induced drain leakage current during the turn-off and erase operations in the programming operation.

[0196] In some embodiments, the first set of dummy cells may be located among different sets of first lower select transistors, and can be used as storage cells after an erase operation on the first set of dummy cells. Using the first set of dummy cells as storage cells after an erase operation means that the first dummy cells included in the first set of dummy cells can be erased and then programmed to have a target threshold voltage; thus, the first dummy cells included in the first set of dummy cells can be used as storage cells. Here, converting the first set of dummy cells into storage cells only requires an erase operation.

[0197] refer to Figure 10 , Figure 10 A waveform diagram is provided for programming operations on a first set of dummy units according to an embodiment of this disclosure. For example... Figure 10As shown, applying a programming voltage Vpgm to a portion of the first dummy cell set refers to programming the first dummy cell set so that a portion of the first dummy cell set has a target threshold voltage; thus, this portion of the first dummy cell set can be used as a storage cell.

[0198] In some embodiments, the first set of dummy cells may be located between the first set of lower select transistors and the second set of lower select transistors. After an erase operation, the first set of dummy cells can be used as a regular BSG. Using the first set of dummy cells as a regular BSG after an erase operation means that the first dummy cells included in the first set of dummy cells can be erased and then programmed to have a preset threshold voltage; thus, the first dummy cells included in the first set of dummy cells can be reconfigured as a regular BSG. Here, converting the first set of dummy cells into a regular BSG requires first performing an erase operation and then a programming operation.

[0199] like Figure 8 As shown in Figure (a), the memory string further includes: a bottom dummy cell (i.e., a second dummy cell) located between the lower select transistor and the memory cell; the memory block includes multiple sets 226 of second dummy cells, each set 226 including multiple second dummy cells that are equidistant from the source line and interconnected. Each set 226 of second dummy cells corresponds to one layer of second dummy cells.

[0200] Figure 8 Figure (a) illustrates two second dummy unit sets 226. In fact, the embodiments of this disclosure do not have a special limitation on the number of second dummy unit sets, and an appropriate number of second dummy unit sets can be set according to the actual situation.

[0201] In some embodiments, the aforementioned peripheral circuit is specifically configured as follows:

[0202] Perform an erase operation on all second dummy cells in the set 226 of second dummy cells;

[0203] Program the second dummy units in the set 226 of all second dummy units to make the second dummy units in the set 226 of second dummy units have the target threshold voltage.

[0204] Here, after erasing the second set of dummy cells, they can be used as storage units. Using the second set of dummy cells as storage units after erasing means that after erasing the second dummy cells included in the second set of dummy cells, a programming operation can be performed to make the second dummy cells included in the second set of dummy cells have a target threshold voltage; thus, the second dummy cells included in the second set of dummy cells can be used as storage units. Here, converting the second set of dummy cells into storage units only requires an erasing operation.

[0205] like Figure 9 As shown, applying a programming voltage Vpgm to a portion of the bottom dummy word lines (i.e., the second dummy cell set) and a portion of the lower select transistors refers to performing a programming operation on a portion of the second dummy cell set and a portion of the lower select transistors. In other words, the second dummy cell set and a portion of the lower select transistors can be used as memory cells.

[0206] As previously mentioned, the memory block includes a set of downselect transistors and a second set of dummy cells located between the set of downselect transistors and the word line; wherein, the set of downselect transistors includes a first set of downselect transistors, a second set of downselect transistors, and a first set of dummy cells. The following will combine... Figure 11 It explains in detail how to operate on the lower selection tube set.

[0207] like Figure 11 As shown, in step S1101, a programming operation is performed on the memory cells in the memory block, that is, a programming operation is performed on the word lines in the memory block. During the programming operation, the process of applying voltage to the lower selection transistor set and the second dummy cell set can be referred to... Figure 4 The relevant descriptions will not be repeated here.

[0208] In step S1102, it is determined whether the programming operation for all memory cells in the memory block has been completed, that is, whether the programming operation for all word lines in the memory block has been completed. If yes, then step S1103 is executed; if no, then step S1101 is executed. In other words, step S1103 can only be executed after the programming operation for all word lines in the memory block has been completed.

[0209] In step S1103, an erasure operation is performed on the entire set of lower selection transistors and at least a portion of the set of second dummy cells; wherein, the set of lower selection transistors includes the first set of lower selection transistors, the second set of lower selection transistors, and the first set of dummy cells.

[0210] Here, after erasing the entire set of downselect transistors and at least a portion of the set of second dummy cells, the entire set of downselect transistors and at least a portion of the set of second dummy cells can be divided into two parts. The first part is set adjacent to the source line. After erasing, the first part can be readjusted so that it can be used as a regular BSG. The second part is set adjacent to the first part. After erasing, the second part can be used as a memory cell.

[0211] In step S1104, a fixed number of layers is selected for readjustment, so that some of the lower selection transistors have a preset threshold voltage.

[0212] Here, after the erase operation, the second lower selection tube set can be readjusted and used as a normal BSG; the second lower selection tube set and part of the first lower selection tube set can be readjusted and used as a normal BSG; the second lower selection tube set and part of the first dummy unit set can also be readjusted and used as a normal BSG; the second lower selection tube set, part of the first lower selection tube set and part of the first dummy unit set can also be readjusted and used as a normal BSG.

[0213] Here, "fixed layer number" refers to the fixed layer closest to the source line. For example, if the source line is set as layer 0, then layers 1, 2, 3, 4, ..., n are arranged from bottom to top. In this case, you can choose to use layer 1, or layers 1 and 2, or layers 1 to 3, or layers 1 to 4 as a standard BSG. That is, a fixed number of layers adjacent to and consecutively set with the source line can be readjusted and converted into a standard BSG.

[0214] In step S1105, other layers are selected as storage units.

[0215] Here, after the erase operation is performed, other layers can be selected as storage units; thus, programming operations can be performed on other layers.

[0216] refer to Figure 12 , Figure 12 This is a schematic diagram of the structure of a memory system provided in an embodiment of this disclosure. Figure 12 As shown, this disclosure provides a memory system, which includes: a memory as described in the above technical solution; and a controller coupled to the memory and configured to control the memory.

[0217] In some embodiments, the controller 402 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

[0218] In some embodiments, the controller 402 is designed to operate in a high duty cycle environment (Solid State Drive, SSD) or an embedded Multi-Media Card (eMMC), which serves as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays.

[0219] Controller 402 can be configured to control the operation of memory 300, such as read, erase, and program operations. Controller 402 can also be configured to manage various functions relating to data stored or to be stored in memory 300, including but not limited to bad block management, garbage collection, logical address to physical address translation, wear leveling, etc. In some embodiments, controller 402 is also configured to process error correcting codes (ECCs) relating to data read from or written to memory 300.

[0220] Controller 402 can also perform any other suitable function, such as formatting memory 300. Controller 402 can communicate with external devices (e.g., a host) according to a specific communication protocol. For example, controller 402 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Drive Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, etc.

[0221] The controller 402 and one or more memories 300 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 400 can be implemented and packaged into different types of end electronic products.

[0222] refer to Figure 13 , Figure 13 This is a schematic diagram of an electronic device provided according to an embodiment of this disclosure. (As shown...) Figure 13 As shown, this disclosure provides an electronic device 500, which includes: a memory system 400 as described in the above technical solution; and a host 502 coupled to the memory system 400.

[0223] In some embodiments, electronic device 500 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having memory therein.

[0224] like Figure 13 As shown, electronic device 500 may include host 502 and memory system 400, the memory system 400 having one or more memories 300 and controller 402. Host 502 may be a processor of electronic device (e.g., a central processing unit (CPU)) or a system-on-chip (SoC) (e.g., an application processor (AP)). Host 502 may be configured to send data to or receive data from memory 300.

[0225] In some embodiments, controller 402 is coupled to memory 300 and host 502 and is configured to control memory 300. Controller 402 can manage data stored in memory 300 and communicate with host 502.

[0226] refer to Figure 14A , Figure 14A This is a schematic diagram of a memory card with memory provided in an embodiment of this disclosure. Figure 14AAs shown, controller 402 and a single memory 300 can be integrated into memory card 404. Memory card 404 may include Personal Computer Memory Card International Association (PCMCIA) cards, CF cards, Smart Media (SM) cards, memory sticks, multimedia cards (e.g., MMC, Reduced-Size MMC (RS-MMC), Micro MMC (MMCmicro)), SD cards (e.g., SD, MiniSD, MicroSD, Secure Digital High Capacity (SDHC)), UFS, etc. Memory card 404 may also include components for connecting memory card 404 to a host computer (e.g., Figure 13 The memory card connector 406 is coupled to the host 502.

[0227] refer to Figure 14B , Figure 14B This is a schematic diagram of a solid-state drive with memory provided according to an embodiment of this disclosure. Figure 14B As shown, controller 402 and multiple memories 300 can be integrated into solid-state drive 408. Solid-state drive 408 may also include a connection between solid-state drive 408 and a host (e.g., Figure 13 The solid-state drive connector 410 is coupled to the host 502. In some embodiments, the storage capacity and / or operating speed of the solid-state drive 408 is greater than the storage capacity and / or operating speed of the memory card 404.

[0228] refer to Figure 15 , Figure 15 This is a flowchart illustrating a memory operation method provided in an embodiment of this disclosure. Figure 15 As shown, this disclosure provides an operation method for a memory, the memory including multiple memory blocks, each memory block including multiple memory strings; each memory string including an upper select transistor, a memory cell and a lower select transistor connected in series between a bit line and a source line; wherein all lower select transistors in the same memory block form a lower select transistor set; the above operation method includes:

[0229] Step S1501: Program the memory cells in the memory block;

[0230] Step S1502: Perform an erase operation on at least a portion of the lower selection tubes in the lower selection tube set.

[0231] In this embodiment of the disclosure, after the programming operation of the memory cell in the memory block is completed, at least a portion of the lower select transistors in the lower select transistor set can be erased. Subsequently, some lower select transistors can be readjusted to form lower select transistors with a preset threshold voltage, which are used to generate gate-induced drain leakage current during the turn-off and erase operations in the programming operation. The remaining lower select transistors can then be used to store data, thereby increasing the storage density.

[0232] In some embodiments, within the same memory block, multiple lower select transistors in different memory strings are interconnected, with the upper select transistors being electrically isolated from each other and having the same distance from the source line; the lower select transistor set includes multiple first lower select transistor sets, each first lower select transistor set including multiple lower select transistors having the same distance from the source line and the multiple lower select transistors having different threshold voltages;

[0233] Step S1501 includes:

[0234] Based on the fact that multiple downselect transistors in the first downselect transistor set have different threshold voltages, programming and verification operations are performed on the memory cells in the memory block.

[0235] In some embodiments, step S1502 includes:

[0236] Perform an erase operation on all the lower selectors in the first set of lower selectors;

[0237] Following step S1502, the above operation method further includes:

[0238] Program the lower select transistors in at least one set of first lower select transistors that are closest to the source line so that all lower select transistors in at least one set of first lower select transistors that are closest to the source line have a preset threshold voltage;

[0239] Program the remaining lower select transistors in the first set of lower select transistors to achieve the target threshold voltage.

[0240] In this embodiment of the present disclosure, after erasing the lower select transistors in the first set of lower select transistors, some of the lower select transistors can be readjusted to form a normal BSG; wherein, the lower select transistors used as the normal BSG have a preset threshold voltage; and the remaining lower select transistors can be used as memory cells.

[0241] In some embodiments, step S1502 includes:

[0242] An erase operation is performed on all the lower select transistors in the first lower select transistor set, so that at least one lower select transistor in the first lower select transistor set that is closest to the electrode has a preset threshold voltage;

[0243] Following step S1502, the above operation method further includes:

[0244] Program the remaining lower select transistors in the first set of lower select transistors to achieve the target threshold voltage.

[0245] In this embodiment of the present disclosure, the erasure depth of the erase operation on the lower select transistors in the first lower select transistor set can be controlled to be different. After some lower select transistors are erased, no further adjustment is required to form a normal BSG; the remaining lower select transistors can be used as storage units.

[0246] In some embodiments, programming operations are performed on the remaining lower selectors in the first lower selector set, including:

[0247] Perform single-level cell SLC programming operations on the remaining lower selectors in the first set of lower selectors;

[0248] Among them, the lower selection transistors with preset threshold voltage in the first set of lower selection transistors are used to generate gate-induced drain leakage current during the turn-off and erase operations in the programming operation.

[0249] In some embodiments, the lower select transistor set further includes at least one second lower select transistor set located between the source line and the first lower select transistor set, each second lower select transistor set including a plurality of lower select transistors at the same distance from the source line;

[0250] During the programming operation of the memory cells in the memory block, a turn-off voltage is applied to the lower selection transistor in the second lower selection transistor set.

[0251] In some embodiments, step S1502 includes:

[0252] Perform an erase operation on all the lower selectors in the entire set of second lower selectors;

[0253] Following step S1502, the above operation method further includes:

[0254] Perform programming operations on the lower selectors in the entire set of second lower selectors;

[0255] Program the remaining lower select transistors in the first set of lower select transistors to achieve the target threshold voltage, including:

[0256] During the programming operation of the remaining lower select transistors in the first set of lower select transistors, a turn-off voltage is applied to the lower select transistors in the second set of lower select transistors.

[0257] In this embodiment of the disclosure, the second lower selection transistor set is a regular BSG, which is responsible for turning off during the programming operation of the memory unit.

[0258] In some embodiments, the lower select transistor set further includes a plurality of first dummy cell sets, each first dummy cell set including a plurality of first dummy cells at the same distance from the source line, the first dummy cell sets being located between different first lower select transistor sets or between the first lower select transistor set and the second lower select transistor set.

[0259] In some embodiments, step S1502 includes:

[0260] Perform an erase operation on the first dummy cells in the entire set of first dummy cells.

[0261] In some embodiments, when the first set of dummy units is located between different sets of first lower selection tubes, after step S1502, the above-described operation method further includes:

[0262] Program the first dummy cells in the entire set of first dummy cells to make the first dummy cells in the set of first dummy cells have a target threshold voltage;

[0263] When the first set of dummy units is located between the first set of lower selection tubes and the second set of lower selection tubes, after step S1502, the above operation method further includes:

[0264] The first dummy cells in the entire set of first dummy cells are programmed so that all the first dummy cells in the set of first dummy cells have a preset threshold voltage; wherein, the first dummy cells in the set of first dummy cells with the preset threshold voltage are used to generate gate-induced drain leakage current during the turn-off and erase operations in the programming operation.

[0265] In some embodiments, the memory string further includes a plurality of second dummy cells located between the memory cell and the lower select transistor, and the memory block includes a plurality of sets of second dummy cells, each set of second dummy cells including a plurality of second dummy cells at the same distance from the source line;

[0266] In addition to step S1502, the above operation method also includes:

[0267] Perform an erase operation on all second dummy cells in the set of all second dummy cells;

[0268] Following step S1502, the above operation method further includes:

[0269] Program the second dummy cells in the entire set of second dummy cells to make the second dummy cells in the set of second dummy cells have the target threshold voltage.

[0270] This disclosure provides a memory and its operation method, as well as a memory system. The memory includes: a memory cell array and peripheral circuitry coupled to the memory cell array; the memory cell array includes multiple memory blocks, each memory block including multiple memory strings; each memory string includes an upper select transistor, a memory cell, and a lower select transistor connected in series between a bit line and a source line; wherein all lower select transistors in the same memory block form a lower select transistor set; the peripheral circuitry is configured to: perform programming operations on the memory cells in the memory block; and perform erase operations on at least a portion of the lower select transistors in the lower select transistor set. In this disclosure, after programming the memory cells in the memory block, at least a portion of the lower select transistors in the lower select transistor set can be erased. This allows for subsequent readjustment of some lower select transistors to form lower select transistors with a preset threshold voltage, used to generate gate-induced drain leakage current during turn-off and erase operations in the programming operation. Furthermore, the remaining lower select transistors can be used to store data, thereby increasing storage density.

[0271] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0272] The above description is merely a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. Any equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A memory, characterized in that, The memory includes: a memory cell array and peripheral circuitry coupled to the memory cell array; the memory cell array includes multiple memory blocks, each memory block including multiple memory strings; each memory string includes an upper select transistor, a memory cell, and a lower select transistor connected in series between a bit line and a source line; wherein all lower select transistors in the same memory block form a lower select transistor set. The peripheral circuit is configured as follows: Perform programming operations on the storage cells in the storage block; An erase operation is performed on at least a portion of the lower select transistors in the set of lower select transistors, and at least a portion of the memory cells in the memory block are in a programmed state.

2. The memory according to claim 1, characterized in that, In the same memory block, multiple lower select transistors in different memory strings are interconnected, with the upper select transistors being electrically isolated from each other and having the same distance from the source line; the lower select transistor set includes multiple first lower select transistor sets, each first lower select transistor set including multiple lower select transistors having the same distance from the source line and the multiple lower select transistors having different threshold voltages; The peripheral circuit is specifically configured as follows: Based on the fact that multiple downselect transistors in the first downselect transistor set have different threshold voltages, programming and verification operations are performed on the memory cells in the memory block.

3. The memory according to claim 2, characterized in that, The peripheral circuit is specifically configured as follows: Perform an erase operation on all the lower selection tubes in the first set of lower selection tubes; The lower select transistors in at least one of the first lower select transistor sets that are closest to the source line are programmed to have a preset threshold voltage. The remaining lower select transistors in the first lower select transistor set are programmed to have the target threshold voltage.

4. The memory according to claim 2, characterized in that, The peripheral circuit is specifically configured as follows: An erase operation is performed on all the lower select transistors in the first lower select transistor set, such that at least one lower select transistor in the first lower select transistor set that is closest to the source line has a preset threshold voltage. The remaining lower select transistors in the first lower select transistor set are programmed to have the target threshold voltage.

5. The memory according to claim 3 or 4, characterized in that, The peripheral circuit is specifically configured as follows: Perform single-level cell (SLC) programming operations on the remaining lower selection transistors in the first set of lower selection transistors; Among them, the lower select transistors with preset threshold voltage in the first set of lower select transistors are used to generate gate-induced drain leakage current during the turn-off and erase operations in the programming operation.

6. The memory according to claim 5, characterized in that, The lower select transistor set also includes at least one second lower select transistor set located between the source line and the first lower select transistor set, each second lower select transistor set including a plurality of lower select transistors at the same distance from the source line; During the programming operation of the memory cells in the memory block, a turn-off voltage is applied to the lower selection transistors in the second set of lower selection transistors.

7. The memory according to claim 6, characterized in that, The peripheral circuit is specifically configured as follows: Perform an erase operation on all the lower selectors in the second set of lower selectors; Perform programming operations on all the lower selection tubes in the second set of lower selection tubes; During the programming operation of the remaining lower select transistors in the first lower select transistor set, a turn-off voltage is applied to the lower select transistors in the second lower select transistor set.

8. The memory according to claim 7, characterized in that, The lower select transistor set also includes multiple first dummy cell sets. Each first dummy cell set includes multiple first dummy cells at the same distance from the source line. The first dummy cell sets are located between different first lower select transistor sets or between the first lower select transistor set and the second lower select transistor set.

9. The memory according to claim 8, characterized in that, The peripheral circuit is specifically configured as follows: Perform an erase operation on all the first dummy cells in the first set of dummy cells.

10. The memory according to claim 9, characterized in that, When the first set of dummy units is located between different sets of the first lower selection transistors, the peripheral circuit is specifically configured as follows: Program the first dummy units in all the first dummy unit sets to make the first dummy units in the first dummy unit sets have a target threshold voltage; When the first set of dummy units is located between the first set of lower selection transistors and the second set of lower selection transistors, the peripheral circuit is specifically configured as follows: Programming operations are performed on all the first dummy units in the first dummy unit set so that all the first dummy units in the first dummy unit set have a preset threshold voltage; wherein, the first dummy units in the first dummy unit set with the preset threshold voltage are used to generate gate-induced drain leakage current during the turn-off and erase operations in the programming operation.

11. The memory according to claim 2, characterized in that, The storage string further includes a plurality of second dummy units located between the storage cell and the lower select transistor, and the storage block includes a plurality of sets of second dummy units, each set of second dummy units including a plurality of second dummy units at the same distance from the source line; The peripheral circuit is specifically configured as follows: Perform an erase operation on all second dummy cells in the set of second dummy cells; Program the second dummy units in the entire set of the second dummy units to make the second dummy units in the set of the second dummy units have a target threshold voltage.

12. A memory system, characterized in that, The memory system includes: The memory as described in any one of claims 1 to 11; and A controller coupled to the memory and configured to control the memory.

13. A method for operating a memory, characterized in that, The memory includes multiple memory blocks, and each memory block includes multiple memory strings; each memory string includes an upper select transistor, a memory cell, and a lower select transistor connected in series between a bit line and a source line; wherein all lower select transistors in the same memory block form a lower select transistor set; The operation method includes: Perform programming operations on the storage cells in the storage block; An erase operation is performed on at least a portion of the lower select transistors in the set of lower select transistors, and at least a portion of the memory cells in the memory block are in a programmed state.

14. The method of operating the memory according to claim 13, characterized in that, In the same memory block, multiple lower select transistors in different memory strings are interconnected, with the upper select transistors being electrically isolated from each other and having the same distance from the source line; the lower select transistor set includes multiple first lower select transistor sets, each first lower select transistor set including multiple lower select transistors having the same distance from the source line and the multiple lower select transistors having different threshold voltages; The programming operation on the storage cells in the storage block includes: Based on the fact that multiple downselect transistors in the first downselect transistor set have different threshold voltages, programming and verification operations are performed on the memory cells in the memory block.

15. The method of operating the memory according to claim 14, characterized in that, The erase operation on at least a portion of the lower selector tubes in the lower selector tube set includes: Perform an erase operation on all the lower selection tubes in the first set of lower selection tubes; After performing the erase operation on at least a portion of the lower selector tubes in the lower selector tube set, the operation method further includes: The lower select transistors in at least one of the first lower select transistor sets that are closest to the source line are programmed to have a preset threshold voltage. The remaining lower select transistors in the first lower select transistor set are programmed to have the target threshold voltage.

16. The method of operating the memory according to claim 14, characterized in that, The erase operation on at least a portion of the lower selector tubes in the lower selector tube set includes: An erase operation is performed on all the lower select transistors in the first lower select transistor set, such that at least one lower select transistor in the first lower select transistor set that is closest to the source line has a preset threshold voltage. After performing the erase operation on at least a portion of the lower selector tubes in the lower selector tube set, the operation method further includes: The remaining lower select transistors in the first lower select transistor set are programmed to have the target threshold voltage.

17. The method of operating the memory according to claim 15 or 16, characterized in that, The programming operation on the remaining lower selectors in the first lower selector set includes: Perform single-level cell (SLC) programming operations on the remaining lower selection transistors in the first set of lower selection transistors; Among them, the lower select transistors with preset threshold voltage in the first set of lower select transistors are used to generate gate-induced drain leakage current during the turn-off and erase operations in the programming operation.

18. The method of operating the memory according to claim 17, characterized in that, The lower select transistor set also includes at least one second lower select transistor set located between the source line and the first lower select transistor set, each second lower select transistor set including a plurality of lower select transistors at the same distance from the source line; During the programming operation of the memory cells in the memory block, a turn-off voltage is applied to the lower selection transistors in the second set of lower selection transistors.

19. The method of operating the memory according to claim 18, characterized in that, The erase operation on at least a portion of the lower selector tubes in the lower selector tube set includes: Perform an erase operation on all the lower selectors in the second set of lower selectors; After performing the erase operation on at least a portion of the lower selector tubes in the lower selector tube set, the operation method further includes: Perform programming operations on all the lower selection tubes in the second set of lower selection tubes; The step of programming the remaining lower-select transistors in the first lower-select transistor set to have a target threshold voltage includes: During the programming operation of the remaining lower select transistors in the first lower select transistor set, a turn-off voltage is applied to the lower select transistors in the second lower select transistor set.

20. The method of operating the memory according to claim 19, characterized in that, The lower select transistor set also includes multiple first dummy cell sets. Each first dummy cell set includes multiple first dummy cells at the same distance from the source line. The first dummy cell sets are located between different first lower select transistor sets or between the first lower select transistor set and the second lower select transistor set.

21. The method of operating the memory according to claim 20, characterized in that, The erase operation on at least a portion of the lower selector tubes in the lower selector tube set includes: Perform an erase operation on all the first dummy cells in the first set of dummy cells.

22. The method of operating the memory according to claim 21, characterized in that, When the first set of dummy units is located between different sets of first lower selection tubes, after performing an erase operation on at least a portion of the lower selection tubes in the set of lower selection tubes, the operation method further includes: Program the first dummy units in all the first dummy unit sets to make the first dummy units in the first dummy unit sets have a target threshold voltage; When the first set of dummy units is located between the first set of lower selection tubes and the second set of lower selection tubes, after performing an erase operation on at least a portion of the lower selection tubes in the set of lower selection tubes, the operation method further includes: Programming operations are performed on all the first dummy units in the first dummy unit set so that all the first dummy units in the first dummy unit set have a preset threshold voltage; wherein, the first dummy units in the first dummy unit set with the preset threshold voltage are used to generate gate-induced drain leakage current during the turn-off and erase operations in the programming operation.

23. The method of operating the memory according to claim 14, characterized in that, The storage string further includes a plurality of second dummy units located between the storage cell and the lower select transistor, and the storage block includes a plurality of sets of second dummy units, each set of second dummy units including a plurality of second dummy units at the same distance from the source line; While performing the erase operation on at least a portion of the lower selection tubes in the lower selection tube set, the operation method further includes: Perform an erase operation on all second dummy cells in the set of second dummy cells; After performing the erase operation on at least a portion of the lower selector tubes in the lower selector tube set, the operation method further includes: Program the second dummy units in the entire set of the second dummy units to make the second dummy units in the set of the second dummy units have a target threshold voltage.

Images